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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zve64f,+zvfh,+xsfvfexpa \3; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zve64f,+zvfh,+xsfvfexpa \5; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK6 7define <vscale x 1 x float> @test_intrinsic_sf_vfexpa_v_nxv1f32(<vscale x 1 x float> %0, iXLen %1) {8; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_nxv1f32:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma11; CHECK-NEXT: sf.vfexpa.v v8, v812; CHECK-NEXT: ret13entry:14 %f = call <vscale x 1 x float> @llvm.riscv.sf.vfexpa.nxv1f32(15 <vscale x 1 x float> poison,16 <vscale x 1 x float> %0,17 iXLen %1)18 ret <vscale x 1 x float> %f19}20 21define <vscale x 2 x float> @test_intrinsic_sf_vfexpa_v_nxv2f32(<vscale x 2 x float> %0, iXLen %1) {22; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_nxv2f32:23; CHECK: # %bb.0: # %entry24; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma25; CHECK-NEXT: sf.vfexpa.v v8, v826; CHECK-NEXT: ret27entry:28 %f = call <vscale x 2 x float> @llvm.riscv.sf.vfexpa.nxv2f32(29 <vscale x 2 x float> poison,30 <vscale x 2 x float> %0,31 iXLen %1)32 ret <vscale x 2 x float> %f33}34 35define <vscale x 4 x float> @test_intrinsic_sf_vfexpa_v_nxv4f32(<vscale x 4 x float> %0, iXLen %1) {36; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_nxv4f32:37; CHECK: # %bb.0: # %entry38; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma39; CHECK-NEXT: sf.vfexpa.v v8, v840; CHECK-NEXT: ret41entry:42 %f = call <vscale x 4 x float> @llvm.riscv.sf.vfexpa.nxv4f32(43 <vscale x 4 x float> poison,44 <vscale x 4 x float> %0,45 iXLen %1)46 ret <vscale x 4 x float> %f47}48 49define <vscale x 8 x float> @test_intrinsic_sf_vfexpa_v_nxv8f32(<vscale x 8 x float> %0, iXLen %1) {50; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_nxv8f32:51; CHECK: # %bb.0: # %entry52; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma53; CHECK-NEXT: sf.vfexpa.v v8, v854; CHECK-NEXT: ret55entry:56 %f = call <vscale x 8 x float> @llvm.riscv.sf.vfexpa.nxv8f32(57 <vscale x 8 x float> poison,58 <vscale x 8 x float> %0,59 iXLen %1)60 ret <vscale x 8 x float> %f61}62 63define <vscale x 16 x float> @test_intrinsic_sf_vfexpa_v_nxv16f32(<vscale x 16 x float> %0, iXLen %1) {64; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_nxv16f32:65; CHECK: # %bb.0: # %entry66; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma67; CHECK-NEXT: sf.vfexpa.v v8, v868; CHECK-NEXT: ret69entry:70 %f = call <vscale x 16 x float> @llvm.riscv.sf.vfexpa.nxv16f32(71 <vscale x 16 x float> poison,72 <vscale x 16 x float> %0,73 iXLen %1)74 ret <vscale x 16 x float> %f75}76 77define <vscale x 1 x float> @test_intrinsic_sf_vfexpa_v_mask_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x i1> %m, iXLen %vl) {78; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_mask_nxv1f32:79; CHECK: # %bb.0: # %entry80; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu81; CHECK-NEXT: sf.vfexpa.v v8, v9, v0.t82; CHECK-NEXT: ret83entry:84 %f = call <vscale x 1 x float> @llvm.riscv.sf.vfexpa.mask.nxv1f32(85 <vscale x 1 x float> %0,86 <vscale x 1 x float> %1,87 <vscale x 1 x i1> %m,88 iXLen %vl,89 iXLen 0)90 ret <vscale x 1 x float> %f91}92 93define <vscale x 2 x float> @test_intrinsic_sf_vfexpa_v_mask_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x i1> %m, iXLen %vl) {94; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_mask_nxv2f32:95; CHECK: # %bb.0: # %entry96; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu97; CHECK-NEXT: sf.vfexpa.v v8, v9, v0.t98; CHECK-NEXT: ret99entry:100 %f = call <vscale x 2 x float> @llvm.riscv.sf.vfexpa.mask.nxv2f32(101 <vscale x 2 x float> %0,102 <vscale x 2 x float> %1,103 <vscale x 2 x i1> %m,104 iXLen %vl,105 iXLen 0)106 ret <vscale x 2 x float> %f107}108 109define <vscale x 4 x float> @test_intrinsic_sf_vfexpa_v_mask_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x i1> %m, iXLen %vl) {110; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_mask_nxv4f32:111; CHECK: # %bb.0: # %entry112; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu113; CHECK-NEXT: sf.vfexpa.v v8, v10, v0.t114; CHECK-NEXT: ret115entry:116 %f = call <vscale x 4 x float> @llvm.riscv.sf.vfexpa.mask.nxv4f32(117 <vscale x 4 x float> %0,118 <vscale x 4 x float> %1,119 <vscale x 4 x i1> %m,120 iXLen %vl,121 iXLen 0)122 ret <vscale x 4 x float> %f123}124 125define <vscale x 8 x float> @test_intrinsic_sf_vfexpa_v_mask_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x i1> %m, iXLen %vl) {126; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_mask_nxv8f32:127; CHECK: # %bb.0: # %entry128; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu129; CHECK-NEXT: sf.vfexpa.v v8, v12, v0.t130; CHECK-NEXT: ret131entry:132 %f = call <vscale x 8 x float> @llvm.riscv.sf.vfexpa.mask.nxv8f32(133 <vscale x 8 x float> %0,134 <vscale x 8 x float> %1,135 <vscale x 8 x i1> %m,136 iXLen %vl,137 iXLen 0)138 ret <vscale x 8 x float> %f139}140 141define <vscale x 16 x float> @test_intrinsic_sf_vfexpa_v_mask_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x i1> %m, iXLen %vl) {142; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_mask_nxv16f32:143; CHECK: # %bb.0: # %entry144; CHECK-NEXT: vsetvli zero, a0, e32, m8, tu, mu145; CHECK-NEXT: sf.vfexpa.v v8, v16, v0.t146; CHECK-NEXT: ret147entry:148 %f = call <vscale x 16 x float> @llvm.riscv.sf.vfexpa.mask.nxv16f32(149 <vscale x 16 x float> %0,150 <vscale x 16 x float> %1,151 <vscale x 16 x i1> %m,152 iXLen %vl,153 iXLen 0)154 ret <vscale x 16 x float> %f155}156 157define <vscale x 1 x half> @test_intrinsic_sf_vfexpa_v_nxv1f16(<vscale x 1 x half> %0, iXLen %1) {158; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_nxv1f16:159; CHECK: # %bb.0: # %entry160; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma161; CHECK-NEXT: sf.vfexpa.v v8, v8162; CHECK-NEXT: ret163entry:164 %f = call <vscale x 1 x half> @llvm.riscv.sf.vfexpa.nxv1f16(165 <vscale x 1 x half> poison,166 <vscale x 1 x half> %0,167 iXLen %1)168 ret <vscale x 1 x half> %f169}170 171define <vscale x 2 x half> @test_intrinsic_sf_vfexpa_v_nxv2f16(<vscale x 2 x half> %0, iXLen %1) {172; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_nxv2f16:173; CHECK: # %bb.0: # %entry174; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma175; CHECK-NEXT: sf.vfexpa.v v8, v8176; CHECK-NEXT: ret177entry:178 %f = call <vscale x 2 x half> @llvm.riscv.sf.vfexpa.nxv2f16(179 <vscale x 2 x half> poison,180 <vscale x 2 x half> %0,181 iXLen %1)182 ret <vscale x 2 x half> %f183}184 185define <vscale x 4 x half> @test_intrinsic_sf_vfexpa_v_nxv4f16(<vscale x 4 x half> %0, iXLen %1) {186; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_nxv4f16:187; CHECK: # %bb.0: # %entry188; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma189; CHECK-NEXT: sf.vfexpa.v v8, v8190; CHECK-NEXT: ret191entry:192 %f = call <vscale x 4 x half> @llvm.riscv.sf.vfexpa.nxv4f16(193 <vscale x 4 x half> poison,194 <vscale x 4 x half> %0,195 iXLen %1)196 ret <vscale x 4 x half> %f197}198 199define <vscale x 8 x half> @test_intrinsic_sf_vfexpa_v_nxv8f16(<vscale x 8 x half> %0, iXLen %1) {200; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_nxv8f16:201; CHECK: # %bb.0: # %entry202; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma203; CHECK-NEXT: sf.vfexpa.v v8, v8204; CHECK-NEXT: ret205entry:206 %f = call <vscale x 8 x half> @llvm.riscv.sf.vfexpa.nxv8f16(207 <vscale x 8 x half> poison,208 <vscale x 8 x half> %0,209 iXLen %1)210 ret <vscale x 8 x half> %f211}212 213define <vscale x 16 x half> @test_intrinsic_sf_vfexpa_v_nxv16f16(<vscale x 16 x half> %0, iXLen %1) {214; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_nxv16f16:215; CHECK: # %bb.0: # %entry216; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma217; CHECK-NEXT: sf.vfexpa.v v8, v8218; CHECK-NEXT: ret219entry:220 %f = call <vscale x 16 x half> @llvm.riscv.sf.vfexpa.nxv16f16(221 <vscale x 16 x half> poison,222 <vscale x 16 x half> %0,223 iXLen %1)224 ret <vscale x 16 x half> %f225}226 227define <vscale x 32 x half> @test_intrinsic_sf_vfexpa_v_nxv32f16(<vscale x 32 x half> %0, iXLen %1) {228; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_nxv32f16:229; CHECK: # %bb.0: # %entry230; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma231; CHECK-NEXT: sf.vfexpa.v v8, v8232; CHECK-NEXT: ret233entry:234 %f = call <vscale x 32 x half> @llvm.riscv.sf.vfexpa.nxv32f16(235 <vscale x 32 x half> poison,236 <vscale x 32 x half> %0,237 iXLen %1)238 ret <vscale x 32 x half> %f239}240 241define <vscale x 1 x half> @test_intrinsic_sf_vfexpa_v_mask_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i1> %m, iXLen %vl) {242; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_mask_nxv1f16:243; CHECK: # %bb.0: # %entry244; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu245; CHECK-NEXT: sf.vfexpa.v v8, v9, v0.t246; CHECK-NEXT: ret247entry:248 %f = call <vscale x 1 x half> @llvm.riscv.sf.vfexpa.mask.nxv1f16(249 <vscale x 1 x half> %0,250 <vscale x 1 x half> %1,251 <vscale x 1 x i1> %m,252 iXLen %vl,253 iXLen 0)254 ret <vscale x 1 x half> %f255}256 257define <vscale x 2 x half> @test_intrinsic_sf_vfexpa_v_mask_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x i1> %m, iXLen %vl) {258; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_mask_nxv2f16:259; CHECK: # %bb.0: # %entry260; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu261; CHECK-NEXT: sf.vfexpa.v v8, v9, v0.t262; CHECK-NEXT: ret263entry:264 %f = call <vscale x 2 x half> @llvm.riscv.sf.vfexpa.mask.nxv2f16(265 <vscale x 2 x half> %0,266 <vscale x 2 x half> %1,267 <vscale x 2 x i1> %m,268 iXLen %vl,269 iXLen 0)270 ret <vscale x 2 x half> %f271}272 273define <vscale x 4 x half> @test_intrinsic_sf_vfexpa_v_mask_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x i1> %m, iXLen %vl) {274; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_mask_nxv4f16:275; CHECK: # %bb.0: # %entry276; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu277; CHECK-NEXT: sf.vfexpa.v v8, v9, v0.t278; CHECK-NEXT: ret279entry:280 %f = call <vscale x 4 x half> @llvm.riscv.sf.vfexpa.mask.nxv4f16(281 <vscale x 4 x half> %0,282 <vscale x 4 x half> %1,283 <vscale x 4 x i1> %m,284 iXLen %vl,285 iXLen 0)286 ret <vscale x 4 x half> %f287}288 289define <vscale x 8 x half> @test_intrinsic_sf_vfexpa_v_mask_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i1> %m, iXLen %vl) {290; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_mask_nxv8f16:291; CHECK: # %bb.0: # %entry292; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu293; CHECK-NEXT: sf.vfexpa.v v8, v10, v0.t294; CHECK-NEXT: ret295entry:296 %f = call <vscale x 8 x half> @llvm.riscv.sf.vfexpa.mask.nxv8f16(297 <vscale x 8 x half> %0,298 <vscale x 8 x half> %1,299 <vscale x 8 x i1> %m,300 iXLen %vl,301 iXLen 0)302 ret <vscale x 8 x half> %f303}304 305define <vscale x 16 x half> @test_intrinsic_sf_vfexpa_v_mask_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x i1> %m, iXLen %vl) {306; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_mask_nxv16f16:307; CHECK: # %bb.0: # %entry308; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu309; CHECK-NEXT: sf.vfexpa.v v8, v12, v0.t310; CHECK-NEXT: ret311entry:312 %f = call <vscale x 16 x half> @llvm.riscv.sf.vfexpa.mask.nxv16f16(313 <vscale x 16 x half> %0,314 <vscale x 16 x half> %1,315 <vscale x 16 x i1> %m,316 iXLen %vl,317 iXLen 0)318 ret <vscale x 16 x half> %f319}320 321define <vscale x 32 x half> @test_intrinsic_sf_vfexpa_v_mask_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x i1> %m, iXLen %vl) {322; CHECK-LABEL: test_intrinsic_sf_vfexpa_v_mask_nxv32f16:323; CHECK: # %bb.0: # %entry324; CHECK-NEXT: vsetvli zero, a0, e16, m8, tu, mu325; CHECK-NEXT: sf.vfexpa.v v8, v16, v0.t326; CHECK-NEXT: ret327entry:328 %f = call <vscale x 32 x half> @llvm.riscv.sf.vfexpa.mask.nxv32f16(329 <vscale x 32 x half> %0,330 <vscale x 32 x half> %1,331 <vscale x 32 x i1> %m,332 iXLen %vl,333 iXLen 0)334 ret <vscale x 32 x half> %f335}336