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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+xsfvfnrclipxfqf \3; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+xsfvfnrclipxfqf \5; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s6 7define <vscale x 1 x i8> @intrinsic_sf_vfnrclip_xu_f_qf_nxv1i8_nxv1f32(<vscale x 1 x float> %0, float %1, iXLen %2) nounwind {8; CHECK-LABEL: intrinsic_sf_vfnrclip_xu_f_qf_nxv1i8_nxv1f32:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma11; CHECK-NEXT: sf.vfnrclip.xu.f.qf v9, v8, fa012; CHECK-NEXT: vmv1r.v v8, v913; CHECK-NEXT: ret14entry:15 %a = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.iXLen(16 <vscale x 1 x i8> poison,17 <vscale x 1 x float> %0,18 float %1,19 iXLen 7, iXLen %2)20 21 ret <vscale x 1 x i8> %a22}23 24define <vscale x 1 x i8> @intrinsic_sf_vfnrclip_xu_f_qf_mask_nxv1i8_nxv1f32(<vscale x 1 x i8> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {25; CHECK-LABEL: intrinsic_sf_vfnrclip_xu_f_qf_mask_nxv1i8_nxv1f32:26; CHECK: # %bb.0: # %entry27; CHECK-NEXT: fsrmi a1, 028; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu29; CHECK-NEXT: sf.vfnrclip.xu.f.qf v8, v9, fa0, v0.t30; CHECK-NEXT: fsrm a131; CHECK-NEXT: ret32entry:33 %a = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.iXLen(34 <vscale x 1 x i8> %0,35 <vscale x 1 x float> %1,36 float %2,37 <vscale x 1 x i1> %3,38 iXLen 0, iXLen %4, iXLen 1)39 40 ret <vscale x 1 x i8> %a41}42 43define <vscale x 2 x i8> @intrinsic_sf_vfnrclip_xu_f_qf_nxv2i8_nxv2f32(<vscale x 2 x float> %0, float %1, iXLen %2) nounwind {44; CHECK-LABEL: intrinsic_sf_vfnrclip_xu_f_qf_nxv2i8_nxv2f32:45; CHECK: # %bb.0: # %entry46; CHECK-NEXT: fsrmi a1, 047; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma48; CHECK-NEXT: sf.vfnrclip.xu.f.qf v9, v8, fa049; CHECK-NEXT: fsrm a150; CHECK-NEXT: vmv1r.v v8, v951; CHECK-NEXT: ret52entry:53 %a = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.iXLen(54 <vscale x 2 x i8> poison,55 <vscale x 2 x float> %0,56 float %1,57 iXLen 0, iXLen %2)58 59 ret <vscale x 2 x i8> %a60}61 62define <vscale x 2 x i8> @intrinsic_sf_vfnrclip_xu_f_qf_mask_nxv2i8_nxv2f32(<vscale x 2 x i8> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {63; CHECK-LABEL: intrinsic_sf_vfnrclip_xu_f_qf_mask_nxv2i8_nxv2f32:64; CHECK: # %bb.0: # %entry65; CHECK-NEXT: fsrmi a1, 066; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu67; CHECK-NEXT: sf.vfnrclip.xu.f.qf v8, v9, fa0, v0.t68; CHECK-NEXT: fsrm a169; CHECK-NEXT: ret70entry:71 %a = call <vscale x 2 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.iXLen(72 <vscale x 2 x i8> %0,73 <vscale x 2 x float> %1,74 float %2,75 <vscale x 2 x i1> %3,76 iXLen 0, iXLen %4, iXLen 1)77 78 ret <vscale x 2 x i8> %a79}80 81define <vscale x 4 x i8> @intrinsic_sf_vfnrclip_xu_f_qf_nxv4i8_nxv4f32(<vscale x 4 x float> %0, float %1, iXLen %2) nounwind {82; CHECK-LABEL: intrinsic_sf_vfnrclip_xu_f_qf_nxv4i8_nxv4f32:83; CHECK: # %bb.0: # %entry84; CHECK-NEXT: fsrmi a1, 085; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma86; CHECK-NEXT: sf.vfnrclip.xu.f.qf v10, v8, fa087; CHECK-NEXT: fsrm a188; CHECK-NEXT: vmv1r.v v8, v1089; CHECK-NEXT: ret90entry:91 %a = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.iXLen(92 <vscale x 4 x i8> poison,93 <vscale x 4 x float> %0,94 float %1,95 iXLen 0, iXLen %2)96 97 ret <vscale x 4 x i8> %a98}99 100define <vscale x 4 x i8> @intrinsic_sf_vfnrclip_xu_f_qf_mask_nxv4i8_nxv4f32(<vscale x 4 x i8> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {101; CHECK-LABEL: intrinsic_sf_vfnrclip_xu_f_qf_mask_nxv4i8_nxv4f32:102; CHECK: # %bb.0: # %entry103; CHECK-NEXT: fsrmi a1, 0104; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu105; CHECK-NEXT: sf.vfnrclip.xu.f.qf v8, v10, fa0, v0.t106; CHECK-NEXT: fsrm a1107; CHECK-NEXT: ret108entry:109 %a = call <vscale x 4 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.iXLen(110 <vscale x 4 x i8> %0,111 <vscale x 4 x float> %1,112 float %2,113 <vscale x 4 x i1> %3,114 iXLen 0, iXLen %4, iXLen 1)115 116 ret <vscale x 4 x i8> %a117}118 119define <vscale x 8 x i8> @intrinsic_sf_vfnrclip_xu_f_qf_nxv8i8_nxv8f32(<vscale x 8 x float> %0, float %1, iXLen %2) nounwind {120; CHECK-LABEL: intrinsic_sf_vfnrclip_xu_f_qf_nxv8i8_nxv8f32:121; CHECK: # %bb.0: # %entry122; CHECK-NEXT: fsrmi a1, 0123; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma124; CHECK-NEXT: sf.vfnrclip.xu.f.qf v12, v8, fa0125; CHECK-NEXT: fsrm a1126; CHECK-NEXT: vmv.v.v v8, v12127; CHECK-NEXT: ret128entry:129 %a = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.iXLen(130 <vscale x 8 x i8> poison,131 <vscale x 8 x float> %0,132 float %1,133 iXLen 0, iXLen %2)134 135 ret <vscale x 8 x i8> %a136}137 138define <vscale x 8 x i8> @intrinsic_sf_vfnrclip_xu_f_qf_mask_nxv8i8_nxv8f32(<vscale x 8 x i8> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {139; CHECK-LABEL: intrinsic_sf_vfnrclip_xu_f_qf_mask_nxv8i8_nxv8f32:140; CHECK: # %bb.0: # %entry141; CHECK-NEXT: fsrmi a1, 0142; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu143; CHECK-NEXT: sf.vfnrclip.xu.f.qf v8, v12, fa0, v0.t144; CHECK-NEXT: fsrm a1145; CHECK-NEXT: ret146entry:147 %a = call <vscale x 8 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv8i8.nxv8f32.iXLen(148 <vscale x 8 x i8> %0,149 <vscale x 8 x float> %1,150 float %2,151 <vscale x 8 x i1> %3,152 iXLen 0, iXLen %4, iXLen 1)153 154 ret <vscale x 8 x i8> %a155}156 157define <vscale x 16 x i8> @intrinsic_sf_vfnrclip_xu_f_qf_nxv16i8_nxv16f32(<vscale x 16 x float> %0, float %1, iXLen %2) nounwind {158; CHECK-LABEL: intrinsic_sf_vfnrclip_xu_f_qf_nxv16i8_nxv16f32:159; CHECK: # %bb.0: # %entry160; CHECK-NEXT: fsrmi a1, 0161; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma162; CHECK-NEXT: sf.vfnrclip.xu.f.qf v16, v8, fa0163; CHECK-NEXT: fsrm a1164; CHECK-NEXT: vmv.v.v v8, v16165; CHECK-NEXT: ret166entry:167 %a = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.iXLen(168 <vscale x 16 x i8> poison,169 <vscale x 16 x float> %0,170 float %1,171 iXLen 0, iXLen %2)172 173 ret <vscale x 16 x i8> %a174}175 176define <vscale x 16 x i8> @intrinsic_sf_vfnrclip_xu_f_qf_mask_nxv16i8_nxv16f32(<vscale x 16 x i8> %0, <vscale x 16 x float> %1, float %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {177; CHECK-LABEL: intrinsic_sf_vfnrclip_xu_f_qf_mask_nxv16i8_nxv16f32:178; CHECK: # %bb.0: # %entry179; CHECK-NEXT: fsrmi a1, 0180; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu181; CHECK-NEXT: sf.vfnrclip.xu.f.qf v8, v16, fa0, v0.t182; CHECK-NEXT: fsrm a1183; CHECK-NEXT: ret184entry:185 %a = call <vscale x 16 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv16i8.nxv16f32.iXLen(186 <vscale x 16 x i8> %0,187 <vscale x 16 x float> %1,188 float %2,189 <vscale x 16 x i1> %3,190 iXLen 0, iXLen %4, iXLen 1)191 192 ret <vscale x 16 x i8> %a193}194