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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfbfmin,+xsfvfwmaccqqq \3; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfbfmin,+xsfvfwmaccqqq \5; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK6 7define <vscale x 1 x float> @intrinsic_vfwmacc_4x4x4_tu_f32mf2(<vscale x 1 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 1 x bfloat> %2, iXLen %3) nounwind {8; CHECK-LABEL: intrinsic_vfwmacc_4x4x4_tu_f32mf2:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma11; CHECK-NEXT: sf.vfwmacc.4x4x4 v8, v9, v1012; CHECK-NEXT: ret13entry:14 %a = call <vscale x 1 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.iXLen(15 <vscale x 1 x float> %0,16 <vscale x 4 x bfloat> %1,17 <vscale x 1 x bfloat> %2,18 iXLen %3, iXLen 2)19 20 ret <vscale x 1 x float> %a21}22 23define <vscale x 1 x float> @intrinsic_vfwmacc_4x4x4_ta_f32mf2(<vscale x 1 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 1 x bfloat> %2, iXLen %3) nounwind {24; CHECK-LABEL: intrinsic_vfwmacc_4x4x4_ta_f32mf2:25; CHECK: # %bb.0: # %entry26; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma27; CHECK-NEXT: sf.vfwmacc.4x4x4 v8, v9, v1028; CHECK-NEXT: ret29entry:30 %a = call <vscale x 1 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv1f32.nxv4bf16.nxv1bf16.iXLen(31 <vscale x 1 x float> %0,32 <vscale x 4 x bfloat> %1,33 <vscale x 1 x bfloat> %2,34 iXLen %3, iXLen 3)35 36 ret <vscale x 1 x float> %a37}38 39define <vscale x 2 x float> @intrinsic_vfwmacc_4x4x4_tu_f32m1(<vscale x 2 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 2 x bfloat> %2, iXLen %3) nounwind {40; CHECK-LABEL: intrinsic_vfwmacc_4x4x4_tu_f32m1:41; CHECK: # %bb.0: # %entry42; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma43; CHECK-NEXT: sf.vfwmacc.4x4x4 v8, v9, v1044; CHECK-NEXT: ret45entry:46 %a = call <vscale x 2 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.iXLen(47 <vscale x 2 x float> %0,48 <vscale x 4 x bfloat> %1,49 <vscale x 2 x bfloat> %2,50 iXLen %3, iXLen 2)51 52 ret <vscale x 2 x float> %a53}54 55define <vscale x 2 x float> @intrinsic_vfwmacc_4x4x4_ta_f32m1(<vscale x 2 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 2 x bfloat> %2, iXLen %3) nounwind {56; CHECK-LABEL: intrinsic_vfwmacc_4x4x4_ta_f32m1:57; CHECK: # %bb.0: # %entry58; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma59; CHECK-NEXT: sf.vfwmacc.4x4x4 v8, v9, v1060; CHECK-NEXT: ret61entry:62 %a = call <vscale x 2 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv2f32.nxv4bf16.nxv2bf16.iXLen(63 <vscale x 2 x float> %0,64 <vscale x 4 x bfloat> %1,65 <vscale x 2 x bfloat> %2,66 iXLen %3, iXLen 3)67 68 ret <vscale x 2 x float> %a69}70 71define <vscale x 4 x float> @intrinsic_vfwmacc_4x4x4_tu_f32m2(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, iXLen %3) nounwind {72; CHECK-LABEL: intrinsic_vfwmacc_4x4x4_tu_f32m2:73; CHECK: # %bb.0: # %entry74; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma75; CHECK-NEXT: sf.vfwmacc.4x4x4 v8, v10, v1176; CHECK-NEXT: ret77entry:78 %a = call <vscale x 4 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.iXLen(79 <vscale x 4 x float> %0,80 <vscale x 4 x bfloat> %1,81 <vscale x 4 x bfloat> %2,82 iXLen %3, iXLen 2)83 84 ret <vscale x 4 x float> %a85}86 87define <vscale x 4 x float> @intrinsic_vfwmacc_4x4x4_ta_f32m2(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, iXLen %3) nounwind {88; CHECK-LABEL: intrinsic_vfwmacc_4x4x4_ta_f32m2:89; CHECK: # %bb.0: # %entry90; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma91; CHECK-NEXT: sf.vfwmacc.4x4x4 v8, v10, v1192; CHECK-NEXT: ret93entry:94 %a = call <vscale x 4 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv4f32.nxv4bf16.nxv4bf16.iXLen(95 <vscale x 4 x float> %0,96 <vscale x 4 x bfloat> %1,97 <vscale x 4 x bfloat> %2,98 iXLen %3, iXLen 3)99 100 ret <vscale x 4 x float> %a101}102 103define <vscale x 8 x float> @intrinsic_vfwmacc_4x4x4_tu_f32m4(<vscale x 8 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 8 x bfloat> %2, iXLen %3) nounwind {104; CHECK-LABEL: intrinsic_vfwmacc_4x4x4_tu_f32m4:105; CHECK: # %bb.0: # %entry106; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma107; CHECK-NEXT: sf.vfwmacc.4x4x4 v8, v12, v14108; CHECK-NEXT: ret109entry:110 %a = call <vscale x 8 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.iXLen(111 <vscale x 8 x float> %0,112 <vscale x 4 x bfloat> %1,113 <vscale x 8 x bfloat> %2,114 iXLen %3, iXLen 2)115 116 ret <vscale x 8 x float> %a117}118 119define <vscale x 8 x float> @intrinsic_vfwmacc_4x4x4_ta_f32m4(<vscale x 8 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 8 x bfloat> %2, iXLen %3) nounwind {120; CHECK-LABEL: intrinsic_vfwmacc_4x4x4_ta_f32m4:121; CHECK: # %bb.0: # %entry122; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma123; CHECK-NEXT: sf.vfwmacc.4x4x4 v8, v12, v14124; CHECK-NEXT: ret125entry:126 %a = call <vscale x 8 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv8f32.nxv4bf16.nxv8bf16.iXLen(127 <vscale x 8 x float> %0,128 <vscale x 4 x bfloat> %1,129 <vscale x 8 x bfloat> %2,130 iXLen %3, iXLen 3)131 132 ret <vscale x 8 x float> %a133}134 135define <vscale x 16 x float> @intrinsic_vfwmacc_4x4x4_tu_f32m8(<vscale x 16 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 16 x bfloat> %2, iXLen %3) nounwind {136; CHECK-LABEL: intrinsic_vfwmacc_4x4x4_tu_f32m8:137; CHECK: # %bb.0: # %entry138; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma139; CHECK-NEXT: sf.vfwmacc.4x4x4 v8, v16, v20140; CHECK-NEXT: ret141entry:142 %a = call <vscale x 16 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.iXLen(143 <vscale x 16 x float> %0,144 <vscale x 4 x bfloat> %1,145 <vscale x 16 x bfloat> %2,146 iXLen %3, iXLen 2)147 148 ret <vscale x 16 x float> %a149}150 151define <vscale x 16 x float> @intrinsic_vfwmacc_4x4x4_ta_f32m8(<vscale x 16 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 16 x bfloat> %2, iXLen %3) nounwind {152; CHECK-LABEL: intrinsic_vfwmacc_4x4x4_ta_f32m8:153; CHECK: # %bb.0: # %entry154; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma155; CHECK-NEXT: sf.vfwmacc.4x4x4 v8, v16, v20156; CHECK-NEXT: ret157entry:158 %a = call <vscale x 16 x float> @llvm.riscv.sf.vfwmacc.4x4x4.nxv16f32.nxv4bf16.nxv16bf16.iXLen(159 <vscale x 16 x float> %0,160 <vscale x 4 x bfloat> %1,161 <vscale x 16 x bfloat> %2,162 iXLen %3, iXLen 3)163 164 ret <vscale x 16 x float> %a165}166