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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+xsfvqmaccqoq \3; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+xsfvqmaccqoq \5; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK6 7define <vscale x 2 x i32> @intrinsic_vqmacc_4x8x4_tu_i32m1(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, iXLen %3) nounwind {8; CHECK-LABEL: intrinsic_vqmacc_4x8x4_tu_i32m1:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, ma11; CHECK-NEXT: sf.vqmacc.4x8x4 v8, v9, v1012; CHECK-NEXT: ret13entry:14 %a = call <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv8i8(15 <vscale x 2 x i32> %0,16 <vscale x 8 x i8> %1,17 <vscale x 4 x i8> %2,18 iXLen %3, iXLen 2)19 20 ret <vscale x 2 x i32> %a21}22 23define <vscale x 2 x i32> @intrinsic_vqmacc_4x8x4_ta_i32m1(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 4 x i8> %2, iXLen %3) nounwind {24; CHECK-LABEL: intrinsic_vqmacc_4x8x4_ta_i32m1:25; CHECK: # %bb.0: # %entry26; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma27; CHECK-NEXT: sf.vqmacc.4x8x4 v8, v9, v1028; CHECK-NEXT: ret29entry:30 %a = call <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv8i8(31 <vscale x 2 x i32> %0,32 <vscale x 8 x i8> %1,33 <vscale x 4 x i8> %2,34 iXLen %3, iXLen 3)35 36 ret <vscale x 2 x i32> %a37}38 39define <vscale x 4 x i32> @intrinsic_vqmacc_4x8x4_tu_i32m2(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {40; CHECK-LABEL: intrinsic_vqmacc_4x8x4_tu_i32m2:41; CHECK: # %bb.0: # %entry42; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma43; CHECK-NEXT: sf.vqmacc.4x8x4 v8, v10, v1144; CHECK-NEXT: ret45entry:46 %a = call <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv16i8(47 <vscale x 4 x i32> %0,48 <vscale x 8 x i8> %1,49 <vscale x 8 x i8> %2,50 iXLen %3, iXLen 2)51 52 ret <vscale x 4 x i32> %a53}54 55define <vscale x 4 x i32> @intrinsic_vqmacc_4x8x4_ta_i32m2(<vscale x 4 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {56; CHECK-LABEL: intrinsic_vqmacc_4x8x4_ta_i32m2:57; CHECK: # %bb.0: # %entry58; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma59; CHECK-NEXT: sf.vqmacc.4x8x4 v8, v10, v1160; CHECK-NEXT: ret61entry:62 %a = call <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv16i8(63 <vscale x 4 x i32> %0,64 <vscale x 8 x i8> %1,65 <vscale x 8 x i8> %2,66 iXLen %3, iXLen 3)67 68 ret <vscale x 4 x i32> %a69}70 71define <vscale x 8 x i32> @intrinsic_vqmacc_4x8x4_tu_i32m4(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {72; CHECK-LABEL: intrinsic_vqmacc_4x8x4_tu_i32m4:73; CHECK: # %bb.0: # %entry74; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, ma75; CHECK-NEXT: sf.vqmacc.4x8x4 v8, v12, v1476; CHECK-NEXT: ret77entry:78 %a = call <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv32i8(79 <vscale x 8 x i32> %0,80 <vscale x 8 x i8> %1,81 <vscale x 16 x i8> %2,82 iXLen %3, iXLen 2)83 84 ret <vscale x 8 x i32> %a85}86 87define <vscale x 8 x i32> @intrinsic_vqmacc_4x8x4_ta_i32m4(<vscale x 8 x i32> %0, <vscale x 8 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {88; CHECK-LABEL: intrinsic_vqmacc_4x8x4_ta_i32m4:89; CHECK: # %bb.0: # %entry90; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma91; CHECK-NEXT: sf.vqmacc.4x8x4 v8, v12, v1492; CHECK-NEXT: ret93entry:94 %a = call <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv32i8(95 <vscale x 8 x i32> %0,96 <vscale x 8 x i8> %1,97 <vscale x 16 x i8> %2,98 iXLen %3, iXLen 3)99 100 ret <vscale x 8 x i32> %a101}102 103define <vscale x 16 x i32> @intrinsic_vqmacc_4x8x4_tu_i32m8(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {104; CHECK-LABEL: intrinsic_vqmacc_4x8x4_tu_i32m8:105; CHECK: # %bb.0: # %entry106; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, ma107; CHECK-NEXT: sf.vqmacc.4x8x4 v8, v16, v20108; CHECK-NEXT: ret109entry:110 %a = call <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv64i8(111 <vscale x 16 x i32> %0,112 <vscale x 8 x i8> %1,113 <vscale x 32 x i8> %2,114 iXLen %3, iXLen 2)115 116 ret <vscale x 16 x i32> %a117}118 119define <vscale x 16 x i32> @intrinsic_vqmacc_4x8x4_ta_i32m8(<vscale x 16 x i32> %0, <vscale x 8 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {120; CHECK-LABEL: intrinsic_vqmacc_4x8x4_ta_i32m8:121; CHECK: # %bb.0: # %entry122; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma123; CHECK-NEXT: sf.vqmacc.4x8x4 v8, v16, v20124; CHECK-NEXT: ret125entry:126 %a = call <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv64i8(127 <vscale x 16 x i32> %0,128 <vscale x 8 x i8> %1,129 <vscale x 32 x i8> %2,130 iXLen %3, iXLen 3)131 132 ret <vscale x 16 x i32> %a133}134