524 lines · plain
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc %s -o - -mtriple=riscv64 -mattr=+v \3# RUN: -run-pass=phi-node-elimination,register-coalescer,riscv-insert-vsetvli | FileCheck %s4 5--- |6 define void @xsfmm_same_state(<vscale x 32 x half> %tile1, <vscale x 32 x half> %tile2, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) {7 entry:8 tail call void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64 2, <vscale x 32 x half> %tile1, <vscale x 32 x half> %tile2, i64 %tm, i64 %tn, i64 %tk, i64 2)9 tail call void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64 2, <vscale x 32 x half> %tile1, <vscale x 32 x half> %tile2, i64 %tm, i64 %tn, i64 %tk, i64 2)10 ret void11 }12 13 define void @xsfmm_different_state(<vscale x 32 x half> %tile1, <vscale x 32 x half> %tile2, i64 %tm, i64 %tn, i64 %tk) {14 entry:15 tail call void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64 2, <vscale x 32 x half> %tile1, <vscale x 32 x half> %tile2, i64 %tm, i64 %tn, i64 %tk, i64 2)16 tail call void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64 2, <vscale x 32 x half> %tile1, <vscale x 32 x half> %tile2, i64 %tm, i64 %tn, i64 %tk, i64 4)17 ret void18 }19 20 define void @xsfmm_different_state_bf(<vscale x 32 x half> %tile1, <vscale x 32 x bfloat> %tile2, i64 %tm, i64 %tn, i64 %tk) {21 entry:22 tail call void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64 2, <vscale x 32 x half> %tile1, <vscale x 32 x half> %tile1, i64 %tm, i64 %tn, i64 %tk, i64 2)23 tail call void @llvm.riscv.sf.mm.f.f.i64.nxv32bf16(i64 2, <vscale x 32 x bfloat> %tile2, <vscale x 32 x bfloat> %tile2, i64 %tm, i64 %tn, i64 %tk, i64 2)24 tail call void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64 2, <vscale x 32 x half> %tile1, <vscale x 32 x half> %tile1, i64 %tm, i64 %tn, i64 %tk, i64 2)25 ret void26 }27 28 define <vscale x 64 x i8> @interleave_rvv_and_xsfmm(<vscale x 64 x i8> %tile, i64 %vl, ptr %base) {29 entry:30 %0 = call <vscale x 64 x i8> @llvm.riscv.sf.vtmv.v.t.nxv64i8.i64(i64 1, i64 %vl)31 %1 = call <vscale x 64 x i8> @llvm.riscv.vadd.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %tile, <vscale x 64 x i8> %0, i64 %vl)32 call void @llvm.riscv.sf.vste16.i64(i64 1, ptr %base, i64 %vl)33 ret <vscale x 64 x i8> %134 }35 36 define <vscale x 64 x i8> @interleave_rvv_and_xsfmm2(<vscale x 64 x i8> %tile, i64 %vl, ptr %base) {37 entry:38 %0 = call <vscale x 64 x i8> @llvm.riscv.vadd.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %tile, <vscale x 64 x i8> %tile, i64 %vl)39 %1 = call <vscale x 64 x i8> @llvm.riscv.sf.vtmv.v.t.nxv64i8.i64(i64 1, i64 %vl)40 %2 = call <vscale x 64 x i8> @llvm.riscv.vadd.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %tile, <vscale x 64 x i8> %0, i64 %vl)41 call void @llvm.riscv.sf.vste16.i64(i64 1, ptr %base, i64 %vl)42 ret <vscale x 64 x i8> %243 }44 45 define void @consecutive_xsfmm(<vscale x 32 x half> %tile, i64 %tm, i64 %tn, i64 %tk, ptr %base) {46 entry:47 tail call void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64 0, <vscale x 32 x half> %tile, <vscale x 32 x half> %tile, i64 %tm, i64 %tn, i64 %tk, i64 2)48 call void @llvm.riscv.sf.vste16.i64(i64 0, ptr %base, i64 %tn)49 ret void50 }51 52 define i64 @vsettnt_max(i64 %vl) {53 entry:54 %0 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %vl, i64 1, i64 2)55 %1 = call i64 @llvm.riscv.sf.vsettnt_max.i64(i64 1, i64 2)56 ret i64 %057 }58 59 define i64 @single_vsettm(i64 %vl) {60 entry:61 %0 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %vl, i64 1, i64 2)62 ret i64 %063 }64 65 define i64 @single_vsettn(i64 %vl) {66 entry:67 %0 = call i64 @llvm.riscv.sf.vsettn.i64(i64 %vl, i64 1, i64 2)68 ret i64 %069 }70 71 define i64 @single_vsettk(i64 %vl) {72 entry:73 %0 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %vl, i64 1, i64 2)74 ret i64 %075 }76 77 define void @sf_vtzero(i64 %tm, i64 %tn) {78 entry:79 call void @llvm.riscv.sf.vtzero.i64(i64 1, i64 %tm, i64 %tn, i64 3, i64 4)80 ret void81 }82 83 declare void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64, <vscale x 32 x half>, <vscale x 32 x half>, i64, i64, i64, i64)84 declare void @llvm.riscv.sf.mm.f.f.i64.nxv32bf16(i64, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64, i64, i64, i64)85 declare <vscale x 64 x i8> @llvm.riscv.sf.vtmv.v.t.nxv64i8.i64(i64, i64)86 declare <vscale x 64 x i8> @llvm.riscv.vadd.nxv64i8.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, <vscale x 64 x i8>, i64)87 declare void @llvm.riscv.sf.vste16.i64(i64, ptr, i64)88 declare i64 @llvm.riscv.sf.vsettnt_max.i64(i64, i64)89 declare i64 @llvm.riscv.sf.vsettm.i64(i64, i64, i64)90 declare i64 @llvm.riscv.sf.vsettn.i64(i64, i64, i64)91 declare i64 @llvm.riscv.sf.vsettk.i64(i64, i64, i64)92 declare void @llvm.riscv.sf.vtzero.i64(i64, i64, i64, i64, i64)93...94---95name: xsfmm_same_state96alignment: 497tracksRegLiveness: true98registers:99 - { id: 0, class: vrm8 }100 - { id: 1, class: vrm8 }101 - { id: 2, class: gprnox0 }102 - { id: 3, class: gprnox0 }103 - { id: 4, class: gprnox0 }104liveins:105 - { reg: '$v8m8', virtual-reg: '%0' }106 - { reg: '$v8m8', virtual-reg: '%1' }107 - { reg: '$x10', virtual-reg: '%2' }108 - { reg: '$x11', virtual-reg: '%3' }109 - { reg: '$x12', virtual-reg: '%4' }110frameInfo:111 maxAlignment: 1112machineFunctionInfo: {}113body: |114 bb.0.entry:115 liveins: $v8m8, $v16m8, $x10, $x11, $x12116 ; CHECK-LABEL: name: xsfmm_same_state117 ; CHECK: liveins: $v8m8, $v16m8, $x10, $x11, $x12118 ; CHECK-NEXT: {{ $}}119 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x12120 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprnox0 = COPY $x11121 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gprnox0 = COPY $x10122 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vrm8 = COPY $v16m8123 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vrm8 = COPY $v8m8124 ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY1]], 1032 /* e16, w2 */, implicit-def $vl, implicit-def $vtype125 ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTM [[COPY2]], 4, 2, implicit-def $vtype, implicit $vtype126 ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTK [[COPY]], 4, 2, implicit-def $vtype, implicit $vtype127 ; CHECK-NEXT: PseudoSF_MM_F_F $t2, [[COPY4]], [[COPY3]], 7, $noreg, $noreg, $noreg, 4, 2, implicit $frm, implicit $vl, implicit $vtype128 ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTM [[COPY2]], 4, 2, implicit-def $vtype, implicit $vtype129 ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTK [[COPY]], 4, 2, implicit-def $vtype, implicit $vtype130 ; CHECK-NEXT: PseudoSF_MM_F_F $t2, [[COPY4]], [[COPY3]], 7, $noreg, $noreg, $noreg, 4, 2, implicit $frm, implicit $vl, implicit $vtype131 ; CHECK-NEXT: PseudoRET132 %4:gprnox0 = COPY $x12133 %3:gprnox0 = COPY $x11134 %2:gprnox0 = COPY $x10135 %1:vrm8 = COPY $v16m8136 %0:vrm8 = COPY $v8m8137 PseudoSF_MM_F_F $t2, %0:vrm8, %1:vrm8, 7, %2:gprnox0, %3:gprnox0, %4:gprnox0, 4, 2, implicit $frm138 PseudoSF_MM_F_F $t2, %0:vrm8, %1:vrm8, 7, %2:gprnox0, %3:gprnox0, %4:gprnox0, 4, 2, implicit $frm139 PseudoRET140...141---142name: xsfmm_different_state143alignment: 4144tracksRegLiveness: true145registers:146 - { id: 0, class: vrm8 }147 - { id: 1, class: vrm8 }148 - { id: 2, class: gprnox0 }149 - { id: 3, class: gprnox0 }150 - { id: 4, class: gprnox0 }151liveins:152 - { reg: '$v8m8', virtual-reg: '%0' }153 - { reg: '$v8m8', virtual-reg: '%1' }154 - { reg: '$x10', virtual-reg: '%2' }155 - { reg: '$x11', virtual-reg: '%3' }156 - { reg: '$x12', virtual-reg: '%4' }157frameInfo:158 maxAlignment: 1159machineFunctionInfo: {}160body: |161 bb.0.entry:162 liveins: $v8m8, $v16m8, $x10, $x11, $x12163 ; CHECK-LABEL: name: xsfmm_different_state164 ; CHECK: liveins: $v8m8, $v16m8, $x10, $x11, $x12165 ; CHECK-NEXT: {{ $}}166 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x12167 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprnox0 = COPY $x11168 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gprnox0 = COPY $x10169 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vrm8 = COPY $v16m8170 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vrm8 = COPY $v8m8171 ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY1]], 1032 /* e16, w2 */, implicit-def $vl, implicit-def $vtype172 ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTM [[COPY2]], 4, 2, implicit-def $vtype, implicit $vtype173 ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTK [[COPY]], 4, 2, implicit-def $vtype, implicit $vtype174 ; CHECK-NEXT: PseudoSF_MM_F_F $t2, [[COPY4]], [[COPY3]], 7, $noreg, $noreg, $noreg, 4, 2, implicit $frm, implicit $vl, implicit $vtype175 ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY1]], 1544 /* e16, w4 */, implicit-def $vl, implicit-def $vtype176 ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTM [[COPY2]], 4, 3, implicit-def $vtype, implicit $vtype177 ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTK [[COPY]], 4, 3, implicit-def $vtype, implicit $vtype178 ; CHECK-NEXT: PseudoSF_MM_F_F $t2, [[COPY4]], [[COPY3]], 7, $noreg, $noreg, $noreg, 4, 4, implicit $frm, implicit $vl, implicit $vtype179 ; CHECK-NEXT: PseudoRET180 %4:gprnox0 = COPY $x12181 %3:gprnox0 = COPY $x11182 %2:gprnox0 = COPY $x10183 %1:vrm8 = COPY $v16m8184 %0:vrm8 = COPY $v8m8185 PseudoSF_MM_F_F $t2, %0:vrm8, %1:vrm8, 7, %2:gprnox0, %3:gprnox0, %4:gprnox0, 4, 2, implicit $frm186 PseudoSF_MM_F_F $t2, %0:vrm8, %1:vrm8, 7, %2:gprnox0, %3:gprnox0, %4:gprnox0, 4, 4, implicit $frm187 PseudoRET188...189---190name: xsfmm_different_state_bf191alignment: 4192tracksRegLiveness: true193registers:194 - { id: 0, class: vrm8 }195 - { id: 1, class: vrm8 }196 - { id: 2, class: gprnox0 }197 - { id: 3, class: gprnox0 }198 - { id: 4, class: gprnox0 }199liveins:200 - { reg: '$v8m8', virtual-reg: '%0' }201 - { reg: '$v8m8', virtual-reg: '%1' }202 - { reg: '$x10', virtual-reg: '%2' }203 - { reg: '$x11', virtual-reg: '%3' }204 - { reg: '$x12', virtual-reg: '%4' }205frameInfo:206 maxAlignment: 1207machineFunctionInfo: {}208body: |209 bb.0.entry:210 liveins: $v8m8, $v16m8, $x10, $x11, $x12211 ; CHECK-LABEL: name: xsfmm_different_state_bf212 ; CHECK: liveins: $v8m8, $v16m8, $x10, $x11, $x12213 ; CHECK-NEXT: {{ $}}214 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x12215 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprnox0 = COPY $x11216 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gprnox0 = COPY $x10217 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vrm8 = COPY $v16m8218 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vrm8 = COPY $v8m8219 ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY1]], 1032 /* e16, w2 */, implicit-def $vl, implicit-def $vtype220 ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTM [[COPY2]], 4, 2, implicit-def $vtype, implicit $vtype221 ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTK [[COPY]], 4, 2, implicit-def $vtype, implicit $vtype222 ; CHECK-NEXT: PseudoSF_MM_F_F $t2, [[COPY4]], [[COPY4]], 7, $noreg, $noreg, $noreg, 4, 2, implicit $frm, implicit $vl, implicit $vtype223 ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY1]], 1288 /* e16, w2 */, implicit-def $vl, implicit-def $vtype224 ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTM [[COPY2]], 4, 2, implicit-def $vtype, implicit $vtype225 ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTK [[COPY]], 4, 2, implicit-def $vtype, implicit $vtype226 ; CHECK-NEXT: PseudoSF_MM_F_F_ALT $t2, [[COPY3]], [[COPY3]], 7, $noreg, $noreg, $noreg, 4, 2, implicit $frm, implicit $vl, implicit $vtype227 ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY1]], 1032 /* e16, w2 */, implicit-def $vl, implicit-def $vtype228 ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTM [[COPY2]], 4, 2, implicit-def $vtype, implicit $vtype229 ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTK [[COPY]], 4, 2, implicit-def $vtype, implicit $vtype230 ; CHECK-NEXT: PseudoSF_MM_F_F $t2, [[COPY4]], [[COPY4]], 7, $noreg, $noreg, $noreg, 4, 2, implicit $frm, implicit $vl, implicit $vtype231 ; CHECK-NEXT: PseudoRET232 %4:gprnox0 = COPY $x12233 %3:gprnox0 = COPY $x11234 %2:gprnox0 = COPY $x10235 %1:vrm8 = COPY $v16m8236 %0:vrm8 = COPY $v8m8237 PseudoSF_MM_F_F $t2, %0:vrm8, %0:vrm8, 7, %2:gprnox0, %3:gprnox0, %4:gprnox0, 4, 2, implicit $frm238 PseudoSF_MM_F_F_ALT $t2, %1:vrm8, %1:vrm8, 7, %2:gprnox0, %3:gprnox0, %4:gprnox0, 4, 2, implicit $frm239 PseudoSF_MM_F_F $t2, %0:vrm8, %0:vrm8, 7, %2:gprnox0, %3:gprnox0, %4:gprnox0, 4, 2, implicit $frm240 PseudoRET241...242---243name: interleave_rvv_and_xsfmm244alignment: 4245tracksRegLiveness: true246registers:247 - { id: 0, class: vrm8 }248 - { id: 1, class: gprnox0 }249 - { id: 2, class: gpr }250 - { id: 3, class: gpr }251 - { id: 4, class: vrm8 }252 - { id: 5, class: vrm8 }253liveins:254 - { reg: '$v8m8', virtual-reg: '%0' }255 - { reg: '$x10', virtual-reg: '%1' }256 - { reg: '$x11', virtual-reg: '%2' }257frameInfo:258 maxAlignment: 1259machineFunctionInfo: {}260body: |261 bb.0.entry:262 liveins: $v8m8, $x10, $x11263 ; CHECK-LABEL: name: interleave_rvv_and_xsfmm264 ; CHECK: liveins: $v8m8, $x10, $x11265 ; CHECK-NEXT: {{ $}}266 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x11267 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprnox0 = COPY $x10268 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vrm8 = COPY $v8m8269 ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1270 ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY1]], 512 /* e8, w1 */, implicit-def $vl, implicit-def $vtype271 ; CHECK-NEXT: [[PseudoSF_VTMV_V_T:%[0-9]+]]:vrm8 = PseudoSF_VTMV_V_T [[ADDI]], $noreg, 3, 1, implicit $vl, implicit $vtype272 ; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY1]], 195 /* e8, m8, ta, ma */, implicit-def $vl, implicit-def $vtype273 ; CHECK-NEXT: [[PseudoVADD_VV_M8_:%[0-9]+]]:vrm8 = PseudoVADD_VV_M8 $noreg, [[COPY2]], [[PseudoSF_VTMV_V_T]], $noreg, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype274 ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY1]], 520 /* e16, w1 */, implicit-def $vl, implicit-def $vtype275 ; CHECK-NEXT: PseudoSF_VSTE16 [[ADDI]], [[COPY]], $noreg, 4, 1, implicit $vl, implicit $vtype276 ; CHECK-NEXT: $v8m8 = COPY [[PseudoVADD_VV_M8_]], implicit $vtype277 ; CHECK-NEXT: PseudoRET implicit $v8m8278 %2:gpr = COPY $x11279 %1:gprnox0 = COPY $x10280 %0:vrm8 = COPY $v8m8281 %3:gpr = ADDI $x0, 1282 %4:vrm8 = PseudoSF_VTMV_V_T %3:gpr, %1:gprnox0, 3, 1283 %5:vrm8 = PseudoVADD_VV_M8 $noreg, %0:vrm8, killed %4:vrm8, %1:gprnox0, 3, 0284 PseudoSF_VSTE16 %3:gpr, %2:gpr, %1:gprnox0, 4, 1285 $v8m8 = COPY %5:vrm8286 PseudoRET implicit $v8m8287...288---289name: interleave_rvv_and_xsfmm2290alignment: 4291tracksRegLiveness: true292registers:293 - { id: 0, class: vrm8 }294 - { id: 1, class: gprnox0 }295 - { id: 2, class: gpr }296 - { id: 3, class: gpr }297 - { id: 4, class: vrm8 }298 - { id: 5, class: vrm8 }299liveins:300 - { reg: '$v8m8', virtual-reg: '%0' }301 - { reg: '$x10', virtual-reg: '%1' }302 - { reg: '$x11', virtual-reg: '%2' }303frameInfo:304 maxAlignment: 1305machineFunctionInfo: {}306body: |307 bb.0.entry:308 liveins: $v8m8, $x10, $x11309 ; CHECK-LABEL: name: interleave_rvv_and_xsfmm2310 ; CHECK: liveins: $v8m8, $x10, $x11311 ; CHECK-NEXT: {{ $}}312 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x11313 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprnox0 = COPY $x10314 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vrm8 = COPY $v8m8315 ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1316 ; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY1]], 195 /* e8, m8, ta, ma */, implicit-def $vl, implicit-def $vtype317 ; CHECK-NEXT: [[PseudoVADD_VV_M8_:%[0-9]+]]:vrm8 = PseudoVADD_VV_M8 $noreg, [[COPY2]], [[COPY2]], $noreg, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype318 ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY1]], 512 /* e8, w1 */, implicit-def $vl, implicit-def $vtype319 ; CHECK-NEXT: dead [[PseudoSF_VTMV_V_T:%[0-9]+]]:vrm8 = PseudoSF_VTMV_V_T [[ADDI]], $noreg, 3, 1, implicit $vl, implicit $vtype320 ; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY1]], 195 /* e8, m8, ta, ma */, implicit-def $vl, implicit-def $vtype321 ; CHECK-NEXT: [[PseudoVADD_VV_M8_1:%[0-9]+]]:vrm8 = PseudoVADD_VV_M8 $noreg, [[PseudoVADD_VV_M8_]], [[PseudoVADD_VV_M8_]], $noreg, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype322 ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY1]], 520 /* e16, w1 */, implicit-def $vl, implicit-def $vtype323 ; CHECK-NEXT: PseudoSF_VSTE16 [[ADDI]], [[COPY]], $noreg, 4, 1, implicit $vl, implicit $vtype324 ; CHECK-NEXT: $v8m8 = COPY [[PseudoVADD_VV_M8_1]], implicit $vtype325 ; CHECK-NEXT: PseudoRET implicit $v8m8326 %2:gpr = COPY $x11327 %1:gprnox0 = COPY $x10328 %0:vrm8 = COPY $v8m8329 %3:gpr = ADDI $x0, 1330 %4:vrm8 = PseudoVADD_VV_M8 $noreg, %0:vrm8, killed %0:vrm8, %1:gprnox0, 3, 0331 %5:vrm8 = PseudoSF_VTMV_V_T %3:gpr, %1:gprnox0, 3, 1332 %6:vrm8 = PseudoVADD_VV_M8 $noreg, %4:vrm8, killed %4:vrm8, %1:gprnox0, 3, 0333 PseudoSF_VSTE16 %3:gpr, %2:gpr, %1:gprnox0, 4, 1334 $v8m8 = COPY %6:vrm8335 PseudoRET implicit $v8m8336...337---338name: consecutive_xsfmm339alignment: 4340tracksRegLiveness: true341registers:342 - { id: 0, class: vrm8 }343 - { id: 1, class: gprnox0 }344 - { id: 2, class: gprnox0 }345 - { id: 3, class: gprnox0 }346 - { id: 4, class: gprnox0 }347liveins:348 - { reg: '$v8m8', virtual-reg: '%0' }349 - { reg: '$x10', virtual-reg: '%1' }350 - { reg: '$x11', virtual-reg: '%2' }351 - { reg: '$x12', virtual-reg: '%3' }352 - { reg: '$x13', virtual-reg: '%4' }353frameInfo:354 maxAlignment: 1355machineFunctionInfo: {}356body: |357 bb.0.entry:358 liveins: $v8m8, $x10, $x11, $x12, $x13359 ; CHECK-LABEL: name: consecutive_xsfmm360 ; CHECK: liveins: $v8m8, $x10, $x11, $x12, $x13361 ; CHECK-NEXT: {{ $}}362 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrm8 = COPY $v8m8363 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprnox0 = COPY $x10364 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gprnox0 = COPY $x11365 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gprnox0 = COPY $x12366 ; CHECK-NEXT: dead [[COPY4:%[0-9]+]]:gprnox0 = COPY $x13367 ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY2]], 1032 /* e16, w2 */, implicit-def $vl, implicit-def $vtype368 ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTM [[COPY1]], 4, 2, implicit-def $vtype, implicit $vtype369 ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTK [[COPY3]], 4, 2, implicit-def $vtype, implicit $vtype370 ; CHECK-NEXT: PseudoSF_MM_F_F $t2, [[COPY]], [[COPY]], 7, $noreg, $noreg, $noreg, 4, 2, implicit $frm, implicit $vl, implicit $vtype371 ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY3]], 520 /* e16, w1 */, implicit-def $vl, implicit-def $vtype372 ; CHECK-NEXT: PseudoSF_VSTE16 [[COPY1]], [[COPY2]], $noreg, 4, 1, implicit $vl, implicit $vtype373 ; CHECK-NEXT: PseudoRET374 %0:vrm8 = COPY $v8m8375 %1:gprnox0 = COPY $x10376 %2:gprnox0 = COPY $x11377 %3:gprnox0 = COPY $x12378 %4:gprnox0 = COPY $x13379 PseudoSF_MM_F_F $t2, %0:vrm8, %0:vrm8, 7, %1:gprnox0, %2:gprnox0, %3:gprnox0, 4, 2, implicit $frm380 PseudoSF_VSTE16 %1:gprnox0, %2:gprnox0, %3:gprnox0, 4, 1381 PseudoRET382...383---384name: vsettnt_max385alignment: 4386tracksRegLiveness: true387registers:388 - { id: 0, class: gprnox0 }389liveins:390 - { reg: '$x10', virtual-reg: '%0' }391frameInfo:392 maxAlignment: 1393machineFunctionInfo: {}394body: |395 bb.0.entry:396 liveins: $x10397 ; CHECK-LABEL: name: vsettnt_max398 ; CHECK: liveins: $x10399 ; CHECK-NEXT: {{ $}}400 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x10401 ; CHECK-NEXT: dead [[PseudoSF_VSETTNTX0_:%[0-9]+]]:gprnox0 = PseudoSF_VSETTNTX0 killed $x0, 520 /* e16, w1 */, implicit-def $vl, implicit-def $vtype402 ; CHECK-NEXT: dead [[PseudoSF_VSETTK:%[0-9]+]]:gprnox0 = PseudoSF_VSETTK [[COPY]], 4, 1, implicit-def $vtype, implicit $vtype, implicit $vtype403 ; CHECK-NEXT: dead [[PseudoSF_VSETTNTX0_1:%[0-9]+]]:gprnox0 = PseudoSF_VSETTNTX0 $x0, 520 /* e16, w1 */, implicit-def $vl, implicit-def $vtype, implicit $vtype404 ; CHECK-NEXT: [[PseudoSF_VSETTM:%[0-9]+]]:gprnox0 = PseudoSF_VSETTM [[COPY]], 4, 1, implicit-def $vtype, implicit $vtype, implicit $vtype405 ; CHECK-NEXT: $x10 = COPY [[PseudoSF_VSETTM]]406 ; CHECK-NEXT: PseudoRET implicit $x10407 %0:gprnox0 = COPY $x10408 %1:gprnox0 = PseudoSF_VSETTK %0:gprnox0, 4, 1, implicit-def $vtype, implicit $vtype409 %2:gprnox0 = PseudoSF_VSETTNTX0 $x0, 520, implicit-def $vl, implicit-def $vtype, implicit $vtype410 %3:gprnox0 = PseudoSF_VSETTM %0:gprnox0, 4, 1, implicit-def $vtype, implicit $vtype411 $x10 = COPY %3:gprnox0412 PseudoRET implicit $x10413...414---415name: single_vsettm416alignment: 4417tracksRegLiveness: true418registers:419 - { id: 0, class: gprnox0 }420liveins:421 - { reg: '$x10', virtual-reg: '%0' }422frameInfo:423 maxAlignment: 1424machineFunctionInfo: {}425body: |426 bb.0.entry:427 liveins: $x10428 ; CHECK-LABEL: name: single_vsettm429 ; CHECK: liveins: $x10430 ; CHECK-NEXT: {{ $}}431 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x10432 ; CHECK-NEXT: dead [[PseudoSF_VSETTNTX0_:%[0-9]+]]:gprnox0 = PseudoSF_VSETTNTX0 killed $x0, 520 /* e16, w1 */, implicit-def $vl, implicit-def $vtype433 ; CHECK-NEXT: [[PseudoSF_VSETTM:%[0-9]+]]:gprnox0 = PseudoSF_VSETTM [[COPY]], 4, 1, implicit-def $vtype, implicit $vtype, implicit $vtype434 ; CHECK-NEXT: $x10 = COPY [[PseudoSF_VSETTM]]435 ; CHECK-NEXT: PseudoRET implicit $x10436 %0:gprnox0 = COPY $x10437 %1:gprnox0 = PseudoSF_VSETTM %0:gprnox0, 4, 1, implicit-def $vtype, implicit $vtype438 $x10 = COPY %1:gprnox0439 PseudoRET implicit $x10440...441---442name: single_vsettn443alignment: 4444tracksRegLiveness: true445registers:446 - { id: 0, class: gprnox0 }447liveins:448 - { reg: '$x10', virtual-reg: '%0' }449frameInfo:450 maxAlignment: 1451machineFunctionInfo: {}452body: |453 bb.0.entry:454 liveins: $x10455 ; CHECK-LABEL: name: single_vsettn456 ; CHECK: liveins: $x10457 ; CHECK-NEXT: {{ $}}458 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x10459 ; CHECK-NEXT: [[PseudoSF_VSETTNT:%[0-9]+]]:gprnox0 = PseudoSF_VSETTNT [[COPY]], 520 /* e16, w1 */, implicit-def $vl, implicit-def $vtype, implicit $vtype460 ; CHECK-NEXT: $x10 = COPY [[PseudoSF_VSETTNT]]461 ; CHECK-NEXT: PseudoRET implicit $x10462 %0:gprnox0 = COPY $x10463 %1:gprnox0 = PseudoSF_VSETTNT %0:gprnox0, 520, implicit-def $vl, implicit-def $vtype, implicit $vtype464 $x10 = COPY %1:gprnox0465 PseudoRET implicit $x10466...467---468name: single_vsettk469alignment: 4470tracksRegLiveness: true471registers:472 - { id: 0, class: gprnox0 }473liveins:474 - { reg: '$x10', virtual-reg: '%0' }475frameInfo:476 maxAlignment: 1477machineFunctionInfo: {}478body: |479 bb.0.entry:480 liveins: $x10481 ; CHECK-LABEL: name: single_vsettk482 ; CHECK: liveins: $x10483 ; CHECK-NEXT: {{ $}}484 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x10485 ; CHECK-NEXT: dead [[PseudoSF_VSETTNTX0_:%[0-9]+]]:gprnox0 = PseudoSF_VSETTNTX0 killed $x0, 520 /* e16, w1 */, implicit-def $vl, implicit-def $vtype486 ; CHECK-NEXT: [[PseudoSF_VSETTK:%[0-9]+]]:gprnox0 = PseudoSF_VSETTK [[COPY]], 4, 1, implicit-def $vtype, implicit $vtype, implicit $vtype487 ; CHECK-NEXT: $x10 = COPY [[PseudoSF_VSETTK]]488 ; CHECK-NEXT: PseudoRET implicit $x10489 %0:gprnox0 = COPY $x10490 %1:gprnox0 = PseudoSF_VSETTK %0:gprnox0, 4, 1, implicit-def $vtype, implicit $vtype491 $x10 = COPY %1:gprnox0492 PseudoRET implicit $x10493...494---495name: sf_vtzero496alignment: 4497tracksRegLiveness: true498registers:499 - { id: 0, class: gprnox0 }500 - { id: 1, class: gprnox0 }501liveins:502 - { reg: '$x10', virtual-reg: '%0' }503 - { reg: '$x11', virtual-reg: '%1' }504frameInfo:505 maxAlignment: 1506machineFunctionInfo: {}507body: |508 bb.0.entry:509 liveins: $x10, $x11510 ; CHECK-LABEL: name: sf_vtzero511 ; CHECK: liveins: $x10, $x11512 ; CHECK-NEXT: {{ $}}513 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x10514 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprnox0 = COPY $x11515 ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY1]], 1536 /* e8, w4 */, implicit-def $vl, implicit-def $vtype516 ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTM [[COPY]], 3, 3, implicit-def $vtype, implicit $vtype517 ; CHECK-NEXT: PseudoSF_VTZERO_T $t1, $noreg, $noreg, 3, 4, implicit $vl, implicit $vtype518 ; CHECK-NEXT: PseudoRET519 %0:gprnox0 = COPY $x10520 %1:gprnox0 = COPY $x11521 PseudoSF_VTZERO_T $t1, %0:gprnox0, %1:gprnox0, 3, 4522 PseudoRET523...524