99 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \3; RUN: -mattr=+zvfh -mattr=+zvfbfmin -mattr=+xsfmmbase \4; RUN: -mattr=+xsfmm32a -mattr=+xsfmm32a8f -mattr=+xsfmm32a4i -mattr=+xsfmm64a64f \5; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK6; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \7; RUN: -mattr=+zvfh -mattr=+zvfbfmin -mattr=+xsfmmbase \8; RUN: -mattr=+zvfbfmin -mattr=+xsfmmbase \9; RUN: -mattr=+xsfmm32a -mattr=+xsfmm32a8f -mattr=+xsfmm32a4i -mattr=+xsfmm64a64f \10; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK11 12define <vscale x 32 x bfloat> @test_sf_vtmv_v_t_bf16m8(iXLen %tss, iXLen %vl) {13; CHECK-LABEL: test_sf_vtmv_v_t_bf16m8:14; CHECK: # %bb.0: # %entry15; CHECK-NEXT: sf.vsettnt zero, a1, e16, w116; CHECK-NEXT: sf.vtmv.v.t v8, a017; CHECK-NEXT: ret18 entry:19 %0 = call <vscale x 32 x bfloat> @llvm.riscv.sf.vtmv.v.t.nxv32bf16.iXLen(iXLen %tss, iXLen %vl)20 ret <vscale x 32 x bfloat> %021}22 23define <vscale x 32 x half> @test_sf_vtmv_v_t_f16(iXLen %tss, iXLen %vl) {24; CHECK-LABEL: test_sf_vtmv_v_t_f16:25; CHECK: # %bb.0: # %entry26; CHECK-NEXT: sf.vsettnt zero, a1, e16, w127; CHECK-NEXT: sf.vtmv.v.t v8, a028; CHECK-NEXT: ret29 entry:30 %0 = call <vscale x 32 x half> @llvm.riscv.sf.vtmv.v.t.nxv32f16.iXLen(iXLen %tss, iXLen %vl)31 ret <vscale x 32 x half> %032}33 34define <vscale x 16 x float> @test_sf_vtmv_v_t_f32(iXLen %tss, iXLen %vl) {35; CHECK-LABEL: test_sf_vtmv_v_t_f32:36; CHECK: # %bb.0: # %entry37; CHECK-NEXT: sf.vsettnt zero, a1, e32, w138; CHECK-NEXT: sf.vtmv.v.t v8, a039; CHECK-NEXT: ret40 entry:41 %0 = call <vscale x 16 x float> @llvm.riscv.sf.vtmv.v.t.nxv16f32.iXLen(iXLen %tss, iXLen %vl)42 ret <vscale x 16 x float> %043}44 45define <vscale x 8 x double> @test_sf_vtmv_v_t_f64(iXLen %tss, iXLen %vl) {46; CHECK-LABEL: test_sf_vtmv_v_t_f64:47; CHECK: # %bb.0: # %entry48; CHECK-NEXT: sf.vsettnt zero, a1, e64, w149; CHECK-NEXT: sf.vtmv.v.t v8, a050; CHECK-NEXT: ret51 entry:52 %0 = call <vscale x 8 x double> @llvm.riscv.sf.vtmv.v.t.nxv8f64.iXLen(iXLen %tss, iXLen %vl)53 ret <vscale x 8 x double> %054}55 56define <vscale x 64 x i8> @test_sf_vtmv_v_t_i8(iXLen %tss, iXLen %vl) {57; CHECK-LABEL: test_sf_vtmv_v_t_i8:58; CHECK: # %bb.0: # %entry59; CHECK-NEXT: sf.vsettnt zero, a1, e8, w160; CHECK-NEXT: sf.vtmv.v.t v8, a061; CHECK-NEXT: ret62 entry:63 %0 = call <vscale x 64 x i8> @llvm.riscv.sf.vtmv.v.t.nxv64i8.iXLen(iXLen %tss, iXLen %vl)64 ret <vscale x 64 x i8> %065}66 67define <vscale x 32 x i16> @test_sf_vtmv_v_t_i16(iXLen %tss, iXLen %vl) {68; CHECK-LABEL: test_sf_vtmv_v_t_i16:69; CHECK: # %bb.0: # %entry70; CHECK-NEXT: sf.vsettnt zero, a1, e16, w171; CHECK-NEXT: sf.vtmv.v.t v8, a072; CHECK-NEXT: ret73 entry:74 %0 = call <vscale x 32 x i16> @llvm.riscv.sf.vtmv.v.t.nxv32i16.iXLen(iXLen %tss, iXLen %vl)75 ret <vscale x 32 x i16> %076}77 78define <vscale x 16 x i32> @test_sf_vtmv_v_t_i32(iXLen %tss, iXLen %vl) {79; CHECK-LABEL: test_sf_vtmv_v_t_i32:80; CHECK: # %bb.0: # %entry81; CHECK-NEXT: sf.vsettnt zero, a1, e32, w182; CHECK-NEXT: sf.vtmv.v.t v8, a083; CHECK-NEXT: ret84 entry:85 %0 = call <vscale x 16 x i32> @llvm.riscv.sf.vtmv.v.t.nxv16i32.iXLen(iXLen %tss, iXLen %vl)86 ret <vscale x 16 x i32> %087}88 89define <vscale x 8 x i64> @test_sf_vtmv_v_t_i64(iXLen %tss, iXLen %vl) {90; CHECK-LABEL: test_sf_vtmv_v_t_i64:91; CHECK: # %bb.0: # %entry92; CHECK-NEXT: sf.vsettnt zero, a1, e64, w193; CHECK-NEXT: sf.vtmv.v.t v8, a094; CHECK-NEXT: ret95 entry:96 %0 = call <vscale x 8 x i64> @llvm.riscv.sf.vtmv.v.t.nxv8i64.iXLen(iXLen %tss, iXLen %vl)97 ret <vscale x 8 x i64> %098}99