88 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK3 4define i32 @splat_vector_split_i64() {5; CHECK-LABEL: splat_vector_split_i64:6; CHECK: # %bb.0:7; CHECK-NEXT: addi sp, sp, -168; CHECK-NEXT: .cfi_def_cfa_offset 169; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma10; CHECK-NEXT: vmv.v.i v10, 311; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma12; CHECK-NEXT: vmv.v.i v8, 013; CHECK-NEXT: lui a1, 104448014; CHECK-NEXT: li a2, 5615; CHECK-NEXT: li a3, 4016; CHECK-NEXT: lui a4, 1617; CHECK-NEXT: lui a0, 408018; CHECK-NEXT: addi a5, sp, 819; CHECK-NEXT: sw a1, 8(sp)20; CHECK-NEXT: sw zero, 12(sp)21; CHECK-NEXT: addi a1, a4, -25622; CHECK-NEXT: vsetivli zero, 4, e64, m2, tu, ma23; CHECK-NEXT: vslideup.vi v8, v10, 324; CHECK-NEXT: vsetvli a4, zero, e64, m2, ta, ma25; CHECK-NEXT: vlse64.v v10, (a5), zero26; CHECK-NEXT: vsrl.vx v12, v8, a227; CHECK-NEXT: vsrl.vx v14, v8, a328; CHECK-NEXT: vsrl.vi v16, v8, 2429; CHECK-NEXT: vsll.vx v18, v8, a230; CHECK-NEXT: vand.vx v14, v14, a131; CHECK-NEXT: vor.vv v14, v14, v1232; CHECK-NEXT: vand.vx v12, v8, a133; CHECK-NEXT: vsll.vx v12, v12, a334; CHECK-NEXT: vor.vv v12, v18, v1235; CHECK-NEXT: vsrl.vi v18, v8, 836; CHECK-NEXT: vand.vx v16, v16, a037; CHECK-NEXT: vand.vv v18, v18, v1038; CHECK-NEXT: vor.vv v16, v18, v1639; CHECK-NEXT: lui a1, 6168140; CHECK-NEXT: lui a2, 20971541; CHECK-NEXT: lui a3, 34952542; CHECK-NEXT: addi a1, a1, -24143; CHECK-NEXT: addi a2, a2, 81944; CHECK-NEXT: addi a3, a3, 136545; CHECK-NEXT: vor.vv v14, v16, v1446; CHECK-NEXT: vsetvli a4, zero, e32, m2, ta, ma47; CHECK-NEXT: vmv.v.x v16, a148; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma49; CHECK-NEXT: vand.vv v10, v8, v1050; CHECK-NEXT: vand.vx v8, v8, a051; CHECK-NEXT: vsll.vi v8, v8, 2452; CHECK-NEXT: vsll.vi v10, v10, 853; CHECK-NEXT: vor.vv v8, v8, v1054; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma55; CHECK-NEXT: vmv.v.x v10, a256; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma57; CHECK-NEXT: vor.vv v8, v12, v858; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma59; CHECK-NEXT: vmv.v.x v12, a360; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma61; CHECK-NEXT: vor.vv v8, v8, v1462; CHECK-NEXT: vsrl.vi v14, v8, 463; CHECK-NEXT: vand.vv v8, v8, v1664; CHECK-NEXT: vand.vv v14, v14, v1665; CHECK-NEXT: vsll.vi v8, v8, 466; CHECK-NEXT: vor.vv v8, v14, v867; CHECK-NEXT: vsrl.vi v14, v8, 268; CHECK-NEXT: vand.vv v8, v8, v1069; CHECK-NEXT: vand.vv v10, v14, v1070; CHECK-NEXT: vsll.vi v8, v8, 271; CHECK-NEXT: vor.vv v8, v10, v872; CHECK-NEXT: vsrl.vi v10, v8, 173; CHECK-NEXT: vand.vv v8, v8, v1274; CHECK-NEXT: vand.vv v10, v10, v1275; CHECK-NEXT: vadd.vv v8, v8, v876; CHECK-NEXT: vor.vv v8, v10, v877; CHECK-NEXT: vslidedown.vi v8, v8, 378; CHECK-NEXT: vmv.x.s a0, v879; CHECK-NEXT: addi sp, sp, 1680; CHECK-NEXT: .cfi_def_cfa_offset 081; CHECK-NEXT: ret82 %1 = insertelement <vscale x 2 x i64> zeroinitializer, i64 3, i64 383 %2 = tail call <vscale x 2 x i64> @llvm.bitreverse.nxv2i64(<vscale x 2 x i64> %1)84 %3 = extractelement <vscale x 2 x i64> %2, i32 385 %4 = trunc i64 %3 to i3286 ret i32 %487}88