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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -O3 -mtriple=riscv64 -mattr=+v < %s | FileCheck %s3 4define void @constant_splat_fixed(ptr %p) {5; CHECK-LABEL: constant_splat_fixed:6; CHECK: # %bb.0:7; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma8; CHECK-NEXT: vmv.v.i v8, 09; CHECK-NEXT: vse32.v v8, (a0)10; CHECK-NEXT: ret11 store <4 x i32> zeroinitializer, ptr %p12 ret void13}14 15define void @constant_splat_scalable(ptr %p) {16; CHECK-LABEL: constant_splat_scalable:17; CHECK: # %bb.0:18; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma19; CHECK-NEXT: vmv.v.i v8, 020; CHECK-NEXT: vse32.v v8, (a0)21; CHECK-NEXT: ret22 store <vscale x 1 x i32> zeroinitializer, ptr %p23 ret void24}25 26; FIXME: We should be able to use the earlier splat of zero here27; since VLMAX >= 4.28define void @constant_splat_scalable_then_fixed(ptr %p, ptr %p2) {29; CHECK-LABEL: constant_splat_scalable_then_fixed:30; CHECK: # %bb.0:31; CHECK-NEXT: vsetvli a2, zero, e32, mf2, ta, ma32; CHECK-NEXT: vmv.v.i v8, 033; CHECK-NEXT: vse32.v v8, (a0)34; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma35; CHECK-NEXT: vmv.v.i v8, 036; CHECK-NEXT: vse32.v v8, (a1)37; CHECK-NEXT: ret38 store <vscale x 1 x i32> zeroinitializer, ptr %p39 store <4 x i32> zeroinitializer, ptr %p240 ret void41}42 43; We could widen the first splat to VLMAX, but this might not44; be generally profitable.45define void @constant_splat_fixed_then_scalable(ptr %p, ptr %p2) {46; CHECK-LABEL: constant_splat_fixed_then_scalable:47; CHECK: # %bb.0:48; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma49; CHECK-NEXT: vmv.v.i v8, 050; CHECK-NEXT: vse32.v v8, (a1)51; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma52; CHECK-NEXT: vmv.v.i v8, 053; CHECK-NEXT: vse32.v v8, (a0)54; CHECK-NEXT: ret55 store <4 x i32> zeroinitializer, ptr %p256 store <vscale x 1 x i32> zeroinitializer, ptr %p57 ret void58}59 60define void @splat_scalable(ptr %p, i32 %v) {61; CHECK-LABEL: splat_scalable:62; CHECK: # %bb.0:63; CHECK-NEXT: vsetvli a2, zero, e32, mf2, ta, ma64; CHECK-NEXT: vmv.v.x v8, a165; CHECK-NEXT: vse32.v v8, (a0)66; CHECK-NEXT: ret67 %elt.head = insertelement <vscale x 1 x i32> poison, i32 %v, i32 068 %splat = shufflevector <vscale x 1 x i32> %elt.head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer69 store <vscale x 1 x i32> %splat, ptr %p70 ret void71}72 73define void @splat_fixed(ptr %p, i32 %v) {74; CHECK-LABEL: splat_fixed:75; CHECK: # %bb.0:76; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma77; CHECK-NEXT: vmv.v.x v8, a178; CHECK-NEXT: vse32.v v8, (a0)79; CHECK-NEXT: ret80 %elt.head = insertelement <4 x i32> poison, i32 %v, i32 081 %splat = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer82 store <4 x i32> %splat, ptr %p83 ret void84}85 86; FIXME: We should reschedule the first splat to reduce the need87; for toggling VL88define void @mixed_splats1(ptr %p, i32 %v) {89; CHECK-LABEL: mixed_splats1:90; CHECK: # %bb.0:91; CHECK-NEXT: vsetvli a2, zero, e32, mf2, ta, ma92; CHECK-NEXT: vmv.v.x v8, a193; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma94; CHECK-NEXT: vmv.v.i v9, 095; CHECK-NEXT: vse32.v v9, (a0)96; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma97; CHECK-NEXT: vse32.v v8, (a0)98; CHECK-NEXT: ret99 %elt.head = insertelement <vscale x 1 x i32> poison, i32 %v, i32 0100 %splat = shufflevector <vscale x 1 x i32> %elt.head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer101 102 store <4 x i32> zeroinitializer, ptr %p103 store <vscale x 1 x i32> %splat, ptr %p104 ret void105}106 107define void @mixed_splats2(ptr %p, i32 %v) {108; CHECK-LABEL: mixed_splats2:109; CHECK: # %bb.0:110; CHECK-NEXT: vsetvli a2, zero, e32, mf2, ta, ma111; CHECK-NEXT: vmv.v.x v8, a1112; CHECK-NEXT: vse32.v v8, (a0)113; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma114; CHECK-NEXT: vmv.v.i v8, 0115; CHECK-NEXT: vse32.v v8, (a0)116; CHECK-NEXT: ret117 %elt.head = insertelement <vscale x 1 x i32> poison, i32 %v, i32 0118 %splat = shufflevector <vscale x 1 x i32> %elt.head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer119 120 store <vscale x 1 x i32> %splat, ptr %p121 store <4 x i32> zeroinitializer, ptr %p122 ret void123}124 125define void @extract_vector(ptr %p, i32 %v) {126; CHECK-LABEL: extract_vector:127; CHECK: # %bb.0:128; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma129; CHECK-NEXT: vmv.v.x v8, a1130; CHECK-NEXT: vse32.v v8, (a0)131; CHECK-NEXT: ret132 %elt.head = insertelement <vscale x 1 x i32> poison, i32 %v, i32 0133 %splat = shufflevector <vscale x 1 x i32> %elt.head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer134 135 %fv = call <4 x i32> @llvm.vector.extract.v4i32.nxv1132(<vscale x 1 x i32> %splat, i64 0)136 store <4 x i32> %fv, ptr %p137 ret void138}139 140define void @extract_vector_multiuse1(ptr %p, ptr %p2, i32 %v) {141; CHECK-LABEL: extract_vector_multiuse1:142; CHECK: # %bb.0:143; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma144; CHECK-NEXT: vmv.v.x v8, a2145; CHECK-NEXT: vse32.v v8, (a0)146; CHECK-NEXT: vse32.v v8, (a1)147; CHECK-NEXT: ret148 %elt.head = insertelement <vscale x 1 x i32> poison, i32 %v, i32 0149 %splat = shufflevector <vscale x 1 x i32> %elt.head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer150 151 %fv = call <4 x i32> @llvm.vector.extract.v4i32.nxv1132(<vscale x 1 x i32> %splat, i64 0)152 store <4 x i32> %fv, ptr %p153 store <4 x i32> %fv, ptr %p2154 ret void155}156 157define <vscale x 1 x i32> @extract_vector_multiuse2(ptr %p, ptr %p2, i32 %v) {158; CHECK-LABEL: extract_vector_multiuse2:159; CHECK: # %bb.0:160; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma161; CHECK-NEXT: vmv.v.x v8, a2162; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma163; CHECK-NEXT: vse32.v v8, (a0)164; CHECK-NEXT: ret165 %elt.head = insertelement <vscale x 1 x i32> poison, i32 %v, i32 0166 %splat = shufflevector <vscale x 1 x i32> %elt.head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer167 168 %fv = call <4 x i32> @llvm.vector.extract.v4i32.nxv1132(<vscale x 1 x i32> %splat, i64 0)169 store <4 x i32> %fv, ptr %p170 ret <vscale x 1 x i32> %splat171}172 173define void @extract_vector_mixed1(ptr %p, ptr %p2, i32 %v) {174; CHECK-LABEL: extract_vector_mixed1:175; CHECK: # %bb.0:176; CHECK-NEXT: vsetvli a3, zero, e32, mf2, ta, ma177; CHECK-NEXT: vmv.v.x v8, a2178; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma179; CHECK-NEXT: vse32.v v8, (a0)180; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma181; CHECK-NEXT: vse32.v v8, (a1)182; CHECK-NEXT: ret183 %elt.head = insertelement <vscale x 1 x i32> poison, i32 %v, i32 0184 %splat = shufflevector <vscale x 1 x i32> %elt.head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer185 186 %fv = call <4 x i32> @llvm.vector.extract.v4i32.nxv1132(<vscale x 1 x i32> %splat, i64 0)187 188 store <4 x i32> %fv, ptr %p189 store <vscale x 1 x i32> %splat, ptr %p2190 ret void191}192 193define void @extract_vector_mixed2(ptr %p, ptr %p2, i32 %v) {194; CHECK-LABEL: extract_vector_mixed2:195; CHECK: # %bb.0:196; CHECK-NEXT: vsetvli a3, zero, e32, mf2, ta, ma197; CHECK-NEXT: vmv.v.x v8, a2198; CHECK-NEXT: vse32.v v8, (a0)199; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma200; CHECK-NEXT: vse32.v v8, (a1)201; CHECK-NEXT: ret202 %elt.head = insertelement <vscale x 1 x i32> poison, i32 %v, i32 0203 %splat = shufflevector <vscale x 1 x i32> %elt.head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer204 store <vscale x 1 x i32> %splat, ptr %p205 206 %fv = call <4 x i32> @llvm.vector.extract.v4i32.nxv1132(<vscale x 1 x i32> %splat, i64 0)207 store <4 x i32> %fv, ptr %p2208 ret void209}210 211define void @extract_vector_mixed3(ptr %p, ptr %p2, i32 %v) {212; CHECK-LABEL: extract_vector_mixed3:213; CHECK: # %bb.0:214; CHECK-NEXT: vsetvli a3, zero, e32, mf2, ta, ma215; CHECK-NEXT: vmv.v.x v8, a2216; CHECK-NEXT: vse32.v v8, (a0)217; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma218; CHECK-NEXT: vse32.v v8, (a1)219; CHECK-NEXT: ret220 %elt.head = insertelement <vscale x 1 x i32> poison, i32 %v, i32 0221 %splat = shufflevector <vscale x 1 x i32> %elt.head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer222 %fv = call <4 x i32> @llvm.vector.extract.v4i32.nxv1132(<vscale x 1 x i32> %splat, i64 0)223 224 store <vscale x 1 x i32> %splat, ptr %p225 store <4 x i32> %fv, ptr %p2226 ret void227}228 229