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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=riscv64 -mattr=+v | FileCheck %s3 4define <2 x i64> @vec_v2i64(<2 x i64> %x, <2 x i64> %y) nounwind {5; CHECK-LABEL: vec_v2i64:6; CHECK: # %bb.0:7; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma8; CHECK-NEXT: vmsle.vi v0, v8, -19; CHECK-NEXT: li a0, -110; CHECK-NEXT: srli a1, a0, 111; CHECK-NEXT: slli a0, a0, 6312; CHECK-NEXT: vmv.v.x v10, a113; CHECK-NEXT: vmerge.vxm v10, v10, a0, v014; CHECK-NEXT: vsll.vv v11, v8, v915; CHECK-NEXT: vsra.vv v9, v11, v916; CHECK-NEXT: vmsne.vv v0, v8, v917; CHECK-NEXT: vmerge.vvm v8, v11, v10, v018; CHECK-NEXT: ret19 %tmp = call <2 x i64> @llvm.sshl.sat.v2i64(<2 x i64> %x, <2 x i64> %y)20 ret <2 x i64> %tmp21}22 23define <4 x i32> @vec_v4i32(<4 x i32> %x, <4 x i32> %y) nounwind {24; CHECK-LABEL: vec_v4i32:25; CHECK: # %bb.0:26; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma27; CHECK-NEXT: vmsle.vi v0, v8, -128; CHECK-NEXT: lui a0, 52428829; CHECK-NEXT: addi a1, a0, -130; CHECK-NEXT: vmv.v.x v10, a131; CHECK-NEXT: vmerge.vxm v10, v10, a0, v032; CHECK-NEXT: vsll.vv v11, v8, v933; CHECK-NEXT: vsra.vv v9, v11, v934; CHECK-NEXT: vmsne.vv v0, v8, v935; CHECK-NEXT: vmerge.vvm v8, v11, v10, v036; CHECK-NEXT: ret37 %tmp = call <4 x i32> @llvm.sshl.sat.v4i32(<4 x i32> %x, <4 x i32> %y)38 ret <4 x i32> %tmp39}40 41define <8 x i16> @vec_v8i16(<8 x i16> %x, <8 x i16> %y) nounwind {42; CHECK-LABEL: vec_v8i16:43; CHECK: # %bb.0:44; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma45; CHECK-NEXT: vmsle.vi v0, v8, -146; CHECK-NEXT: lui a0, 847; CHECK-NEXT: addi a1, a0, -148; CHECK-NEXT: vmv.v.x v10, a149; CHECK-NEXT: vmerge.vxm v10, v10, a0, v050; CHECK-NEXT: vsll.vv v11, v8, v951; CHECK-NEXT: vsra.vv v9, v11, v952; CHECK-NEXT: vmsne.vv v0, v8, v953; CHECK-NEXT: vmerge.vvm v8, v11, v10, v054; CHECK-NEXT: ret55 %tmp = call <8 x i16> @llvm.sshl.sat.v8i16(<8 x i16> %x, <8 x i16> %y)56 ret <8 x i16> %tmp57}58 59define <16 x i8> @vec_v16i8(<16 x i8> %x, <16 x i8> %y) nounwind {60; CHECK-LABEL: vec_v16i8:61; CHECK: # %bb.0:62; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma63; CHECK-NEXT: vmsle.vi v0, v8, -164; CHECK-NEXT: li a0, 12765; CHECK-NEXT: vmv.v.x v10, a066; CHECK-NEXT: li a0, 12867; CHECK-NEXT: vmerge.vxm v10, v10, a0, v068; CHECK-NEXT: vsll.vv v11, v8, v969; CHECK-NEXT: vsra.vv v9, v11, v970; CHECK-NEXT: vmsne.vv v0, v8, v971; CHECK-NEXT: vmerge.vvm v8, v11, v10, v072; CHECK-NEXT: ret73 %tmp = call <16 x i8> @llvm.sshl.sat.v16i8(<16 x i8> %x, <16 x i8> %y)74 ret <16 x i8> %tmp75}76 77define <vscale x 2 x i64> @vec_nxv2i64(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y) nounwind {78; CHECK-LABEL: vec_nxv2i64:79; CHECK: # %bb.0:80; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma81; CHECK-NEXT: vmsle.vi v0, v8, -182; CHECK-NEXT: li a0, -183; CHECK-NEXT: srli a1, a0, 184; CHECK-NEXT: slli a0, a0, 6385; CHECK-NEXT: vmv.v.x v12, a186; CHECK-NEXT: vmerge.vxm v12, v12, a0, v087; CHECK-NEXT: vsll.vv v14, v8, v1088; CHECK-NEXT: vsra.vv v10, v14, v1089; CHECK-NEXT: vmsne.vv v0, v8, v1090; CHECK-NEXT: vmerge.vvm v8, v14, v12, v091; CHECK-NEXT: ret92 %tmp = call <vscale x 2 x i64> @llvm.sshl.sat.nxv2i64(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y)93 ret <vscale x 2 x i64> %tmp94}95 96define <vscale x 4 x i32> @vec_nxv4i32(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y) nounwind {97; CHECK-LABEL: vec_nxv4i32:98; CHECK: # %bb.0:99; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma100; CHECK-NEXT: vmsle.vi v0, v8, -1101; CHECK-NEXT: lui a0, 524288102; CHECK-NEXT: addi a1, a0, -1103; CHECK-NEXT: vmv.v.x v12, a1104; CHECK-NEXT: vmerge.vxm v12, v12, a0, v0105; CHECK-NEXT: vsll.vv v14, v8, v10106; CHECK-NEXT: vsra.vv v10, v14, v10107; CHECK-NEXT: vmsne.vv v0, v8, v10108; CHECK-NEXT: vmerge.vvm v8, v14, v12, v0109; CHECK-NEXT: ret110 %tmp = call <vscale x 4 x i32> @llvm.sshl.sat.nxv4i32(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y)111 ret <vscale x 4 x i32> %tmp112}113 114define <vscale x 8 x i16> @vec_nxv8i16(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y) nounwind {115; CHECK-LABEL: vec_nxv8i16:116; CHECK: # %bb.0:117; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma118; CHECK-NEXT: vmsle.vi v0, v8, -1119; CHECK-NEXT: lui a0, 8120; CHECK-NEXT: addi a1, a0, -1121; CHECK-NEXT: vmv.v.x v12, a1122; CHECK-NEXT: vmerge.vxm v12, v12, a0, v0123; CHECK-NEXT: vsll.vv v14, v8, v10124; CHECK-NEXT: vsra.vv v10, v14, v10125; CHECK-NEXT: vmsne.vv v0, v8, v10126; CHECK-NEXT: vmerge.vvm v8, v14, v12, v0127; CHECK-NEXT: ret128 %tmp = call <vscale x 8 x i16> @llvm.sshl.sat.nxv8i16(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y)129 ret <vscale x 8 x i16> %tmp130}131 132define <vscale x 16 x i8> @vec_nxv16i8(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y) nounwind {133; CHECK-LABEL: vec_nxv16i8:134; CHECK: # %bb.0:135; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma136; CHECK-NEXT: vmsle.vi v0, v8, -1137; CHECK-NEXT: li a0, 127138; CHECK-NEXT: vmv.v.x v12, a0139; CHECK-NEXT: li a0, 128140; CHECK-NEXT: vmerge.vxm v12, v12, a0, v0141; CHECK-NEXT: vsll.vv v14, v8, v10142; CHECK-NEXT: vsra.vv v10, v14, v10143; CHECK-NEXT: vmsne.vv v0, v8, v10144; CHECK-NEXT: vmerge.vvm v8, v14, v12, v0145; CHECK-NEXT: ret146 %tmp = call <vscale x 16 x i8> @llvm.sshl.sat.nxv16i8(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y)147 ret <vscale x 16 x i8> %tmp148}149