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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zfbfmin,+zvfh,+zvfbfmin -verify-machineinstrs | FileCheck --check-prefixes=CHECK,RV32,ZFMIN %s3; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zfbfmin,+zvfh,+zvfbfmin -verify-machineinstrs | FileCheck --check-prefixes=CHECK,RV64,ZFMIN %s4; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zvfhmin,+zvfbfmin -verify-machineinstrs | FileCheck --check-prefixes=CHECK,RV32,NOZFMIN %s5; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvfhmin,+zvfbfmin -verify-machineinstrs | FileCheck --check-prefixes=CHECK,RV64,NOZFMIN %s6 7define i64 @i64(<vscale x 1 x i64> %v, i1 %c) {8; RV32-LABEL: i64:9; RV32: # %bb.0:10; RV32-NEXT: addi sp, sp, -1611; RV32-NEXT: .cfi_def_cfa_offset 1612; RV32-NEXT: csrr a1, vlenb13; RV32-NEXT: sub sp, sp, a114; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x01, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 1 * vlenb15; RV32-NEXT: addi a1, sp, 1616; RV32-NEXT: vs1r.v v8, (a1) # vscale x 8-byte Folded Spill17; RV32-NEXT: andi a0, a0, 118; RV32-NEXT: #APP19; RV32-NEXT: #NO_APP20; RV32-NEXT: beqz a0, .LBB0_221; RV32-NEXT: # %bb.1: # %truebb22; RV32-NEXT: li a0, 3223; RV32-NEXT: vl1r.v v9, (a1) # vscale x 8-byte Folded Reload24; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma25; RV32-NEXT: vsrl.vx v8, v9, a026; RV32-NEXT: vmv.x.s a1, v827; RV32-NEXT: vmv.x.s a0, v928; RV32-NEXT: j .LBB0_329; RV32-NEXT: .LBB0_2: # %falsebb30; RV32-NEXT: li a1, 031; RV32-NEXT: .LBB0_3: # %falsebb32; RV32-NEXT: csrr a2, vlenb33; RV32-NEXT: add sp, sp, a234; RV32-NEXT: .cfi_def_cfa sp, 1635; RV32-NEXT: addi sp, sp, 1636; RV32-NEXT: .cfi_def_cfa_offset 037; RV32-NEXT: ret38;39; RV64-LABEL: i64:40; RV64: # %bb.0:41; RV64-NEXT: addi sp, sp, -1642; RV64-NEXT: .cfi_def_cfa_offset 1643; RV64-NEXT: csrr a1, vlenb44; RV64-NEXT: sub sp, sp, a145; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x01, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 1 * vlenb46; RV64-NEXT: addi a1, sp, 1647; RV64-NEXT: vs1r.v v8, (a1) # vscale x 8-byte Folded Spill48; RV64-NEXT: andi a0, a0, 149; RV64-NEXT: #APP50; RV64-NEXT: #NO_APP51; RV64-NEXT: beqz a0, .LBB0_252; RV64-NEXT: # %bb.1: # %truebb53; RV64-NEXT: ld a0, 16(sp) # 8-byte Folded Reload54; RV64-NEXT: .LBB0_2: # %falsebb55; RV64-NEXT: csrr a1, vlenb56; RV64-NEXT: add sp, sp, a157; RV64-NEXT: .cfi_def_cfa sp, 1658; RV64-NEXT: addi sp, sp, 1659; RV64-NEXT: .cfi_def_cfa_offset 060; RV64-NEXT: ret61 tail call void asm sideeffect "", "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()62 br i1 %c, label %truebb, label %falsebb63truebb:64 %x = extractelement <vscale x 1 x i64> %v, i32 065 ret i64 %x66falsebb:67 ret i64 068}69 70define i32 @i32(<vscale x 2 x i32> %v, i1 %c) {71; CHECK-LABEL: i32:72; CHECK: # %bb.0:73; CHECK-NEXT: addi sp, sp, -1674; CHECK-NEXT: .cfi_def_cfa_offset 1675; CHECK-NEXT: csrr a1, vlenb76; CHECK-NEXT: sub sp, sp, a177; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x01, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 1 * vlenb78; CHECK-NEXT: addi a1, sp, 1679; CHECK-NEXT: vs1r.v v8, (a1) # vscale x 8-byte Folded Spill80; CHECK-NEXT: andi a0, a0, 181; CHECK-NEXT: #APP82; CHECK-NEXT: #NO_APP83; CHECK-NEXT: beqz a0, .LBB1_284; CHECK-NEXT: # %bb.1: # %truebb85; CHECK-NEXT: lw a0, 16(sp) # 8-byte Folded Reload86; CHECK-NEXT: .LBB1_2: # %falsebb87; CHECK-NEXT: csrr a1, vlenb88; CHECK-NEXT: add sp, sp, a189; CHECK-NEXT: .cfi_def_cfa sp, 1690; CHECK-NEXT: addi sp, sp, 1691; CHECK-NEXT: .cfi_def_cfa_offset 092; CHECK-NEXT: ret93 tail call void asm sideeffect "", "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()94 br i1 %c, label %truebb, label %falsebb95truebb:96 %x = extractelement <vscale x 2 x i32> %v, i32 097 ret i32 %x98falsebb:99 ret i32 0100}101 102define i16 @i16(<vscale x 4 x i16> %v, i1 %c) {103; CHECK-LABEL: i16:104; CHECK: # %bb.0:105; CHECK-NEXT: addi sp, sp, -16106; CHECK-NEXT: .cfi_def_cfa_offset 16107; CHECK-NEXT: csrr a1, vlenb108; CHECK-NEXT: sub sp, sp, a1109; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x01, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 1 * vlenb110; CHECK-NEXT: addi a1, sp, 16111; CHECK-NEXT: vs1r.v v8, (a1) # vscale x 8-byte Folded Spill112; CHECK-NEXT: andi a0, a0, 1113; CHECK-NEXT: #APP114; CHECK-NEXT: #NO_APP115; CHECK-NEXT: beqz a0, .LBB2_2116; CHECK-NEXT: # %bb.1: # %truebb117; CHECK-NEXT: lh a0, 16(sp) # 8-byte Folded Reload118; CHECK-NEXT: .LBB2_2: # %falsebb119; CHECK-NEXT: csrr a1, vlenb120; CHECK-NEXT: add sp, sp, a1121; CHECK-NEXT: .cfi_def_cfa sp, 16122; CHECK-NEXT: addi sp, sp, 16123; CHECK-NEXT: .cfi_def_cfa_offset 0124; CHECK-NEXT: ret125 tail call void asm sideeffect "", "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()126 br i1 %c, label %truebb, label %falsebb127truebb:128 %x = extractelement <vscale x 4 x i16> %v, i32 0129 ret i16 %x130falsebb:131 ret i16 0132}133 134define i8 @i8(<vscale x 8 x i8> %v, i1 %c) {135; CHECK-LABEL: i8:136; CHECK: # %bb.0:137; CHECK-NEXT: addi sp, sp, -16138; CHECK-NEXT: .cfi_def_cfa_offset 16139; CHECK-NEXT: csrr a1, vlenb140; CHECK-NEXT: sub sp, sp, a1141; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x01, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 1 * vlenb142; CHECK-NEXT: addi a1, sp, 16143; CHECK-NEXT: vs1r.v v8, (a1) # vscale x 8-byte Folded Spill144; CHECK-NEXT: andi a0, a0, 1145; CHECK-NEXT: #APP146; CHECK-NEXT: #NO_APP147; CHECK-NEXT: beqz a0, .LBB3_2148; CHECK-NEXT: # %bb.1: # %truebb149; CHECK-NEXT: lb a0, 16(sp) # 8-byte Folded Reload150; CHECK-NEXT: .LBB3_2: # %falsebb151; CHECK-NEXT: csrr a1, vlenb152; CHECK-NEXT: add sp, sp, a1153; CHECK-NEXT: .cfi_def_cfa sp, 16154; CHECK-NEXT: addi sp, sp, 16155; CHECK-NEXT: .cfi_def_cfa_offset 0156; CHECK-NEXT: ret157 tail call void asm sideeffect "", "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()158 br i1 %c, label %truebb, label %falsebb159truebb:160 %x = extractelement <vscale x 8 x i8> %v, i32 0161 ret i8 %x162falsebb:163 ret i8 0164}165 166define double @f64(<vscale x 1 x double> %v, i1 %c) {167; RV32-LABEL: f64:168; RV32: # %bb.0:169; RV32-NEXT: addi sp, sp, -16170; RV32-NEXT: .cfi_def_cfa_offset 16171; RV32-NEXT: csrr a1, vlenb172; RV32-NEXT: sub sp, sp, a1173; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x01, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 1 * vlenb174; RV32-NEXT: addi a1, sp, 16175; RV32-NEXT: vs1r.v v8, (a1) # vscale x 8-byte Folded Spill176; RV32-NEXT: andi a0, a0, 1177; RV32-NEXT: #APP178; RV32-NEXT: #NO_APP179; RV32-NEXT: beqz a0, .LBB4_2180; RV32-NEXT: # %bb.1: # %truebb181; RV32-NEXT: fld fa0, 16(sp) # 8-byte Folded Reload182; RV32-NEXT: j .LBB4_3183; RV32-NEXT: .LBB4_2: # %falsebb184; RV32-NEXT: fcvt.d.w fa0, zero185; RV32-NEXT: .LBB4_3: # %falsebb186; RV32-NEXT: csrr a0, vlenb187; RV32-NEXT: add sp, sp, a0188; RV32-NEXT: .cfi_def_cfa sp, 16189; RV32-NEXT: addi sp, sp, 16190; RV32-NEXT: .cfi_def_cfa_offset 0191; RV32-NEXT: ret192;193; RV64-LABEL: f64:194; RV64: # %bb.0:195; RV64-NEXT: addi sp, sp, -16196; RV64-NEXT: .cfi_def_cfa_offset 16197; RV64-NEXT: csrr a1, vlenb198; RV64-NEXT: sub sp, sp, a1199; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x01, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 1 * vlenb200; RV64-NEXT: addi a1, sp, 16201; RV64-NEXT: vs1r.v v8, (a1) # vscale x 8-byte Folded Spill202; RV64-NEXT: andi a0, a0, 1203; RV64-NEXT: #APP204; RV64-NEXT: #NO_APP205; RV64-NEXT: beqz a0, .LBB4_2206; RV64-NEXT: # %bb.1: # %truebb207; RV64-NEXT: fld fa0, 16(sp) # 8-byte Folded Reload208; RV64-NEXT: j .LBB4_3209; RV64-NEXT: .LBB4_2: # %falsebb210; RV64-NEXT: fmv.d.x fa0, zero211; RV64-NEXT: .LBB4_3: # %falsebb212; RV64-NEXT: csrr a0, vlenb213; RV64-NEXT: add sp, sp, a0214; RV64-NEXT: .cfi_def_cfa sp, 16215; RV64-NEXT: addi sp, sp, 16216; RV64-NEXT: .cfi_def_cfa_offset 0217; RV64-NEXT: ret218 tail call void asm sideeffect "", "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()219 br i1 %c, label %truebb, label %falsebb220truebb:221 %x = extractelement <vscale x 1 x double> %v, i32 0222 ret double %x223falsebb:224 ret double 0.0225}226 227define float @f32(<vscale x 2 x float> %v, i1 %c) {228; CHECK-LABEL: f32:229; CHECK: # %bb.0:230; CHECK-NEXT: addi sp, sp, -16231; CHECK-NEXT: .cfi_def_cfa_offset 16232; CHECK-NEXT: csrr a1, vlenb233; CHECK-NEXT: sub sp, sp, a1234; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x01, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 1 * vlenb235; CHECK-NEXT: addi a1, sp, 16236; CHECK-NEXT: vs1r.v v8, (a1) # vscale x 8-byte Folded Spill237; CHECK-NEXT: andi a0, a0, 1238; CHECK-NEXT: #APP239; CHECK-NEXT: #NO_APP240; CHECK-NEXT: beqz a0, .LBB5_2241; CHECK-NEXT: # %bb.1: # %truebb242; CHECK-NEXT: flw fa0, 16(sp) # 8-byte Folded Reload243; CHECK-NEXT: j .LBB5_3244; CHECK-NEXT: .LBB5_2: # %falsebb245; CHECK-NEXT: fmv.w.x fa0, zero246; CHECK-NEXT: .LBB5_3: # %falsebb247; CHECK-NEXT: csrr a0, vlenb248; CHECK-NEXT: add sp, sp, a0249; CHECK-NEXT: .cfi_def_cfa sp, 16250; CHECK-NEXT: addi sp, sp, 16251; CHECK-NEXT: .cfi_def_cfa_offset 0252; CHECK-NEXT: ret253 tail call void asm sideeffect "", "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()254 br i1 %c, label %truebb, label %falsebb255truebb:256 %x = extractelement <vscale x 2 x float> %v, i32 0257 ret float %x258falsebb:259 ret float 0.0260}261 262define half @f16(<vscale x 1 x half> %v, i1 %c) {263; ZFMIN-LABEL: f16:264; ZFMIN: # %bb.0:265; ZFMIN-NEXT: addi sp, sp, -16266; ZFMIN-NEXT: .cfi_def_cfa_offset 16267; ZFMIN-NEXT: csrr a1, vlenb268; ZFMIN-NEXT: sub sp, sp, a1269; ZFMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x01, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 1 * vlenb270; ZFMIN-NEXT: addi a1, sp, 16271; ZFMIN-NEXT: vs1r.v v8, (a1) # vscale x 8-byte Folded Spill272; ZFMIN-NEXT: andi a0, a0, 1273; ZFMIN-NEXT: #APP274; ZFMIN-NEXT: #NO_APP275; ZFMIN-NEXT: beqz a0, .LBB6_2276; ZFMIN-NEXT: # %bb.1: # %truebb277; ZFMIN-NEXT: flh fa0, 16(sp) # 8-byte Folded Reload278; ZFMIN-NEXT: j .LBB6_3279; ZFMIN-NEXT: .LBB6_2: # %falsebb280; ZFMIN-NEXT: fmv.h.x fa0, zero281; ZFMIN-NEXT: .LBB6_3: # %falsebb282; ZFMIN-NEXT: csrr a0, vlenb283; ZFMIN-NEXT: add sp, sp, a0284; ZFMIN-NEXT: .cfi_def_cfa sp, 16285; ZFMIN-NEXT: addi sp, sp, 16286; ZFMIN-NEXT: .cfi_def_cfa_offset 0287; ZFMIN-NEXT: ret288;289; NOZFMIN-LABEL: f16:290; NOZFMIN: # %bb.0:291; NOZFMIN-NEXT: addi sp, sp, -16292; NOZFMIN-NEXT: .cfi_def_cfa_offset 16293; NOZFMIN-NEXT: csrr a1, vlenb294; NOZFMIN-NEXT: sub sp, sp, a1295; NOZFMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x01, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 1 * vlenb296; NOZFMIN-NEXT: addi a1, sp, 16297; NOZFMIN-NEXT: vs1r.v v8, (a1) # vscale x 8-byte Folded Spill298; NOZFMIN-NEXT: andi a0, a0, 1299; NOZFMIN-NEXT: #APP300; NOZFMIN-NEXT: #NO_APP301; NOZFMIN-NEXT: beqz a0, .LBB6_2302; NOZFMIN-NEXT: # %bb.1: # %truebb303; NOZFMIN-NEXT: lh a0, 16(sp) # 8-byte Folded Reload304; NOZFMIN-NEXT: lui a1, 1048560305; NOZFMIN-NEXT: or a0, a0, a1306; NOZFMIN-NEXT: j .LBB6_3307; NOZFMIN-NEXT: .LBB6_2: # %falsebb308; NOZFMIN-NEXT: lui a0, 1048560309; NOZFMIN-NEXT: .LBB6_3: # %falsebb310; NOZFMIN-NEXT: fmv.w.x fa0, a0311; NOZFMIN-NEXT: csrr a0, vlenb312; NOZFMIN-NEXT: add sp, sp, a0313; NOZFMIN-NEXT: .cfi_def_cfa sp, 16314; NOZFMIN-NEXT: addi sp, sp, 16315; NOZFMIN-NEXT: .cfi_def_cfa_offset 0316; NOZFMIN-NEXT: ret317 tail call void asm sideeffect "", "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()318 br i1 %c, label %truebb, label %falsebb319truebb:320 %x = extractelement <vscale x 1 x half> %v, i32 0321 ret half %x322falsebb:323 ret half 0.0324}325 326define bfloat @bf16(<vscale x 2 x bfloat> %v, i1 %c) {327; ZFMIN-LABEL: bf16:328; ZFMIN: # %bb.0:329; ZFMIN-NEXT: addi sp, sp, -16330; ZFMIN-NEXT: .cfi_def_cfa_offset 16331; ZFMIN-NEXT: csrr a1, vlenb332; ZFMIN-NEXT: sub sp, sp, a1333; ZFMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x01, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 1 * vlenb334; ZFMIN-NEXT: addi a1, sp, 16335; ZFMIN-NEXT: vs1r.v v8, (a1) # vscale x 8-byte Folded Spill336; ZFMIN-NEXT: andi a0, a0, 1337; ZFMIN-NEXT: #APP338; ZFMIN-NEXT: #NO_APP339; ZFMIN-NEXT: beqz a0, .LBB7_2340; ZFMIN-NEXT: # %bb.1: # %truebb341; ZFMIN-NEXT: lh a0, 16(sp) # 8-byte Folded Reload342; ZFMIN-NEXT: fmv.h.x fa0, a0343; ZFMIN-NEXT: j .LBB7_3344; ZFMIN-NEXT: .LBB7_2: # %falsebb345; ZFMIN-NEXT: fmv.h.x fa0, zero346; ZFMIN-NEXT: .LBB7_3: # %falsebb347; ZFMIN-NEXT: csrr a0, vlenb348; ZFMIN-NEXT: add sp, sp, a0349; ZFMIN-NEXT: .cfi_def_cfa sp, 16350; ZFMIN-NEXT: addi sp, sp, 16351; ZFMIN-NEXT: .cfi_def_cfa_offset 0352; ZFMIN-NEXT: ret353;354; NOZFMIN-LABEL: bf16:355; NOZFMIN: # %bb.0:356; NOZFMIN-NEXT: addi sp, sp, -16357; NOZFMIN-NEXT: .cfi_def_cfa_offset 16358; NOZFMIN-NEXT: csrr a1, vlenb359; NOZFMIN-NEXT: sub sp, sp, a1360; NOZFMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x01, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 1 * vlenb361; NOZFMIN-NEXT: addi a1, sp, 16362; NOZFMIN-NEXT: vs1r.v v8, (a1) # vscale x 8-byte Folded Spill363; NOZFMIN-NEXT: andi a0, a0, 1364; NOZFMIN-NEXT: #APP365; NOZFMIN-NEXT: #NO_APP366; NOZFMIN-NEXT: beqz a0, .LBB7_2367; NOZFMIN-NEXT: # %bb.1: # %truebb368; NOZFMIN-NEXT: lh a0, 16(sp) # 8-byte Folded Reload369; NOZFMIN-NEXT: lui a1, 1048560370; NOZFMIN-NEXT: or a0, a0, a1371; NOZFMIN-NEXT: j .LBB7_3372; NOZFMIN-NEXT: .LBB7_2: # %falsebb373; NOZFMIN-NEXT: lui a0, 1048560374; NOZFMIN-NEXT: .LBB7_3: # %falsebb375; NOZFMIN-NEXT: fmv.w.x fa0, a0376; NOZFMIN-NEXT: csrr a0, vlenb377; NOZFMIN-NEXT: add sp, sp, a0378; NOZFMIN-NEXT: .cfi_def_cfa sp, 16379; NOZFMIN-NEXT: addi sp, sp, 16380; NOZFMIN-NEXT: .cfi_def_cfa_offset 0381; NOZFMIN-NEXT: ret382 tail call void asm sideeffect "", "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()383 br i1 %c, label %truebb, label %falsebb384truebb:385 %x = extractelement <vscale x 2 x bfloat> %v, i32 0386 ret bfloat %x387falsebb:388 ret bfloat 0.0389}390 391