401 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv64 -mattr=+m,+v -O2 < %s \3; RUN: | FileCheck %s -check-prefix=RV64IV4; RUN: llc -mtriple=riscv32 -mattr=+m,+v -O2 < %s \5; RUN: | FileCheck %s -check-prefix=RV32IV6 7; Tests adapted from AArch64.8 9; Test prolog sequences for stack probing when vector is involved.10 11; The space for vector objects needs probing in the general case, because12; the stack adjustment may happen to be too big (i.e. greater than the13; probe size).14 15define void @f_vector(ptr %out) #0 {16; RV64IV-LABEL: f_vector:17; RV64IV: # %bb.0: # %entry18; RV64IV-NEXT: csrr t1, vlenb19; RV64IV-NEXT: slli t1, t1, 120; RV64IV-NEXT: .cfi_def_cfa t1, -1621; RV64IV-NEXT: lui t2, 122; RV64IV-NEXT: .LBB0_1: # %entry23; RV64IV-NEXT: # =>This Inner Loop Header: Depth=124; RV64IV-NEXT: sub sp, sp, t225; RV64IV-NEXT: sd zero, 0(sp)26; RV64IV-NEXT: sub t1, t1, t227; RV64IV-NEXT: bge t1, t2, .LBB0_128; RV64IV-NEXT: # %bb.2: # %entry29; RV64IV-NEXT: .cfi_def_cfa_register sp30; RV64IV-NEXT: sub sp, sp, t131; RV64IV-NEXT: .cfi_escape 0x0f, 0x0a, 0x72, 0x00, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 2 * vlenb32; RV64IV-NEXT: csrr a0, vlenb33; RV64IV-NEXT: slli a0, a0, 134; RV64IV-NEXT: add sp, sp, a035; RV64IV-NEXT: .cfi_def_cfa sp, 036; RV64IV-NEXT: ret37;38; RV32IV-LABEL: f_vector:39; RV32IV: # %bb.0: # %entry40; RV32IV-NEXT: csrr t1, vlenb41; RV32IV-NEXT: slli t1, t1, 142; RV32IV-NEXT: .cfi_def_cfa t1, -1643; RV32IV-NEXT: lui t2, 144; RV32IV-NEXT: .LBB0_1: # %entry45; RV32IV-NEXT: # =>This Inner Loop Header: Depth=146; RV32IV-NEXT: sub sp, sp, t247; RV32IV-NEXT: sw zero, 0(sp)48; RV32IV-NEXT: sub t1, t1, t249; RV32IV-NEXT: bge t1, t2, .LBB0_150; RV32IV-NEXT: # %bb.2: # %entry51; RV32IV-NEXT: .cfi_def_cfa_register sp52; RV32IV-NEXT: sub sp, sp, t153; RV32IV-NEXT: .cfi_escape 0x0f, 0x0a, 0x72, 0x00, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 2 * vlenb54; RV32IV-NEXT: csrr a0, vlenb55; RV32IV-NEXT: slli a0, a0, 156; RV32IV-NEXT: add sp, sp, a057; RV32IV-NEXT: .cfi_def_cfa sp, 058; RV32IV-NEXT: ret59entry:60 %vec = alloca <vscale x 4 x float>, align 1661 ret void62}63 64; As above, but with 4 vectors of stack space.65define void @f4_vector(ptr %out) #0 {66; RV64IV-LABEL: f4_vector:67; RV64IV: # %bb.0: # %entry68; RV64IV-NEXT: csrr t1, vlenb69; RV64IV-NEXT: slli t1, t1, 370; RV64IV-NEXT: .cfi_def_cfa t1, -6471; RV64IV-NEXT: lui t2, 172; RV64IV-NEXT: .LBB1_1: # %entry73; RV64IV-NEXT: # =>This Inner Loop Header: Depth=174; RV64IV-NEXT: sub sp, sp, t275; RV64IV-NEXT: sd zero, 0(sp)76; RV64IV-NEXT: sub t1, t1, t277; RV64IV-NEXT: bge t1, t2, .LBB1_178; RV64IV-NEXT: # %bb.2: # %entry79; RV64IV-NEXT: .cfi_def_cfa_register sp80; RV64IV-NEXT: sub sp, sp, t181; RV64IV-NEXT: .cfi_escape 0x0f, 0x0a, 0x72, 0x00, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 8 * vlenb82; RV64IV-NEXT: csrr a0, vlenb83; RV64IV-NEXT: slli a0, a0, 384; RV64IV-NEXT: add sp, sp, a085; RV64IV-NEXT: .cfi_def_cfa sp, 086; RV64IV-NEXT: ret87;88; RV32IV-LABEL: f4_vector:89; RV32IV: # %bb.0: # %entry90; RV32IV-NEXT: csrr t1, vlenb91; RV32IV-NEXT: slli t1, t1, 392; RV32IV-NEXT: .cfi_def_cfa t1, -6493; RV32IV-NEXT: lui t2, 194; RV32IV-NEXT: .LBB1_1: # %entry95; RV32IV-NEXT: # =>This Inner Loop Header: Depth=196; RV32IV-NEXT: sub sp, sp, t297; RV32IV-NEXT: sw zero, 0(sp)98; RV32IV-NEXT: sub t1, t1, t299; RV32IV-NEXT: bge t1, t2, .LBB1_1100; RV32IV-NEXT: # %bb.2: # %entry101; RV32IV-NEXT: .cfi_def_cfa_register sp102; RV32IV-NEXT: sub sp, sp, t1103; RV32IV-NEXT: .cfi_escape 0x0f, 0x0a, 0x72, 0x00, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 8 * vlenb104; RV32IV-NEXT: csrr a0, vlenb105; RV32IV-NEXT: slli a0, a0, 3106; RV32IV-NEXT: add sp, sp, a0107; RV32IV-NEXT: .cfi_def_cfa sp, 0108; RV32IV-NEXT: ret109entry:110 %vec1 = alloca <vscale x 4 x float>, align 16111 %vec2 = alloca <vscale x 4 x float>, align 16112 %vec3 = alloca <vscale x 4 x float>, align 16113 %vec4 = alloca <vscale x 4 x float>, align 16114 ret void115}116 117; As above, but with 16 vectors of stack space.118; The stack adjustment is less than or equal to 16 x 256 = 4096, so119; we can allocate the locals at once.120define void @f16_vector(ptr %out) #0 {121; RV64IV-LABEL: f16_vector:122; RV64IV: # %bb.0: # %entry123; RV64IV-NEXT: csrr t1, vlenb124; RV64IV-NEXT: slli t1, t1, 5125; RV64IV-NEXT: .cfi_def_cfa t1, -256126; RV64IV-NEXT: lui t2, 1127; RV64IV-NEXT: .LBB2_1: # %entry128; RV64IV-NEXT: # =>This Inner Loop Header: Depth=1129; RV64IV-NEXT: sub sp, sp, t2130; RV64IV-NEXT: sd zero, 0(sp)131; RV64IV-NEXT: sub t1, t1, t2132; RV64IV-NEXT: bge t1, t2, .LBB2_1133; RV64IV-NEXT: # %bb.2: # %entry134; RV64IV-NEXT: .cfi_def_cfa_register sp135; RV64IV-NEXT: sub sp, sp, t1136; RV64IV-NEXT: .cfi_escape 0x0f, 0x0a, 0x72, 0x00, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 32 * vlenb137; RV64IV-NEXT: csrr a0, vlenb138; RV64IV-NEXT: slli a0, a0, 5139; RV64IV-NEXT: add sp, sp, a0140; RV64IV-NEXT: .cfi_def_cfa sp, 0141; RV64IV-NEXT: ret142;143; RV32IV-LABEL: f16_vector:144; RV32IV: # %bb.0: # %entry145; RV32IV-NEXT: csrr t1, vlenb146; RV32IV-NEXT: slli t1, t1, 5147; RV32IV-NEXT: .cfi_def_cfa t1, -256148; RV32IV-NEXT: lui t2, 1149; RV32IV-NEXT: .LBB2_1: # %entry150; RV32IV-NEXT: # =>This Inner Loop Header: Depth=1151; RV32IV-NEXT: sub sp, sp, t2152; RV32IV-NEXT: sw zero, 0(sp)153; RV32IV-NEXT: sub t1, t1, t2154; RV32IV-NEXT: bge t1, t2, .LBB2_1155; RV32IV-NEXT: # %bb.2: # %entry156; RV32IV-NEXT: .cfi_def_cfa_register sp157; RV32IV-NEXT: sub sp, sp, t1158; RV32IV-NEXT: .cfi_escape 0x0f, 0x0a, 0x72, 0x00, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 32 * vlenb159; RV32IV-NEXT: csrr a0, vlenb160; RV32IV-NEXT: slli a0, a0, 5161; RV32IV-NEXT: add sp, sp, a0162; RV32IV-NEXT: .cfi_def_cfa sp, 0163; RV32IV-NEXT: ret164entry:165 %vec1 = alloca <vscale x 4 x float>, align 16166 %vec2 = alloca <vscale x 4 x float>, align 16167 %vec3 = alloca <vscale x 4 x float>, align 16168 %vec4 = alloca <vscale x 4 x float>, align 16169 %vec5 = alloca <vscale x 4 x float>, align 16170 %vec6 = alloca <vscale x 4 x float>, align 16171 %vec7 = alloca <vscale x 4 x float>, align 16172 %vec8 = alloca <vscale x 4 x float>, align 16173 %vec9 = alloca <vscale x 4 x float>, align 16174 %vec10 = alloca <vscale x 4 x float>, align 16175 %vec11 = alloca <vscale x 4 x float>, align 16176 %vec12 = alloca <vscale x 4 x float>, align 16177 %vec13 = alloca <vscale x 4 x float>, align 16178 %vec14 = alloca <vscale x 4 x float>, align 16179 %vec15 = alloca <vscale x 4 x float>, align 16180 %vec16 = alloca <vscale x 4 x float>, align 16181 ret void182}183 184; As above, but with 17 vectors of stack space.185define void @f17_vector(ptr %out) #0 {186; RV64IV-LABEL: f17_vector:187; RV64IV: # %bb.0: # %entry188; RV64IV-NEXT: csrr t1, vlenb189; RV64IV-NEXT: li a0, 34190; RV64IV-NEXT: mul t1, t1, a0191; RV64IV-NEXT: .cfi_def_cfa t1, -272192; RV64IV-NEXT: lui t2, 1193; RV64IV-NEXT: .LBB3_1: # %entry194; RV64IV-NEXT: # =>This Inner Loop Header: Depth=1195; RV64IV-NEXT: sub sp, sp, t2196; RV64IV-NEXT: sd zero, 0(sp)197; RV64IV-NEXT: sub t1, t1, t2198; RV64IV-NEXT: bge t1, t2, .LBB3_1199; RV64IV-NEXT: # %bb.2: # %entry200; RV64IV-NEXT: .cfi_def_cfa_register sp201; RV64IV-NEXT: sub sp, sp, t1202; RV64IV-NEXT: .cfi_escape 0x0f, 0x0a, 0x72, 0x00, 0x11, 0x22, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 34 * vlenb203; RV64IV-NEXT: csrr a0, vlenb204; RV64IV-NEXT: li a1, 34205; RV64IV-NEXT: mul a0, a0, a1206; RV64IV-NEXT: add sp, sp, a0207; RV64IV-NEXT: .cfi_def_cfa sp, 0208; RV64IV-NEXT: ret209;210; RV32IV-LABEL: f17_vector:211; RV32IV: # %bb.0: # %entry212; RV32IV-NEXT: csrr t1, vlenb213; RV32IV-NEXT: li a0, 34214; RV32IV-NEXT: mul t1, t1, a0215; RV32IV-NEXT: .cfi_def_cfa t1, -272216; RV32IV-NEXT: lui t2, 1217; RV32IV-NEXT: .LBB3_1: # %entry218; RV32IV-NEXT: # =>This Inner Loop Header: Depth=1219; RV32IV-NEXT: sub sp, sp, t2220; RV32IV-NEXT: sw zero, 0(sp)221; RV32IV-NEXT: sub t1, t1, t2222; RV32IV-NEXT: bge t1, t2, .LBB3_1223; RV32IV-NEXT: # %bb.2: # %entry224; RV32IV-NEXT: .cfi_def_cfa_register sp225; RV32IV-NEXT: sub sp, sp, t1226; RV32IV-NEXT: .cfi_escape 0x0f, 0x0a, 0x72, 0x00, 0x11, 0x22, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 34 * vlenb227; RV32IV-NEXT: csrr a0, vlenb228; RV32IV-NEXT: li a1, 34229; RV32IV-NEXT: mul a0, a0, a1230; RV32IV-NEXT: add sp, sp, a0231; RV32IV-NEXT: .cfi_def_cfa sp, 0232; RV32IV-NEXT: ret233entry:234 %vec1 = alloca <vscale x 4 x float>, align 16235 %vec2 = alloca <vscale x 4 x float>, align 16236 %vec3 = alloca <vscale x 4 x float>, align 16237 %vec4 = alloca <vscale x 4 x float>, align 16238 %vec5 = alloca <vscale x 4 x float>, align 16239 %vec6 = alloca <vscale x 4 x float>, align 16240 %vec7 = alloca <vscale x 4 x float>, align 16241 %vec8 = alloca <vscale x 4 x float>, align 16242 %vec9 = alloca <vscale x 4 x float>, align 16243 %vec10 = alloca <vscale x 4 x float>, align 16244 %vec11 = alloca <vscale x 4 x float>, align 16245 %vec12 = alloca <vscale x 4 x float>, align 16246 %vec13 = alloca <vscale x 4 x float>, align 16247 %vec14 = alloca <vscale x 4 x float>, align 16248 %vec15 = alloca <vscale x 4 x float>, align 16249 %vec16 = alloca <vscale x 4 x float>, align 16250 %vec17 = alloca <vscale x 4 x float>, align 16251 ret void252}253 254; A vector and a 16-byte fixed size object.255define void @f1_vector_16_arr(ptr %out) #0 {256; RV64IV-LABEL: f1_vector_16_arr:257; RV64IV: # %bb.0: # %entry258; RV64IV-NEXT: addi sp, sp, -16259; RV64IV-NEXT: .cfi_def_cfa_offset 16260; RV64IV-NEXT: csrr t1, vlenb261; RV64IV-NEXT: slli t1, t1, 1262; RV64IV-NEXT: .cfi_def_cfa t1, -16263; RV64IV-NEXT: lui t2, 1264; RV64IV-NEXT: .LBB4_1: # %entry265; RV64IV-NEXT: # =>This Inner Loop Header: Depth=1266; RV64IV-NEXT: sub sp, sp, t2267; RV64IV-NEXT: sd zero, 0(sp)268; RV64IV-NEXT: sub t1, t1, t2269; RV64IV-NEXT: bge t1, t2, .LBB4_1270; RV64IV-NEXT: # %bb.2: # %entry271; RV64IV-NEXT: .cfi_def_cfa_register sp272; RV64IV-NEXT: sub sp, sp, t1273; RV64IV-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 2 * vlenb274; RV64IV-NEXT: csrr a0, vlenb275; RV64IV-NEXT: slli a0, a0, 1276; RV64IV-NEXT: add sp, sp, a0277; RV64IV-NEXT: .cfi_def_cfa sp, 16278; RV64IV-NEXT: addi sp, sp, 16279; RV64IV-NEXT: .cfi_def_cfa_offset 0280; RV64IV-NEXT: ret281;282; RV32IV-LABEL: f1_vector_16_arr:283; RV32IV: # %bb.0: # %entry284; RV32IV-NEXT: addi sp, sp, -16285; RV32IV-NEXT: .cfi_def_cfa_offset 16286; RV32IV-NEXT: csrr t1, vlenb287; RV32IV-NEXT: slli t1, t1, 1288; RV32IV-NEXT: .cfi_def_cfa t1, -16289; RV32IV-NEXT: lui t2, 1290; RV32IV-NEXT: .LBB4_1: # %entry291; RV32IV-NEXT: # =>This Inner Loop Header: Depth=1292; RV32IV-NEXT: sub sp, sp, t2293; RV32IV-NEXT: sw zero, 0(sp)294; RV32IV-NEXT: sub t1, t1, t2295; RV32IV-NEXT: bge t1, t2, .LBB4_1296; RV32IV-NEXT: # %bb.2: # %entry297; RV32IV-NEXT: .cfi_def_cfa_register sp298; RV32IV-NEXT: sub sp, sp, t1299; RV32IV-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 2 * vlenb300; RV32IV-NEXT: csrr a0, vlenb301; RV32IV-NEXT: slli a0, a0, 1302; RV32IV-NEXT: add sp, sp, a0303; RV32IV-NEXT: .cfi_def_cfa sp, 16304; RV32IV-NEXT: addi sp, sp, 16305; RV32IV-NEXT: .cfi_def_cfa_offset 0306; RV32IV-NEXT: ret307entry:308 %vec = alloca <vscale x 4 x float>, align 16309 %arr = alloca i8, i64 16, align 1310 ret void311}312 313; A large vector object and a large slot, both of which need probing.314define void @f1_vector_4096_arr(ptr %out) #0 {315; RV64IV-LABEL: f1_vector_4096_arr:316; RV64IV: # %bb.0: # %entry317; RV64IV-NEXT: lui a0, 1318; RV64IV-NEXT: sub sp, sp, a0319; RV64IV-NEXT: sd zero, 0(sp)320; RV64IV-NEXT: .cfi_def_cfa_offset 4096321; RV64IV-NEXT: lui a0, 1322; RV64IV-NEXT: sub sp, sp, a0323; RV64IV-NEXT: sd zero, 0(sp)324; RV64IV-NEXT: .cfi_def_cfa_offset 8192325; RV64IV-NEXT: lui a0, 1326; RV64IV-NEXT: sub sp, sp, a0327; RV64IV-NEXT: sd zero, 0(sp)328; RV64IV-NEXT: .cfi_def_cfa_offset 12288329; RV64IV-NEXT: addi sp, sp, -16330; RV64IV-NEXT: .cfi_def_cfa_offset 12304331; RV64IV-NEXT: csrr t1, vlenb332; RV64IV-NEXT: slli t1, t1, 7333; RV64IV-NEXT: .cfi_def_cfa t1, -1024334; RV64IV-NEXT: lui t2, 1335; RV64IV-NEXT: .LBB5_1: # %entry336; RV64IV-NEXT: # =>This Inner Loop Header: Depth=1337; RV64IV-NEXT: sub sp, sp, t2338; RV64IV-NEXT: sd zero, 0(sp)339; RV64IV-NEXT: sub t1, t1, t2340; RV64IV-NEXT: bge t1, t2, .LBB5_1341; RV64IV-NEXT: # %bb.2: # %entry342; RV64IV-NEXT: .cfi_def_cfa_register sp343; RV64IV-NEXT: sub sp, sp, t1344; RV64IV-NEXT: .cfi_escape 0x0f, 0x10, 0x72, 0x00, 0x11, 0x90, 0xe0, 0x00, 0x22, 0x11, 0x80, 0x01, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 12304 + 128 * vlenb345; RV64IV-NEXT: csrr a0, vlenb346; RV64IV-NEXT: slli a0, a0, 7347; RV64IV-NEXT: add sp, sp, a0348; RV64IV-NEXT: .cfi_def_cfa sp, 12304349; RV64IV-NEXT: lui a0, 3350; RV64IV-NEXT: addi a0, a0, 16351; RV64IV-NEXT: add sp, sp, a0352; RV64IV-NEXT: .cfi_def_cfa_offset 0353; RV64IV-NEXT: ret354;355; RV32IV-LABEL: f1_vector_4096_arr:356; RV32IV: # %bb.0: # %entry357; RV32IV-NEXT: lui a0, 1358; RV32IV-NEXT: sub sp, sp, a0359; RV32IV-NEXT: sw zero, 0(sp)360; RV32IV-NEXT: .cfi_def_cfa_offset 4096361; RV32IV-NEXT: lui a0, 1362; RV32IV-NEXT: sub sp, sp, a0363; RV32IV-NEXT: sw zero, 0(sp)364; RV32IV-NEXT: .cfi_def_cfa_offset 8192365; RV32IV-NEXT: lui a0, 1366; RV32IV-NEXT: sub sp, sp, a0367; RV32IV-NEXT: sw zero, 0(sp)368; RV32IV-NEXT: .cfi_def_cfa_offset 12288369; RV32IV-NEXT: addi sp, sp, -16370; RV32IV-NEXT: .cfi_def_cfa_offset 12304371; RV32IV-NEXT: csrr t1, vlenb372; RV32IV-NEXT: slli t1, t1, 7373; RV32IV-NEXT: .cfi_def_cfa t1, -1024374; RV32IV-NEXT: lui t2, 1375; RV32IV-NEXT: .LBB5_1: # %entry376; RV32IV-NEXT: # =>This Inner Loop Header: Depth=1377; RV32IV-NEXT: sub sp, sp, t2378; RV32IV-NEXT: sw zero, 0(sp)379; RV32IV-NEXT: sub t1, t1, t2380; RV32IV-NEXT: bge t1, t2, .LBB5_1381; RV32IV-NEXT: # %bb.2: # %entry382; RV32IV-NEXT: .cfi_def_cfa_register sp383; RV32IV-NEXT: sub sp, sp, t1384; RV32IV-NEXT: .cfi_escape 0x0f, 0x10, 0x72, 0x00, 0x11, 0x90, 0xe0, 0x00, 0x22, 0x11, 0x80, 0x01, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 12304 + 128 * vlenb385; RV32IV-NEXT: csrr a0, vlenb386; RV32IV-NEXT: slli a0, a0, 7387; RV32IV-NEXT: add sp, sp, a0388; RV32IV-NEXT: .cfi_def_cfa sp, 12304389; RV32IV-NEXT: lui a0, 3390; RV32IV-NEXT: addi a0, a0, 16391; RV32IV-NEXT: add sp, sp, a0392; RV32IV-NEXT: .cfi_def_cfa_offset 0393; RV32IV-NEXT: ret394entry:395 %vec = alloca <vscale x 256 x float>, align 16396 %arr = alloca i8, i64 12288, align 1397 ret void398}399 400attributes #0 = { uwtable(async) "probe-stack"="inline-asm" "frame-pointer"="none" }401