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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+m,+v -verify-machineinstrs < %s | FileCheck %s -check-prefixes=CHECK,RV323; RUN: llc -mtriple=riscv64 -mattr=+m,+v -verify-machineinstrs < %s | FileCheck %s -check-prefixes=CHECK,RV644 5define <vscale x 1 x i8> @stepvector_nxv1i8() {6; CHECK-LABEL: stepvector_nxv1i8:7; CHECK: # %bb.0:8; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma9; CHECK-NEXT: vid.v v810; CHECK-NEXT: ret11 %v = call <vscale x 1 x i8> @llvm.stepvector.nxv1i8()12 ret <vscale x 1 x i8> %v13}14 15define <vscale x 2 x i8> @stepvector_nxv2i8() {16; CHECK-LABEL: stepvector_nxv2i8:17; CHECK: # %bb.0:18; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma19; CHECK-NEXT: vid.v v820; CHECK-NEXT: ret21 %v = call <vscale x 2 x i8> @llvm.stepvector.nxv2i8()22 ret <vscale x 2 x i8> %v23}24 25define <vscale x 3 x i8> @stepvector_nxv3i8() {26; CHECK-LABEL: stepvector_nxv3i8:27; CHECK: # %bb.0:28; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma29; CHECK-NEXT: vid.v v830; CHECK-NEXT: ret31 %v = call <vscale x 3 x i8> @llvm.stepvector.nxv3i8()32 ret <vscale x 3 x i8> %v33}34 35define <vscale x 4 x i8> @stepvector_nxv4i8() {36; CHECK-LABEL: stepvector_nxv4i8:37; CHECK: # %bb.0:38; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma39; CHECK-NEXT: vid.v v840; CHECK-NEXT: ret41 %v = call <vscale x 4 x i8> @llvm.stepvector.nxv4i8()42 ret <vscale x 4 x i8> %v43}44 45define <vscale x 8 x i8> @stepvector_nxv8i8() {46; CHECK-LABEL: stepvector_nxv8i8:47; CHECK: # %bb.0:48; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma49; CHECK-NEXT: vid.v v850; CHECK-NEXT: ret51 %v = call <vscale x 8 x i8> @llvm.stepvector.nxv8i8()52 ret <vscale x 8 x i8> %v53}54 55define <vscale x 8 x i8> @add_stepvector_nxv8i8() {56; CHECK-LABEL: add_stepvector_nxv8i8:57; CHECK: # %bb.0: # %entry58; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma59; CHECK-NEXT: vid.v v860; CHECK-NEXT: vadd.vv v8, v8, v861; CHECK-NEXT: ret62entry:63 %0 = call <vscale x 8 x i8> @llvm.stepvector.nxv8i8()64 %1 = call <vscale x 8 x i8> @llvm.stepvector.nxv8i8()65 %2 = add <vscale x 8 x i8> %0, %166 ret <vscale x 8 x i8> %267}68 69define <vscale x 8 x i8> @mul_stepvector_nxv8i8() {70; CHECK-LABEL: mul_stepvector_nxv8i8:71; CHECK: # %bb.0: # %entry72; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma73; CHECK-NEXT: vid.v v874; CHECK-NEXT: li a0, 375; CHECK-NEXT: vmul.vx v8, v8, a076; CHECK-NEXT: ret77entry:78 %2 = call <vscale x 8 x i8> @llvm.stepvector.nxv8i8()79 %3 = mul <vscale x 8 x i8> %2, splat (i8 3)80 ret <vscale x 8 x i8> %381}82 83define <vscale x 8 x i8> @shl_stepvector_nxv8i8() {84; CHECK-LABEL: shl_stepvector_nxv8i8:85; CHECK: # %bb.0: # %entry86; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma87; CHECK-NEXT: vid.v v888; CHECK-NEXT: vsll.vi v8, v8, 289; CHECK-NEXT: ret90entry:91 %2 = call <vscale x 8 x i8> @llvm.stepvector.nxv8i8()92 %3 = shl <vscale x 8 x i8> %2, splat (i8 2)93 ret <vscale x 8 x i8> %394}95 96define <vscale x 16 x i8> @stepvector_nxv16i8() {97; CHECK-LABEL: stepvector_nxv16i8:98; CHECK: # %bb.0:99; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma100; CHECK-NEXT: vid.v v8101; CHECK-NEXT: ret102 %v = call <vscale x 16 x i8> @llvm.stepvector.nxv16i8()103 ret <vscale x 16 x i8> %v104}105 106define <vscale x 32 x i8> @stepvector_nxv32i8() {107; CHECK-LABEL: stepvector_nxv32i8:108; CHECK: # %bb.0:109; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma110; CHECK-NEXT: vid.v v8111; CHECK-NEXT: ret112 %v = call <vscale x 32 x i8> @llvm.stepvector.nxv32i8()113 ret <vscale x 32 x i8> %v114}115 116define <vscale x 64 x i8> @stepvector_nxv64i8() {117; CHECK-LABEL: stepvector_nxv64i8:118; CHECK: # %bb.0:119; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma120; CHECK-NEXT: vid.v v8121; CHECK-NEXT: ret122 %v = call <vscale x 64 x i8> @llvm.stepvector.nxv64i8()123 ret <vscale x 64 x i8> %v124}125 126define <vscale x 1 x i16> @stepvector_nxv1i16() {127; CHECK-LABEL: stepvector_nxv1i16:128; CHECK: # %bb.0:129; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma130; CHECK-NEXT: vid.v v8131; CHECK-NEXT: ret132 %v = call <vscale x 1 x i16> @llvm.stepvector.nxv1i16()133 ret <vscale x 1 x i16> %v134}135 136define <vscale x 2 x i16> @stepvector_nxv2i16() {137; CHECK-LABEL: stepvector_nxv2i16:138; CHECK: # %bb.0:139; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma140; CHECK-NEXT: vid.v v8141; CHECK-NEXT: ret142 %v = call <vscale x 2 x i16> @llvm.stepvector.nxv2i16()143 ret <vscale x 2 x i16> %v144}145 146define <vscale x 2 x i15> @stepvector_nxv2i15() {147; CHECK-LABEL: stepvector_nxv2i15:148; CHECK: # %bb.0:149; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma150; CHECK-NEXT: vid.v v8151; CHECK-NEXT: ret152 %v = call <vscale x 2 x i15> @llvm.stepvector.nxv2i15()153 ret <vscale x 2 x i15> %v154}155 156define <vscale x 3 x i16> @stepvector_nxv3i16() {157; CHECK-LABEL: stepvector_nxv3i16:158; CHECK: # %bb.0:159; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma160; CHECK-NEXT: vid.v v8161; CHECK-NEXT: ret162 %v = call <vscale x 3 x i16> @llvm.stepvector.nxv3i16()163 ret <vscale x 3 x i16> %v164}165 166define <vscale x 4 x i16> @stepvector_nxv4i16() {167; CHECK-LABEL: stepvector_nxv4i16:168; CHECK: # %bb.0:169; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma170; CHECK-NEXT: vid.v v8171; CHECK-NEXT: ret172 %v = call <vscale x 4 x i16> @llvm.stepvector.nxv4i16()173 ret <vscale x 4 x i16> %v174}175 176define <vscale x 8 x i16> @stepvector_nxv8i16() {177; CHECK-LABEL: stepvector_nxv8i16:178; CHECK: # %bb.0:179; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma180; CHECK-NEXT: vid.v v8181; CHECK-NEXT: ret182 %v = call <vscale x 8 x i16> @llvm.stepvector.nxv8i16()183 ret <vscale x 8 x i16> %v184}185 186define <vscale x 16 x i16> @stepvector_nxv16i16() {187; CHECK-LABEL: stepvector_nxv16i16:188; CHECK: # %bb.0:189; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma190; CHECK-NEXT: vid.v v8191; CHECK-NEXT: ret192 %v = call <vscale x 16 x i16> @llvm.stepvector.nxv16i16()193 ret <vscale x 16 x i16> %v194}195 196define <vscale x 16 x i16> @add_stepvector_nxv16i16() {197; CHECK-LABEL: add_stepvector_nxv16i16:198; CHECK: # %bb.0: # %entry199; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma200; CHECK-NEXT: vid.v v8201; CHECK-NEXT: vadd.vv v8, v8, v8202; CHECK-NEXT: ret203entry:204 %0 = call <vscale x 16 x i16> @llvm.stepvector.nxv16i16()205 %1 = call <vscale x 16 x i16> @llvm.stepvector.nxv16i16()206 %2 = add <vscale x 16 x i16> %0, %1207 ret <vscale x 16 x i16> %2208}209 210define <vscale x 16 x i16> @mul_stepvector_nxv16i16() {211; CHECK-LABEL: mul_stepvector_nxv16i16:212; CHECK: # %bb.0: # %entry213; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma214; CHECK-NEXT: vid.v v8215; CHECK-NEXT: li a0, 3216; CHECK-NEXT: vmul.vx v8, v8, a0217; CHECK-NEXT: ret218entry:219 %2 = call <vscale x 16 x i16> @llvm.stepvector.nxv16i16()220 %3 = mul <vscale x 16 x i16> %2, splat (i16 3)221 ret <vscale x 16 x i16> %3222}223 224define <vscale x 16 x i16> @shl_stepvector_nxv16i16() {225; CHECK-LABEL: shl_stepvector_nxv16i16:226; CHECK: # %bb.0: # %entry227; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma228; CHECK-NEXT: vid.v v8229; CHECK-NEXT: vsll.vi v8, v8, 2230; CHECK-NEXT: ret231entry:232 %2 = call <vscale x 16 x i16> @llvm.stepvector.nxv16i16()233 %3 = shl <vscale x 16 x i16> %2, splat (i16 2)234 ret <vscale x 16 x i16> %3235}236 237define <vscale x 32 x i16> @stepvector_nxv32i16() {238; CHECK-LABEL: stepvector_nxv32i16:239; CHECK: # %bb.0:240; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma241; CHECK-NEXT: vid.v v8242; CHECK-NEXT: ret243 %v = call <vscale x 32 x i16> @llvm.stepvector.nxv32i16()244 ret <vscale x 32 x i16> %v245}246 247define <vscale x 1 x i32> @stepvector_nxv1i32() {248; CHECK-LABEL: stepvector_nxv1i32:249; CHECK: # %bb.0:250; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma251; CHECK-NEXT: vid.v v8252; CHECK-NEXT: ret253 %v = call <vscale x 1 x i32> @llvm.stepvector.nxv1i32()254 ret <vscale x 1 x i32> %v255}256 257define <vscale x 2 x i32> @stepvector_nxv2i32() {258; CHECK-LABEL: stepvector_nxv2i32:259; CHECK: # %bb.0:260; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma261; CHECK-NEXT: vid.v v8262; CHECK-NEXT: ret263 %v = call <vscale x 2 x i32> @llvm.stepvector.nxv2i32()264 ret <vscale x 2 x i32> %v265}266 267define <vscale x 3 x i32> @stepvector_nxv3i32() {268; CHECK-LABEL: stepvector_nxv3i32:269; CHECK: # %bb.0:270; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma271; CHECK-NEXT: vid.v v8272; CHECK-NEXT: ret273 %v = call <vscale x 3 x i32> @llvm.stepvector.nxv3i32()274 ret <vscale x 3 x i32> %v275}276 277define <vscale x 4 x i32> @stepvector_nxv4i32() {278; CHECK-LABEL: stepvector_nxv4i32:279; CHECK: # %bb.0:280; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma281; CHECK-NEXT: vid.v v8282; CHECK-NEXT: ret283 %v = call <vscale x 4 x i32> @llvm.stepvector.nxv4i32()284 ret <vscale x 4 x i32> %v285}286 287define <vscale x 8 x i32> @stepvector_nxv8i32() {288; CHECK-LABEL: stepvector_nxv8i32:289; CHECK: # %bb.0:290; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma291; CHECK-NEXT: vid.v v8292; CHECK-NEXT: ret293 %v = call <vscale x 8 x i32> @llvm.stepvector.nxv8i32()294 ret <vscale x 8 x i32> %v295}296 297define <vscale x 16 x i32> @stepvector_nxv16i32() {298; CHECK-LABEL: stepvector_nxv16i32:299; CHECK: # %bb.0:300; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma301; CHECK-NEXT: vid.v v8302; CHECK-NEXT: ret303 %v = call <vscale x 16 x i32> @llvm.stepvector.nxv16i32()304 ret <vscale x 16 x i32> %v305}306 307define <vscale x 16 x i32> @add_stepvector_nxv16i32() {308; CHECK-LABEL: add_stepvector_nxv16i32:309; CHECK: # %bb.0: # %entry310; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma311; CHECK-NEXT: vid.v v8312; CHECK-NEXT: vadd.vv v8, v8, v8313; CHECK-NEXT: ret314entry:315 %0 = call <vscale x 16 x i32> @llvm.stepvector.nxv16i32()316 %1 = call <vscale x 16 x i32> @llvm.stepvector.nxv16i32()317 %2 = add <vscale x 16 x i32> %0, %1318 ret <vscale x 16 x i32> %2319}320 321define <vscale x 16 x i32> @mul_stepvector_nxv16i32() {322; CHECK-LABEL: mul_stepvector_nxv16i32:323; CHECK: # %bb.0: # %entry324; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma325; CHECK-NEXT: vid.v v8326; CHECK-NEXT: li a0, 3327; CHECK-NEXT: vmul.vx v8, v8, a0328; CHECK-NEXT: ret329entry:330 %2 = call <vscale x 16 x i32> @llvm.stepvector.nxv16i32()331 %3 = mul <vscale x 16 x i32> %2, splat (i32 3)332 ret <vscale x 16 x i32> %3333}334 335define <vscale x 16 x i32> @shl_stepvector_nxv16i32() {336; CHECK-LABEL: shl_stepvector_nxv16i32:337; CHECK: # %bb.0: # %entry338; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma339; CHECK-NEXT: vid.v v8340; CHECK-NEXT: vsll.vi v8, v8, 2341; CHECK-NEXT: ret342entry:343 %2 = call <vscale x 16 x i32> @llvm.stepvector.nxv16i32()344 %3 = shl <vscale x 16 x i32> %2, splat (i32 2)345 ret <vscale x 16 x i32> %3346}347 348define <vscale x 1 x i64> @stepvector_nxv1i64() {349; CHECK-LABEL: stepvector_nxv1i64:350; CHECK: # %bb.0:351; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma352; CHECK-NEXT: vid.v v8353; CHECK-NEXT: ret354 %v = call <vscale x 1 x i64> @llvm.stepvector.nxv1i64()355 ret <vscale x 1 x i64> %v356}357 358define <vscale x 2 x i64> @stepvector_nxv2i64() {359; CHECK-LABEL: stepvector_nxv2i64:360; CHECK: # %bb.0:361; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma362; CHECK-NEXT: vid.v v8363; CHECK-NEXT: ret364 %v = call <vscale x 2 x i64> @llvm.stepvector.nxv2i64()365 ret <vscale x 2 x i64> %v366}367 368define <vscale x 3 x i64> @stepvector_nxv3i64() {369; CHECK-LABEL: stepvector_nxv3i64:370; CHECK: # %bb.0:371; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma372; CHECK-NEXT: vid.v v8373; CHECK-NEXT: ret374 %v = call <vscale x 3 x i64> @llvm.stepvector.nxv3i64()375 ret <vscale x 3 x i64> %v376}377 378define <vscale x 4 x i64> @stepvector_nxv4i64() {379; CHECK-LABEL: stepvector_nxv4i64:380; CHECK: # %bb.0:381; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma382; CHECK-NEXT: vid.v v8383; CHECK-NEXT: ret384 %v = call <vscale x 4 x i64> @llvm.stepvector.nxv4i64()385 ret <vscale x 4 x i64> %v386}387 388define <vscale x 8 x i64> @stepvector_nxv8i64() {389; CHECK-LABEL: stepvector_nxv8i64:390; CHECK: # %bb.0:391; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma392; CHECK-NEXT: vid.v v8393; CHECK-NEXT: ret394 %v = call <vscale x 8 x i64> @llvm.stepvector.nxv8i64()395 ret <vscale x 8 x i64> %v396}397 398define <vscale x 8 x i64> @add_stepvector_nxv8i64() {399; CHECK-LABEL: add_stepvector_nxv8i64:400; CHECK: # %bb.0: # %entry401; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma402; CHECK-NEXT: vid.v v8403; CHECK-NEXT: vadd.vv v8, v8, v8404; CHECK-NEXT: ret405entry:406 %0 = call <vscale x 8 x i64> @llvm.stepvector.nxv8i64()407 %1 = call <vscale x 8 x i64> @llvm.stepvector.nxv8i64()408 %2 = add <vscale x 8 x i64> %0, %1409 ret <vscale x 8 x i64> %2410}411 412define <vscale x 8 x i64> @mul_stepvector_nxv8i64() {413; CHECK-LABEL: mul_stepvector_nxv8i64:414; CHECK: # %bb.0: # %entry415; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma416; CHECK-NEXT: vid.v v8417; CHECK-NEXT: li a0, 3418; CHECK-NEXT: vmul.vx v8, v8, a0419; CHECK-NEXT: ret420entry:421 %2 = call <vscale x 8 x i64> @llvm.stepvector.nxv8i64()422 %3 = mul <vscale x 8 x i64> %2, splat (i64 3)423 ret <vscale x 8 x i64> %3424}425 426define <vscale x 8 x i64> @mul_bigimm_stepvector_nxv8i64() {427; RV32-LABEL: mul_bigimm_stepvector_nxv8i64:428; RV32: # %bb.0: # %entry429; RV32-NEXT: addi sp, sp, -16430; RV32-NEXT: .cfi_def_cfa_offset 16431; RV32-NEXT: li a0, 7432; RV32-NEXT: lui a1, 797989433; RV32-NEXT: addi a1, a1, -683434; RV32-NEXT: sw a1, 8(sp)435; RV32-NEXT: sw a0, 12(sp)436; RV32-NEXT: addi a0, sp, 8437; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma438; RV32-NEXT: vlse64.v v8, (a0), zero439; RV32-NEXT: vid.v v16440; RV32-NEXT: vmul.vv v8, v16, v8441; RV32-NEXT: addi sp, sp, 16442; RV32-NEXT: .cfi_def_cfa_offset 0443; RV32-NEXT: ret444;445; RV64-LABEL: mul_bigimm_stepvector_nxv8i64:446; RV64: # %bb.0: # %entry447; RV64-NEXT: vsetvli a0, zero, e64, m8, ta, ma448; RV64-NEXT: vid.v v8449; RV64-NEXT: lui a0, 1987450; RV64-NEXT: addi a0, a0, -731451; RV64-NEXT: slli a0, a0, 12452; RV64-NEXT: addi a0, a0, -683453; RV64-NEXT: vmul.vx v8, v8, a0454; RV64-NEXT: ret455entry:456 %2 = call <vscale x 8 x i64> @llvm.stepvector.nxv8i64()457 %3 = mul <vscale x 8 x i64> %2, splat (i64 33333333333)458 ret <vscale x 8 x i64> %3459}460 461define <vscale x 8 x i64> @shl_stepvector_nxv8i64() {462; CHECK-LABEL: shl_stepvector_nxv8i64:463; CHECK: # %bb.0: # %entry464; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma465; CHECK-NEXT: vid.v v8466; CHECK-NEXT: vsll.vi v8, v8, 2467; CHECK-NEXT: ret468entry:469 %2 = call <vscale x 8 x i64> @llvm.stepvector.nxv8i64()470 %3 = shl <vscale x 8 x i64> %2, splat (i64 2)471 ret <vscale x 8 x i64> %3472}473 474define <vscale x 16 x i64> @stepvector_nxv16i64() {475; RV32-LABEL: stepvector_nxv16i64:476; RV32: # %bb.0:477; RV32-NEXT: addi sp, sp, -16478; RV32-NEXT: .cfi_def_cfa_offset 16479; RV32-NEXT: csrr a0, vlenb480; RV32-NEXT: sw a0, 8(sp)481; RV32-NEXT: sw zero, 12(sp)482; RV32-NEXT: addi a0, sp, 8483; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma484; RV32-NEXT: vlse64.v v16, (a0), zero485; RV32-NEXT: vid.v v8486; RV32-NEXT: vadd.vv v16, v8, v16487; RV32-NEXT: addi sp, sp, 16488; RV32-NEXT: .cfi_def_cfa_offset 0489; RV32-NEXT: ret490;491; RV64-LABEL: stepvector_nxv16i64:492; RV64: # %bb.0:493; RV64-NEXT: csrr a0, vlenb494; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma495; RV64-NEXT: vid.v v8496; RV64-NEXT: vadd.vx v16, v8, a0497; RV64-NEXT: ret498 %v = call <vscale x 16 x i64> @llvm.stepvector.nxv16i64()499 ret <vscale x 16 x i64> %v500}501 502define <vscale x 16 x i64> @add_stepvector_nxv16i64() {503; RV32-LABEL: add_stepvector_nxv16i64:504; RV32: # %bb.0: # %entry505; RV32-NEXT: addi sp, sp, -16506; RV32-NEXT: .cfi_def_cfa_offset 16507; RV32-NEXT: csrr a0, vlenb508; RV32-NEXT: slli a0, a0, 1509; RV32-NEXT: sw a0, 8(sp)510; RV32-NEXT: sw zero, 12(sp)511; RV32-NEXT: addi a0, sp, 8512; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma513; RV32-NEXT: vlse64.v v16, (a0), zero514; RV32-NEXT: vid.v v8515; RV32-NEXT: vadd.vv v8, v8, v8516; RV32-NEXT: vadd.vv v16, v8, v16517; RV32-NEXT: addi sp, sp, 16518; RV32-NEXT: .cfi_def_cfa_offset 0519; RV32-NEXT: ret520;521; RV64-LABEL: add_stepvector_nxv16i64:522; RV64: # %bb.0: # %entry523; RV64-NEXT: csrr a0, vlenb524; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma525; RV64-NEXT: vid.v v8526; RV64-NEXT: slli a0, a0, 1527; RV64-NEXT: vadd.vv v8, v8, v8528; RV64-NEXT: vadd.vx v16, v8, a0529; RV64-NEXT: ret530entry:531 %0 = call <vscale x 16 x i64> @llvm.stepvector.nxv16i64()532 %1 = call <vscale x 16 x i64> @llvm.stepvector.nxv16i64()533 %2 = add <vscale x 16 x i64> %0, %1534 ret <vscale x 16 x i64> %2535}536 537define <vscale x 16 x i64> @mul_stepvector_nxv16i64() {538; RV32-LABEL: mul_stepvector_nxv16i64:539; RV32: # %bb.0: # %entry540; RV32-NEXT: addi sp, sp, -16541; RV32-NEXT: .cfi_def_cfa_offset 16542; RV32-NEXT: csrr a0, vlenb543; RV32-NEXT: slli a1, a0, 1544; RV32-NEXT: add a0, a1, a0545; RV32-NEXT: sw a0, 8(sp)546; RV32-NEXT: sw zero, 12(sp)547; RV32-NEXT: addi a0, sp, 8548; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma549; RV32-NEXT: vlse64.v v16, (a0), zero550; RV32-NEXT: vid.v v8551; RV32-NEXT: li a0, 3552; RV32-NEXT: vmul.vx v8, v8, a0553; RV32-NEXT: vadd.vv v16, v8, v16554; RV32-NEXT: addi sp, sp, 16555; RV32-NEXT: .cfi_def_cfa_offset 0556; RV32-NEXT: ret557;558; RV64-LABEL: mul_stepvector_nxv16i64:559; RV64: # %bb.0: # %entry560; RV64-NEXT: vsetvli a0, zero, e64, m8, ta, ma561; RV64-NEXT: vid.v v8562; RV64-NEXT: li a0, 3563; RV64-NEXT: csrr a1, vlenb564; RV64-NEXT: vmul.vx v8, v8, a0565; RV64-NEXT: slli a0, a1, 1566; RV64-NEXT: add a0, a0, a1567; RV64-NEXT: vadd.vx v16, v8, a0568; RV64-NEXT: ret569entry:570 %2 = call <vscale x 16 x i64> @llvm.stepvector.nxv16i64()571 %3 = mul <vscale x 16 x i64> %2, splat (i64 3)572 ret <vscale x 16 x i64> %3573}574 575define <vscale x 16 x i64> @mul_bigimm_stepvector_nxv16i64() {576; RV32-LABEL: mul_bigimm_stepvector_nxv16i64:577; RV32: # %bb.0: # %entry578; RV32-NEXT: addi sp, sp, -16579; RV32-NEXT: .cfi_def_cfa_offset 16580; RV32-NEXT: li a0, 7581; RV32-NEXT: lui a1, 797989582; RV32-NEXT: csrr a2, vlenb583; RV32-NEXT: lui a3, 11557584; RV32-NEXT: addi a1, a1, -683585; RV32-NEXT: srli a4, a2, 2586; RV32-NEXT: sw a1, 8(sp)587; RV32-NEXT: sw a0, 12(sp)588; RV32-NEXT: slli a0, a2, 3589; RV32-NEXT: sub a0, a0, a4590; RV32-NEXT: lui a1, 92455591; RV32-NEXT: addi a3, a3, -683592; RV32-NEXT: mul a3, a2, a3593; RV32-NEXT: srli a2, a2, 3594; RV32-NEXT: addi a1, a1, -1368595; RV32-NEXT: mulhu a1, a2, a1596; RV32-NEXT: add a0, a1, a0597; RV32-NEXT: addi a1, sp, 8598; RV32-NEXT: sw a3, 0(sp)599; RV32-NEXT: sw a0, 4(sp)600; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, ma601; RV32-NEXT: vlse64.v v8, (a1), zero602; RV32-NEXT: mv a0, sp603; RV32-NEXT: vlse64.v v16, (a0), zero604; RV32-NEXT: vid.v v24605; RV32-NEXT: vmul.vv v8, v24, v8606; RV32-NEXT: vadd.vv v16, v8, v16607; RV32-NEXT: addi sp, sp, 16608; RV32-NEXT: .cfi_def_cfa_offset 0609; RV32-NEXT: ret610;611; RV64-LABEL: mul_bigimm_stepvector_nxv16i64:612; RV64: # %bb.0: # %entry613; RV64-NEXT: csrr a0, vlenb614; RV64-NEXT: lui a1, 1987615; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, ma616; RV64-NEXT: vid.v v8617; RV64-NEXT: addi a1, a1, -731618; RV64-NEXT: slli a1, a1, 12619; RV64-NEXT: addi a1, a1, -683620; RV64-NEXT: mul a0, a0, a1621; RV64-NEXT: vmul.vx v8, v8, a1622; RV64-NEXT: vadd.vx v16, v8, a0623; RV64-NEXT: ret624entry:625 %2 = call <vscale x 16 x i64> @llvm.stepvector.nxv16i64()626 %3 = mul <vscale x 16 x i64> %2, splat (i64 33333333333)627 ret <vscale x 16 x i64> %3628}629 630define <vscale x 16 x i64> @shl_stepvector_nxv16i64() {631; RV32-LABEL: shl_stepvector_nxv16i64:632; RV32: # %bb.0: # %entry633; RV32-NEXT: addi sp, sp, -16634; RV32-NEXT: .cfi_def_cfa_offset 16635; RV32-NEXT: csrr a0, vlenb636; RV32-NEXT: slli a0, a0, 2637; RV32-NEXT: sw a0, 8(sp)638; RV32-NEXT: sw zero, 12(sp)639; RV32-NEXT: addi a0, sp, 8640; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma641; RV32-NEXT: vlse64.v v16, (a0), zero642; RV32-NEXT: vid.v v8643; RV32-NEXT: vsll.vi v8, v8, 2644; RV32-NEXT: vadd.vv v16, v8, v16645; RV32-NEXT: addi sp, sp, 16646; RV32-NEXT: .cfi_def_cfa_offset 0647; RV32-NEXT: ret648;649; RV64-LABEL: shl_stepvector_nxv16i64:650; RV64: # %bb.0: # %entry651; RV64-NEXT: csrr a0, vlenb652; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma653; RV64-NEXT: vid.v v8654; RV64-NEXT: slli a0, a0, 2655; RV64-NEXT: vsll.vi v8, v8, 2656; RV64-NEXT: vadd.vx v16, v8, a0657; RV64-NEXT: ret658entry:659 %2 = call <vscale x 16 x i64> @llvm.stepvector.nxv16i64()660 %3 = shl <vscale x 16 x i64> %2, splat (i64 2)661 ret <vscale x 16 x i64> %3662}663 664; maximum step is 4 * 2 = 8, so maximum step value is 7, so hi 61 bits are known665; zero666define <vscale x 2 x i64> @hi_bits_known_zero() vscale_range(2, 4) {667; CHECK-LABEL: hi_bits_known_zero:668; CHECK: # %bb.0:669; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma670; CHECK-NEXT: vmv.v.i v8, 0671; CHECK-NEXT: ret672 %step = call <vscale x 2 x i64> @llvm.stepvector.nxv2i64()673 %and = and <vscale x 2 x i64> %step, splat (i64 u0xfffffffffffffff8)674 ret <vscale x 2 x i64> %and675}676 677; the maximum step here overflows so don't set the known hi bits678define <vscale x 2 x i64> @hi_bits_known_zero_overflow() vscale_range(2, 4) {679; CHECK-LABEL: hi_bits_known_zero_overflow:680; CHECK: # %bb.0:681; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma682; CHECK-NEXT: vid.v v8683; CHECK-NEXT: li a0, -1684; CHECK-NEXT: vmul.vx v8, v8, a0685; CHECK-NEXT: vand.vi v8, v8, -8686; CHECK-NEXT: ret687 %step = call <vscale x 2 x i64> @llvm.stepvector.nxv2i64()688 %step.mul = mul <vscale x 2 x i64> %step, splat (i64 u0xffffffffffffffff)689 %and = and <vscale x 2 x i64> %step.mul, splat (i64 u0xfffffffffffffff8)690 ret <vscale x 2 x i64> %and691}692 693; step values are multiple of 8, so lo 3 bits are known zero694define <vscale x 2 x i64> @lo_bits_known_zero() {695; CHECK-LABEL: lo_bits_known_zero:696; CHECK: # %bb.0:697; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma698; CHECK-NEXT: vmv.v.i v8, 0699; CHECK-NEXT: ret700 %step = call <vscale x 2 x i64> @llvm.stepvector.nxv2i64()701 %step.mul = mul <vscale x 2 x i64> %step, splat (i64 8)702 %and = and <vscale x 2 x i64> %step.mul, splat (i64 7)703 ret <vscale x 2 x i64> %and704}705