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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+v,+zvfh,+zvfbfmin,+optimized-zero-stride-load \3; RUN: -verify-machineinstrs < %s \4; RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-RV32,CHECK-OPT,CHECK-OPT-RV325; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+v,+zvfh,+zvfbfmin,+optimized-zero-stride-load \6; RUN: -verify-machineinstrs < %s \7; RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-RV64,CHECK-OPT,CHECK-OPT-RV648; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+v,+zvfh,+zvfbfmin \9; RUN: -verify-machineinstrs < %s \10; RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-RV32,CHECK-NO-OPT,CHECK-NO-OPT-ZVFH,CHECK-NO-OPT-RV3211; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+v,+zvfh,+zvfbfmin \12; RUN: -verify-machineinstrs < %s \13; RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-RV64,CHECK-NO-OPT,CHECK-NO-OPT-ZVFH,CHECK-NO-OPT-RV6414; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+v,+zvfhmin,+zvfbfmin,+optimized-zero-stride-load \15; RUN: -verify-machineinstrs < %s \16; RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-RV32,CHECK-OPT,CHECK-OPT-RV3217; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+v,+zvfhmin,+zvfbfmin,+optimized-zero-stride-load \18; RUN: -verify-machineinstrs < %s \19; RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-RV64,CHECK-OPT,CHECK-OPT-RV6420; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+v,+zvfhmin,+zvfbfmin \21; RUN: -verify-machineinstrs < %s \22; RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-RV32,CHECK-NO-OPT,CHECK-NO-OPT-ZVFHMIN,CHECK-NO-OPT-RV3223; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+v,+zvfhmin,+zvfbfmin \24; RUN: -verify-machineinstrs < %s \25; RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-RV64,CHECK-NO-OPT,CHECK-NO-OPT-ZVFHMIN,CHECK-NO-OPT-RV6426 27define <vscale x 1 x i8> @strided_vpload_nxv1i8_i8(ptr %ptr, i8 signext %stride, <vscale x 1 x i1> %m, i32 zeroext %evl) {28; CHECK-LABEL: strided_vpload_nxv1i8_i8:29; CHECK: # %bb.0:30; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, ma31; CHECK-NEXT: vlse8.v v8, (a0), a1, v0.t32; CHECK-NEXT: ret33 %load = call <vscale x 1 x i8> @llvm.experimental.vp.strided.load.nxv1i8.p0.i8(ptr %ptr, i8 %stride, <vscale x 1 x i1> %m, i32 %evl)34 ret <vscale x 1 x i8> %load35}36 37define <vscale x 1 x i8> @strided_vpload_nxv1i8_i16(ptr %ptr, i16 signext %stride, <vscale x 1 x i1> %m, i32 zeroext %evl) {38; CHECK-LABEL: strided_vpload_nxv1i8_i16:39; CHECK: # %bb.0:40; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, ma41; CHECK-NEXT: vlse8.v v8, (a0), a1, v0.t42; CHECK-NEXT: ret43 %load = call <vscale x 1 x i8> @llvm.experimental.vp.strided.load.nxv1i8.p0.i16(ptr %ptr, i16 %stride, <vscale x 1 x i1> %m, i32 %evl)44 ret <vscale x 1 x i8> %load45}46 47define <vscale x 1 x i8> @strided_vpload_nxv1i8_i64(ptr %ptr, i64 signext %stride, <vscale x 1 x i1> %m, i32 zeroext %evl) {48; CHECK-RV32-LABEL: strided_vpload_nxv1i8_i64:49; CHECK-RV32: # %bb.0:50; CHECK-RV32-NEXT: vsetvli zero, a3, e8, mf8, ta, ma51; CHECK-RV32-NEXT: vlse8.v v8, (a0), a1, v0.t52; CHECK-RV32-NEXT: ret53;54; CHECK-RV64-LABEL: strided_vpload_nxv1i8_i64:55; CHECK-RV64: # %bb.0:56; CHECK-RV64-NEXT: vsetvli zero, a2, e8, mf8, ta, ma57; CHECK-RV64-NEXT: vlse8.v v8, (a0), a1, v0.t58; CHECK-RV64-NEXT: ret59 %load = call <vscale x 1 x i8> @llvm.experimental.vp.strided.load.nxv1i8.p0.i64(ptr %ptr, i64 %stride, <vscale x 1 x i1> %m, i32 %evl)60 ret <vscale x 1 x i8> %load61}62 63define <vscale x 1 x i8> @strided_vpload_nxv1i8_i64_allones_mask(ptr %ptr, i64 signext %stride, i32 zeroext %evl) {64; CHECK-RV32-LABEL: strided_vpload_nxv1i8_i64_allones_mask:65; CHECK-RV32: # %bb.0:66; CHECK-RV32-NEXT: vsetvli zero, a3, e8, mf8, ta, ma67; CHECK-RV32-NEXT: vlse8.v v8, (a0), a168; CHECK-RV32-NEXT: ret69;70; CHECK-RV64-LABEL: strided_vpload_nxv1i8_i64_allones_mask:71; CHECK-RV64: # %bb.0:72; CHECK-RV64-NEXT: vsetvli zero, a2, e8, mf8, ta, ma73; CHECK-RV64-NEXT: vlse8.v v8, (a0), a174; CHECK-RV64-NEXT: ret75 %load = call <vscale x 1 x i8> @llvm.experimental.vp.strided.load.nxv1i8.p0.i64(ptr %ptr, i64 %stride, <vscale x 1 x i1> splat (i1 true), i32 %evl)76 ret <vscale x 1 x i8> %load77}78 79define <vscale x 1 x i8> @strided_vpload_nxv1i8(ptr %ptr, i32 signext %stride, <vscale x 1 x i1> %m, i32 zeroext %evl) {80; CHECK-LABEL: strided_vpload_nxv1i8:81; CHECK: # %bb.0:82; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, ma83; CHECK-NEXT: vlse8.v v8, (a0), a1, v0.t84; CHECK-NEXT: ret85 %load = call <vscale x 1 x i8> @llvm.experimental.vp.strided.load.nxv1i8.p0.i32(ptr %ptr, i32 signext %stride, <vscale x 1 x i1> %m, i32 %evl)86 ret <vscale x 1 x i8> %load87}88 89define <vscale x 1 x i8> @strided_vpload_nxv1i8_allones_mask(ptr %ptr, i32 signext %stride, i32 zeroext %evl) {90; CHECK-LABEL: strided_vpload_nxv1i8_allones_mask:91; CHECK: # %bb.0:92; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, ma93; CHECK-NEXT: vlse8.v v8, (a0), a194; CHECK-NEXT: ret95 %load = call <vscale x 1 x i8> @llvm.experimental.vp.strided.load.nxv1i8.p0.i32(ptr %ptr, i32 signext %stride, <vscale x 1 x i1> splat (i1 true), i32 %evl)96 ret <vscale x 1 x i8> %load97}98 99define <vscale x 2 x i8> @strided_vpload_nxv2i8(ptr %ptr, i32 signext %stride, <vscale x 2 x i1> %m, i32 zeroext %evl) {100; CHECK-LABEL: strided_vpload_nxv2i8:101; CHECK: # %bb.0:102; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, ma103; CHECK-NEXT: vlse8.v v8, (a0), a1, v0.t104; CHECK-NEXT: ret105 %load = call <vscale x 2 x i8> @llvm.experimental.vp.strided.load.nxv2i8.p0.i32(ptr %ptr, i32 signext %stride, <vscale x 2 x i1> %m, i32 %evl)106 ret <vscale x 2 x i8> %load107}108 109define <vscale x 4 x i8> @strided_vpload_nxv4i8(ptr %ptr, i32 signext %stride, <vscale x 4 x i1> %m, i32 zeroext %evl) {110; CHECK-LABEL: strided_vpload_nxv4i8:111; CHECK: # %bb.0:112; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, ma113; CHECK-NEXT: vlse8.v v8, (a0), a1, v0.t114; CHECK-NEXT: ret115 %load = call <vscale x 4 x i8> @llvm.experimental.vp.strided.load.nxv4i8.p0.i32(ptr %ptr, i32 signext %stride, <vscale x 4 x i1> %m, i32 %evl)116 ret <vscale x 4 x i8> %load117}118 119define <vscale x 8 x i8> @strided_vpload_nxv8i8(ptr %ptr, i32 signext %stride, <vscale x 8 x i1> %m, i32 zeroext %evl) {120; CHECK-LABEL: strided_vpload_nxv8i8:121; CHECK: # %bb.0:122; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, ma123; CHECK-NEXT: vlse8.v v8, (a0), a1, v0.t124; CHECK-NEXT: ret125 %load = call <vscale x 8 x i8> @llvm.experimental.vp.strided.load.nxv8i8.p0.i32(ptr %ptr, i32 signext %stride, <vscale x 8 x i1> %m, i32 %evl)126 ret <vscale x 8 x i8> %load127}128 129define <vscale x 8 x i8> @strided_vpload_nxv8i8_unit_stride(ptr %ptr, <vscale x 8 x i1> %m, i32 zeroext %evl) {130; CHECK-LABEL: strided_vpload_nxv8i8_unit_stride:131; CHECK: # %bb.0:132; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma133; CHECK-NEXT: vle8.v v8, (a0), v0.t134; CHECK-NEXT: ret135 %load = call <vscale x 8 x i8> @llvm.experimental.vp.strided.load.nxv8i8.p0.i32(ptr %ptr, i32 1, <vscale x 8 x i1> %m, i32 %evl)136 ret <vscale x 8 x i8> %load137}138 139define <vscale x 8 x i8> @strided_vpload_nxv8i8_allones_mask(ptr %ptr, i32 signext %stride, i32 zeroext %evl) {140; CHECK-LABEL: strided_vpload_nxv8i8_allones_mask:141; CHECK: # %bb.0:142; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, ma143; CHECK-NEXT: vlse8.v v8, (a0), a1144; CHECK-NEXT: ret145 %load = call <vscale x 8 x i8> @llvm.experimental.vp.strided.load.nxv8i8.p0.i32(ptr %ptr, i32 signext %stride, <vscale x 8 x i1> splat (i1 true), i32 %evl)146 ret <vscale x 8 x i8> %load147}148 149define <vscale x 1 x i16> @strided_vpload_nxv1i16(ptr %ptr, i32 signext %stride, <vscale x 1 x i1> %m, i32 zeroext %evl) {150; CHECK-LABEL: strided_vpload_nxv1i16:151; CHECK: # %bb.0:152; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, ma153; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t154; CHECK-NEXT: ret155 %load = call <vscale x 1 x i16> @llvm.experimental.vp.strided.load.nxv1i16.p0.i32(ptr %ptr, i32 signext %stride, <vscale x 1 x i1> %m, i32 %evl)156 ret <vscale x 1 x i16> %load157}158 159define <vscale x 2 x i16> @strided_vpload_nxv2i16(ptr %ptr, i32 signext %stride, <vscale x 2 x i1> %m, i32 zeroext %evl) {160; CHECK-LABEL: strided_vpload_nxv2i16:161; CHECK: # %bb.0:162; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, ma163; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t164; CHECK-NEXT: ret165 %load = call <vscale x 2 x i16> @llvm.experimental.vp.strided.load.nxv2i16.p0.i32(ptr %ptr, i32 signext %stride, <vscale x 2 x i1> %m, i32 %evl)166 ret <vscale x 2 x i16> %load167}168 169define <vscale x 2 x i16> @strided_vpload_nxv2i16_allones_mask(ptr %ptr, i32 signext %stride, i32 zeroext %evl) {170; CHECK-LABEL: strided_vpload_nxv2i16_allones_mask:171; CHECK: # %bb.0:172; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, ma173; CHECK-NEXT: vlse16.v v8, (a0), a1174; CHECK-NEXT: ret175 %load = call <vscale x 2 x i16> @llvm.experimental.vp.strided.load.nxv2i16.p0.i32(ptr %ptr, i32 signext %stride, <vscale x 2 x i1> splat (i1 true), i32 %evl)176 ret <vscale x 2 x i16> %load177}178 179define <vscale x 4 x i16> @strided_vpload_nxv4i16(ptr %ptr, i32 signext %stride, <vscale x 4 x i1> %m, i32 zeroext %evl) {180; CHECK-LABEL: strided_vpload_nxv4i16:181; CHECK: # %bb.0:182; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, ma183; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t184; CHECK-NEXT: ret185 %load = call <vscale x 4 x i16> @llvm.experimental.vp.strided.load.nxv4i16.p0.i32(ptr %ptr, i32 signext %stride, <vscale x 4 x i1> %m, i32 %evl)186 ret <vscale x 4 x i16> %load187}188 189define <vscale x 4 x i16> @strided_vpload_nxv4i16_unit_stride(ptr %ptr, <vscale x 4 x i1> %m, i32 zeroext %evl) {190; CHECK-LABEL: strided_vpload_nxv4i16_unit_stride:191; CHECK: # %bb.0:192; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma193; CHECK-NEXT: vle16.v v8, (a0), v0.t194; CHECK-NEXT: ret195 %load = call <vscale x 4 x i16> @llvm.experimental.vp.strided.load.nxv4i16.p0.i32(ptr %ptr, i32 2, <vscale x 4 x i1> %m, i32 %evl)196 ret <vscale x 4 x i16> %load197}198 199define <vscale x 8 x i16> @strided_vpload_nxv8i16(ptr %ptr, i32 signext %stride, <vscale x 8 x i1> %m, i32 zeroext %evl) {200; CHECK-LABEL: strided_vpload_nxv8i16:201; CHECK: # %bb.0:202; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, ma203; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t204; CHECK-NEXT: ret205 %load = call <vscale x 8 x i16> @llvm.experimental.vp.strided.load.nxv8i16.p0.i32(ptr %ptr, i32 signext %stride, <vscale x 8 x i1> %m, i32 %evl)206 ret <vscale x 8 x i16> %load207}208 209define <vscale x 1 x i32> @strided_vpload_nxv1i32(ptr %ptr, i32 signext %stride, <vscale x 1 x i1> %m, i32 zeroext %evl) {210; CHECK-LABEL: strided_vpload_nxv1i32:211; CHECK: # %bb.0:212; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, ma213; CHECK-NEXT: vlse32.v v8, (a0), a1, v0.t214; CHECK-NEXT: ret215 %load = call <vscale x 1 x i32> @llvm.experimental.vp.strided.load.nxv1i32.p0.i32(ptr %ptr, i32 signext %stride, <vscale x 1 x i1> %m, i32 %evl)216 ret <vscale x 1 x i32> %load217}218 219define <vscale x 2 x i32> @strided_vpload_nxv2i32(ptr %ptr, i32 signext %stride, <vscale x 2 x i1> %m, i32 zeroext %evl) {220; CHECK-LABEL: strided_vpload_nxv2i32:221; CHECK: # %bb.0:222; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, ma223; CHECK-NEXT: vlse32.v v8, (a0), a1, v0.t224; CHECK-NEXT: ret225 %load = call <vscale x 2 x i32> @llvm.experimental.vp.strided.load.nxv2i32.p0.i32(ptr %ptr, i32 signext %stride, <vscale x 2 x i1> %m, i32 %evl)226 ret <vscale x 2 x i32> %load227}228 229define <vscale x 2 x i32> @strided_vpload_nxv2i32_unit_stride(ptr %ptr, <vscale x 2 x i1> %m, i32 zeroext %evl) {230; CHECK-LABEL: strided_vpload_nxv2i32_unit_stride:231; CHECK: # %bb.0:232; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma233; CHECK-NEXT: vle32.v v8, (a0), v0.t234; CHECK-NEXT: ret235 %load = call <vscale x 2 x i32> @llvm.experimental.vp.strided.load.nxv2i32.p0.i32(ptr %ptr, i32 4, <vscale x 2 x i1> %m, i32 %evl)236 ret <vscale x 2 x i32> %load237}238 239define <vscale x 4 x i32> @strided_vpload_nxv4i32(ptr %ptr, i32 signext %stride, <vscale x 4 x i1> %m, i32 zeroext %evl) {240; CHECK-LABEL: strided_vpload_nxv4i32:241; CHECK: # %bb.0:242; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, ma243; CHECK-NEXT: vlse32.v v8, (a0), a1, v0.t244; CHECK-NEXT: ret245 %load = call <vscale x 4 x i32> @llvm.experimental.vp.strided.load.nxv4i32.p0.i32(ptr %ptr, i32 signext %stride, <vscale x 4 x i1> %m, i32 %evl)246 ret <vscale x 4 x i32> %load247}248 249define <vscale x 4 x i32> @strided_vpload_nxv4i32_allones_mask(ptr %ptr, i32 signext %stride, i32 zeroext %evl) {250; CHECK-LABEL: strided_vpload_nxv4i32_allones_mask:251; CHECK: # %bb.0:252; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, ma253; CHECK-NEXT: vlse32.v v8, (a0), a1254; CHECK-NEXT: ret255 %load = call <vscale x 4 x i32> @llvm.experimental.vp.strided.load.nxv4i32.p0.i32(ptr %ptr, i32 signext %stride, <vscale x 4 x i1> splat (i1 true), i32 %evl)256 ret <vscale x 4 x i32> %load257}258 259define <vscale x 8 x i32> @strided_vpload_nxv8i32(ptr %ptr, i32 signext %stride, <vscale x 8 x i1> %m, i32 zeroext %evl) {260; CHECK-LABEL: strided_vpload_nxv8i32:261; CHECK: # %bb.0:262; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, ma263; CHECK-NEXT: vlse32.v v8, (a0), a1, v0.t264; CHECK-NEXT: ret265 %load = call <vscale x 8 x i32> @llvm.experimental.vp.strided.load.nxv8i32.p0.i32(ptr %ptr, i32 signext %stride, <vscale x 8 x i1> %m, i32 %evl)266 ret <vscale x 8 x i32> %load267}268 269define <vscale x 1 x i64> @strided_vpload_nxv1i64(ptr %ptr, i32 signext %stride, <vscale x 1 x i1> %m, i32 zeroext %evl) {270; CHECK-LABEL: strided_vpload_nxv1i64:271; CHECK: # %bb.0:272; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, ma273; CHECK-NEXT: vlse64.v v8, (a0), a1, v0.t274; CHECK-NEXT: ret275 %load = call <vscale x 1 x i64> @llvm.experimental.vp.strided.load.nxv1i64.p0.i32(ptr %ptr, i32 signext %stride, <vscale x 1 x i1> %m, i32 %evl)276 ret <vscale x 1 x i64> %load277}278 279define <vscale x 1 x i64> @strided_vpload_nxv1i64_unit_stride(ptr %ptr, <vscale x 1 x i1> %m, i32 zeroext %evl) {280; CHECK-LABEL: strided_vpload_nxv1i64_unit_stride:281; CHECK: # %bb.0:282; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma283; CHECK-NEXT: vle64.v v8, (a0), v0.t284; CHECK-NEXT: ret285 %load = call <vscale x 1 x i64> @llvm.experimental.vp.strided.load.nxv1i64.p0.i32(ptr %ptr, i32 8, <vscale x 1 x i1> %m, i32 %evl)286 ret <vscale x 1 x i64> %load287}288 289define <vscale x 1 x i64> @strided_vpload_nxv1i64_allones_mask(ptr %ptr, i32 signext %stride, i32 zeroext %evl) {290; CHECK-LABEL: strided_vpload_nxv1i64_allones_mask:291; CHECK: # %bb.0:292; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, ma293; CHECK-NEXT: vlse64.v v8, (a0), a1294; CHECK-NEXT: ret295 %load = call <vscale x 1 x i64> @llvm.experimental.vp.strided.load.nxv1i64.p0.i32(ptr %ptr, i32 signext %stride, <vscale x 1 x i1> splat (i1 true), i32 %evl)296 ret <vscale x 1 x i64> %load297}298 299define <vscale x 2 x i64> @strided_vpload_nxv2i64(ptr %ptr, i32 signext %stride, <vscale x 2 x i1> %m, i32 zeroext %evl) {300; CHECK-LABEL: strided_vpload_nxv2i64:301; CHECK: # %bb.0:302; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, ma303; CHECK-NEXT: vlse64.v v8, (a0), a1, v0.t304; CHECK-NEXT: ret305 %load = call <vscale x 2 x i64> @llvm.experimental.vp.strided.load.nxv2i64.p0.i32(ptr %ptr, i32 signext %stride, <vscale x 2 x i1> %m, i32 %evl)306 ret <vscale x 2 x i64> %load307}308 309define <vscale x 4 x i64> @strided_vpload_nxv4i64(ptr %ptr, i32 signext %stride, <vscale x 4 x i1> %m, i32 zeroext %evl) {310; CHECK-LABEL: strided_vpload_nxv4i64:311; CHECK: # %bb.0:312; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, ma313; CHECK-NEXT: vlse64.v v8, (a0), a1, v0.t314; CHECK-NEXT: ret315 %load = call <vscale x 4 x i64> @llvm.experimental.vp.strided.load.nxv4i64.p0.i32(ptr %ptr, i32 signext %stride, <vscale x 4 x i1> %m, i32 %evl)316 ret <vscale x 4 x i64> %load317}318 319define <vscale x 8 x i64> @strided_vpload_nxv8i64(ptr %ptr, i32 signext %stride, <vscale x 8 x i1> %m, i32 zeroext %evl) {320; CHECK-LABEL: strided_vpload_nxv8i64:321; CHECK: # %bb.0:322; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma323; CHECK-NEXT: vlse64.v v8, (a0), a1, v0.t324; CHECK-NEXT: ret325 %load = call <vscale x 8 x i64> @llvm.experimental.vp.strided.load.nxv8i64.p0.i32(ptr %ptr, i32 signext %stride, <vscale x 8 x i1> %m, i32 %evl)326 ret <vscale x 8 x i64> %load327}328 329define <vscale x 1 x bfloat> @strided_vpload_nxv1bf16(ptr %ptr, i32 signext %stride, <vscale x 1 x i1> %m, i32 zeroext %evl) {330; CHECK-LABEL: strided_vpload_nxv1bf16:331; CHECK: # %bb.0:332; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, ma333; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t334; CHECK-NEXT: ret335 %load = call <vscale x 1 x bfloat> @llvm.experimental.vp.strided.load.nxv1bf16.p0.i32(ptr %ptr, i32 signext %stride, <vscale x 1 x i1> %m, i32 %evl)336 ret <vscale x 1 x bfloat> %load337}338 339define <vscale x 2 x bfloat> @strided_vpload_nxv2bf16(ptr %ptr, i32 signext %stride, <vscale x 2 x i1> %m, i32 zeroext %evl) {340; CHECK-LABEL: strided_vpload_nxv2bf16:341; CHECK: # %bb.0:342; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, ma343; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t344; CHECK-NEXT: ret345 %load = call <vscale x 2 x bfloat> @llvm.experimental.vp.strided.load.nxv2bf16.p0.i32(ptr %ptr, i32 signext %stride, <vscale x 2 x i1> %m, i32 %evl)346 ret <vscale x 2 x bfloat> %load347}348 349define <vscale x 2 x bfloat> @strided_vpload_nxv2bf16_allones_mask(ptr %ptr, i32 signext %stride, i32 zeroext %evl) {350; CHECK-LABEL: strided_vpload_nxv2bf16_allones_mask:351; CHECK: # %bb.0:352; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, ma353; CHECK-NEXT: vlse16.v v8, (a0), a1354; CHECK-NEXT: ret355 %load = call <vscale x 2 x bfloat> @llvm.experimental.vp.strided.load.nxv2bf16.p0.i32(ptr %ptr, i32 signext %stride, <vscale x 2 x i1> splat (i1 true), i32 %evl)356 ret <vscale x 2 x bfloat> %load357}358 359define <vscale x 4 x bfloat> @strided_vpload_nxv4bf16(ptr %ptr, i32 signext %stride, <vscale x 4 x i1> %m, i32 zeroext %evl) {360; CHECK-LABEL: strided_vpload_nxv4bf16:361; CHECK: # %bb.0:362; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, ma363; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t364; CHECK-NEXT: ret365 %load = call <vscale x 4 x bfloat> @llvm.experimental.vp.strided.load.nxv4bf16.p0.i32(ptr %ptr, i32 signext %stride, <vscale x 4 x i1> %m, i32 %evl)366 ret <vscale x 4 x bfloat> %load367}368 369define <vscale x 4 x bfloat> @strided_vpload_nxv4bf16_unit_stride(ptr %ptr, <vscale x 4 x i1> %m, i32 zeroext %evl) {370; CHECK-LABEL: strided_vpload_nxv4bf16_unit_stride:371; CHECK: # %bb.0:372; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma373; CHECK-NEXT: vle16.v v8, (a0), v0.t374; CHECK-NEXT: ret375 %load = call <vscale x 4 x bfloat> @llvm.experimental.vp.strided.load.nxv4bf16.p0.i32(ptr %ptr, i32 2, <vscale x 4 x i1> %m, i32 %evl)376 ret <vscale x 4 x bfloat> %load377}378 379define <vscale x 8 x bfloat> @strided_vpload_nxv8bf16(ptr %ptr, i32 signext %stride, <vscale x 8 x i1> %m, i32 zeroext %evl) {380; CHECK-LABEL: strided_vpload_nxv8bf16:381; CHECK: # %bb.0:382; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, ma383; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t384; CHECK-NEXT: ret385 %load = call <vscale x 8 x bfloat> @llvm.experimental.vp.strided.load.nxv8bf16.p0.i32(ptr %ptr, i32 signext %stride, <vscale x 8 x i1> %m, i32 %evl)386 ret <vscale x 8 x bfloat> %load387}388 389define <vscale x 1 x half> @strided_vpload_nxv1f16(ptr %ptr, i32 signext %stride, <vscale x 1 x i1> %m, i32 zeroext %evl) {390; CHECK-LABEL: strided_vpload_nxv1f16:391; CHECK: # %bb.0:392; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, ma393; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t394; CHECK-NEXT: ret395 %load = call <vscale x 1 x half> @llvm.experimental.vp.strided.load.nxv1f16.p0.i32(ptr %ptr, i32 signext %stride, <vscale x 1 x i1> %m, i32 %evl)396 ret <vscale x 1 x half> %load397}398 399define <vscale x 2 x half> @strided_vpload_nxv2f16(ptr %ptr, i32 signext %stride, <vscale x 2 x i1> %m, i32 zeroext %evl) {400; CHECK-LABEL: strided_vpload_nxv2f16:401; CHECK: # %bb.0:402; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, ma403; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t404; CHECK-NEXT: ret405 %load = call <vscale x 2 x half> @llvm.experimental.vp.strided.load.nxv2f16.p0.i32(ptr %ptr, i32 signext %stride, <vscale x 2 x i1> %m, i32 %evl)406 ret <vscale x 2 x half> %load407}408 409define <vscale x 2 x half> @strided_vpload_nxv2f16_allones_mask(ptr %ptr, i32 signext %stride, i32 zeroext %evl) {410; CHECK-LABEL: strided_vpload_nxv2f16_allones_mask:411; CHECK: # %bb.0:412; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, ma413; CHECK-NEXT: vlse16.v v8, (a0), a1414; CHECK-NEXT: ret415 %load = call <vscale x 2 x half> @llvm.experimental.vp.strided.load.nxv2f16.p0.i32(ptr %ptr, i32 signext %stride, <vscale x 2 x i1> splat (i1 true), i32 %evl)416 ret <vscale x 2 x half> %load417}418 419define <vscale x 4 x half> @strided_vpload_nxv4f16(ptr %ptr, i32 signext %stride, <vscale x 4 x i1> %m, i32 zeroext %evl) {420; CHECK-LABEL: strided_vpload_nxv4f16:421; CHECK: # %bb.0:422; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, ma423; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t424; CHECK-NEXT: ret425 %load = call <vscale x 4 x half> @llvm.experimental.vp.strided.load.nxv4f16.p0.i32(ptr %ptr, i32 signext %stride, <vscale x 4 x i1> %m, i32 %evl)426 ret <vscale x 4 x half> %load427}428 429define <vscale x 4 x half> @strided_vpload_nxv4f16_unit_stride(ptr %ptr, <vscale x 4 x i1> %m, i32 zeroext %evl) {430; CHECK-LABEL: strided_vpload_nxv4f16_unit_stride:431; CHECK: # %bb.0:432; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma433; CHECK-NEXT: vle16.v v8, (a0), v0.t434; CHECK-NEXT: ret435 %load = call <vscale x 4 x half> @llvm.experimental.vp.strided.load.nxv4f16.p0.i32(ptr %ptr, i32 2, <vscale x 4 x i1> %m, i32 %evl)436 ret <vscale x 4 x half> %load437}438 439define <vscale x 8 x half> @strided_vpload_nxv8f16(ptr %ptr, i32 signext %stride, <vscale x 8 x i1> %m, i32 zeroext %evl) {440; CHECK-LABEL: strided_vpload_nxv8f16:441; CHECK: # %bb.0:442; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, ma443; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t444; CHECK-NEXT: ret445 %load = call <vscale x 8 x half> @llvm.experimental.vp.strided.load.nxv8f16.p0.i32(ptr %ptr, i32 signext %stride, <vscale x 8 x i1> %m, i32 %evl)446 ret <vscale x 8 x half> %load447}448 449define <vscale x 1 x float> @strided_vpload_nxv1f32(ptr %ptr, i32 signext %stride, <vscale x 1 x i1> %m, i32 zeroext %evl) {450; CHECK-LABEL: strided_vpload_nxv1f32:451; CHECK: # %bb.0:452; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, ma453; CHECK-NEXT: vlse32.v v8, (a0), a1, v0.t454; CHECK-NEXT: ret455 %load = call <vscale x 1 x float> @llvm.experimental.vp.strided.load.nxv1f32.p0.i32(ptr %ptr, i32 signext %stride, <vscale x 1 x i1> %m, i32 %evl)456 ret <vscale x 1 x float> %load457}458 459define <vscale x 2 x float> @strided_vpload_nxv2f32(ptr %ptr, i32 signext %stride, <vscale x 2 x i1> %m, i32 zeroext %evl) {460; CHECK-LABEL: strided_vpload_nxv2f32:461; CHECK: # %bb.0:462; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, ma463; CHECK-NEXT: vlse32.v v8, (a0), a1, v0.t464; CHECK-NEXT: ret465 %load = call <vscale x 2 x float> @llvm.experimental.vp.strided.load.nxv2f32.p0.i32(ptr %ptr, i32 signext %stride, <vscale x 2 x i1> %m, i32 %evl)466 ret <vscale x 2 x float> %load467}468 469define <vscale x 2 x float> @strided_vpload_nxv2f32_unit_stride(ptr %ptr, <vscale x 2 x i1> %m, i32 zeroext %evl) {470; CHECK-LABEL: strided_vpload_nxv2f32_unit_stride:471; CHECK: # %bb.0:472; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma473; CHECK-NEXT: vle32.v v8, (a0), v0.t474; CHECK-NEXT: ret475 %load = call <vscale x 2 x float> @llvm.experimental.vp.strided.load.nxv2f32.p0.i32(ptr %ptr, i32 4, <vscale x 2 x i1> %m, i32 %evl)476 ret <vscale x 2 x float> %load477}478 479define <vscale x 4 x float> @strided_vpload_nxv4f32(ptr %ptr, i32 signext %stride, <vscale x 4 x i1> %m, i32 zeroext %evl) {480; CHECK-LABEL: strided_vpload_nxv4f32:481; CHECK: # %bb.0:482; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, ma483; CHECK-NEXT: vlse32.v v8, (a0), a1, v0.t484; CHECK-NEXT: ret485 %load = call <vscale x 4 x float> @llvm.experimental.vp.strided.load.nxv4f32.p0.i32(ptr %ptr, i32 signext %stride, <vscale x 4 x i1> %m, i32 %evl)486 ret <vscale x 4 x float> %load487}488 489define <vscale x 8 x float> @strided_vpload_nxv8f32(ptr %ptr, i32 signext %stride, <vscale x 8 x i1> %m, i32 zeroext %evl) {490; CHECK-LABEL: strided_vpload_nxv8f32:491; CHECK: # %bb.0:492; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, ma493; CHECK-NEXT: vlse32.v v8, (a0), a1, v0.t494; CHECK-NEXT: ret495 %load = call <vscale x 8 x float> @llvm.experimental.vp.strided.load.nxv8f32.p0.i32(ptr %ptr, i32 signext %stride, <vscale x 8 x i1> %m, i32 %evl)496 ret <vscale x 8 x float> %load497}498 499define <vscale x 8 x float> @strided_vpload_nxv8f32_allones_mask(ptr %ptr, i32 signext %stride, i32 zeroext %evl) {500; CHECK-LABEL: strided_vpload_nxv8f32_allones_mask:501; CHECK: # %bb.0:502; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, ma503; CHECK-NEXT: vlse32.v v8, (a0), a1504; CHECK-NEXT: ret505 %load = call <vscale x 8 x float> @llvm.experimental.vp.strided.load.nxv8f32.p0.i32(ptr %ptr, i32 signext %stride, <vscale x 8 x i1> splat (i1 true), i32 %evl)506 ret <vscale x 8 x float> %load507}508 509define <vscale x 1 x double> @strided_vpload_nxv1f64(ptr %ptr, i32 signext %stride, <vscale x 1 x i1> %m, i32 zeroext %evl) {510; CHECK-LABEL: strided_vpload_nxv1f64:511; CHECK: # %bb.0:512; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, ma513; CHECK-NEXT: vlse64.v v8, (a0), a1, v0.t514; CHECK-NEXT: ret515 %load = call <vscale x 1 x double> @llvm.experimental.vp.strided.load.nxv1f64.p0.i32(ptr %ptr, i32 signext %stride, <vscale x 1 x i1> %m, i32 %evl)516 ret <vscale x 1 x double> %load517}518 519define <vscale x 1 x double> @strided_vpload_nxv1f64_unit_stride(ptr %ptr, <vscale x 1 x i1> %m, i32 zeroext %evl) {520; CHECK-LABEL: strided_vpload_nxv1f64_unit_stride:521; CHECK: # %bb.0:522; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma523; CHECK-NEXT: vle64.v v8, (a0), v0.t524; CHECK-NEXT: ret525 %load = call <vscale x 1 x double> @llvm.experimental.vp.strided.load.nxv1f64.p0.i32(ptr %ptr, i32 8, <vscale x 1 x i1> %m, i32 %evl)526 ret <vscale x 1 x double> %load527}528 529define <vscale x 2 x double> @strided_vpload_nxv2f64(ptr %ptr, i32 signext %stride, <vscale x 2 x i1> %m, i32 zeroext %evl) {530; CHECK-LABEL: strided_vpload_nxv2f64:531; CHECK: # %bb.0:532; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, ma533; CHECK-NEXT: vlse64.v v8, (a0), a1, v0.t534; CHECK-NEXT: ret535 %load = call <vscale x 2 x double> @llvm.experimental.vp.strided.load.nxv2f64.p0.i32(ptr %ptr, i32 signext %stride, <vscale x 2 x i1> %m, i32 %evl)536 ret <vscale x 2 x double> %load537}538 539define <vscale x 4 x double> @strided_vpload_nxv4f64(ptr %ptr, i32 signext %stride, <vscale x 4 x i1> %m, i32 zeroext %evl) {540; CHECK-LABEL: strided_vpload_nxv4f64:541; CHECK: # %bb.0:542; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, ma543; CHECK-NEXT: vlse64.v v8, (a0), a1, v0.t544; CHECK-NEXT: ret545 %load = call <vscale x 4 x double> @llvm.experimental.vp.strided.load.nxv4f64.p0.i32(ptr %ptr, i32 signext %stride, <vscale x 4 x i1> %m, i32 %evl)546 ret <vscale x 4 x double> %load547}548 549define <vscale x 4 x double> @strided_vpload_nxv4f64_allones_mask(ptr %ptr, i32 signext %stride, i32 zeroext %evl) {550; CHECK-LABEL: strided_vpload_nxv4f64_allones_mask:551; CHECK: # %bb.0:552; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, ma553; CHECK-NEXT: vlse64.v v8, (a0), a1554; CHECK-NEXT: ret555 %load = call <vscale x 4 x double> @llvm.experimental.vp.strided.load.nxv4f64.p0.i32(ptr %ptr, i32 signext %stride, <vscale x 4 x i1> splat (i1 true), i32 %evl)556 ret <vscale x 4 x double> %load557}558 559define <vscale x 8 x double> @strided_vpload_nxv8f64(ptr %ptr, i32 signext %stride, <vscale x 8 x i1> %m, i32 zeroext %evl) {560; CHECK-LABEL: strided_vpload_nxv8f64:561; CHECK: # %bb.0:562; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma563; CHECK-NEXT: vlse64.v v8, (a0), a1, v0.t564; CHECK-NEXT: ret565 %load = call <vscale x 8 x double> @llvm.experimental.vp.strided.load.nxv8f64.p0.i32(ptr %ptr, i32 signext %stride, <vscale x 8 x i1> %m, i32 %evl)566 ret <vscale x 8 x double> %load567}568 569; Widening570define <vscale x 3 x double> @strided_vpload_nxv3f64(ptr %ptr, i32 signext %stride, <vscale x 3 x i1> %mask, i32 zeroext %evl) {571; CHECK-LABEL: strided_vpload_nxv3f64:572; CHECK: # %bb.0:573; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, ma574; CHECK-NEXT: vlse64.v v8, (a0), a1, v0.t575; CHECK-NEXT: ret576 %v = call <vscale x 3 x double> @llvm.experimental.vp.strided.load.nxv3f64.p0.i32(ptr %ptr, i32 %stride, <vscale x 3 x i1> %mask, i32 %evl)577 ret <vscale x 3 x double> %v578}579 580define <vscale x 3 x double> @strided_vpload_nxv3f64_allones_mask(ptr %ptr, i32 signext %stride, i32 zeroext %evl) {581; CHECK-LABEL: strided_vpload_nxv3f64_allones_mask:582; CHECK: # %bb.0:583; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, ma584; CHECK-NEXT: vlse64.v v8, (a0), a1585; CHECK-NEXT: ret586 %v = call <vscale x 3 x double> @llvm.experimental.vp.strided.load.nxv3f64.p0.i32(ptr %ptr, i32 %stride, <vscale x 3 x i1> splat (i1 true), i32 %evl)587 ret <vscale x 3 x double> %v588}589 590; Splitting591define <vscale x 16 x double> @strided_load_nxv16f64(ptr %ptr, i64 %stride, <vscale x 16 x i1> %mask, i32 zeroext %evl) {592; CHECK-RV32-LABEL: strided_load_nxv16f64:593; CHECK-RV32: # %bb.0:594; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma595; CHECK-RV32-NEXT: vmv1r.v v9, v0596; CHECK-RV32-NEXT: csrr a4, vlenb597; CHECK-RV32-NEXT: sub a2, a3, a4598; CHECK-RV32-NEXT: sltu a5, a3, a2599; CHECK-RV32-NEXT: addi a5, a5, -1600; CHECK-RV32-NEXT: and a2, a5, a2601; CHECK-RV32-NEXT: bltu a3, a4, .LBB55_2602; CHECK-RV32-NEXT: # %bb.1:603; CHECK-RV32-NEXT: mv a3, a4604; CHECK-RV32-NEXT: .LBB55_2:605; CHECK-RV32-NEXT: mul a5, a3, a1606; CHECK-RV32-NEXT: srli a4, a4, 3607; CHECK-RV32-NEXT: vsetvli a6, zero, e8, mf4, ta, ma608; CHECK-RV32-NEXT: vslidedown.vx v8, v9, a4609; CHECK-RV32-NEXT: add a5, a0, a5610; CHECK-RV32-NEXT: vmv1r.v v0, v8611; CHECK-RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma612; CHECK-RV32-NEXT: vlse64.v v16, (a5), a1, v0.t613; CHECK-RV32-NEXT: vmv1r.v v0, v9614; CHECK-RV32-NEXT: vsetvli zero, a3, e64, m8, ta, ma615; CHECK-RV32-NEXT: vlse64.v v8, (a0), a1, v0.t616; CHECK-RV32-NEXT: ret617;618; CHECK-RV64-LABEL: strided_load_nxv16f64:619; CHECK-RV64: # %bb.0:620; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma621; CHECK-RV64-NEXT: vmv1r.v v9, v0622; CHECK-RV64-NEXT: csrr a4, vlenb623; CHECK-RV64-NEXT: sub a3, a2, a4624; CHECK-RV64-NEXT: sltu a5, a2, a3625; CHECK-RV64-NEXT: addi a5, a5, -1626; CHECK-RV64-NEXT: and a3, a5, a3627; CHECK-RV64-NEXT: bltu a2, a4, .LBB55_2628; CHECK-RV64-NEXT: # %bb.1:629; CHECK-RV64-NEXT: mv a2, a4630; CHECK-RV64-NEXT: .LBB55_2:631; CHECK-RV64-NEXT: mul a5, a2, a1632; CHECK-RV64-NEXT: srli a4, a4, 3633; CHECK-RV64-NEXT: vsetvli a6, zero, e8, mf4, ta, ma634; CHECK-RV64-NEXT: vslidedown.vx v8, v9, a4635; CHECK-RV64-NEXT: add a5, a0, a5636; CHECK-RV64-NEXT: vmv1r.v v0, v8637; CHECK-RV64-NEXT: vsetvli zero, a3, e64, m8, ta, ma638; CHECK-RV64-NEXT: vlse64.v v16, (a5), a1, v0.t639; CHECK-RV64-NEXT: vmv1r.v v0, v9640; CHECK-RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma641; CHECK-RV64-NEXT: vlse64.v v8, (a0), a1, v0.t642; CHECK-RV64-NEXT: ret643 %v = call <vscale x 16 x double> @llvm.experimental.vp.strided.load.nxv16f64.p0.i64(ptr %ptr, i64 %stride, <vscale x 16 x i1> %mask, i32 %evl)644 ret <vscale x 16 x double> %v645}646 647define <vscale x 16 x double> @strided_load_nxv16f64_allones_mask(ptr %ptr, i64 %stride, i32 zeroext %evl) {648; CHECK-RV32-LABEL: strided_load_nxv16f64_allones_mask:649; CHECK-RV32: # %bb.0:650; CHECK-RV32-NEXT: csrr a4, vlenb651; CHECK-RV32-NEXT: sub a2, a3, a4652; CHECK-RV32-NEXT: sltu a5, a3, a2653; CHECK-RV32-NEXT: addi a5, a5, -1654; CHECK-RV32-NEXT: and a2, a5, a2655; CHECK-RV32-NEXT: bltu a3, a4, .LBB56_2656; CHECK-RV32-NEXT: # %bb.1:657; CHECK-RV32-NEXT: mv a3, a4658; CHECK-RV32-NEXT: .LBB56_2:659; CHECK-RV32-NEXT: mul a4, a3, a1660; CHECK-RV32-NEXT: add a4, a0, a4661; CHECK-RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma662; CHECK-RV32-NEXT: vlse64.v v16, (a4), a1663; CHECK-RV32-NEXT: vsetvli zero, a3, e64, m8, ta, ma664; CHECK-RV32-NEXT: vlse64.v v8, (a0), a1665; CHECK-RV32-NEXT: ret666;667; CHECK-RV64-LABEL: strided_load_nxv16f64_allones_mask:668; CHECK-RV64: # %bb.0:669; CHECK-RV64-NEXT: csrr a4, vlenb670; CHECK-RV64-NEXT: sub a3, a2, a4671; CHECK-RV64-NEXT: sltu a5, a2, a3672; CHECK-RV64-NEXT: addi a5, a5, -1673; CHECK-RV64-NEXT: and a3, a5, a3674; CHECK-RV64-NEXT: bltu a2, a4, .LBB56_2675; CHECK-RV64-NEXT: # %bb.1:676; CHECK-RV64-NEXT: mv a2, a4677; CHECK-RV64-NEXT: .LBB56_2:678; CHECK-RV64-NEXT: mul a4, a2, a1679; CHECK-RV64-NEXT: add a4, a0, a4680; CHECK-RV64-NEXT: vsetvli zero, a3, e64, m8, ta, ma681; CHECK-RV64-NEXT: vlse64.v v16, (a4), a1682; CHECK-RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma683; CHECK-RV64-NEXT: vlse64.v v8, (a0), a1684; CHECK-RV64-NEXT: ret685 %v = call <vscale x 16 x double> @llvm.experimental.vp.strided.load.nxv16f64.p0.i64(ptr %ptr, i64 %stride, <vscale x 16 x i1> splat (i1 true), i32 %evl)686 ret <vscale x 16 x double> %v687}688 689; Widening + splitting (with HiIsEmpty == true)690; NOTE: We can't return <vscale x 17 x double> as that introduces a vector691; store that can't yet be legalized through widening. In order to test purely692; the vp.strided.load legalization, we manually split it.693define <vscale x 16 x double> @strided_load_nxv17f64(ptr %ptr, i64 %stride, <vscale x 17 x i1> %mask, i32 zeroext %evl, ptr %hi_ptr) {694; CHECK-RV32-LABEL: strided_load_nxv17f64:695; CHECK-RV32: # %bb.0:696; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma697; CHECK-RV32-NEXT: vmv1r.v v8, v0698; CHECK-RV32-NEXT: csrr a2, vlenb699; CHECK-RV32-NEXT: slli a7, a2, 1700; CHECK-RV32-NEXT: mv a6, a3701; CHECK-RV32-NEXT: bltu a3, a7, .LBB57_2702; CHECK-RV32-NEXT: # %bb.1:703; CHECK-RV32-NEXT: mv a6, a7704; CHECK-RV32-NEXT: .LBB57_2:705; CHECK-RV32-NEXT: sub a5, a6, a2706; CHECK-RV32-NEXT: sltu t0, a6, a5707; CHECK-RV32-NEXT: addi t0, t0, -1708; CHECK-RV32-NEXT: and t0, t0, a5709; CHECK-RV32-NEXT: mv a5, a6710; CHECK-RV32-NEXT: bltu a6, a2, .LBB57_4711; CHECK-RV32-NEXT: # %bb.3:712; CHECK-RV32-NEXT: mv a5, a2713; CHECK-RV32-NEXT: .LBB57_4:714; CHECK-RV32-NEXT: mul t1, a5, a1715; CHECK-RV32-NEXT: srli t2, a2, 3716; CHECK-RV32-NEXT: sub a7, a3, a7717; CHECK-RV32-NEXT: vsetvli t3, zero, e8, mf4, ta, ma718; CHECK-RV32-NEXT: vslidedown.vx v0, v8, t2719; CHECK-RV32-NEXT: add t1, a0, t1720; CHECK-RV32-NEXT: vsetvli zero, t0, e64, m8, ta, ma721; CHECK-RV32-NEXT: vlse64.v v16, (t1), a1, v0.t722; CHECK-RV32-NEXT: sltu a3, a3, a7723; CHECK-RV32-NEXT: addi a3, a3, -1724; CHECK-RV32-NEXT: and a3, a3, a7725; CHECK-RV32-NEXT: bltu a3, a2, .LBB57_6726; CHECK-RV32-NEXT: # %bb.5:727; CHECK-RV32-NEXT: mv a3, a2728; CHECK-RV32-NEXT: .LBB57_6:729; CHECK-RV32-NEXT: mul a6, a6, a1730; CHECK-RV32-NEXT: srli a2, a2, 2731; CHECK-RV32-NEXT: vsetvli a7, zero, e8, mf2, ta, ma732; CHECK-RV32-NEXT: vslidedown.vx v0, v8, a2733; CHECK-RV32-NEXT: add a6, a0, a6734; CHECK-RV32-NEXT: vsetvli zero, a3, e64, m8, ta, ma735; CHECK-RV32-NEXT: vlse64.v v24, (a6), a1, v0.t736; CHECK-RV32-NEXT: vmv1r.v v0, v8737; CHECK-RV32-NEXT: vsetvli zero, a5, e64, m8, ta, ma738; CHECK-RV32-NEXT: vlse64.v v8, (a0), a1, v0.t739; CHECK-RV32-NEXT: vs1r.v v24, (a4)740; CHECK-RV32-NEXT: ret741;742; CHECK-RV64-LABEL: strided_load_nxv17f64:743; CHECK-RV64: # %bb.0:744; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma745; CHECK-RV64-NEXT: vmv1r.v v8, v0746; CHECK-RV64-NEXT: csrr a4, vlenb747; CHECK-RV64-NEXT: slli a7, a4, 1748; CHECK-RV64-NEXT: mv a6, a2749; CHECK-RV64-NEXT: bltu a2, a7, .LBB57_2750; CHECK-RV64-NEXT: # %bb.1:751; CHECK-RV64-NEXT: mv a6, a7752; CHECK-RV64-NEXT: .LBB57_2:753; CHECK-RV64-NEXT: sub a5, a6, a4754; CHECK-RV64-NEXT: sltu t0, a6, a5755; CHECK-RV64-NEXT: addi t0, t0, -1756; CHECK-RV64-NEXT: and t0, t0, a5757; CHECK-RV64-NEXT: mv a5, a6758; CHECK-RV64-NEXT: bltu a6, a4, .LBB57_4759; CHECK-RV64-NEXT: # %bb.3:760; CHECK-RV64-NEXT: mv a5, a4761; CHECK-RV64-NEXT: .LBB57_4:762; CHECK-RV64-NEXT: mul t1, a5, a1763; CHECK-RV64-NEXT: srli t2, a4, 3764; CHECK-RV64-NEXT: sub a7, a2, a7765; CHECK-RV64-NEXT: vsetvli t3, zero, e8, mf4, ta, ma766; CHECK-RV64-NEXT: vslidedown.vx v0, v8, t2767; CHECK-RV64-NEXT: add t1, a0, t1768; CHECK-RV64-NEXT: vsetvli zero, t0, e64, m8, ta, ma769; CHECK-RV64-NEXT: vlse64.v v16, (t1), a1, v0.t770; CHECK-RV64-NEXT: sltu a2, a2, a7771; CHECK-RV64-NEXT: addi a2, a2, -1772; CHECK-RV64-NEXT: and a2, a2, a7773; CHECK-RV64-NEXT: bltu a2, a4, .LBB57_6774; CHECK-RV64-NEXT: # %bb.5:775; CHECK-RV64-NEXT: mv a2, a4776; CHECK-RV64-NEXT: .LBB57_6:777; CHECK-RV64-NEXT: mul a6, a6, a1778; CHECK-RV64-NEXT: srli a4, a4, 2779; CHECK-RV64-NEXT: vsetvli a7, zero, e8, mf2, ta, ma780; CHECK-RV64-NEXT: vslidedown.vx v0, v8, a4781; CHECK-RV64-NEXT: add a6, a0, a6782; CHECK-RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma783; CHECK-RV64-NEXT: vlse64.v v24, (a6), a1, v0.t784; CHECK-RV64-NEXT: vmv1r.v v0, v8785; CHECK-RV64-NEXT: vsetvli zero, a5, e64, m8, ta, ma786; CHECK-RV64-NEXT: vlse64.v v8, (a0), a1, v0.t787; CHECK-RV64-NEXT: vs1r.v v24, (a3)788; CHECK-RV64-NEXT: ret789 %v = call <vscale x 17 x double> @llvm.experimental.vp.strided.load.nxv17f64.p0.i64(ptr %ptr, i64 %stride, <vscale x 17 x i1> %mask, i32 %evl)790 %lo = call <vscale x 16 x double> @llvm.experimental.vector.extract.nxv16f64(<vscale x 17 x double> %v, i64 0)791 %hi = call <vscale x 1 x double> @llvm.experimental.vector.extract.nxv1f64(<vscale x 17 x double> %v, i64 16)792 store <vscale x 1 x double> %hi, ptr %hi_ptr793 ret <vscale x 16 x double> %lo794}795 796; Test unmasked integer zero strided797define <vscale x 1 x i8> @zero_strided_unmasked_vpload_nxv1i8_i8(ptr %ptr) {798; CHECK-OPT-LABEL: zero_strided_unmasked_vpload_nxv1i8_i8:799; CHECK-OPT: # %bb.0:800; CHECK-OPT-NEXT: vsetivli zero, 4, e8, mf8, ta, ma801; CHECK-OPT-NEXT: vlse8.v v8, (a0), zero802; CHECK-OPT-NEXT: ret803;804; CHECK-NO-OPT-LABEL: zero_strided_unmasked_vpload_nxv1i8_i8:805; CHECK-NO-OPT: # %bb.0:806; CHECK-NO-OPT-NEXT: lbu a0, 0(a0)807; CHECK-NO-OPT-NEXT: vsetivli zero, 4, e8, mf8, ta, ma808; CHECK-NO-OPT-NEXT: vmv.v.x v8, a0809; CHECK-NO-OPT-NEXT: ret810 %load = call <vscale x 1 x i8> @llvm.experimental.vp.strided.load.nxv1i8.p0.i8(ptr %ptr, i8 0, <vscale x 1 x i1> splat (i1 true), i32 4)811 ret <vscale x 1 x i8> %load812}813 814; Test unmasked float zero strided815define <vscale x 1 x half> @zero_strided_unmasked_vpload_nxv1f16(ptr %ptr) {816; CHECK-OPT-LABEL: zero_strided_unmasked_vpload_nxv1f16:817; CHECK-OPT: # %bb.0:818; CHECK-OPT-NEXT: vsetivli zero, 4, e16, mf4, ta, ma819; CHECK-OPT-NEXT: vlse16.v v8, (a0), zero820; CHECK-OPT-NEXT: ret821;822; CHECK-NO-OPT-ZVFH-LABEL: zero_strided_unmasked_vpload_nxv1f16:823; CHECK-NO-OPT-ZVFH: # %bb.0:824; CHECK-NO-OPT-ZVFH-NEXT: flh fa5, 0(a0)825; CHECK-NO-OPT-ZVFH-NEXT: vsetivli zero, 4, e16, mf4, ta, ma826; CHECK-NO-OPT-ZVFH-NEXT: vfmv.v.f v8, fa5827; CHECK-NO-OPT-ZVFH-NEXT: ret828;829; CHECK-NO-OPT-ZVFHMIN-LABEL: zero_strided_unmasked_vpload_nxv1f16:830; CHECK-NO-OPT-ZVFHMIN: # %bb.0:831; CHECK-NO-OPT-ZVFHMIN-NEXT: lh a0, 0(a0)832; CHECK-NO-OPT-ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf4, ta, ma833; CHECK-NO-OPT-ZVFHMIN-NEXT: vmv.v.x v8, a0834; CHECK-NO-OPT-ZVFHMIN-NEXT: ret835 %load = call <vscale x 1 x half> @llvm.experimental.vp.strided.load.nxv1f16.p0.i32(ptr %ptr, i32 0, <vscale x 1 x i1> splat (i1 true), i32 4)836 ret <vscale x 1 x half> %load837}838 839define <vscale x 1 x i64> @zero_strided_vadd_nxv1i64(<vscale x 1 x i64> %v, ptr %ptr) {840; CHECK-RV32-LABEL: zero_strided_vadd_nxv1i64:841; CHECK-RV32: # %bb.0:842; CHECK-RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma843; CHECK-RV32-NEXT: vlse64.v v9, (a0), zero844; CHECK-RV32-NEXT: vadd.vv v8, v8, v9845; CHECK-RV32-NEXT: ret846;847; CHECK-RV64-LABEL: zero_strided_vadd_nxv1i64:848; CHECK-RV64: # %bb.0:849; CHECK-RV64-NEXT: ld a0, 0(a0)850; CHECK-RV64-NEXT: vsetvli a1, zero, e64, m1, ta, ma851; CHECK-RV64-NEXT: vadd.vx v8, v8, a0852; CHECK-RV64-NEXT: ret853 %vscale = call i32 @llvm.vscale()854 %load = call <vscale x 1 x i64> @llvm.experimental.vp.strided.load.nxv1i64.p0.i32(ptr %ptr, i32 0, <vscale x 1 x i1> splat (i1 true), i32 %vscale)855 %w = add <vscale x 1 x i64> %v, %load856 ret <vscale x 1 x i64> %w857}858 859define <vscale x 16 x i64> @zero_strided_vadd_nxv16i64(<vscale x 16 x i64> %v, ptr %ptr) {860; CHECK-RV32-LABEL: zero_strided_vadd_nxv16i64:861; CHECK-RV32: # %bb.0:862; CHECK-RV32-NEXT: csrr a1, vlenb863; CHECK-RV32-NEXT: srli a2, a1, 3864; CHECK-RV32-NEXT: sub a1, a2, a1865; CHECK-RV32-NEXT: sltu a3, a2, a1866; CHECK-RV32-NEXT: addi a3, a3, -1867; CHECK-RV32-NEXT: and a1, a3, a1868; CHECK-RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma869; CHECK-RV32-NEXT: vlse64.v v24, (a0), zero870; CHECK-RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma871; CHECK-RV32-NEXT: vlse64.v v0, (a0), zero872; CHECK-RV32-NEXT: vsetvli a0, zero, e64, m8, ta, ma873; CHECK-RV32-NEXT: vadd.vv v8, v8, v24874; CHECK-RV32-NEXT: vadd.vv v16, v16, v0875; CHECK-RV32-NEXT: ret876;877; CHECK-RV64-LABEL: zero_strided_vadd_nxv16i64:878; CHECK-RV64: # %bb.0:879; CHECK-RV64-NEXT: ld a0, 0(a0)880; CHECK-RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma881; CHECK-RV64-NEXT: vadd.vx v8, v8, a0882; CHECK-RV64-NEXT: vadd.vx v16, v16, a0883; CHECK-RV64-NEXT: ret884 %vscale = call i32 @llvm.vscale()885 %load = call <vscale x 16 x i64> @llvm.experimental.vp.strided.load.nxv16i64.p0.i32(ptr %ptr, i32 0, <vscale x 16 x i1> splat (i1 true), i32 %vscale)886 %w = add <vscale x 16 x i64> %v, %load887 ret <vscale x 16 x i64> %w888}889 890define <vscale x 1 x ptr> @zero_strided_vadd_nxv1p0(<vscale x 1 x ptr> %v, ptr %ptr) {891; CHECK-OPT-RV32-LABEL: zero_strided_vadd_nxv1p0:892; CHECK-OPT-RV32: # %bb.0:893; CHECK-OPT-RV32-NEXT: vsetvli a1, zero, e32, mf2, ta, ma894; CHECK-OPT-RV32-NEXT: vlse32.v v8, (a0), zero895; CHECK-OPT-RV32-NEXT: ret896;897; CHECK-OPT-RV64-LABEL: zero_strided_vadd_nxv1p0:898; CHECK-OPT-RV64: # %bb.0:899; CHECK-OPT-RV64-NEXT: vsetvli a1, zero, e64, m1, ta, ma900; CHECK-OPT-RV64-NEXT: vlse64.v v8, (a0), zero901; CHECK-OPT-RV64-NEXT: ret902;903; CHECK-NO-OPT-RV32-LABEL: zero_strided_vadd_nxv1p0:904; CHECK-NO-OPT-RV32: # %bb.0:905; CHECK-NO-OPT-RV32-NEXT: lw a0, 0(a0)906; CHECK-NO-OPT-RV32-NEXT: vsetvli a1, zero, e32, mf2, ta, ma907; CHECK-NO-OPT-RV32-NEXT: vmv.v.x v8, a0908; CHECK-NO-OPT-RV32-NEXT: ret909;910; CHECK-NO-OPT-RV64-LABEL: zero_strided_vadd_nxv1p0:911; CHECK-NO-OPT-RV64: # %bb.0:912; CHECK-NO-OPT-RV64-NEXT: ld a0, 0(a0)913; CHECK-NO-OPT-RV64-NEXT: vsetvli a1, zero, e64, m1, ta, ma914; CHECK-NO-OPT-RV64-NEXT: vmv.v.x v8, a0915; CHECK-NO-OPT-RV64-NEXT: ret916 %vscale = call i32 @llvm.vscale()917 %load = call <vscale x 1 x ptr> @llvm.experimental.vp.strided.load.nxv1p0.p0.i32(ptr %ptr, i32 0, <vscale x 1 x i1> splat (i1 true), i32 %vscale)918 ret <vscale x 1 x ptr> %load919}920