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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+v,+zvfh,+zvfbfmin \3; RUN: -verify-machineinstrs < %s | FileCheck %s \4; RUN: -check-prefixes=CHECK,CHECK-RV325; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+v,+zvfh,+zvfbfmin \6; RUN: -verify-machineinstrs < %s | FileCheck %s \7; RUN: -check-prefixes=CHECK,CHECK-RV648; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+v,+zvfhmin,+zvfbfmin \9; RUN: -verify-machineinstrs < %s | FileCheck %s \10; RUN: -check-prefixes=CHECK,CHECK-RV3211; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+v,+zvfhmin,+zvfbfmin \12; RUN: -verify-machineinstrs < %s | FileCheck %s \13; RUN: -check-prefixes=CHECK,CHECK-RV6414 15define void @strided_vpstore_nxv1i8_i8(<vscale x 1 x i8> %val, ptr %ptr, i8 signext %stride, <vscale x 1 x i1> %m, i32 zeroext %evl) {16; CHECK-LABEL: strided_vpstore_nxv1i8_i8:17; CHECK: # %bb.0:18; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, ma19; CHECK-NEXT: vsse8.v v8, (a0), a1, v0.t20; CHECK-NEXT: ret21 call void @llvm.experimental.vp.strided.store.nxv1i8.p0.i8(<vscale x 1 x i8> %val, ptr %ptr, i8 %stride, <vscale x 1 x i1> %m, i32 %evl)22 ret void23}24 25define void @strided_vpstore_nxv1i8_i16(<vscale x 1 x i8> %val, ptr %ptr, i16 signext %stride, <vscale x 1 x i1> %m, i32 zeroext %evl) {26; CHECK-LABEL: strided_vpstore_nxv1i8_i16:27; CHECK: # %bb.0:28; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, ma29; CHECK-NEXT: vsse8.v v8, (a0), a1, v0.t30; CHECK-NEXT: ret31 call void @llvm.experimental.vp.strided.store.nxv1i8.p0.i16(<vscale x 1 x i8> %val, ptr %ptr, i16 %stride, <vscale x 1 x i1> %m, i32 %evl)32 ret void33}34 35define void @strided_vpstore_nxv1i8_i64(<vscale x 1 x i8> %val, ptr %ptr, i64 signext %stride, <vscale x 1 x i1> %m, i32 zeroext %evl) {36; CHECK-RV32-LABEL: strided_vpstore_nxv1i8_i64:37; CHECK-RV32: # %bb.0:38; CHECK-RV32-NEXT: vsetvli zero, a3, e8, mf8, ta, ma39; CHECK-RV32-NEXT: vsse8.v v8, (a0), a1, v0.t40; CHECK-RV32-NEXT: ret41;42; CHECK-RV64-LABEL: strided_vpstore_nxv1i8_i64:43; CHECK-RV64: # %bb.0:44; CHECK-RV64-NEXT: vsetvli zero, a2, e8, mf8, ta, ma45; CHECK-RV64-NEXT: vsse8.v v8, (a0), a1, v0.t46; CHECK-RV64-NEXT: ret47 call void @llvm.experimental.vp.strided.store.nxv1i8.p0.i64(<vscale x 1 x i8> %val, ptr %ptr, i64 %stride, <vscale x 1 x i1> %m, i32 %evl)48 ret void49}50 51define void @strided_vpstore_nxv1i8(<vscale x 1 x i8> %val, ptr %ptr, i32 signext %strided, <vscale x 1 x i1> %m, i32 zeroext %evl) {52; CHECK-LABEL: strided_vpstore_nxv1i8:53; CHECK: # %bb.0:54; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, ma55; CHECK-NEXT: vsse8.v v8, (a0), a1, v0.t56; CHECK-NEXT: ret57 call void @llvm.experimental.vp.strided.store.nxv1i8.p0.i32(<vscale x 1 x i8> %val, ptr %ptr, i32 %strided, <vscale x 1 x i1> %m, i32 %evl)58 ret void59}60 61define void @strided_vpstore_nxv2i8(<vscale x 2 x i8> %val, ptr %ptr, i32 signext %strided, <vscale x 2 x i1> %m, i32 zeroext %evl) {62; CHECK-LABEL: strided_vpstore_nxv2i8:63; CHECK: # %bb.0:64; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, ma65; CHECK-NEXT: vsse8.v v8, (a0), a1, v0.t66; CHECK-NEXT: ret67 call void @llvm.experimental.vp.strided.store.nxv2i8.p0.i32(<vscale x 2 x i8> %val, ptr %ptr, i32 %strided, <vscale x 2 x i1> %m, i32 %evl)68 ret void69}70 71define void @strided_vpstore_nxv4i8(<vscale x 4 x i8> %val, ptr %ptr, i32 signext %strided, <vscale x 4 x i1> %m, i32 zeroext %evl) {72; CHECK-LABEL: strided_vpstore_nxv4i8:73; CHECK: # %bb.0:74; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, ma75; CHECK-NEXT: vsse8.v v8, (a0), a1, v0.t76; CHECK-NEXT: ret77 call void @llvm.experimental.vp.strided.store.nxv4i8.p0.i32(<vscale x 4 x i8> %val, ptr %ptr, i32 %strided, <vscale x 4 x i1> %m, i32 %evl)78 ret void79}80 81define void @strided_vpstore_nxv8i8(<vscale x 8 x i8> %val, ptr %ptr, i32 signext %strided, <vscale x 8 x i1> %m, i32 zeroext %evl) {82; CHECK-LABEL: strided_vpstore_nxv8i8:83; CHECK: # %bb.0:84; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, ma85; CHECK-NEXT: vsse8.v v8, (a0), a1, v0.t86; CHECK-NEXT: ret87 call void @llvm.experimental.vp.strided.store.nxv8i8.p0.i32(<vscale x 8 x i8> %val, ptr %ptr, i32 %strided, <vscale x 8 x i1> %m, i32 %evl)88 ret void89}90 91define void @strided_vpstore_nxv8i8_unit_stride(<vscale x 8 x i8> %val, ptr %ptr, <vscale x 8 x i1> %m, i32 zeroext %evl) {92; CHECK-LABEL: strided_vpstore_nxv8i8_unit_stride:93; CHECK: # %bb.0:94; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma95; CHECK-NEXT: vse8.v v8, (a0), v0.t96; CHECK-NEXT: ret97 call void @llvm.experimental.vp.strided.store.nxv8i8.p0.i32(<vscale x 8 x i8> %val, ptr %ptr, i32 1, <vscale x 8 x i1> %m, i32 %evl)98 ret void99}100 101define void @strided_vpstore_nxv1i16(<vscale x 1 x i16> %val, ptr %ptr, i32 signext %strided, <vscale x 1 x i1> %m, i32 zeroext %evl) {102; CHECK-LABEL: strided_vpstore_nxv1i16:103; CHECK: # %bb.0:104; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, ma105; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t106; CHECK-NEXT: ret107 call void @llvm.experimental.vp.strided.store.nxv1i16.p0.i32(<vscale x 1 x i16> %val, ptr %ptr, i32 %strided, <vscale x 1 x i1> %m, i32 %evl)108 ret void109}110 111define void @strided_vpstore_nxv2i16(<vscale x 2 x i16> %val, ptr %ptr, i32 signext %strided, <vscale x 2 x i1> %m, i32 zeroext %evl) {112; CHECK-LABEL: strided_vpstore_nxv2i16:113; CHECK: # %bb.0:114; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, ma115; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t116; CHECK-NEXT: ret117 call void @llvm.experimental.vp.strided.store.nxv2i16.p0.i32(<vscale x 2 x i16> %val, ptr %ptr, i32 %strided, <vscale x 2 x i1> %m, i32 %evl)118 ret void119}120 121define void @strided_vpstore_nxv4i16(<vscale x 4 x i16> %val, ptr %ptr, i32 signext %strided, <vscale x 4 x i1> %m, i32 zeroext %evl) {122; CHECK-LABEL: strided_vpstore_nxv4i16:123; CHECK: # %bb.0:124; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, ma125; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t126; CHECK-NEXT: ret127 call void @llvm.experimental.vp.strided.store.nxv4i16.p0.i32(<vscale x 4 x i16> %val, ptr %ptr, i32 %strided, <vscale x 4 x i1> %m, i32 %evl)128 ret void129}130 131define void @strided_vpstore_nxv4i16_unit_stride(<vscale x 4 x i16> %val, ptr %ptr, <vscale x 4 x i1> %m, i32 zeroext %evl) {132; CHECK-LABEL: strided_vpstore_nxv4i16_unit_stride:133; CHECK: # %bb.0:134; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma135; CHECK-NEXT: vse16.v v8, (a0), v0.t136; CHECK-NEXT: ret137 call void @llvm.experimental.vp.strided.store.nxv4i16.p0.i32(<vscale x 4 x i16> %val, ptr %ptr, i32 2, <vscale x 4 x i1> %m, i32 %evl)138 ret void139}140 141define void @strided_vpstore_nxv8i16(<vscale x 8 x i16> %val, ptr %ptr, i32 signext %strided, <vscale x 8 x i1> %m, i32 zeroext %evl) {142; CHECK-LABEL: strided_vpstore_nxv8i16:143; CHECK: # %bb.0:144; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, ma145; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t146; CHECK-NEXT: ret147 call void @llvm.experimental.vp.strided.store.nxv8i16.p0.i32(<vscale x 8 x i16> %val, ptr %ptr, i32 %strided, <vscale x 8 x i1> %m, i32 %evl)148 ret void149}150 151define void @strided_vpstore_nxv1i32(<vscale x 1 x i32> %val, ptr %ptr, i32 signext %strided, <vscale x 1 x i1> %m, i32 zeroext %evl) {152; CHECK-LABEL: strided_vpstore_nxv1i32:153; CHECK: # %bb.0:154; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, ma155; CHECK-NEXT: vsse32.v v8, (a0), a1, v0.t156; CHECK-NEXT: ret157 call void @llvm.experimental.vp.strided.store.nxv1i32.p0.i32(<vscale x 1 x i32> %val, ptr %ptr, i32 %strided, <vscale x 1 x i1> %m, i32 %evl)158 ret void159}160 161define void @strided_vpstore_nxv2i32(<vscale x 2 x i32> %val, ptr %ptr, i32 signext %strided, <vscale x 2 x i1> %m, i32 zeroext %evl) {162; CHECK-LABEL: strided_vpstore_nxv2i32:163; CHECK: # %bb.0:164; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, ma165; CHECK-NEXT: vsse32.v v8, (a0), a1, v0.t166; CHECK-NEXT: ret167 call void @llvm.experimental.vp.strided.store.nxv2i32.p0.i32(<vscale x 2 x i32> %val, ptr %ptr, i32 %strided, <vscale x 2 x i1> %m, i32 %evl)168 ret void169}170 171define void @strided_vpstore_nxv4i32(<vscale x 4 x i32> %val, ptr %ptr, i32 signext %strided, <vscale x 4 x i1> %m, i32 zeroext %evl) {172; CHECK-LABEL: strided_vpstore_nxv4i32:173; CHECK: # %bb.0:174; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, ma175; CHECK-NEXT: vsse32.v v8, (a0), a1, v0.t176; CHECK-NEXT: ret177 call void @llvm.experimental.vp.strided.store.nxv4i32.p0.i32(<vscale x 4 x i32> %val, ptr %ptr, i32 %strided, <vscale x 4 x i1> %m, i32 %evl)178 ret void179}180 181define void @strided_vpstore_nxv4i32_unit_stride(<vscale x 4 x i32> %val, ptr %ptr, <vscale x 4 x i1> %m, i32 zeroext %evl) {182; CHECK-LABEL: strided_vpstore_nxv4i32_unit_stride:183; CHECK: # %bb.0:184; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma185; CHECK-NEXT: vse32.v v8, (a0), v0.t186; CHECK-NEXT: ret187 call void @llvm.experimental.vp.strided.store.nxv4i32.p0.i32(<vscale x 4 x i32> %val, ptr %ptr, i32 4, <vscale x 4 x i1> %m, i32 %evl)188 ret void189}190 191define void @strided_vpstore_nxv8i32(<vscale x 8 x i32> %val, ptr %ptr, i32 signext %strided, <vscale x 8 x i1> %m, i32 zeroext %evl) {192; CHECK-LABEL: strided_vpstore_nxv8i32:193; CHECK: # %bb.0:194; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, ma195; CHECK-NEXT: vsse32.v v8, (a0), a1, v0.t196; CHECK-NEXT: ret197 call void @llvm.experimental.vp.strided.store.nxv8i32.p0.i32(<vscale x 8 x i32> %val, ptr %ptr, i32 %strided, <vscale x 8 x i1> %m, i32 %evl)198 ret void199}200 201define void @strided_vpstore_nxv1i64(<vscale x 1 x i64> %val, ptr %ptr, i32 signext %strided, <vscale x 1 x i1> %m, i32 zeroext %evl) {202; CHECK-LABEL: strided_vpstore_nxv1i64:203; CHECK: # %bb.0:204; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, ma205; CHECK-NEXT: vsse64.v v8, (a0), a1, v0.t206; CHECK-NEXT: ret207 call void @llvm.experimental.vp.strided.store.nxv1i64.p0.i32(<vscale x 1 x i64> %val, ptr %ptr, i32 %strided, <vscale x 1 x i1> %m, i32 %evl)208 ret void209}210 211define void @strided_vpstore_nxv1i64_unit_stride(<vscale x 1 x i64> %val, ptr %ptr, <vscale x 1 x i1> %m, i32 zeroext %evl) {212; CHECK-LABEL: strided_vpstore_nxv1i64_unit_stride:213; CHECK: # %bb.0:214; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma215; CHECK-NEXT: vse64.v v8, (a0), v0.t216; CHECK-NEXT: ret217 call void @llvm.experimental.vp.strided.store.nxv1i64.p0.i32(<vscale x 1 x i64> %val, ptr %ptr, i32 8, <vscale x 1 x i1> %m, i32 %evl)218 ret void219}220 221define void @strided_vpstore_nxv2i64(<vscale x 2 x i64> %val, ptr %ptr, i32 signext %strided, <vscale x 2 x i1> %m, i32 zeroext %evl) {222; CHECK-LABEL: strided_vpstore_nxv2i64:223; CHECK: # %bb.0:224; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, ma225; CHECK-NEXT: vsse64.v v8, (a0), a1, v0.t226; CHECK-NEXT: ret227 call void @llvm.experimental.vp.strided.store.nxv2i64.p0.i32(<vscale x 2 x i64> %val, ptr %ptr, i32 %strided, <vscale x 2 x i1> %m, i32 %evl)228 ret void229}230 231define void @strided_vpstore_nxv4i64(<vscale x 4 x i64> %val, ptr %ptr, i32 signext %strided, <vscale x 4 x i1> %m, i32 zeroext %evl) {232; CHECK-LABEL: strided_vpstore_nxv4i64:233; CHECK: # %bb.0:234; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, ma235; CHECK-NEXT: vsse64.v v8, (a0), a1, v0.t236; CHECK-NEXT: ret237 call void @llvm.experimental.vp.strided.store.nxv4i64.p0.i32(<vscale x 4 x i64> %val, ptr %ptr, i32 %strided, <vscale x 4 x i1> %m, i32 %evl)238 ret void239}240 241define void @strided_vpstore_nxv8i64(<vscale x 8 x i64> %val, ptr %ptr, i32 signext %strided, <vscale x 8 x i1> %m, i32 zeroext %evl) {242; CHECK-LABEL: strided_vpstore_nxv8i64:243; CHECK: # %bb.0:244; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma245; CHECK-NEXT: vsse64.v v8, (a0), a1, v0.t246; CHECK-NEXT: ret247 call void @llvm.experimental.vp.strided.store.nxv8i64.p0.i32(<vscale x 8 x i64> %val, ptr %ptr, i32 %strided, <vscale x 8 x i1> %m, i32 %evl)248 ret void249}250 251define void @strided_vpstore_nxv1bf16(<vscale x 1 x bfloat> %val, ptr %ptr, i32 signext %strided, <vscale x 1 x i1> %m, i32 zeroext %evl) {252; CHECK-LABEL: strided_vpstore_nxv1bf16:253; CHECK: # %bb.0:254; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, ma255; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t256; CHECK-NEXT: ret257 call void @llvm.experimental.vp.strided.store.nxv1bf16.p0.i32(<vscale x 1 x bfloat> %val, ptr %ptr, i32 %strided, <vscale x 1 x i1> %m, i32 %evl)258 ret void259}260 261define void @strided_vpstore_nxv2bf16(<vscale x 2 x bfloat> %val, ptr %ptr, i32 signext %strided, <vscale x 2 x i1> %m, i32 zeroext %evl) {262; CHECK-LABEL: strided_vpstore_nxv2bf16:263; CHECK: # %bb.0:264; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, ma265; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t266; CHECK-NEXT: ret267 call void @llvm.experimental.vp.strided.store.nxv2bf16.p0.i32(<vscale x 2 x bfloat> %val, ptr %ptr, i32 %strided, <vscale x 2 x i1> %m, i32 %evl)268 ret void269}270 271define void @strided_vpstore_nxv4bf16(<vscale x 4 x bfloat> %val, ptr %ptr, i32 signext %strided, <vscale x 4 x i1> %m, i32 zeroext %evl) {272; CHECK-LABEL: strided_vpstore_nxv4bf16:273; CHECK: # %bb.0:274; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, ma275; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t276; CHECK-NEXT: ret277 call void @llvm.experimental.vp.strided.store.nxv4bf16.p0.i32(<vscale x 4 x bfloat> %val, ptr %ptr, i32 %strided, <vscale x 4 x i1> %m, i32 %evl)278 ret void279}280 281define void @strided_vpstore_nxv4bf16_unit_stride(<vscale x 4 x bfloat> %val, ptr %ptr, <vscale x 4 x i1> %m, i32 zeroext %evl) {282; CHECK-LABEL: strided_vpstore_nxv4bf16_unit_stride:283; CHECK: # %bb.0:284; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma285; CHECK-NEXT: vse16.v v8, (a0), v0.t286; CHECK-NEXT: ret287 call void @llvm.experimental.vp.strided.store.nxv4bf16.p0.i32(<vscale x 4 x bfloat> %val, ptr %ptr, i32 2, <vscale x 4 x i1> %m, i32 %evl)288 ret void289}290 291define void @strided_vpstore_nxv8bf16(<vscale x 8 x bfloat> %val, ptr %ptr, i32 signext %strided, <vscale x 8 x i1> %m, i32 zeroext %evl) {292; CHECK-LABEL: strided_vpstore_nxv8bf16:293; CHECK: # %bb.0:294; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, ma295; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t296; CHECK-NEXT: ret297 call void @llvm.experimental.vp.strided.store.nxv8bf16.p0.i32(<vscale x 8 x bfloat> %val, ptr %ptr, i32 %strided, <vscale x 8 x i1> %m, i32 %evl)298 ret void299}300 301define void @strided_vpstore_nxv1f16(<vscale x 1 x half> %val, ptr %ptr, i32 signext %strided, <vscale x 1 x i1> %m, i32 zeroext %evl) {302; CHECK-LABEL: strided_vpstore_nxv1f16:303; CHECK: # %bb.0:304; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, ma305; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t306; CHECK-NEXT: ret307 call void @llvm.experimental.vp.strided.store.nxv1f16.p0.i32(<vscale x 1 x half> %val, ptr %ptr, i32 %strided, <vscale x 1 x i1> %m, i32 %evl)308 ret void309}310 311define void @strided_vpstore_nxv2f16(<vscale x 2 x half> %val, ptr %ptr, i32 signext %strided, <vscale x 2 x i1> %m, i32 zeroext %evl) {312; CHECK-LABEL: strided_vpstore_nxv2f16:313; CHECK: # %bb.0:314; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, ma315; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t316; CHECK-NEXT: ret317 call void @llvm.experimental.vp.strided.store.nxv2f16.p0.i32(<vscale x 2 x half> %val, ptr %ptr, i32 %strided, <vscale x 2 x i1> %m, i32 %evl)318 ret void319}320 321define void @strided_vpstore_nxv4f16(<vscale x 4 x half> %val, ptr %ptr, i32 signext %strided, <vscale x 4 x i1> %m, i32 zeroext %evl) {322; CHECK-LABEL: strided_vpstore_nxv4f16:323; CHECK: # %bb.0:324; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, ma325; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t326; CHECK-NEXT: ret327 call void @llvm.experimental.vp.strided.store.nxv4f16.p0.i32(<vscale x 4 x half> %val, ptr %ptr, i32 %strided, <vscale x 4 x i1> %m, i32 %evl)328 ret void329}330 331define void @strided_vpstore_nxv4f16_unit_stride(<vscale x 4 x half> %val, ptr %ptr, <vscale x 4 x i1> %m, i32 zeroext %evl) {332; CHECK-LABEL: strided_vpstore_nxv4f16_unit_stride:333; CHECK: # %bb.0:334; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma335; CHECK-NEXT: vse16.v v8, (a0), v0.t336; CHECK-NEXT: ret337 call void @llvm.experimental.vp.strided.store.nxv4f16.p0.i32(<vscale x 4 x half> %val, ptr %ptr, i32 2, <vscale x 4 x i1> %m, i32 %evl)338 ret void339}340 341define void @strided_vpstore_nxv8f16(<vscale x 8 x half> %val, ptr %ptr, i32 signext %strided, <vscale x 8 x i1> %m, i32 zeroext %evl) {342; CHECK-LABEL: strided_vpstore_nxv8f16:343; CHECK: # %bb.0:344; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, ma345; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t346; CHECK-NEXT: ret347 call void @llvm.experimental.vp.strided.store.nxv8f16.p0.i32(<vscale x 8 x half> %val, ptr %ptr, i32 %strided, <vscale x 8 x i1> %m, i32 %evl)348 ret void349}350 351define void @strided_vpstore_nxv1f32(<vscale x 1 x float> %val, ptr %ptr, i32 signext %strided, <vscale x 1 x i1> %m, i32 zeroext %evl) {352; CHECK-LABEL: strided_vpstore_nxv1f32:353; CHECK: # %bb.0:354; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, ma355; CHECK-NEXT: vsse32.v v8, (a0), a1, v0.t356; CHECK-NEXT: ret357 call void @llvm.experimental.vp.strided.store.nxv1f32.p0.i32(<vscale x 1 x float> %val, ptr %ptr, i32 %strided, <vscale x 1 x i1> %m, i32 %evl)358 ret void359}360 361define void @strided_vpstore_nxv2f32(<vscale x 2 x float> %val, ptr %ptr, i32 signext %strided, <vscale x 2 x i1> %m, i32 zeroext %evl) {362; CHECK-LABEL: strided_vpstore_nxv2f32:363; CHECK: # %bb.0:364; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, ma365; CHECK-NEXT: vsse32.v v8, (a0), a1, v0.t366; CHECK-NEXT: ret367 call void @llvm.experimental.vp.strided.store.nxv2f32.p0.i32(<vscale x 2 x float> %val, ptr %ptr, i32 %strided, <vscale x 2 x i1> %m, i32 %evl)368 ret void369}370 371define void @strided_vpstore_nxv4f32(<vscale x 4 x float> %val, ptr %ptr, i32 signext %strided, <vscale x 4 x i1> %m, i32 zeroext %evl) {372; CHECK-LABEL: strided_vpstore_nxv4f32:373; CHECK: # %bb.0:374; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, ma375; CHECK-NEXT: vsse32.v v8, (a0), a1, v0.t376; CHECK-NEXT: ret377 call void @llvm.experimental.vp.strided.store.nxv4f32.p0.i32(<vscale x 4 x float> %val, ptr %ptr, i32 %strided, <vscale x 4 x i1> %m, i32 %evl)378 ret void379}380 381define void @strided_vpstore_nxv4f32_unit_stride(<vscale x 4 x float> %val, ptr %ptr, <vscale x 4 x i1> %m, i32 zeroext %evl) {382; CHECK-LABEL: strided_vpstore_nxv4f32_unit_stride:383; CHECK: # %bb.0:384; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma385; CHECK-NEXT: vse32.v v8, (a0), v0.t386; CHECK-NEXT: ret387 call void @llvm.experimental.vp.strided.store.nxv4f32.p0.i32(<vscale x 4 x float> %val, ptr %ptr, i32 4, <vscale x 4 x i1> %m, i32 %evl)388 ret void389}390 391define void @strided_vpstore_nxv8f32(<vscale x 8 x float> %val, ptr %ptr, i32 signext %strided, <vscale x 8 x i1> %m, i32 zeroext %evl) {392; CHECK-LABEL: strided_vpstore_nxv8f32:393; CHECK: # %bb.0:394; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, ma395; CHECK-NEXT: vsse32.v v8, (a0), a1, v0.t396; CHECK-NEXT: ret397 call void @llvm.experimental.vp.strided.store.nxv8f32.p0.i32(<vscale x 8 x float> %val, ptr %ptr, i32 %strided, <vscale x 8 x i1> %m, i32 %evl)398 ret void399}400 401define void @strided_vpstore_nxv1f64(<vscale x 1 x double> %val, ptr %ptr, i32 signext %strided, <vscale x 1 x i1> %m, i32 zeroext %evl) {402; CHECK-LABEL: strided_vpstore_nxv1f64:403; CHECK: # %bb.0:404; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, ma405; CHECK-NEXT: vsse64.v v8, (a0), a1, v0.t406; CHECK-NEXT: ret407 call void @llvm.experimental.vp.strided.store.nxv1f64.p0.i32(<vscale x 1 x double> %val, ptr %ptr, i32 %strided, <vscale x 1 x i1> %m, i32 %evl)408 ret void409}410 411define void @strided_vpstore_nxv1f64_unit_stride(<vscale x 1 x double> %val, ptr %ptr, <vscale x 1 x i1> %m, i32 zeroext %evl) {412; CHECK-LABEL: strided_vpstore_nxv1f64_unit_stride:413; CHECK: # %bb.0:414; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma415; CHECK-NEXT: vse64.v v8, (a0), v0.t416; CHECK-NEXT: ret417 call void @llvm.experimental.vp.strided.store.nxv1f64.p0.i32(<vscale x 1 x double> %val, ptr %ptr, i32 8, <vscale x 1 x i1> %m, i32 %evl)418 ret void419}420 421define void @strided_vpstore_nxv2f64(<vscale x 2 x double> %val, ptr %ptr, i32 signext %strided, <vscale x 2 x i1> %m, i32 zeroext %evl) {422; CHECK-LABEL: strided_vpstore_nxv2f64:423; CHECK: # %bb.0:424; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, ma425; CHECK-NEXT: vsse64.v v8, (a0), a1, v0.t426; CHECK-NEXT: ret427 call void @llvm.experimental.vp.strided.store.nxv2f64.p0.i32(<vscale x 2 x double> %val, ptr %ptr, i32 %strided, <vscale x 2 x i1> %m, i32 %evl)428 ret void429}430 431define void @strided_vpstore_nxv4f64(<vscale x 4 x double> %val, ptr %ptr, i32 signext %strided, <vscale x 4 x i1> %m, i32 zeroext %evl) {432; CHECK-LABEL: strided_vpstore_nxv4f64:433; CHECK: # %bb.0:434; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, ma435; CHECK-NEXT: vsse64.v v8, (a0), a1, v0.t436; CHECK-NEXT: ret437 call void @llvm.experimental.vp.strided.store.nxv4f64.p0.i32(<vscale x 4 x double> %val, ptr %ptr, i32 %strided, <vscale x 4 x i1> %m, i32 %evl)438 ret void439}440 441define void @strided_vpstore_nxv8f64(<vscale x 8 x double> %val, ptr %ptr, i32 signext %strided, <vscale x 8 x i1> %m, i32 zeroext %evl) {442; CHECK-LABEL: strided_vpstore_nxv8f64:443; CHECK: # %bb.0:444; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma445; CHECK-NEXT: vsse64.v v8, (a0), a1, v0.t446; CHECK-NEXT: ret447 call void @llvm.experimental.vp.strided.store.nxv8f64.p0.i32(<vscale x 8 x double> %val, ptr %ptr, i32 %strided, <vscale x 8 x i1> %m, i32 %evl)448 ret void449}450 451define void @strided_vpstore_nxv1i8_allones_mask(<vscale x 1 x i8> %val, ptr %ptr, i32 signext %strided, i32 zeroext %evl) {452; CHECK-LABEL: strided_vpstore_nxv1i8_allones_mask:453; CHECK: # %bb.0:454; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, ma455; CHECK-NEXT: vsse8.v v8, (a0), a1456; CHECK-NEXT: ret457 call void @llvm.experimental.vp.strided.store.nxv1i8.p0.i32(<vscale x 1 x i8> %val, ptr %ptr, i32 %strided, <vscale x 1 x i1> splat (i1 true), i32 %evl)458 ret void459}460 461; Widening462define void @strided_vpstore_nxv3f32(<vscale x 3 x float> %v, ptr %ptr, i32 signext %stride, <vscale x 3 x i1> %mask, i32 zeroext %evl) {463; CHECK-LABEL: strided_vpstore_nxv3f32:464; CHECK: # %bb.0:465; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, ma466; CHECK-NEXT: vsse32.v v8, (a0), a1, v0.t467; CHECK-NEXT: ret468 call void @llvm.experimental.vp.strided.store.nxv3f32.p0.i32(<vscale x 3 x float> %v, ptr %ptr, i32 %stride, <vscale x 3 x i1> %mask, i32 %evl)469 ret void470}471 472define void @strided_vpstore_nxv3f32_allones_mask(<vscale x 3 x float> %v, ptr %ptr, i32 signext %stride, i32 zeroext %evl) {473; CHECK-LABEL: strided_vpstore_nxv3f32_allones_mask:474; CHECK: # %bb.0:475; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, ma476; CHECK-NEXT: vsse32.v v8, (a0), a1477; CHECK-NEXT: ret478 call void @llvm.experimental.vp.strided.store.nxv3f32.p0.i32(<vscale x 3 x float> %v, ptr %ptr, i32 %stride, <vscale x 3 x i1> splat (i1 true), i32 %evl)479 ret void480}481 482; Splitting483define void @strided_store_nxv16f64(<vscale x 16 x double> %v, ptr %ptr, i32 signext %stride, <vscale x 16 x i1> %mask, i32 zeroext %evl) {484; CHECK-LABEL: strided_store_nxv16f64:485; CHECK: # %bb.0:486; CHECK-NEXT: csrr a3, vlenb487; CHECK-NEXT: mv a4, a2488; CHECK-NEXT: bltu a2, a3, .LBB46_2489; CHECK-NEXT: # %bb.1:490; CHECK-NEXT: mv a4, a3491; CHECK-NEXT: .LBB46_2:492; CHECK-NEXT: vsetvli zero, a4, e64, m8, ta, ma493; CHECK-NEXT: vsse64.v v8, (a0), a1, v0.t494; CHECK-NEXT: sub a5, a2, a3495; CHECK-NEXT: mul a4, a4, a1496; CHECK-NEXT: srli a3, a3, 3497; CHECK-NEXT: sltu a2, a2, a5498; CHECK-NEXT: vsetvli a6, zero, e8, mf4, ta, ma499; CHECK-NEXT: vslidedown.vx v0, v0, a3500; CHECK-NEXT: addi a2, a2, -1501; CHECK-NEXT: and a2, a2, a5502; CHECK-NEXT: add a0, a0, a4503; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma504; CHECK-NEXT: vsse64.v v16, (a0), a1, v0.t505; CHECK-NEXT: ret506 call void @llvm.experimental.vp.strided.store.nxv16f64.p0.i32(<vscale x 16 x double> %v, ptr %ptr, i32 %stride, <vscale x 16 x i1> %mask, i32 %evl)507 ret void508}509 510define void @strided_store_nxv16f64_allones_mask(<vscale x 16 x double> %v, ptr %ptr, i32 signext %stride, i32 zeroext %evl) {511; CHECK-LABEL: strided_store_nxv16f64_allones_mask:512; CHECK: # %bb.0:513; CHECK-NEXT: csrr a4, vlenb514; CHECK-NEXT: mv a3, a2515; CHECK-NEXT: bltu a2, a4, .LBB47_2516; CHECK-NEXT: # %bb.1:517; CHECK-NEXT: mv a3, a4518; CHECK-NEXT: .LBB47_2:519; CHECK-NEXT: vsetvli zero, a3, e64, m8, ta, ma520; CHECK-NEXT: vsse64.v v8, (a0), a1521; CHECK-NEXT: sub a4, a2, a4522; CHECK-NEXT: mul a3, a3, a1523; CHECK-NEXT: sltu a2, a2, a4524; CHECK-NEXT: addi a2, a2, -1525; CHECK-NEXT: and a2, a2, a4526; CHECK-NEXT: add a0, a0, a3527; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma528; CHECK-NEXT: vsse64.v v16, (a0), a1529; CHECK-NEXT: ret530 call void @llvm.experimental.vp.strided.store.nxv16f64.p0.i32(<vscale x 16 x double> %v, ptr %ptr, i32 %stride, <vscale x 16 x i1> splat (i1 true), i32 %evl)531 ret void532}533 534; Widening + splitting (with HiIsEmpty == true)535define void @strided_store_nxv17f64(<vscale x 17 x double> %v, ptr %ptr, i32 signext %stride, <vscale x 17 x i1> %mask, i32 zeroext %evl) {536; CHECK-LABEL: strided_store_nxv17f64:537; CHECK: # %bb.0:538; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma539; CHECK-NEXT: vmv1r.v v7, v0540; CHECK-NEXT: csrr a4, vlenb541; CHECK-NEXT: slli a6, a4, 1542; CHECK-NEXT: mv a5, a3543; CHECK-NEXT: bltu a3, a6, .LBB48_2544; CHECK-NEXT: # %bb.1:545; CHECK-NEXT: mv a5, a6546; CHECK-NEXT: .LBB48_2:547; CHECK-NEXT: mv a7, a5548; CHECK-NEXT: bltu a5, a4, .LBB48_4549; CHECK-NEXT: # %bb.3:550; CHECK-NEXT: mv a7, a4551; CHECK-NEXT: .LBB48_4:552; CHECK-NEXT: vmv1r.v v0, v7553; CHECK-NEXT: vl8re64.v v24, (a0)554; CHECK-NEXT: vsetvli zero, a7, e64, m8, ta, ma555; CHECK-NEXT: vsse64.v v8, (a1), a2, v0.t556; CHECK-NEXT: sub a0, a5, a4557; CHECK-NEXT: mul a7, a7, a2558; CHECK-NEXT: srli t0, a4, 3559; CHECK-NEXT: sub a6, a3, a6560; CHECK-NEXT: vsetvli t1, zero, e8, mf4, ta, ma561; CHECK-NEXT: vslidedown.vx v0, v7, t0562; CHECK-NEXT: sltu t0, a5, a0563; CHECK-NEXT: add a7, a1, a7564; CHECK-NEXT: sltu a3, a3, a6565; CHECK-NEXT: addi t0, t0, -1566; CHECK-NEXT: addi a3, a3, -1567; CHECK-NEXT: and t0, t0, a0568; CHECK-NEXT: and a0, a3, a6569; CHECK-NEXT: vsetvli zero, t0, e64, m8, ta, ma570; CHECK-NEXT: vsse64.v v16, (a7), a2, v0.t571; CHECK-NEXT: bltu a0, a4, .LBB48_6572; CHECK-NEXT: # %bb.5:573; CHECK-NEXT: mv a0, a4574; CHECK-NEXT: .LBB48_6:575; CHECK-NEXT: mul a3, a5, a2576; CHECK-NEXT: srli a4, a4, 2577; CHECK-NEXT: vsetvli a5, zero, e8, mf2, ta, ma578; CHECK-NEXT: vslidedown.vx v0, v7, a4579; CHECK-NEXT: add a1, a1, a3580; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma581; CHECK-NEXT: vsse64.v v24, (a1), a2, v0.t582; CHECK-NEXT: ret583 call void @llvm.experimental.vp.strided.store.nxv17f64.p0.i32(<vscale x 17 x double> %v, ptr %ptr, i32 %stride, <vscale x 17 x i1> %mask, i32 %evl)584 ret void585}586 587