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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc %s -mtriple=riscv64 -mattr=v -riscv-v-vector-bits-min=128 -run-pass=finalize-isel -o - | FileCheck %s3# RUN: llc %s -mtriple=riscv64 -mattr=v -riscv-v-vector-bits-min=128 -passes=finalize-isel -o - | FileCheck %s4 5# This test makes sure we peak through the COPY instruction between the6# IMPLICIT_DEF and PseudoVLE64_V_M8_MASK in order to select the tail agnostic7# policy. The test is working if the second argument to PseudoVSETVLI has bit 68# set.9 10--- |11 ; ModuleID = 'test.ll'12 source_filename = "test.ll"13 target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"14 target triple = "riscv64"15 16 ; Function Attrs: nounwind17 define <vscale x 8 x i64> @masked_load_nxv8i64(ptr %a, <vscale x 8 x i1> %mask) #0 {18 %load = call <vscale x 8 x i64> @llvm.masked.load.nxv8i64.p0(ptr %a, i32 8, <vscale x 8 x i1> %mask, <vscale x 8 x i64> undef)19 ret <vscale x 8 x i64> %load20 }21 22 attributes #0 = { nounwind "target-features"="+v" }23 24...25---26name: masked_load_nxv8i6427alignment: 428tracksRegLiveness: true29registers:30 - { id: 0, class: gpr }31 - { id: 1, class: vr }32 - { id: 2, class: vrm8nov0 }33 - { id: 3, class: vrm8 }34 - { id: 4, class: vrm8nov0 }35liveins:36 - { reg: '$x10', virtual-reg: '%0' }37 - { reg: '$v0', virtual-reg: '%1' }38frameInfo:39 maxAlignment: 140machineFunctionInfo: {}41body: |42 bb.0 (%ir-block.0):43 liveins: $x10, $v044 45 ; CHECK-LABEL: name: masked_load_nxv8i6446 ; CHECK: liveins: $x10, $v047 ; CHECK-NEXT: {{ $}}48 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v049 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x1050 ; CHECK-NEXT: $v0 = COPY [[COPY]]51 ; CHECK-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF52 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vrm8nov0 = COPY [[DEF]]53 ; CHECK-NEXT: [[PseudoVLE64_V_M8_MASK:%[0-9]+]]:vrm8nov0 = PseudoVLE64_V_M8_MASK [[COPY2]], [[COPY1]], $v0, -1, 6 /* e64 */, 1 /* ta, mu */ :: (load (s512) from %ir.a, align 8)54 ; CHECK-NEXT: $v8m8 = COPY [[PseudoVLE64_V_M8_MASK]]55 ; CHECK-NEXT: PseudoRET implicit $v8m856 %1:vr = COPY $v057 %0:gpr = COPY $x1058 $v0 = COPY %159 %3:vrm8 = IMPLICIT_DEF60 %4:vrm8nov0 = COPY %361 %2:vrm8nov0 = PseudoVLE64_V_M8_MASK %4, %0, $v0, -1, 6, 1 :: (load (s512) from %ir.a, align 8)62 $v8m8 = COPY %263 PseudoRET implicit $v8m864 65...66