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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s3 4define void @trunc_sat_i8i16_maxmin(ptr %x, ptr %y) {5; CHECK-LABEL: trunc_sat_i8i16_maxmin:6; CHECK: # %bb.0:7; CHECK-NEXT: vl1re16.v v8, (a0)8; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma9; CHECK-NEXT: vnclip.wi v8, v8, 010; CHECK-NEXT: vse8.v v8, (a1)11; CHECK-NEXT: ret12 %1 = load <vscale x 4 x i16>, ptr %x, align 1613 %2 = tail call <vscale x 4 x i16> @llvm.smax.v4i16(<vscale x 4 x i16> %1, <vscale x 4 x i16> splat (i16 -128))14 %3 = tail call <vscale x 4 x i16> @llvm.smin.v4i16(<vscale x 4 x i16> %2, <vscale x 4 x i16> splat (i16 127))15 %4 = trunc <vscale x 4 x i16> %3 to <vscale x 4 x i8>16 store <vscale x 4 x i8> %4, ptr %y, align 817 ret void18}19 20define void @trunc_sat_i8i16_minmax(ptr %x, ptr %y) {21; CHECK-LABEL: trunc_sat_i8i16_minmax:22; CHECK: # %bb.0:23; CHECK-NEXT: vl1re16.v v8, (a0)24; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma25; CHECK-NEXT: vnclip.wi v8, v8, 026; CHECK-NEXT: vse8.v v8, (a1)27; CHECK-NEXT: ret28 %1 = load <vscale x 4 x i16>, ptr %x, align 1629 %2 = tail call <vscale x 4 x i16> @llvm.smin.v4i16(<vscale x 4 x i16> %1, <vscale x 4 x i16> splat (i16 127))30 %3 = tail call <vscale x 4 x i16> @llvm.smax.v4i16(<vscale x 4 x i16> %2, <vscale x 4 x i16> splat (i16 -128))31 %4 = trunc <vscale x 4 x i16> %3 to <vscale x 4 x i8>32 store <vscale x 4 x i8> %4, ptr %y, align 833 ret void34}35 36define void @trunc_sat_i8i16_notopt(ptr %x, ptr %y) {37; CHECK-LABEL: trunc_sat_i8i16_notopt:38; CHECK: # %bb.0:39; CHECK-NEXT: vl1re16.v v8, (a0)40; CHECK-NEXT: li a0, -12741; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, ma42; CHECK-NEXT: vmax.vx v8, v8, a043; CHECK-NEXT: li a0, 12844; CHECK-NEXT: vmin.vx v8, v8, a045; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma46; CHECK-NEXT: vnsrl.wi v8, v8, 047; CHECK-NEXT: vse8.v v8, (a1)48; CHECK-NEXT: ret49 %1 = load <vscale x 4 x i16>, ptr %x, align 1650 %2 = tail call <vscale x 4 x i16> @llvm.smax.v4i16(<vscale x 4 x i16> %1, <vscale x 4 x i16> splat (i16 -127))51 %3 = tail call <vscale x 4 x i16> @llvm.smin.v4i16(<vscale x 4 x i16> %2, <vscale x 4 x i16> splat (i16 128))52 %4 = trunc <vscale x 4 x i16> %3 to <vscale x 4 x i8>53 store <vscale x 4 x i8> %4, ptr %y, align 854 ret void55}56 57define void @trunc_sat_u8u16_min(ptr %x, ptr %y) {58; CHECK-LABEL: trunc_sat_u8u16_min:59; CHECK: # %bb.0:60; CHECK-NEXT: vl1re16.v v8, (a0)61; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma62; CHECK-NEXT: vnclipu.wi v8, v8, 063; CHECK-NEXT: vse8.v v8, (a1)64; CHECK-NEXT: ret65 %1 = load <vscale x 4 x i16>, ptr %x, align 1666 %2 = tail call <vscale x 4 x i16> @llvm.umin.v4i16(<vscale x 4 x i16> %1, <vscale x 4 x i16> splat (i16 255))67 %3 = trunc <vscale x 4 x i16> %2 to <vscale x 4 x i8>68 store <vscale x 4 x i8> %3, ptr %y, align 869 ret void70}71 72define void @trunc_sat_u8u16_notopt(ptr %x, ptr %y) {73; CHECK-LABEL: trunc_sat_u8u16_notopt:74; CHECK: # %bb.0:75; CHECK-NEXT: vl1re16.v v8, (a0)76; CHECK-NEXT: li a0, 12777; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, ma78; CHECK-NEXT: vminu.vx v8, v8, a079; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma80; CHECK-NEXT: vnsrl.wi v8, v8, 081; CHECK-NEXT: vse8.v v8, (a1)82; CHECK-NEXT: ret83 %1 = load <vscale x 4 x i16>, ptr %x, align 1684 %2 = tail call <vscale x 4 x i16> @llvm.umin.v4i16(<vscale x 4 x i16> %1, <vscale x 4 x i16> splat (i16 127))85 %3 = trunc <vscale x 4 x i16> %2 to <vscale x 4 x i8>86 store <vscale x 4 x i8> %3, ptr %y, align 887 ret void88}89 90define void @trunc_sat_u8u16_maxmin(ptr %x, ptr %y) {91; CHECK-LABEL: trunc_sat_u8u16_maxmin:92; CHECK: # %bb.0:93; CHECK-NEXT: vl1re16.v v8, (a0)94; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma95; CHECK-NEXT: vmax.vx v8, v8, zero96; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma97; CHECK-NEXT: vnclipu.wi v8, v8, 098; CHECK-NEXT: vse8.v v8, (a1)99; CHECK-NEXT: ret100 %1 = load <vscale x 4 x i16>, ptr %x, align 16101 %2 = tail call <vscale x 4 x i16> @llvm.smax.v4i16(<vscale x 4 x i16> %1, <vscale x 4 x i16> splat (i16 0))102 %3 = tail call <vscale x 4 x i16> @llvm.smin.v4i16(<vscale x 4 x i16> %2, <vscale x 4 x i16> splat (i16 255))103 %4 = trunc <vscale x 4 x i16> %3 to <vscale x 4 x i8>104 store <vscale x 4 x i8> %4, ptr %y, align 8105 ret void106}107 108define void @trunc_sat_u8u16_minmax(ptr %x, ptr %y) {109; CHECK-LABEL: trunc_sat_u8u16_minmax:110; CHECK: # %bb.0:111; CHECK-NEXT: vl1re16.v v8, (a0)112; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma113; CHECK-NEXT: vmax.vx v8, v8, zero114; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma115; CHECK-NEXT: vnclipu.wi v8, v8, 0116; CHECK-NEXT: vse8.v v8, (a1)117; CHECK-NEXT: ret118 %1 = load <vscale x 4 x i16>, ptr %x, align 16119 %2 = tail call <vscale x 4 x i16> @llvm.smin.v4i16(<vscale x 4 x i16> %1, <vscale x 4 x i16> splat (i16 255))120 %3 = tail call <vscale x 4 x i16> @llvm.smax.v4i16(<vscale x 4 x i16> %2, <vscale x 4 x i16> splat (i16 0))121 %4 = trunc <vscale x 4 x i16> %3 to <vscale x 4 x i8>122 store <vscale x 4 x i8> %4, ptr %y, align 8123 ret void124}125 126define void @trunc_sat_i16i32_notopt(ptr %x, ptr %y) {127; CHECK-LABEL: trunc_sat_i16i32_notopt:128; CHECK: # %bb.0:129; CHECK-NEXT: vl2re32.v v8, (a0)130; CHECK-NEXT: lui a0, 1048568131; CHECK-NEXT: addi a0, a0, 1132; CHECK-NEXT: vsetvli a2, zero, e32, m2, ta, ma133; CHECK-NEXT: vmax.vx v8, v8, a0134; CHECK-NEXT: lui a0, 8135; CHECK-NEXT: vmin.vx v8, v8, a0136; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma137; CHECK-NEXT: vnsrl.wi v10, v8, 0138; CHECK-NEXT: vs1r.v v10, (a1)139; CHECK-NEXT: ret140 %1 = load <vscale x 4 x i32>, ptr %x, align 32141 %2 = tail call <vscale x 4 x i32> @llvm.smax.v4i32(<vscale x 4 x i32> %1, <vscale x 4 x i32> splat (i32 -32767))142 %3 = tail call <vscale x 4 x i32> @llvm.smin.v4i32(<vscale x 4 x i32> %2, <vscale x 4 x i32> splat (i32 32768))143 %4 = trunc <vscale x 4 x i32> %3 to <vscale x 4 x i16>144 store <vscale x 4 x i16> %4, ptr %y, align 16145 ret void146}147 148define void @trunc_sat_i16i32_maxmin(ptr %x, ptr %y) {149; CHECK-LABEL: trunc_sat_i16i32_maxmin:150; CHECK: # %bb.0:151; CHECK-NEXT: vl2re32.v v8, (a0)152; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma153; CHECK-NEXT: vnclip.wi v10, v8, 0154; CHECK-NEXT: vs1r.v v10, (a1)155; CHECK-NEXT: ret156 %1 = load <vscale x 4 x i32>, ptr %x, align 32157 %2 = tail call <vscale x 4 x i32> @llvm.smax.v4i32(<vscale x 4 x i32> %1, <vscale x 4 x i32> splat (i32 -32768))158 %3 = tail call <vscale x 4 x i32> @llvm.smin.v4i32(<vscale x 4 x i32> %2, <vscale x 4 x i32> splat (i32 32767))159 %4 = trunc <vscale x 4 x i32> %3 to <vscale x 4 x i16>160 store <vscale x 4 x i16> %4, ptr %y, align 16161 ret void162}163 164define void @trunc_sat_i16i32_minmax(ptr %x, ptr %y) {165; CHECK-LABEL: trunc_sat_i16i32_minmax:166; CHECK: # %bb.0:167; CHECK-NEXT: vl2re32.v v8, (a0)168; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma169; CHECK-NEXT: vnclip.wi v10, v8, 0170; CHECK-NEXT: vs1r.v v10, (a1)171; CHECK-NEXT: ret172 %1 = load <vscale x 4 x i32>, ptr %x, align 32173 %2 = tail call <vscale x 4 x i32> @llvm.smin.v4i32(<vscale x 4 x i32> %1, <vscale x 4 x i32> splat (i32 32767))174 %3 = tail call <vscale x 4 x i32> @llvm.smax.v4i32(<vscale x 4 x i32> %2, <vscale x 4 x i32> splat (i32 -32768))175 %4 = trunc <vscale x 4 x i32> %3 to <vscale x 4 x i16>176 store <vscale x 4 x i16> %4, ptr %y, align 16177 ret void178}179 180define void @trunc_sat_u16u32_notopt(ptr %x, ptr %y) {181; CHECK-LABEL: trunc_sat_u16u32_notopt:182; CHECK: # %bb.0:183; CHECK-NEXT: vl2re32.v v8, (a0)184; CHECK-NEXT: lui a0, 8185; CHECK-NEXT: addi a0, a0, -1186; CHECK-NEXT: vsetvli a2, zero, e32, m2, ta, ma187; CHECK-NEXT: vminu.vx v8, v8, a0188; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma189; CHECK-NEXT: vnsrl.wi v10, v8, 0190; CHECK-NEXT: vs1r.v v10, (a1)191; CHECK-NEXT: ret192 %1 = load <vscale x 4 x i32>, ptr %x, align 32193 %2 = tail call <vscale x 4 x i32> @llvm.umin.v4i32(<vscale x 4 x i32> %1, <vscale x 4 x i32> splat (i32 32767))194 %3 = trunc <vscale x 4 x i32> %2 to <vscale x 4 x i16>195 store <vscale x 4 x i16> %3, ptr %y, align 16196 ret void197}198 199define void @trunc_sat_u16u32_min(ptr %x, ptr %y) {200; CHECK-LABEL: trunc_sat_u16u32_min:201; CHECK: # %bb.0:202; CHECK-NEXT: vl2re32.v v8, (a0)203; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma204; CHECK-NEXT: vnclipu.wi v10, v8, 0205; CHECK-NEXT: vs1r.v v10, (a1)206; CHECK-NEXT: ret207 %1 = load <vscale x 4 x i32>, ptr %x, align 32208 %2 = tail call <vscale x 4 x i32> @llvm.umin.v4i32(<vscale x 4 x i32> %1, <vscale x 4 x i32> splat (i32 65535))209 %3 = trunc <vscale x 4 x i32> %2 to <vscale x 4 x i16>210 store <vscale x 4 x i16> %3, ptr %y, align 16211 ret void212}213 214define void @trunc_sat_u16u32_maxmin(ptr %x, ptr %y) {215; CHECK-LABEL: trunc_sat_u16u32_maxmin:216; CHECK: # %bb.0:217; CHECK-NEXT: vl2re32.v v8, (a0)218; CHECK-NEXT: li a0, 1219; CHECK-NEXT: vsetvli a2, zero, e32, m2, ta, ma220; CHECK-NEXT: vmax.vx v8, v8, a0221; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma222; CHECK-NEXT: vnclipu.wi v10, v8, 0223; CHECK-NEXT: vs1r.v v10, (a1)224; CHECK-NEXT: ret225 %1 = load <vscale x 4 x i32>, ptr %x, align 16226 %2 = tail call <vscale x 4 x i32> @llvm.smax.v4i32(<vscale x 4 x i32> %1, <vscale x 4 x i32> splat (i32 1))227 %3 = tail call <vscale x 4 x i32> @llvm.smin.v4i32(<vscale x 4 x i32> %2, <vscale x 4 x i32> splat (i32 65535))228 %4 = trunc <vscale x 4 x i32> %3 to <vscale x 4 x i16>229 store <vscale x 4 x i16> %4, ptr %y, align 8230 ret void231}232 233define void @trunc_sat_u16u32_minmax(ptr %x, ptr %y) {234; CHECK-LABEL: trunc_sat_u16u32_minmax:235; CHECK: # %bb.0:236; CHECK-NEXT: vl2re32.v v8, (a0)237; CHECK-NEXT: li a0, 50238; CHECK-NEXT: vsetvli a2, zero, e32, m2, ta, ma239; CHECK-NEXT: vmax.vx v8, v8, a0240; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma241; CHECK-NEXT: vnclipu.wi v10, v8, 0242; CHECK-NEXT: vs1r.v v10, (a1)243; CHECK-NEXT: ret244 %1 = load <vscale x 4 x i32>, ptr %x, align 16245 %2 = tail call <vscale x 4 x i32> @llvm.smin.v4i32(<vscale x 4 x i32> %1, <vscale x 4 x i32> splat (i32 65535))246 %3 = tail call <vscale x 4 x i32> @llvm.smax.v4i32(<vscale x 4 x i32> %2, <vscale x 4 x i32> splat (i32 50))247 %4 = trunc <vscale x 4 x i32> %3 to <vscale x 4 x i16>248 store <vscale x 4 x i16> %4, ptr %y, align 8249 ret void250}251 252define void @trunc_sat_i32i64_notopt(ptr %x, ptr %y) {253; CHECK-LABEL: trunc_sat_i32i64_notopt:254; CHECK: # %bb.0:255; CHECK-NEXT: vl4re64.v v8, (a0)256; CHECK-NEXT: lui a0, 524288257; CHECK-NEXT: addi a0, a0, 1258; CHECK-NEXT: vsetvli a2, zero, e64, m4, ta, ma259; CHECK-NEXT: vmax.vx v8, v8, a0260; CHECK-NEXT: li a0, 1261; CHECK-NEXT: slli a0, a0, 31262; CHECK-NEXT: vmin.vx v8, v8, a0263; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma264; CHECK-NEXT: vnsrl.wi v12, v8, 0265; CHECK-NEXT: vs2r.v v12, (a1)266; CHECK-NEXT: ret267 %1 = load <vscale x 4 x i64>, ptr %x, align 64268 %2 = tail call <vscale x 4 x i64> @llvm.smax.v4i64(<vscale x 4 x i64> %1, <vscale x 4 x i64> splat (i64 -2147483647))269 %3 = tail call <vscale x 4 x i64> @llvm.smin.v4i64(<vscale x 4 x i64> %2, <vscale x 4 x i64> splat (i64 2147483648))270 %4 = trunc <vscale x 4 x i64> %3 to <vscale x 4 x i32>271 store <vscale x 4 x i32> %4, ptr %y, align 32272 ret void273}274 275define void @trunc_sat_i32i64_maxmin(ptr %x, ptr %y) {276; CHECK-LABEL: trunc_sat_i32i64_maxmin:277; CHECK: # %bb.0:278; CHECK-NEXT: vl4re64.v v8, (a0)279; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma280; CHECK-NEXT: vnclip.wi v12, v8, 0281; CHECK-NEXT: vs2r.v v12, (a1)282; CHECK-NEXT: ret283 %1 = load <vscale x 4 x i64>, ptr %x, align 64284 %2 = tail call <vscale x 4 x i64> @llvm.smax.v4i64(<vscale x 4 x i64> %1, <vscale x 4 x i64> splat (i64 -2147483648))285 %3 = tail call <vscale x 4 x i64> @llvm.smin.v4i64(<vscale x 4 x i64> %2, <vscale x 4 x i64> splat (i64 2147483647))286 %4 = trunc <vscale x 4 x i64> %3 to <vscale x 4 x i32>287 store <vscale x 4 x i32> %4, ptr %y, align 32288 ret void289}290 291define void @trunc_sat_i32i64_minmax(ptr %x, ptr %y) {292; CHECK-LABEL: trunc_sat_i32i64_minmax:293; CHECK: # %bb.0:294; CHECK-NEXT: vl4re64.v v8, (a0)295; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma296; CHECK-NEXT: vnclip.wi v12, v8, 0297; CHECK-NEXT: vs2r.v v12, (a1)298; CHECK-NEXT: ret299 %1 = load <vscale x 4 x i64>, ptr %x, align 64300 %2 = tail call <vscale x 4 x i64> @llvm.smin.v4i64(<vscale x 4 x i64> %1, <vscale x 4 x i64> splat (i64 2147483647))301 %3 = tail call <vscale x 4 x i64> @llvm.smax.v4i64(<vscale x 4 x i64> %2, <vscale x 4 x i64> splat (i64 -2147483648))302 %4 = trunc <vscale x 4 x i64> %3 to <vscale x 4 x i32>303 store <vscale x 4 x i32> %4, ptr %y, align 32304 ret void305}306 307define void @trunc_sat_u32u64_notopt(ptr %x, ptr %y) {308; CHECK-LABEL: trunc_sat_u32u64_notopt:309; CHECK: # %bb.0:310; CHECK-NEXT: vl4re64.v v8, (a0)311; CHECK-NEXT: lui a0, 524288312; CHECK-NEXT: addiw a0, a0, -1313; CHECK-NEXT: vsetvli a2, zero, e64, m4, ta, ma314; CHECK-NEXT: vminu.vx v8, v8, a0315; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma316; CHECK-NEXT: vnsrl.wi v12, v8, 0317; CHECK-NEXT: vs2r.v v12, (a1)318; CHECK-NEXT: ret319 %1 = load <vscale x 4 x i64>, ptr %x, align 64320 %2 = tail call <vscale x 4 x i64> @llvm.umin.v4i64(<vscale x 4 x i64> %1, <vscale x 4 x i64> splat (i64 2147483647))321 %3 = trunc <vscale x 4 x i64> %2 to <vscale x 4 x i32>322 store <vscale x 4 x i32> %3, ptr %y, align 32323 ret void324}325 326define void @trunc_sat_u32u64_min(ptr %x, ptr %y) {327; CHECK-LABEL: trunc_sat_u32u64_min:328; CHECK: # %bb.0:329; CHECK-NEXT: vl4re64.v v8, (a0)330; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma331; CHECK-NEXT: vnclipu.wi v12, v8, 0332; CHECK-NEXT: vs2r.v v12, (a1)333; CHECK-NEXT: ret334 %1 = load <vscale x 4 x i64>, ptr %x, align 64335 %2 = tail call <vscale x 4 x i64> @llvm.umin.v4i64(<vscale x 4 x i64> %1, <vscale x 4 x i64> splat (i64 4294967295))336 %3 = trunc <vscale x 4 x i64> %2 to <vscale x 4 x i32>337 store <vscale x 4 x i32> %3, ptr %y, align 32338 ret void339}340 341define void @trunc_sat_u32u64_maxmin(ptr %x, ptr %y) {342; CHECK-LABEL: trunc_sat_u32u64_maxmin:343; CHECK: # %bb.0:344; CHECK-NEXT: vl4re64.v v8, (a0)345; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma346; CHECK-NEXT: vmax.vx v8, v8, zero347; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma348; CHECK-NEXT: vnclipu.wi v12, v8, 0349; CHECK-NEXT: vs2r.v v12, (a1)350; CHECK-NEXT: ret351 %1 = load <vscale x 4 x i64>, ptr %x, align 16352 %2 = tail call <vscale x 4 x i64> @llvm.smax.v4i64(<vscale x 4 x i64> %1, <vscale x 4 x i64> splat (i64 0))353 %3 = tail call <vscale x 4 x i64> @llvm.smin.v4i64(<vscale x 4 x i64> %2, <vscale x 4 x i64> splat (i64 4294967295))354 %4 = trunc <vscale x 4 x i64> %3 to <vscale x 4 x i32>355 store <vscale x 4 x i32> %4, ptr %y, align 8356 ret void357}358 359define void @trunc_sat_u32u64_minmax(ptr %x, ptr %y) {360; CHECK-LABEL: trunc_sat_u32u64_minmax:361; CHECK: # %bb.0:362; CHECK-NEXT: vl4re64.v v8, (a0)363; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma364; CHECK-NEXT: vmax.vx v8, v8, zero365; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma366; CHECK-NEXT: vnclipu.wi v12, v8, 0367; CHECK-NEXT: vs2r.v v12, (a1)368; CHECK-NEXT: ret369 %1 = load <vscale x 4 x i64>, ptr %x, align 16370 %2 = tail call <vscale x 4 x i64> @llvm.smin.v4i64(<vscale x 4 x i64> %1, <vscale x 4 x i64> splat (i64 4294967295))371 %3 = tail call <vscale x 4 x i64> @llvm.smax.v4i64(<vscale x 4 x i64> %2, <vscale x 4 x i64> splat (i64 0))372 %4 = trunc <vscale x 4 x i64> %3 to <vscale x 4 x i32>373 store <vscale x 4 x i32> %4, ptr %y, align 8374 ret void375}376 377define void @trunc_sat_i8i32_maxmin(ptr %x, ptr %y) {378; CHECK-LABEL: trunc_sat_i8i32_maxmin:379; CHECK: # %bb.0:380; CHECK-NEXT: vl2re32.v v8, (a0)381; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma382; CHECK-NEXT: vnclip.wi v10, v8, 0383; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma384; CHECK-NEXT: vnclip.wi v8, v10, 0385; CHECK-NEXT: vse8.v v8, (a1)386; CHECK-NEXT: ret387 %1 = load <vscale x 4 x i32>, ptr %x, align 16388 %2 = tail call <vscale x 4 x i32> @llvm.smax.v4i32(<vscale x 4 x i32> %1, <vscale x 4 x i32> splat (i32 -128))389 %3 = tail call <vscale x 4 x i32> @llvm.smin.v4i32(<vscale x 4 x i32> %2, <vscale x 4 x i32> splat (i32 127))390 %4 = trunc <vscale x 4 x i32> %3 to <vscale x 4 x i8>391 store <vscale x 4 x i8> %4, ptr %y, align 8392 ret void393}394 395define void @trunc_sat_i8i32_minmax(ptr %x, ptr %y) {396; CHECK-LABEL: trunc_sat_i8i32_minmax:397; CHECK: # %bb.0:398; CHECK-NEXT: vl2re32.v v8, (a0)399; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma400; CHECK-NEXT: vnclip.wi v10, v8, 0401; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma402; CHECK-NEXT: vnclip.wi v8, v10, 0403; CHECK-NEXT: vse8.v v8, (a1)404; CHECK-NEXT: ret405 %1 = load <vscale x 4 x i32>, ptr %x, align 16406 %2 = tail call <vscale x 4 x i32> @llvm.smin.v4i32(<vscale x 4 x i32> %1, <vscale x 4 x i32> splat (i32 127))407 %3 = tail call <vscale x 4 x i32> @llvm.smax.v4i32(<vscale x 4 x i32> %2, <vscale x 4 x i32> splat (i32 -128))408 %4 = trunc <vscale x 4 x i32> %3 to <vscale x 4 x i8>409 store <vscale x 4 x i8> %4, ptr %y, align 8410 ret void411}412 413define void @trunc_sat_u8u32_min(ptr %x, ptr %y) {414; CHECK-LABEL: trunc_sat_u8u32_min:415; CHECK: # %bb.0:416; CHECK-NEXT: vl2re32.v v8, (a0)417; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma418; CHECK-NEXT: vnclipu.wi v10, v8, 0419; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma420; CHECK-NEXT: vnclipu.wi v8, v10, 0421; CHECK-NEXT: vse8.v v8, (a1)422; CHECK-NEXT: ret423 %1 = load <vscale x 4 x i32>, ptr %x, align 16424 %2 = tail call <vscale x 4 x i32> @llvm.umin.v4i32(<vscale x 4 x i32> %1, <vscale x 4 x i32> splat (i32 255))425 %3 = trunc <vscale x 4 x i32> %2 to <vscale x 4 x i8>426 store <vscale x 4 x i8> %3, ptr %y, align 8427 ret void428}429 430define void @trunc_sat_u8u32_maxmin(ptr %x, ptr %y) {431; CHECK-LABEL: trunc_sat_u8u32_maxmin:432; CHECK: # %bb.0:433; CHECK-NEXT: vl2re32.v v8, (a0)434; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma435; CHECK-NEXT: vmax.vx v8, v8, zero436; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma437; CHECK-NEXT: vnclipu.wi v10, v8, 0438; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma439; CHECK-NEXT: vnclipu.wi v8, v10, 0440; CHECK-NEXT: vse8.v v8, (a1)441; CHECK-NEXT: ret442 %1 = load <vscale x 4 x i32>, ptr %x, align 16443 %2 = tail call <vscale x 4 x i32> @llvm.smax.v4i32(<vscale x 4 x i32> %1, <vscale x 4 x i32> splat (i32 0))444 %3 = tail call <vscale x 4 x i32> @llvm.smin.v4i32(<vscale x 4 x i32> %2, <vscale x 4 x i32> splat (i32 255))445 %4 = trunc <vscale x 4 x i32> %3 to <vscale x 4 x i8>446 store <vscale x 4 x i8> %4, ptr %y, align 8447 ret void448}449 450define void @trunc_sat_u8u32_minmax(ptr %x, ptr %y) {451; CHECK-LABEL: trunc_sat_u8u32_minmax:452; CHECK: # %bb.0:453; CHECK-NEXT: vl2re32.v v8, (a0)454; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma455; CHECK-NEXT: vmax.vx v8, v8, zero456; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma457; CHECK-NEXT: vnclipu.wi v10, v8, 0458; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma459; CHECK-NEXT: vnclipu.wi v8, v10, 0460; CHECK-NEXT: vse8.v v8, (a1)461; CHECK-NEXT: ret462 %1 = load <vscale x 4 x i32>, ptr %x, align 16463 %2 = tail call <vscale x 4 x i32> @llvm.smin.v4i32(<vscale x 4 x i32> %1, <vscale x 4 x i32> splat (i32 255))464 %3 = tail call <vscale x 4 x i32> @llvm.smax.v4i32(<vscale x 4 x i32> %2, <vscale x 4 x i32> splat (i32 0))465 %4 = trunc <vscale x 4 x i32> %3 to <vscale x 4 x i8>466 store <vscale x 4 x i8> %4, ptr %y, align 8467 ret void468}469 470define void @trunc_sat_i8i64_maxmin(ptr %x, ptr %y) {471; CHECK-LABEL: trunc_sat_i8i64_maxmin:472; CHECK: # %bb.0:473; CHECK-NEXT: vl4re64.v v8, (a0)474; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma475; CHECK-NEXT: vnclip.wi v12, v8, 0476; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma477; CHECK-NEXT: vnclip.wi v8, v12, 0478; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma479; CHECK-NEXT: vnclip.wi v8, v8, 0480; CHECK-NEXT: vse8.v v8, (a1)481; CHECK-NEXT: ret482 %1 = load <vscale x 4 x i64>, ptr %x, align 16483 %2 = tail call <vscale x 4 x i64> @llvm.smax.v4i64(<vscale x 4 x i64> %1, <vscale x 4 x i64> splat (i64 -128))484 %3 = tail call <vscale x 4 x i64> @llvm.smin.v4i64(<vscale x 4 x i64> %2, <vscale x 4 x i64> splat (i64 127))485 %4 = trunc <vscale x 4 x i64> %3 to <vscale x 4 x i8>486 store <vscale x 4 x i8> %4, ptr %y, align 8487 ret void488}489 490define void @trunc_sat_i8i64_minmax(ptr %x, ptr %y) {491; CHECK-LABEL: trunc_sat_i8i64_minmax:492; CHECK: # %bb.0:493; CHECK-NEXT: vl4re64.v v8, (a0)494; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma495; CHECK-NEXT: vnclip.wi v12, v8, 0496; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma497; CHECK-NEXT: vnclip.wi v8, v12, 0498; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma499; CHECK-NEXT: vnclip.wi v8, v8, 0500; CHECK-NEXT: vse8.v v8, (a1)501; CHECK-NEXT: ret502 %1 = load <vscale x 4 x i64>, ptr %x, align 16503 %2 = tail call <vscale x 4 x i64> @llvm.smin.v4i64(<vscale x 4 x i64> %1, <vscale x 4 x i64> splat (i64 127))504 %3 = tail call <vscale x 4 x i64> @llvm.smax.v4i64(<vscale x 4 x i64> %2, <vscale x 4 x i64> splat (i64 -128))505 %4 = trunc <vscale x 4 x i64> %3 to <vscale x 4 x i8>506 store <vscale x 4 x i8> %4, ptr %y, align 8507 ret void508}509 510define void @trunc_sat_u8u64_min(ptr %x, ptr %y) {511; CHECK-LABEL: trunc_sat_u8u64_min:512; CHECK: # %bb.0:513; CHECK-NEXT: vl4re64.v v8, (a0)514; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma515; CHECK-NEXT: vnclipu.wi v12, v8, 0516; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma517; CHECK-NEXT: vnclipu.wi v8, v12, 0518; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma519; CHECK-NEXT: vnclipu.wi v8, v8, 0520; CHECK-NEXT: vse8.v v8, (a1)521; CHECK-NEXT: ret522 %1 = load <vscale x 4 x i64>, ptr %x, align 16523 %2 = tail call <vscale x 4 x i64> @llvm.umin.v4i64(<vscale x 4 x i64> %1, <vscale x 4 x i64> splat (i64 255))524 %3 = trunc <vscale x 4 x i64> %2 to <vscale x 4 x i8>525 store <vscale x 4 x i8> %3, ptr %y, align 8526 ret void527}528 529define void @trunc_sat_u8u64_maxmin(ptr %x, ptr %y) {530; CHECK-LABEL: trunc_sat_u8u64_maxmin:531; CHECK: # %bb.0:532; CHECK-NEXT: vl4re64.v v8, (a0)533; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma534; CHECK-NEXT: vmax.vx v8, v8, zero535; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma536; CHECK-NEXT: vnclipu.wi v12, v8, 0537; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma538; CHECK-NEXT: vnclipu.wi v8, v12, 0539; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma540; CHECK-NEXT: vnclipu.wi v8, v8, 0541; CHECK-NEXT: vse8.v v8, (a1)542; CHECK-NEXT: ret543 %1 = load <vscale x 4 x i64>, ptr %x, align 16544 %2 = tail call <vscale x 4 x i64> @llvm.smax.v4i64(<vscale x 4 x i64> %1, <vscale x 4 x i64> splat (i64 0))545 %3 = tail call <vscale x 4 x i64> @llvm.smin.v4i64(<vscale x 4 x i64> %2, <vscale x 4 x i64> splat (i64 255))546 %4 = trunc <vscale x 4 x i64> %3 to <vscale x 4 x i8>547 store <vscale x 4 x i8> %4, ptr %y, align 8548 ret void549}550 551define void @trunc_sat_u8u64_minmax(ptr %x, ptr %y) {552; CHECK-LABEL: trunc_sat_u8u64_minmax:553; CHECK: # %bb.0:554; CHECK-NEXT: vl4re64.v v8, (a0)555; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma556; CHECK-NEXT: vmax.vx v8, v8, zero557; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma558; CHECK-NEXT: vnclipu.wi v12, v8, 0559; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma560; CHECK-NEXT: vnclipu.wi v8, v12, 0561; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma562; CHECK-NEXT: vnclipu.wi v8, v8, 0563; CHECK-NEXT: vse8.v v8, (a1)564; CHECK-NEXT: ret565 %1 = load <vscale x 4 x i64>, ptr %x, align 16566 %2 = tail call <vscale x 4 x i64> @llvm.smin.v4i64(<vscale x 4 x i64> %1, <vscale x 4 x i64> splat (i64 255))567 %3 = tail call <vscale x 4 x i64> @llvm.smax.v4i64(<vscale x 4 x i64> %2, <vscale x 4 x i64> splat (i64 0))568 %4 = trunc <vscale x 4 x i64> %3 to <vscale x 4 x i8>569 store <vscale x 4 x i8> %4, ptr %y, align 8570 ret void571}572 573define void @trunc_sat_i16i64_maxmin(ptr %x, ptr %y) {574; CHECK-LABEL: trunc_sat_i16i64_maxmin:575; CHECK: # %bb.0:576; CHECK-NEXT: vl4re64.v v8, (a0)577; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma578; CHECK-NEXT: vnclip.wi v12, v8, 0579; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma580; CHECK-NEXT: vnclip.wi v8, v12, 0581; CHECK-NEXT: vs1r.v v8, (a1)582; CHECK-NEXT: ret583 %1 = load <vscale x 4 x i64>, ptr %x, align 32584 %2 = tail call <vscale x 4 x i64> @llvm.smax.v4i64(<vscale x 4 x i64> %1, <vscale x 4 x i64> splat (i64 -32768))585 %3 = tail call <vscale x 4 x i64> @llvm.smin.v4i64(<vscale x 4 x i64> %2, <vscale x 4 x i64> splat (i64 32767))586 %4 = trunc <vscale x 4 x i64> %3 to <vscale x 4 x i16>587 store <vscale x 4 x i16> %4, ptr %y, align 16588 ret void589}590 591define void @trunc_sat_i16i64_minmax(ptr %x, ptr %y) {592; CHECK-LABEL: trunc_sat_i16i64_minmax:593; CHECK: # %bb.0:594; CHECK-NEXT: vl4re64.v v8, (a0)595; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma596; CHECK-NEXT: vnclip.wi v12, v8, 0597; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma598; CHECK-NEXT: vnclip.wi v8, v12, 0599; CHECK-NEXT: vs1r.v v8, (a1)600; CHECK-NEXT: ret601 %1 = load <vscale x 4 x i64>, ptr %x, align 32602 %2 = tail call <vscale x 4 x i64> @llvm.smin.v4i64(<vscale x 4 x i64> %1, <vscale x 4 x i64> splat (i64 32767))603 %3 = tail call <vscale x 4 x i64> @llvm.smax.v4i64(<vscale x 4 x i64> %2, <vscale x 4 x i64> splat (i64 -32768))604 %4 = trunc <vscale x 4 x i64> %3 to <vscale x 4 x i16>605 store <vscale x 4 x i16> %4, ptr %y, align 16606 ret void607}608 609define void @trunc_sat_u16u64_min(ptr %x, ptr %y) {610; CHECK-LABEL: trunc_sat_u16u64_min:611; CHECK: # %bb.0:612; CHECK-NEXT: vl4re64.v v8, (a0)613; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma614; CHECK-NEXT: vnclipu.wi v12, v8, 0615; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma616; CHECK-NEXT: vnclipu.wi v8, v12, 0617; CHECK-NEXT: vs1r.v v8, (a1)618; CHECK-NEXT: ret619 %1 = load <vscale x 4 x i64>, ptr %x, align 32620 %2 = tail call <vscale x 4 x i64> @llvm.umin.v4i64(<vscale x 4 x i64> %1, <vscale x 4 x i64> splat (i64 65535))621 %3 = trunc <vscale x 4 x i64> %2 to <vscale x 4 x i16>622 store <vscale x 4 x i16> %3, ptr %y, align 16623 ret void624}625 626define void @trunc_sat_u16u64_maxmin(ptr %x, ptr %y) {627; CHECK-LABEL: trunc_sat_u16u64_maxmin:628; CHECK: # %bb.0:629; CHECK-NEXT: vl4re64.v v8, (a0)630; CHECK-NEXT: li a0, 1631; CHECK-NEXT: vsetvli a2, zero, e64, m4, ta, ma632; CHECK-NEXT: vmax.vx v8, v8, a0633; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma634; CHECK-NEXT: vnclipu.wi v12, v8, 0635; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma636; CHECK-NEXT: vnclipu.wi v8, v12, 0637; CHECK-NEXT: vs1r.v v8, (a1)638; CHECK-NEXT: ret639 %1 = load <vscale x 4 x i64>, ptr %x, align 16640 %2 = tail call <vscale x 4 x i64> @llvm.smax.v4i64(<vscale x 4 x i64> %1, <vscale x 4 x i64> splat (i64 1))641 %3 = tail call <vscale x 4 x i64> @llvm.smin.v4i64(<vscale x 4 x i64> %2, <vscale x 4 x i64> splat (i64 65535))642 %4 = trunc <vscale x 4 x i64> %3 to <vscale x 4 x i16>643 store <vscale x 4 x i16> %4, ptr %y, align 8644 ret void645}646 647define void @trunc_sat_u16u64_minmax(ptr %x, ptr %y) {648; CHECK-LABEL: trunc_sat_u16u64_minmax:649; CHECK: # %bb.0:650; CHECK-NEXT: vl4re64.v v8, (a0)651; CHECK-NEXT: li a0, 50652; CHECK-NEXT: vsetvli a2, zero, e64, m4, ta, ma653; CHECK-NEXT: vmax.vx v8, v8, a0654; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma655; CHECK-NEXT: vnclipu.wi v12, v8, 0656; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma657; CHECK-NEXT: vnclipu.wi v8, v12, 0658; CHECK-NEXT: vs1r.v v8, (a1)659; CHECK-NEXT: ret660 %1 = load <vscale x 4 x i64>, ptr %x, align 16661 %2 = tail call <vscale x 4 x i64> @llvm.smin.v4i64(<vscale x 4 x i64> %1, <vscale x 4 x i64> splat (i64 65535))662 %3 = tail call <vscale x 4 x i64> @llvm.smax.v4i64(<vscale x 4 x i64> %2, <vscale x 4 x i64> splat (i64 50))663 %4 = trunc <vscale x 4 x i64> %3 to <vscale x 4 x i16>664 store <vscale x 4 x i16> %4, ptr %y, align 8665 ret void666}667