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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc < %s -mtriple=riscv64 -mattr=+v | FileCheck %s3; RUN: llc < %s -mtriple=riscv64 -mattr=+zve64x,+zvl128b | FileCheck %s4 5define <4 x i8> @test_v4i16_v4i8(<4 x i16> %x) {6; CHECK-LABEL: test_v4i16_v4i8:7; CHECK: # %bb.0:8; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma9; CHECK-NEXT: vmax.vx v8, v8, zero10; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma11; CHECK-NEXT: vnclipu.wi v8, v8, 012; CHECK-NEXT: ret13 %a = icmp sgt <4 x i16> %x, zeroinitializer14 %b = sext <4 x i1> %a to <4 x i16>15 %c = icmp ult <4 x i16> %x, splat (i16 256)16 %d = select <4 x i1> %c, <4 x i16> %x, <4 x i16> %b17 %e = trunc <4 x i16> %d to <4 x i8>18 ret <4 x i8> %e19}20 21define <4 x i8> @test_v4i32_v4i8(<4 x i32> %x) {22; CHECK-LABEL: test_v4i32_v4i8:23; CHECK: # %bb.0:24; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma25; CHECK-NEXT: vmax.vx v8, v8, zero26; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma27; CHECK-NEXT: vnclipu.wi v8, v8, 028; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma29; CHECK-NEXT: vnclipu.wi v8, v8, 030; CHECK-NEXT: ret31 %a = icmp sgt <4 x i32> %x, zeroinitializer32 %b = sext <4 x i1> %a to <4 x i32>33 %c = icmp ult <4 x i32> %x, splat (i32 256)34 %d = select <4 x i1> %c, <4 x i32> %x, <4 x i32> %b35 %e = trunc <4 x i32> %d to <4 x i8>36 ret <4 x i8> %e37}38 39define <4 x i8> @test_v4i64_v4i8(<4 x i64> %x) {40; CHECK-LABEL: test_v4i64_v4i8:41; CHECK: # %bb.0:42; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma43; CHECK-NEXT: vmax.vx v8, v8, zero44; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma45; CHECK-NEXT: vnclipu.wi v10, v8, 046; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma47; CHECK-NEXT: vnclipu.wi v8, v10, 048; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma49; CHECK-NEXT: vnclipu.wi v8, v8, 050; CHECK-NEXT: ret51 %a = icmp sgt <4 x i64> %x, zeroinitializer52 %b = sext <4 x i1> %a to <4 x i64>53 %c = icmp ult <4 x i64> %x, splat (i64 256)54 %d = select <4 x i1> %c, <4 x i64> %x, <4 x i64> %b55 %e = trunc <4 x i64> %d to <4 x i8>56 ret <4 x i8> %e57}58 59define <4 x i16> @test_v4i32_v4i16(<4 x i32> %x) {60; CHECK-LABEL: test_v4i32_v4i16:61; CHECK: # %bb.0:62; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma63; CHECK-NEXT: vmax.vx v8, v8, zero64; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma65; CHECK-NEXT: vnclipu.wi v8, v8, 066; CHECK-NEXT: ret67 %a = icmp sgt <4 x i32> %x, zeroinitializer68 %b = sext <4 x i1> %a to <4 x i32>69 %c = icmp ult <4 x i32> %x, splat (i32 65536)70 %d = select <4 x i1> %c, <4 x i32> %x, <4 x i32> %b71 %e = trunc <4 x i32> %d to <4 x i16>72 ret <4 x i16> %e73}74 75define <4 x i16> @test_v4i64_v4i16(<4 x i64> %x) {76; CHECK-LABEL: test_v4i64_v4i16:77; CHECK: # %bb.0:78; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma79; CHECK-NEXT: vmax.vx v8, v8, zero80; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma81; CHECK-NEXT: vnclipu.wi v10, v8, 082; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma83; CHECK-NEXT: vnclipu.wi v8, v10, 084; CHECK-NEXT: ret85 %a = icmp sgt <4 x i64> %x, zeroinitializer86 %b = sext <4 x i1> %a to <4 x i64>87 %c = icmp ult <4 x i64> %x, splat (i64 65536)88 %d = select <4 x i1> %c, <4 x i64> %x, <4 x i64> %b89 %e = trunc <4 x i64> %d to <4 x i16>90 ret <4 x i16> %e91}92 93define <4 x i32> @test_v4i64_v4i32(<4 x i64> %x) {94; CHECK-LABEL: test_v4i64_v4i32:95; CHECK: # %bb.0:96; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma97; CHECK-NEXT: vmax.vx v10, v8, zero98; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma99; CHECK-NEXT: vnclipu.wi v8, v10, 0100; CHECK-NEXT: ret101 %a = icmp sgt <4 x i64> %x, zeroinitializer102 %b = sext <4 x i1> %a to <4 x i64>103 %c = icmp ult <4 x i64> %x, splat (i64 4294967296)104 %d = select <4 x i1> %c, <4 x i64> %x, <4 x i64> %b105 %e = trunc <4 x i64> %d to <4 x i32>106 ret <4 x i32> %e107}108 109define <vscale x 4 x i8> @test_nxv4i16_nxv4i8(<vscale x 4 x i16> %x) {110; CHECK-LABEL: test_nxv4i16_nxv4i8:111; CHECK: # %bb.0:112; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma113; CHECK-NEXT: vmax.vx v8, v8, zero114; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma115; CHECK-NEXT: vnclipu.wi v8, v8, 0116; CHECK-NEXT: ret117 %a = icmp sgt <vscale x 4 x i16> %x, zeroinitializer118 %b = sext <vscale x 4 x i1> %a to <vscale x 4 x i16>119 %c = icmp ult <vscale x 4 x i16> %x, splat (i16 256)120 %d = select <vscale x 4 x i1> %c, <vscale x 4 x i16> %x, <vscale x 4 x i16> %b121 %e = trunc <vscale x 4 x i16> %d to <vscale x 4 x i8>122 ret <vscale x 4 x i8> %e123}124 125define <vscale x 4 x i8> @test_nxv4i32_nxv4i8(<vscale x 4 x i32> %x) {126; CHECK-LABEL: test_nxv4i32_nxv4i8:127; CHECK: # %bb.0:128; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma129; CHECK-NEXT: vmax.vx v8, v8, zero130; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma131; CHECK-NEXT: vnclipu.wi v10, v8, 0132; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma133; CHECK-NEXT: vnclipu.wi v8, v10, 0134; CHECK-NEXT: ret135 %a = icmp sgt <vscale x 4 x i32> %x, zeroinitializer136 %b = sext <vscale x 4 x i1> %a to <vscale x 4 x i32>137 %c = icmp ult <vscale x 4 x i32> %x, splat (i32 256)138 %d = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %x, <vscale x 4 x i32> %b139 %e = trunc <vscale x 4 x i32> %d to <vscale x 4 x i8>140 ret <vscale x 4 x i8> %e141}142 143define <vscale x 4 x i8> @test_nxv4i64_nxv4i8(<vscale x 4 x i64> %x) {144; CHECK-LABEL: test_nxv4i64_nxv4i8:145; CHECK: # %bb.0:146; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma147; CHECK-NEXT: vmax.vx v8, v8, zero148; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma149; CHECK-NEXT: vnclipu.wi v12, v8, 0150; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma151; CHECK-NEXT: vnclipu.wi v8, v12, 0152; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma153; CHECK-NEXT: vnclipu.wi v8, v8, 0154; CHECK-NEXT: ret155 %a = icmp sgt <vscale x 4 x i64> %x, zeroinitializer156 %b = sext <vscale x 4 x i1> %a to <vscale x 4 x i64>157 %c = icmp ult <vscale x 4 x i64> %x, splat (i64 256)158 %d = select <vscale x 4 x i1> %c, <vscale x 4 x i64> %x, <vscale x 4 x i64> %b159 %e = trunc <vscale x 4 x i64> %d to <vscale x 4 x i8>160 ret <vscale x 4 x i8> %e161}162 163define <vscale x 4 x i16> @test_nxv4i32_nxv4i16(<vscale x 4 x i32> %x) {164; CHECK-LABEL: test_nxv4i32_nxv4i16:165; CHECK: # %bb.0:166; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma167; CHECK-NEXT: vmax.vx v10, v8, zero168; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma169; CHECK-NEXT: vnclipu.wi v8, v10, 0170; CHECK-NEXT: ret171 %a = icmp sgt <vscale x 4 x i32> %x, zeroinitializer172 %b = sext <vscale x 4 x i1> %a to <vscale x 4 x i32>173 %c = icmp ult <vscale x 4 x i32> %x, splat (i32 65536)174 %d = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %x, <vscale x 4 x i32> %b175 %e = trunc <vscale x 4 x i32> %d to <vscale x 4 x i16>176 ret <vscale x 4 x i16> %e177}178 179define <vscale x 4 x i16> @test_nxv4i64_nxv4i16(<vscale x 4 x i64> %x) {180; CHECK-LABEL: test_nxv4i64_nxv4i16:181; CHECK: # %bb.0:182; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma183; CHECK-NEXT: vmax.vx v8, v8, zero184; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma185; CHECK-NEXT: vnclipu.wi v12, v8, 0186; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma187; CHECK-NEXT: vnclipu.wi v8, v12, 0188; CHECK-NEXT: ret189 %a = icmp sgt <vscale x 4 x i64> %x, zeroinitializer190 %b = sext <vscale x 4 x i1> %a to <vscale x 4 x i64>191 %c = icmp ult <vscale x 4 x i64> %x, splat (i64 65536)192 %d = select <vscale x 4 x i1> %c, <vscale x 4 x i64> %x, <vscale x 4 x i64> %b193 %e = trunc <vscale x 4 x i64> %d to <vscale x 4 x i16>194 ret <vscale x 4 x i16> %e195}196 197define <vscale x 4 x i32> @test_nxv4i64_nxv4i32(<vscale x 4 x i64> %x) {198; CHECK-LABEL: test_nxv4i64_nxv4i32:199; CHECK: # %bb.0:200; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma201; CHECK-NEXT: vmax.vx v12, v8, zero202; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma203; CHECK-NEXT: vnclipu.wi v8, v12, 0204; CHECK-NEXT: ret205 %a = icmp sgt <vscale x 4 x i64> %x, zeroinitializer206 %b = sext <vscale x 4 x i1> %a to <vscale x 4 x i64>207 %c = icmp ult <vscale x 4 x i64> %x, splat (i64 4294967296)208 %d = select <vscale x 4 x i1> %c, <vscale x 4 x i64> %x, <vscale x 4 x i64> %b209 %e = trunc <vscale x 4 x i64> %d to <vscale x 4 x i32>210 ret <vscale x 4 x i32> %e211}212