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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple riscv64 -mattr=+v -enable-subreg-liveness < %s | FileCheck %s3 4define <vscale x 2 x float> @vrgather_all_undef(ptr %p) {5; CHECK-LABEL: vrgather_all_undef:6; CHECK: # %bb.0: # %entry7; CHECK-NEXT: vsetivli zero, 0, e32, m1, ta, ma8; CHECK-NEXT: vrgather.vi v8, v9, 09; CHECK-NEXT: ret10entry:11 %0 = tail call <vscale x 2 x float> @llvm.riscv.vrgather.vx.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> poison, i64 0, i64 0)12 ret <vscale x 2 x float> %013}14 15define dso_local signext i32 @undef_early_clobber_chain() {16; CHECK-LABEL: undef_early_clobber_chain:17; CHECK: # %bb.0: # %entry18; CHECK-NEXT: addi sp, sp, -40019; CHECK-NEXT: .cfi_def_cfa_offset 40020; CHECK-NEXT: vsetivli zero, 0, e32, m1, ta, ma21; CHECK-NEXT: vrgather.vi v9, v8, 022; CHECK-NEXT: mv a0, sp23; CHECK-NEXT: vse32.v v9, (a0)24; CHECK-NEXT: li a0, 025; CHECK-NEXT: addi sp, sp, 40026; CHECK-NEXT: .cfi_def_cfa_offset 027; CHECK-NEXT: ret28entry:29 %dst = alloca [100 x float], align 830 call void @llvm.lifetime.start.p0(i64 400, ptr nonnull %dst) #431 %0 = tail call <vscale x 2 x float> @llvm.riscv.vrgather.vx.nxv2f32.i64(<vscale x 2 x float> poison, <vscale x 2 x float> poison, i64 0, i64 0)32 call void @llvm.riscv.vse.nxv2f32.i64(<vscale x 2 x float> %0, ptr nonnull %dst, i64 0)33 call void @llvm.lifetime.end.p0(i64 400, ptr nonnull %dst) #434 ret i32 035}36 37define internal void @SubRegLivenessUndefInPhi(i64 %cond) {38; CHECK-LABEL: SubRegLivenessUndefInPhi:39; CHECK: # %bb.0: # %start40; CHECK-NEXT: blez a0, .LBB2_241; CHECK-NEXT: # %bb.1: # %Cond142; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma43; CHECK-NEXT: vid.v v844; CHECK-NEXT: vadd.vi v12, v8, 145; CHECK-NEXT: vadd.vi v10, v8, 346; CHECK-NEXT: j .LBB2_347; CHECK-NEXT: .LBB2_2: # %Cond248; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma49; CHECK-NEXT: vid.v v950; CHECK-NEXT: csrr a0, vlenb51; CHECK-NEXT: srli a1, a0, 252; CHECK-NEXT: srli a0, a0, 353; CHECK-NEXT: vadd.vi v10, v9, 154; CHECK-NEXT: vadd.vi v11, v9, 355; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma56; CHECK-NEXT: vslideup.vx v8, v9, a057; CHECK-NEXT: vslideup.vx v12, v10, a058; CHECK-NEXT: vslideup.vx v10, v11, a059; CHECK-NEXT: .LBB2_3: # %UseSR60; CHECK-NEXT: vl1r.v v14, (zero)61; CHECK-NEXT: vsetivli zero, 4, e8, m1, ta, ma62; CHECK-NEXT: vrgatherei16.vv v15, v14, v863; CHECK-NEXT: vrgatherei16.vv v8, v14, v1264; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma65; CHECK-NEXT: vand.vv v8, v15, v866; CHECK-NEXT: vsetivli zero, 4, e8, m1, ta, ma67; CHECK-NEXT: vrgatherei16.vv v9, v14, v1068; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma69; CHECK-NEXT: vand.vv v8, v8, v970; CHECK-NEXT: vs1r.v v8, (zero)71; CHECK-NEXT: ret72start:73 %0 = icmp sgt i64 %cond, 074 br i1 %0, label %Cond1, label %Cond275 76Cond1: ; preds = %start77 %v15 = tail call <vscale x 1 x i16> @llvm.stepvector.nxv1i16()78 %v17 = tail call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16> poison, <vscale x 1 x i16> %v15, i64 0)79 %vs12.i.i.i = add <vscale x 1 x i16> %v15, splat (i16 1)80 %v18 = tail call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16> poison, <vscale x 1 x i16> %vs12.i.i.i, i64 0)81 %vs16.i.i.i = add <vscale x 1 x i16> %v15, splat (i16 3)82 %v20 = tail call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16> poison, <vscale x 1 x i16> %vs16.i.i.i, i64 0)83 br label %UseSR84 85Cond2: ; preds = %start86 %v15.2 = tail call <vscale x 1 x i16> @llvm.stepvector.nxv1i16()87 %v17.2 = tail call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16> poison, <vscale x 1 x i16> %v15.2, i64 1)88 %vs12.i.i.i.2 = add <vscale x 1 x i16> %v15.2, splat (i16 1)89 %v18.2 = tail call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16> poison, <vscale x 1 x i16> %vs12.i.i.i.2, i64 1)90 %vs16.i.i.i.2 = add <vscale x 1 x i16> %v15.2, splat (i16 3)91 %v20.2 = tail call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16> poison, <vscale x 1 x i16> %vs16.i.i.i.2, i64 1)92 br label %UseSR93 94UseSR: ; preds = %Cond1, Cond295 %v17.3 = phi <vscale x 8 x i16> [ %v17, %Cond1 ], [ %v17.2, %Cond2 ]96 %v18.3 = phi <vscale x 8 x i16> [ %v18, %Cond1 ], [ %v18.2, %Cond2 ]97 %v20.3 = phi <vscale x 8 x i16> [ %v20, %Cond1 ], [ %v20.2, %Cond2 ]98 %v37 = load <vscale x 8 x i8>, ptr addrspace(1) null, align 899 %v38 = tail call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %v37, <vscale x 8 x i16> %v17.3, i64 4)100 %v40 = tail call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %v37, <vscale x 8 x i16> %v18.3, i64 4)101 %v42 = and <vscale x 8 x i8> %v38, %v40102 %v46 = tail call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %v37, <vscale x 8 x i16> %v20.3, i64 4)103 %v60 = and <vscale x 8 x i8> %v42, %v46104 store <vscale x 8 x i8> %v60, ptr addrspace(1) null, align 4105 ret void106}107 108define internal void @SubRegLivenessUndef() {109; CHECK-LABEL: SubRegLivenessUndef:110; CHECK: # %bb.0: # %loopIR.preheader.i.i111; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma112; CHECK-NEXT: vid.v v8113; CHECK-NEXT: vadd.vi v10, v8, 1114; CHECK-NEXT: vadd.vi v12, v8, 3115; CHECK-NEXT: .LBB3_1: # %loopIR3.i.i116; CHECK-NEXT: # =>This Inner Loop Header: Depth=1117; CHECK-NEXT: vl1r.v v14, (zero)118; CHECK-NEXT: vsetivli zero, 4, e8, m1, ta, ma119; CHECK-NEXT: vrgatherei16.vv v15, v14, v8120; CHECK-NEXT: vrgatherei16.vv v9, v14, v10121; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma122; CHECK-NEXT: vand.vv v9, v15, v9123; CHECK-NEXT: vsetivli zero, 4, e8, m1, ta, ma124; CHECK-NEXT: vrgatherei16.vv v11, v14, v12125; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma126; CHECK-NEXT: vand.vv v9, v9, v11127; CHECK-NEXT: vs1r.v v9, (zero)128; CHECK-NEXT: j .LBB3_1129loopIR.preheader.i.i:130 %v15 = tail call <vscale x 1 x i16> @llvm.stepvector.nxv1i16()131 %v17 = tail call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16> poison, <vscale x 1 x i16> %v15, i64 0)132 %vs12.i.i.i = add <vscale x 1 x i16> %v15, splat (i16 1)133 %v18 = tail call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16> poison, <vscale x 1 x i16> %vs12.i.i.i, i64 0)134 %vs16.i.i.i = add <vscale x 1 x i16> %v15, splat (i16 3)135 %v20 = tail call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16> poison, <vscale x 1 x i16> %vs16.i.i.i, i64 0)136 br label %loopIR3.i.i137 138loopIR3.i.i: ; preds = %loopIR3.i.i, %loopIR.preheader.i.i139 %v37 = load <vscale x 8 x i8>, ptr addrspace(1) null, align 8140 %v38 = tail call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %v37, <vscale x 8 x i16> %v17, i64 4)141 %v40 = tail call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %v37, <vscale x 8 x i16> %v18, i64 4)142 %v42 = and <vscale x 8 x i8> %v38, %v40143 %v46 = tail call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %v37, <vscale x 8 x i16> %v20, i64 4)144 %v60 = and <vscale x 8 x i8> %v42, %v46145 store <vscale x 8 x i8> %v60, ptr addrspace(1) null, align 4146 br label %loopIR3.i.i147}148 149define void @repeat_shuffle(<2 x double> %v, ptr noalias %q) {150; CHECK-LABEL: repeat_shuffle:151; CHECK: # %bb.0:152; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma153; CHECK-NEXT: vmv2r.v v10, v8154; CHECK-NEXT: vslideup.vi v10, v8, 2155; CHECK-NEXT: vse64.v v10, (a0)156; CHECK-NEXT: ret157 %w = shufflevector <2 x double> %v, <2 x double> poison, <4 x i32> <i32 0, i32 1, i32 0, i32 1>158 store <4 x double> %w, ptr %q159 ret void160}161