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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \3; RUN: -verify-machineinstrs < %s | FileCheck %s4; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \5; RUN: -verify-machineinstrs < %s | FileCheck %s6 7; Test that we can remove trivially-poison VP operations of various kinds.8 9define <4 x i32> @vload_v4i32_zero_evl(ptr %ptr, <4 x i1> %m) {10; CHECK-LABEL: vload_v4i32_zero_evl:11; CHECK: # %bb.0:12; CHECK-NEXT: ret13 %v = call <4 x i32> @llvm.vp.load.v4i32.p0(ptr %ptr, <4 x i1> %m, i32 0)14 ret <4 x i32> %v15}16 17define <4 x i32> @vload_v4i32_false_mask(ptr %ptr, i32 %evl) {18; CHECK-LABEL: vload_v4i32_false_mask:19; CHECK: # %bb.0:20; CHECK-NEXT: ret21 %v = call <4 x i32> @llvm.vp.load.v4i32.p0(ptr %ptr, <4 x i1> zeroinitializer, i32 %evl)22 ret <4 x i32> %v23}24 25define <4 x i32> @vgather_v4i32_v4i32_zero_evl(<4 x ptr> %ptrs, <4 x i1> %m) {26; CHECK-LABEL: vgather_v4i32_v4i32_zero_evl:27; CHECK: # %bb.0:28; CHECK-NEXT: ret29 %v = call <4 x i32> @llvm.vp.gather.v4i32.v4p0(<4 x ptr> %ptrs, <4 x i1> %m, i32 0)30 ret <4 x i32> %v31}32 33define <4 x i32> @vgather_v4i32_v4i32_false_mask(<4 x ptr> %ptrs, i32 %evl) {34; CHECK-LABEL: vgather_v4i32_v4i32_false_mask:35; CHECK: # %bb.0:36; CHECK-NEXT: ret37 %v = call <4 x i32> @llvm.vp.gather.v4i32.v4p0(<4 x ptr> %ptrs, <4 x i1> zeroinitializer, i32 %evl)38 ret <4 x i32> %v39}40 41define void @vstore_v4i32_zero_evl(<4 x i32> %val, ptr %ptr, <4 x i1> %m) {42; CHECK-LABEL: vstore_v4i32_zero_evl:43; CHECK: # %bb.0:44; CHECK-NEXT: ret45 call void @llvm.vp.store.v4i32.p0(<4 x i32> %val, ptr %ptr, <4 x i1> %m, i32 0)46 ret void47}48 49define void @vstore_v4i32_false_mask(<4 x i32> %val, ptr %ptr, i32 %evl) {50; CHECK-LABEL: vstore_v4i32_false_mask:51; CHECK: # %bb.0:52; CHECK-NEXT: ret53 call void @llvm.vp.store.v4i32.p0(<4 x i32> %val, ptr %ptr, <4 x i1> zeroinitializer, i32 %evl)54 ret void55}56 57define void @vscatter_v4i32_zero_evl(<4 x i32> %val, <4 x ptr> %ptrs, <4 x i1> %m) {58; CHECK-LABEL: vscatter_v4i32_zero_evl:59; CHECK: # %bb.0:60; CHECK-NEXT: ret61 call void @llvm.vp.scatter.v4i32.v4p0(<4 x i32> %val, <4 x ptr> %ptrs, <4 x i1> %m, i32 0)62 ret void63}64 65define void @vscatter_v4i32_false_mask(<4 x i32> %val, <4 x ptr> %ptrs, i32 %evl) {66; CHECK-LABEL: vscatter_v4i32_false_mask:67; CHECK: # %bb.0:68; CHECK-NEXT: ret69 call void @llvm.vp.scatter.v4i32.v4p0(<4 x i32> %val, <4 x ptr> %ptrs, <4 x i1> zeroinitializer, i32 %evl)70 ret void71}72 73define <4 x i32> @vadd_v4i32_zero_evl(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m) {74; CHECK-LABEL: vadd_v4i32_zero_evl:75; CHECK: # %bb.0:76; CHECK-NEXT: ret77 %s = call <4 x i32> @llvm.vp.add.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 0)78 ret <4 x i32> %s79}80 81define <4 x i32> @vadd_v4i32_false_mask(<4 x i32> %va, <4 x i32> %vb, i32 %evl) {82; CHECK-LABEL: vadd_v4i32_false_mask:83; CHECK: # %bb.0:84; CHECK-NEXT: ret85 %s = call <4 x i32> @llvm.vp.add.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> zeroinitializer, i32 %evl)86 ret <4 x i32> %s87}88 89define <4 x i32> @vand_v4i32_zero_evl(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m) {90; CHECK-LABEL: vand_v4i32_zero_evl:91; CHECK: # %bb.0:92; CHECK-NEXT: ret93 %s = call <4 x i32> @llvm.vp.and.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 0)94 ret <4 x i32> %s95}96 97define <4 x i32> @vand_v4i32_false_mask(<4 x i32> %va, <4 x i32> %vb, i32 %evl) {98; CHECK-LABEL: vand_v4i32_false_mask:99; CHECK: # %bb.0:100; CHECK-NEXT: ret101 %s = call <4 x i32> @llvm.vp.and.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> zeroinitializer, i32 %evl)102 ret <4 x i32> %s103}104 105define <4 x i32> @vlshr_v4i32_zero_evl(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m) {106; CHECK-LABEL: vlshr_v4i32_zero_evl:107; CHECK: # %bb.0:108; CHECK-NEXT: ret109 %s = call <4 x i32> @llvm.vp.lshr.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 0)110 ret <4 x i32> %s111}112 113define <4 x i32> @vlshr_v4i32_false_mask(<4 x i32> %va, <4 x i32> %vb, i32 %evl) {114; CHECK-LABEL: vlshr_v4i32_false_mask:115; CHECK: # %bb.0:116; CHECK-NEXT: ret117 %s = call <4 x i32> @llvm.vp.lshr.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> zeroinitializer, i32 %evl)118 ret <4 x i32> %s119}120 121define <4 x i32> @vmul_v4i32_zero_evl(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m) {122; CHECK-LABEL: vmul_v4i32_zero_evl:123; CHECK: # %bb.0:124; CHECK-NEXT: ret125 %s = call <4 x i32> @llvm.vp.mul.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 0)126 ret <4 x i32> %s127}128 129define <4 x i32> @vmul_v4i32_false_mask(<4 x i32> %va, <4 x i32> %vb, i32 %evl) {130; CHECK-LABEL: vmul_v4i32_false_mask:131; CHECK: # %bb.0:132; CHECK-NEXT: ret133 %s = call <4 x i32> @llvm.vp.mul.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> zeroinitializer, i32 %evl)134 ret <4 x i32> %s135}136 137define <4 x i32> @vor_v4i32_zero_evl(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m) {138; CHECK-LABEL: vor_v4i32_zero_evl:139; CHECK: # %bb.0:140; CHECK-NEXT: ret141 %s = call <4 x i32> @llvm.vp.or.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 0)142 ret <4 x i32> %s143}144 145define <4 x i32> @vor_v4i32_false_mask(<4 x i32> %va, <4 x i32> %vb, i32 %evl) {146; CHECK-LABEL: vor_v4i32_false_mask:147; CHECK: # %bb.0:148; CHECK-NEXT: ret149 %s = call <4 x i32> @llvm.vp.or.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> zeroinitializer, i32 %evl)150 ret <4 x i32> %s151}152 153define <4 x i32> @vsdiv_v4i32_zero_evl(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m) {154; CHECK-LABEL: vsdiv_v4i32_zero_evl:155; CHECK: # %bb.0:156; CHECK-NEXT: ret157 %s = call <4 x i32> @llvm.vp.sdiv.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 0)158 ret <4 x i32> %s159}160 161define <4 x i32> @vsdiv_v4i32_false_mask(<4 x i32> %va, <4 x i32> %vb, i32 %evl) {162; CHECK-LABEL: vsdiv_v4i32_false_mask:163; CHECK: # %bb.0:164; CHECK-NEXT: ret165 %s = call <4 x i32> @llvm.vp.sdiv.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> zeroinitializer, i32 %evl)166 ret <4 x i32> %s167}168 169define <4 x i32> @vsrem_v4i32_zero_evl(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m) {170; CHECK-LABEL: vsrem_v4i32_zero_evl:171; CHECK: # %bb.0:172; CHECK-NEXT: ret173 %s = call <4 x i32> @llvm.vp.srem.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 0)174 ret <4 x i32> %s175}176 177define <4 x i32> @vsrem_v4i32_false_mask(<4 x i32> %va, <4 x i32> %vb, i32 %evl) {178; CHECK-LABEL: vsrem_v4i32_false_mask:179; CHECK: # %bb.0:180; CHECK-NEXT: ret181 %s = call <4 x i32> @llvm.vp.srem.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> zeroinitializer, i32 %evl)182 ret <4 x i32> %s183}184 185define <4 x i32> @vsub_v4i32_zero_evl(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m) {186; CHECK-LABEL: vsub_v4i32_zero_evl:187; CHECK: # %bb.0:188; CHECK-NEXT: ret189 %s = call <4 x i32> @llvm.vp.sub.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 0)190 ret <4 x i32> %s191}192 193define <4 x i32> @vsub_v4i32_false_mask(<4 x i32> %va, <4 x i32> %vb, i32 %evl) {194; CHECK-LABEL: vsub_v4i32_false_mask:195; CHECK: # %bb.0:196; CHECK-NEXT: ret197 %s = call <4 x i32> @llvm.vp.sub.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> zeroinitializer, i32 %evl)198 ret <4 x i32> %s199}200 201define <4 x i32> @vudiv_v4i32_zero_evl(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m) {202; CHECK-LABEL: vudiv_v4i32_zero_evl:203; CHECK: # %bb.0:204; CHECK-NEXT: ret205 %s = call <4 x i32> @llvm.vp.udiv.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 0)206 ret <4 x i32> %s207}208 209define <4 x i32> @vudiv_v4i32_false_mask(<4 x i32> %va, <4 x i32> %vb, i32 %evl) {210; CHECK-LABEL: vudiv_v4i32_false_mask:211; CHECK: # %bb.0:212; CHECK-NEXT: ret213 %s = call <4 x i32> @llvm.vp.udiv.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> zeroinitializer, i32 %evl)214 ret <4 x i32> %s215}216 217define <4 x i32> @vurem_v4i32_zero_evl(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m) {218; CHECK-LABEL: vurem_v4i32_zero_evl:219; CHECK: # %bb.0:220; CHECK-NEXT: ret221 %s = call <4 x i32> @llvm.vp.urem.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 0)222 ret <4 x i32> %s223}224 225define <4 x i32> @vurem_v4i32_false_mask(<4 x i32> %va, <4 x i32> %vb, i32 %evl) {226; CHECK-LABEL: vurem_v4i32_false_mask:227; CHECK: # %bb.0:228; CHECK-NEXT: ret229 %s = call <4 x i32> @llvm.vp.urem.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> zeroinitializer, i32 %evl)230 ret <4 x i32> %s231}232 233define <4 x i32> @vxor_v4i32_zero_evl(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m) {234; CHECK-LABEL: vxor_v4i32_zero_evl:235; CHECK: # %bb.0:236; CHECK-NEXT: ret237 %s = call <4 x i32> @llvm.vp.xor.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 0)238 ret <4 x i32> %s239}240 241define <4 x i32> @vxor_v4i32_false_mask(<4 x i32> %va, <4 x i32> %vb, i32 %evl) {242; CHECK-LABEL: vxor_v4i32_false_mask:243; CHECK: # %bb.0:244; CHECK-NEXT: ret245 %s = call <4 x i32> @llvm.vp.xor.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> zeroinitializer, i32 %evl)246 ret <4 x i32> %s247}248 249define <4 x float> @vfadd_v4f32_zero_evl(<4 x float> %va, <4 x float> %vb, <4 x i1> %m) {250; CHECK-LABEL: vfadd_v4f32_zero_evl:251; CHECK: # %bb.0:252; CHECK-NEXT: ret253 %s = call <4 x float> @llvm.vp.fadd.v4f32(<4 x float> %va, <4 x float> %vb, <4 x i1> %m, i32 0)254 ret <4 x float> %s255}256 257define <4 x float> @vfadd_v4f32_false_mask(<4 x float> %va, <4 x float> %vb, i32 %evl) {258; CHECK-LABEL: vfadd_v4f32_false_mask:259; CHECK: # %bb.0:260; CHECK-NEXT: ret261 %s = call <4 x float> @llvm.vp.fadd.v4f32(<4 x float> %va, <4 x float> %vb, <4 x i1> zeroinitializer, i32 %evl)262 ret <4 x float> %s263}264 265define <4 x float> @vfsub_v4f32_zero_evl(<4 x float> %va, <4 x float> %vb, <4 x i1> %m) {266; CHECK-LABEL: vfsub_v4f32_zero_evl:267; CHECK: # %bb.0:268; CHECK-NEXT: ret269 %s = call <4 x float> @llvm.vp.fsub.v4f32(<4 x float> %va, <4 x float> %vb, <4 x i1> %m, i32 0)270 ret <4 x float> %s271}272 273define <4 x float> @vfsub_v4f32_false_mask(<4 x float> %va, <4 x float> %vb, i32 %evl) {274; CHECK-LABEL: vfsub_v4f32_false_mask:275; CHECK: # %bb.0:276; CHECK-NEXT: ret277 %s = call <4 x float> @llvm.vp.fsub.v4f32(<4 x float> %va, <4 x float> %vb, <4 x i1> zeroinitializer, i32 %evl)278 ret <4 x float> %s279}280 281define <4 x float> @vfmul_v4f32_zero_evl(<4 x float> %va, <4 x float> %vb, <4 x i1> %m) {282; CHECK-LABEL: vfmul_v4f32_zero_evl:283; CHECK: # %bb.0:284; CHECK-NEXT: ret285 %s = call <4 x float> @llvm.vp.fmul.v4f32(<4 x float> %va, <4 x float> %vb, <4 x i1> %m, i32 0)286 ret <4 x float> %s287}288 289define <4 x float> @vfmul_v4f32_false_mask(<4 x float> %va, <4 x float> %vb, i32 %evl) {290; CHECK-LABEL: vfmul_v4f32_false_mask:291; CHECK: # %bb.0:292; CHECK-NEXT: ret293 %s = call <4 x float> @llvm.vp.fmul.v4f32(<4 x float> %va, <4 x float> %vb, <4 x i1> zeroinitializer, i32 %evl)294 ret <4 x float> %s295}296 297define <4 x float> @vfdiv_v4f32_zero_evl(<4 x float> %va, <4 x float> %vb, <4 x i1> %m) {298; CHECK-LABEL: vfdiv_v4f32_zero_evl:299; CHECK: # %bb.0:300; CHECK-NEXT: ret301 %s = call <4 x float> @llvm.vp.fdiv.v4f32(<4 x float> %va, <4 x float> %vb, <4 x i1> %m, i32 0)302 ret <4 x float> %s303}304 305define <4 x float> @vfdiv_v4f32_false_mask(<4 x float> %va, <4 x float> %vb, i32 %evl) {306; CHECK-LABEL: vfdiv_v4f32_false_mask:307; CHECK: # %bb.0:308; CHECK-NEXT: ret309 %s = call <4 x float> @llvm.vp.fdiv.v4f32(<4 x float> %va, <4 x float> %vb, <4 x i1> zeroinitializer, i32 %evl)310 ret <4 x float> %s311}312 313define <4 x float> @vfrem_v4f32_zero_evl(<4 x float> %va, <4 x float> %vb, <4 x i1> %m) {314; CHECK-LABEL: vfrem_v4f32_zero_evl:315; CHECK: # %bb.0:316; CHECK-NEXT: ret317 %s = call <4 x float> @llvm.vp.frem.v4f32(<4 x float> %va, <4 x float> %vb, <4 x i1> %m, i32 0)318 ret <4 x float> %s319}320 321define <4 x float> @vfrem_v4f32_false_mask(<4 x float> %va, <4 x float> %vb, i32 %evl) {322; CHECK-LABEL: vfrem_v4f32_false_mask:323; CHECK: # %bb.0:324; CHECK-NEXT: ret325 %s = call <4 x float> @llvm.vp.frem.v4f32(<4 x float> %va, <4 x float> %vb, <4 x i1> zeroinitializer, i32 %evl)326 ret <4 x float> %s327}328 329define i32 @vreduce_add_v4i32_zero_evl(i32 %start, <4 x i32> %val, <4 x i1> %m) {330; CHECK-LABEL: vreduce_add_v4i32_zero_evl:331; CHECK: # %bb.0:332; CHECK-NEXT: ret333 %s = call i32 @llvm.vp.reduce.add.v4i32(i32 %start, <4 x i32> %val, <4 x i1> %m, i32 0)334 ret i32 %s335}336 337define i32 @vreduce_add_v4i32_false_mask(i32 %start, <4 x i32> %val, i32 %evl) {338; CHECK-LABEL: vreduce_add_v4i32_false_mask:339; CHECK: # %bb.0:340; CHECK-NEXT: ret341 %s = call i32 @llvm.vp.reduce.add.v4i32(i32 %start, <4 x i32> %val, <4 x i1> zeroinitializer, i32 %evl)342 ret i32 %s343}344 345define i32 @vreduce_mul_v4i32_zero_evl(i32 %start, <4 x i32> %val, <4 x i1> %m) {346; CHECK-LABEL: vreduce_mul_v4i32_zero_evl:347; CHECK: # %bb.0:348; CHECK-NEXT: ret349 %s = call i32 @llvm.vp.reduce.mul.v4i32(i32 %start, <4 x i32> %val, <4 x i1> %m, i32 0)350 ret i32 %s351}352 353define i32 @vreduce_mul_v4i32_false_mask(i32 %start, <4 x i32> %val, i32 %evl) {354; CHECK-LABEL: vreduce_mul_v4i32_false_mask:355; CHECK: # %bb.0:356; CHECK-NEXT: ret357 %s = call i32 @llvm.vp.reduce.mul.v4i32(i32 %start, <4 x i32> %val, <4 x i1> zeroinitializer, i32 %evl)358 ret i32 %s359}360 361define i32 @vreduce_and_v4i32_zero_evl(i32 %start, <4 x i32> %val, <4 x i1> %m) {362; CHECK-LABEL: vreduce_and_v4i32_zero_evl:363; CHECK: # %bb.0:364; CHECK-NEXT: ret365 %s = call i32 @llvm.vp.reduce.and.v4i32(i32 %start, <4 x i32> %val, <4 x i1> %m, i32 0)366 ret i32 %s367}368 369define i32 @vreduce_and_v4i32_false_mask(i32 %start, <4 x i32> %val, i32 %evl) {370; CHECK-LABEL: vreduce_and_v4i32_false_mask:371; CHECK: # %bb.0:372; CHECK-NEXT: ret373 %s = call i32 @llvm.vp.reduce.and.v4i32(i32 %start, <4 x i32> %val, <4 x i1> zeroinitializer, i32 %evl)374 ret i32 %s375}376 377define i32 @vreduce_or_v4i32_zero_evl(i32 %start, <4 x i32> %val, <4 x i1> %m) {378; CHECK-LABEL: vreduce_or_v4i32_zero_evl:379; CHECK: # %bb.0:380; CHECK-NEXT: ret381 %s = call i32 @llvm.vp.reduce.or.v4i32(i32 %start, <4 x i32> %val, <4 x i1> %m, i32 0)382 ret i32 %s383}384 385define i32 @vreduce_or_v4i32_false_mask(i32 %start, <4 x i32> %val, i32 %evl) {386; CHECK-LABEL: vreduce_or_v4i32_false_mask:387; CHECK: # %bb.0:388; CHECK-NEXT: ret389 %s = call i32 @llvm.vp.reduce.or.v4i32(i32 %start, <4 x i32> %val, <4 x i1> zeroinitializer, i32 %evl)390 ret i32 %s391}392 393define i32 @vreduce_xor_v4i32_zero_evl(i32 %start, <4 x i32> %val, <4 x i1> %m) {394; CHECK-LABEL: vreduce_xor_v4i32_zero_evl:395; CHECK: # %bb.0:396; CHECK-NEXT: ret397 %s = call i32 @llvm.vp.reduce.xor.v4i32(i32 %start, <4 x i32> %val, <4 x i1> %m, i32 0)398 ret i32 %s399}400 401define i32 @vreduce_xor_v4i32_false_mask(i32 %start, <4 x i32> %val, i32 %evl) {402; CHECK-LABEL: vreduce_xor_v4i32_false_mask:403; CHECK: # %bb.0:404; CHECK-NEXT: ret405 %s = call i32 @llvm.vp.reduce.xor.v4i32(i32 %start, <4 x i32> %val, <4 x i1> zeroinitializer, i32 %evl)406 ret i32 %s407}408 409define i32 @vreduce_smax_v4i32_zero_evl(i32 %start, <4 x i32> %val, <4 x i1> %m) {410; CHECK-LABEL: vreduce_smax_v4i32_zero_evl:411; CHECK: # %bb.0:412; CHECK-NEXT: ret413 %s = call i32 @llvm.vp.reduce.smax.v4i32(i32 %start, <4 x i32> %val, <4 x i1> %m, i32 0)414 ret i32 %s415}416 417define i32 @vreduce_smax_v4i32_false_mask(i32 %start, <4 x i32> %val, i32 %evl) {418; CHECK-LABEL: vreduce_smax_v4i32_false_mask:419; CHECK: # %bb.0:420; CHECK-NEXT: ret421 %s = call i32 @llvm.vp.reduce.smax.v4i32(i32 %start, <4 x i32> %val, <4 x i1> zeroinitializer, i32 %evl)422 ret i32 %s423}424 425define i32 @vreduce_smin_v4i32_zero_evl(i32 %start, <4 x i32> %val, <4 x i1> %m) {426; CHECK-LABEL: vreduce_smin_v4i32_zero_evl:427; CHECK: # %bb.0:428; CHECK-NEXT: ret429 %s = call i32 @llvm.vp.reduce.smin.v4i32(i32 %start, <4 x i32> %val, <4 x i1> %m, i32 0)430 ret i32 %s431}432 433define i32 @vreduce_smin_v4i32_false_mask(i32 %start, <4 x i32> %val, i32 %evl) {434; CHECK-LABEL: vreduce_smin_v4i32_false_mask:435; CHECK: # %bb.0:436; CHECK-NEXT: ret437 %s = call i32 @llvm.vp.reduce.smin.v4i32(i32 %start, <4 x i32> %val, <4 x i1> zeroinitializer, i32 %evl)438 ret i32 %s439}440 441define i32 @vreduce_umax_v4i32_zero_evl(i32 %start, <4 x i32> %val, <4 x i1> %m) {442; CHECK-LABEL: vreduce_umax_v4i32_zero_evl:443; CHECK: # %bb.0:444; CHECK-NEXT: ret445 %s = call i32 @llvm.vp.reduce.umax.v4i32(i32 %start, <4 x i32> %val, <4 x i1> %m, i32 0)446 ret i32 %s447}448 449define i32 @vreduce_umax_v4i32_false_mask(i32 %start, <4 x i32> %val, i32 %evl) {450; CHECK-LABEL: vreduce_umax_v4i32_false_mask:451; CHECK: # %bb.0:452; CHECK-NEXT: ret453 %s = call i32 @llvm.vp.reduce.umax.v4i32(i32 %start, <4 x i32> %val, <4 x i1> zeroinitializer, i32 %evl)454 ret i32 %s455}456 457define i32 @vreduce_umin_v4i32_zero_evl(i32 %start, <4 x i32> %val, <4 x i1> %m) {458; CHECK-LABEL: vreduce_umin_v4i32_zero_evl:459; CHECK: # %bb.0:460; CHECK-NEXT: ret461 %s = call i32 @llvm.vp.reduce.umin.v4i32(i32 %start, <4 x i32> %val, <4 x i1> %m, i32 0)462 ret i32 %s463}464 465define i32 @vreduce_umin_v4i32_false_mask(i32 %start, <4 x i32> %val, i32 %evl) {466; CHECK-LABEL: vreduce_umin_v4i32_false_mask:467; CHECK: # %bb.0:468; CHECK-NEXT: ret469 %s = call i32 @llvm.vp.reduce.umin.v4i32(i32 %start, <4 x i32> %val, <4 x i1> zeroinitializer, i32 %evl)470 ret i32 %s471}472 473define float @vreduce_seq_fadd_v4f32_zero_evl(float %start, <4 x float> %val, <4 x i1> %m) {474; CHECK-LABEL: vreduce_seq_fadd_v4f32_zero_evl:475; CHECK: # %bb.0:476; CHECK-NEXT: ret477 %s = call float @llvm.vp.reduce.fadd.v4f32(float %start, <4 x float> %val, <4 x i1> %m, i32 0)478 ret float %s479}480 481define float @vreduce_seq_fadd_v4f32_false_mask(float %start, <4 x float> %val, i32 %evl) {482; CHECK-LABEL: vreduce_seq_fadd_v4f32_false_mask:483; CHECK: # %bb.0:484; CHECK-NEXT: ret485 %s = call float @llvm.vp.reduce.fadd.v4f32(float %start, <4 x float> %val, <4 x i1> zeroinitializer, i32 %evl)486 ret float %s487}488 489define float @vreduce_fadd_v4f32_zero_evl(float %start, <4 x float> %val, <4 x i1> %m) {490; CHECK-LABEL: vreduce_fadd_v4f32_zero_evl:491; CHECK: # %bb.0:492; CHECK-NEXT: ret493 %s = call reassoc float @llvm.vp.reduce.fadd.v4f32(float %start, <4 x float> %val, <4 x i1> %m, i32 0)494 ret float %s495}496 497define float @vreduce_fadd_v4f32_false_mask(float %start, <4 x float> %val, i32 %evl) {498; CHECK-LABEL: vreduce_fadd_v4f32_false_mask:499; CHECK: # %bb.0:500; CHECK-NEXT: ret501 %s = call reassoc float @llvm.vp.reduce.fadd.v4f32(float %start, <4 x float> %val, <4 x i1> zeroinitializer, i32 %evl)502 ret float %s503}504 505define float @vreduce_seq_fmul_v4f32_zero_evl(float %start, <4 x float> %val, <4 x i1> %m) {506; CHECK-LABEL: vreduce_seq_fmul_v4f32_zero_evl:507; CHECK: # %bb.0:508; CHECK-NEXT: ret509 %s = call float @llvm.vp.reduce.fmul.v4f32(float %start, <4 x float> %val, <4 x i1> %m, i32 0)510 ret float %s511}512 513define float @vreduce_seq_fmul_v4f32_false_mask(float %start, <4 x float> %val, i32 %evl) {514; CHECK-LABEL: vreduce_seq_fmul_v4f32_false_mask:515; CHECK: # %bb.0:516; CHECK-NEXT: ret517 %s = call float @llvm.vp.reduce.fmul.v4f32(float %start, <4 x float> %val, <4 x i1> zeroinitializer, i32 %evl)518 ret float %s519}520 521define float @vreduce_fmul_v4f32_zero_evl(float %start, <4 x float> %val, <4 x i1> %m) {522; CHECK-LABEL: vreduce_fmul_v4f32_zero_evl:523; CHECK: # %bb.0:524; CHECK-NEXT: ret525 %s = call reassoc float @llvm.vp.reduce.fmul.v4f32(float %start, <4 x float> %val, <4 x i1> %m, i32 0)526 ret float %s527}528 529define float @vreduce_fmul_v4f32_false_mask(float %start, <4 x float> %val, i32 %evl) {530; CHECK-LABEL: vreduce_fmul_v4f32_false_mask:531; CHECK: # %bb.0:532; CHECK-NEXT: ret533 %s = call reassoc float @llvm.vp.reduce.fmul.v4f32(float %start, <4 x float> %val, <4 x i1> zeroinitializer, i32 %evl)534 ret float %s535}536 537define float @vreduce_fmin_v4f32_zero_evl(float %start, <4 x float> %val, <4 x i1> %m) {538; CHECK-LABEL: vreduce_fmin_v4f32_zero_evl:539; CHECK: # %bb.0:540; CHECK-NEXT: ret541 %s = call float @llvm.vp.reduce.fmin.v4f32(float %start, <4 x float> %val, <4 x i1> %m, i32 0)542 ret float %s543}544 545define float @vreduce_fmin_v4f32_false_mask(float %start, <4 x float> %val, i32 %evl) {546; CHECK-LABEL: vreduce_fmin_v4f32_false_mask:547; CHECK: # %bb.0:548; CHECK-NEXT: ret549 %s = call float @llvm.vp.reduce.fmin.v4f32(float %start, <4 x float> %val, <4 x i1> zeroinitializer, i32 %evl)550 ret float %s551}552 553define float @vreduce_fmax_v4f32_zero_evl(float %start, <4 x float> %val, <4 x i1> %m) {554; CHECK-LABEL: vreduce_fmax_v4f32_zero_evl:555; CHECK: # %bb.0:556; CHECK-NEXT: ret557 %s = call float @llvm.vp.reduce.fmax.v4f32(float %start, <4 x float> %val, <4 x i1> %m, i32 0)558 ret float %s559}560 561define float @vreduce_fmax_v4f32_false_mask(float %start, <4 x float> %val, i32 %evl) {562; CHECK-LABEL: vreduce_fmax_v4f32_false_mask:563; CHECK: # %bb.0:564; CHECK-NEXT: ret565 %s = call float @llvm.vp.reduce.fmax.v4f32(float %start, <4 x float> %val, <4 x i1> zeroinitializer, i32 %evl)566 ret float %s567}568 569define float @vreduce_fminimum_v4f32_zero_evl(float %start, <4 x float> %val, <4 x i1> %m) {570; CHECK-LABEL: vreduce_fminimum_v4f32_zero_evl:571; CHECK: # %bb.0:572; CHECK-NEXT: ret573 %s = call float @llvm.vp.reduce.fminimum.v4f32(float %start, <4 x float> %val, <4 x i1> %m, i32 0)574 ret float %s575}576 577define float @vreduce_fminimum_v4f32_false_mask(float %start, <4 x float> %val, i32 %evl) {578; CHECK-LABEL: vreduce_fminimum_v4f32_false_mask:579; CHECK: # %bb.0:580; CHECK-NEXT: ret581 %s = call float @llvm.vp.reduce.fminimum.v4f32(float %start, <4 x float> %val, <4 x i1> zeroinitializer, i32 %evl)582 ret float %s583}584 585define float @vreduce_fmaximum_v4f32_zero_evl(float %start, <4 x float> %val, <4 x i1> %m) {586; CHECK-LABEL: vreduce_fmaximum_v4f32_zero_evl:587; CHECK: # %bb.0:588; CHECK-NEXT: ret589 %s = call float @llvm.vp.reduce.fmaximum.v4f32(float %start, <4 x float> %val, <4 x i1> %m, i32 0)590 ret float %s591}592 593define float @vreduce_fmaximum_v4f32_false_mask(float %start, <4 x float> %val, i32 %evl) {594; CHECK-LABEL: vreduce_fmaximum_v4f32_false_mask:595; CHECK: # %bb.0:596; CHECK-NEXT: ret597 %s = call float @llvm.vp.reduce.fmaximum.v4f32(float %start, <4 x float> %val, <4 x i1> zeroinitializer, i32 %evl)598 ret float %s599}600