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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \3; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s --check-prefixes=CHECK,RV324; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \5; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s --check-prefixes=CHECK,RV646 7define <vscale x 1 x float> @intrinsic_vfmacc_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, iXLen %3) nounwind {8; CHECK-LABEL: intrinsic_vfmacc_vv_nxv1f32_nxv1f32_nxv1f32:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma11; CHECK-NEXT: vfmacc.vv v8, v10, v912; CHECK-NEXT: ret13entry:14 %a = call <vscale x 1 x float> @llvm.riscv.vfmacc.nxv1f32.nxv1f32(15 <vscale x 1 x float> %0,16 <vscale x 1 x float> %1,17 <vscale x 1 x float> %2,18 iXLen 7, iXLen %3, iXLen 1)19 20 ret <vscale x 1 x float> %a21}22 23define <vscale x 1 x float> @intrinsic_vfmadd_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, iXLen %3) nounwind {24; CHECK-LABEL: intrinsic_vfmadd_vv_nxv1f32_nxv1f32_nxv1f32:25; CHECK: # %bb.0: # %entry26; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma27; CHECK-NEXT: vfmadd.vv v8, v9, v1028; CHECK-NEXT: ret29entry:30 %a = call <vscale x 1 x float> @llvm.riscv.vfmadd.nxv1f32.nxv1f32(31 <vscale x 1 x float> %0,32 <vscale x 1 x float> %1,33 <vscale x 1 x float> %2,34 iXLen 7, iXLen %3, iXLen 1)35 36 ret <vscale x 1 x float> %a37}38 39define <vscale x 1 x float> @intrinsic_vfmsac_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, iXLen %3) nounwind {40; CHECK-LABEL: intrinsic_vfmsac_vv_nxv1f32_nxv1f32_nxv1f32:41; CHECK: # %bb.0: # %entry42; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma43; CHECK-NEXT: vfmsac.vv v8, v10, v944; CHECK-NEXT: ret45entry:46 %a = call <vscale x 1 x float> @llvm.riscv.vfmsac.nxv1f32.nxv1f32(47 <vscale x 1 x float> %0,48 <vscale x 1 x float> %1,49 <vscale x 1 x float> %2,50 iXLen 7, iXLen %3, iXLen 1)51 52 ret <vscale x 1 x float> %a53}54 55define <vscale x 1 x float> @intrinsic_vfmsub_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, iXLen %3) nounwind {56; CHECK-LABEL: intrinsic_vfmsub_vv_nxv1f32_nxv1f32_nxv1f32:57; CHECK: # %bb.0: # %entry58; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma59; CHECK-NEXT: vfmsub.vv v8, v9, v1060; CHECK-NEXT: ret61entry:62 %a = call <vscale x 1 x float> @llvm.riscv.vfmsub.nxv1f32.nxv1f32(63 <vscale x 1 x float> %0,64 <vscale x 1 x float> %1,65 <vscale x 1 x float> %2,66 iXLen 7, iXLen %3, iXLen 1)67 68 ret <vscale x 1 x float> %a69}70 71define <vscale x 1 x float> @intrinsic_vfnmacc_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, iXLen %3) nounwind {72; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv1f32_nxv1f32_nxv1f32:73; CHECK: # %bb.0: # %entry74; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma75; CHECK-NEXT: vfnmacc.vv v8, v10, v976; CHECK-NEXT: ret77entry:78 %a = call <vscale x 1 x float> @llvm.riscv.vfnmacc.nxv1f32.nxv1f32(79 <vscale x 1 x float> %0,80 <vscale x 1 x float> %1,81 <vscale x 1 x float> %2,82 iXLen 7, iXLen %3, iXLen 1)83 84 ret <vscale x 1 x float> %a85}86 87define <vscale x 1 x float> @intrinsic_vfnmadd_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, iXLen %3) nounwind {88; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv1f32_nxv1f32_nxv1f32:89; CHECK: # %bb.0: # %entry90; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma91; CHECK-NEXT: vfnmadd.vv v8, v9, v1092; CHECK-NEXT: ret93entry:94 %a = call <vscale x 1 x float> @llvm.riscv.vfnmadd.nxv1f32.nxv1f32(95 <vscale x 1 x float> %0,96 <vscale x 1 x float> %1,97 <vscale x 1 x float> %2,98 iXLen 7, iXLen %3, iXLen 1)99 100 ret <vscale x 1 x float> %a101}102 103define <vscale x 1 x float> @intrinsic_vfnmsac_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, iXLen %3) nounwind {104; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv1f32_nxv1f32_nxv1f32:105; CHECK: # %bb.0: # %entry106; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma107; CHECK-NEXT: vfnmsac.vv v8, v10, v9108; CHECK-NEXT: ret109entry:110 %a = call <vscale x 1 x float> @llvm.riscv.vfnmsac.nxv1f32.nxv1f32(111 <vscale x 1 x float> %0,112 <vscale x 1 x float> %1,113 <vscale x 1 x float> %2,114 iXLen 7, iXLen %3, iXLen 1)115 116 ret <vscale x 1 x float> %a117}118 119define <vscale x 1 x float> @intrinsic_vfnmsub_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, iXLen %3) nounwind {120; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv1f32_nxv1f32_nxv1f32:121; CHECK: # %bb.0: # %entry122; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma123; CHECK-NEXT: vfnmsub.vv v8, v9, v10124; CHECK-NEXT: ret125entry:126 %a = call <vscale x 1 x float> @llvm.riscv.vfnmsub.nxv1f32.nxv1f32(127 <vscale x 1 x float> %0,128 <vscale x 1 x float> %1,129 <vscale x 1 x float> %2,130 iXLen 7, iXLen %3, iXLen 1)131 132 ret <vscale x 1 x float> %a133}134 135define <vscale x 1 x float> @intrinsic_vfwmacc_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, iXLen %3) nounwind {136; CHECK-LABEL: intrinsic_vfwmacc_vv_nxv1f32_nxv1f16_nxv1f16:137; CHECK: # %bb.0: # %entry138; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma139; CHECK-NEXT: vfwmacc.vv v8, v9, v10140; CHECK-NEXT: ret141entry:142 %a = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1f16(143 <vscale x 1 x float> %0,144 <vscale x 1 x half> %1,145 <vscale x 1 x half> %2,146 iXLen 7, iXLen %3, iXLen 1)147 148 ret <vscale x 1 x float> %a149}150 151define <vscale x 1 x float> @intrinsic_vfwmsac_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, iXLen %3) nounwind {152; CHECK-LABEL: intrinsic_vfwmsac_vv_nxv1f32_nxv1f16_nxv1f16:153; CHECK: # %bb.0: # %entry154; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma155; CHECK-NEXT: vfwmsac.vv v8, v9, v10156; CHECK-NEXT: ret157entry:158 %a = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1f16(159 <vscale x 1 x float> %0,160 <vscale x 1 x half> %1,161 <vscale x 1 x half> %2,162 iXLen 7, iXLen %3, iXLen 1)163 164 ret <vscale x 1 x float> %a165}166 167define <vscale x 1 x float> @intrinsic_vfwnmacc_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, iXLen %3) nounwind {168; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv1f32_nxv1f16_nxv1f16:169; CHECK: # %bb.0: # %entry170; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma171; CHECK-NEXT: vfwnmacc.vv v8, v9, v10172; CHECK-NEXT: ret173entry:174 %a = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16(175 <vscale x 1 x float> %0,176 <vscale x 1 x half> %1,177 <vscale x 1 x half> %2,178 iXLen 7, iXLen %3, iXLen 1)179 180 ret <vscale x 1 x float> %a181}182 183define <vscale x 1 x float> @intrinsic_vfwnmsac_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, iXLen %3) nounwind {184; CHECK-LABEL: intrinsic_vfwnmsac_vv_nxv1f32_nxv1f16_nxv1f16:185; CHECK: # %bb.0: # %entry186; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma187; CHECK-NEXT: vfwnmsac.vv v8, v9, v10188; CHECK-NEXT: ret189entry:190 %a = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16(191 <vscale x 1 x float> %0,192 <vscale x 1 x half> %1,193 <vscale x 1 x half> %2,194 iXLen 7, iXLen %3, iXLen 1)195 196 ret <vscale x 1 x float> %a197}198 199define <vscale x 1 x i64> @intrinsic_vmacc_vx_nxv1i64_i64_nxv1i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i64> %2, iXLen %3) nounwind {200; RV32-LABEL: intrinsic_vmacc_vx_nxv1i64_i64_nxv1i64:201; RV32: # %bb.0: # %entry202; RV32-NEXT: addi sp, sp, -16203; RV32-NEXT: sw a0, 8(sp)204; RV32-NEXT: sw a1, 12(sp)205; RV32-NEXT: addi a0, sp, 8206; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma207; RV32-NEXT: vlse64.v v10, (a0), zero208; RV32-NEXT: vmacc.vv v8, v9, v10209; RV32-NEXT: addi sp, sp, 16210; RV32-NEXT: ret211;212; RV64-LABEL: intrinsic_vmacc_vx_nxv1i64_i64_nxv1i64:213; RV64: # %bb.0: # %entry214; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma215; RV64-NEXT: vmacc.vx v8, a0, v9216; RV64-NEXT: ret217entry:218 %a = call <vscale x 1 x i64> @llvm.riscv.vmacc.nxv1i64.i64(219 <vscale x 1 x i64> %0,220 i64 %1,221 <vscale x 1 x i64> %2,222 iXLen %3, iXLen 1)223 224 ret <vscale x 1 x i64> %a225}226 227define <vscale x 1 x i64> @intrinsic_vmadd_vx_nxv1i64_i64_nxv1i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i64> %2, iXLen %3) nounwind {228; RV32-LABEL: intrinsic_vmadd_vx_nxv1i64_i64_nxv1i64:229; RV32: # %bb.0: # %entry230; RV32-NEXT: addi sp, sp, -16231; RV32-NEXT: sw a0, 8(sp)232; RV32-NEXT: sw a1, 12(sp)233; RV32-NEXT: addi a0, sp, 8234; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma235; RV32-NEXT: vlse64.v v10, (a0), zero236; RV32-NEXT: vmadd.vv v8, v10, v9237; RV32-NEXT: addi sp, sp, 16238; RV32-NEXT: ret239;240; RV64-LABEL: intrinsic_vmadd_vx_nxv1i64_i64_nxv1i64:241; RV64: # %bb.0: # %entry242; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma243; RV64-NEXT: vmadd.vx v8, a0, v9244; RV64-NEXT: ret245entry:246 %a = call <vscale x 1 x i64> @llvm.riscv.vmadd.nxv1i64.i64(247 <vscale x 1 x i64> %0,248 i64 %1,249 <vscale x 1 x i64> %2,250 iXLen %3, iXLen 1)251 252 ret <vscale x 1 x i64> %a253}254 255define <vscale x 1 x i64> @intrinsic_vnmsac_vx_nxv1i64_i64_nxv1i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i64> %2, iXLen %3) nounwind {256; RV32-LABEL: intrinsic_vnmsac_vx_nxv1i64_i64_nxv1i64:257; RV32: # %bb.0: # %entry258; RV32-NEXT: addi sp, sp, -16259; RV32-NEXT: sw a0, 8(sp)260; RV32-NEXT: sw a1, 12(sp)261; RV32-NEXT: addi a0, sp, 8262; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma263; RV32-NEXT: vlse64.v v10, (a0), zero264; RV32-NEXT: vnmsac.vv v8, v9, v10265; RV32-NEXT: addi sp, sp, 16266; RV32-NEXT: ret267;268; RV64-LABEL: intrinsic_vnmsac_vx_nxv1i64_i64_nxv1i64:269; RV64: # %bb.0: # %entry270; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma271; RV64-NEXT: vnmsac.vx v8, a0, v9272; RV64-NEXT: ret273entry:274 %a = call <vscale x 1 x i64> @llvm.riscv.vnmsac.nxv1i64.i64(275 <vscale x 1 x i64> %0,276 i64 %1,277 <vscale x 1 x i64> %2,278 iXLen %3, iXLen 1)279 280 ret <vscale x 1 x i64> %a281}282 283define <vscale x 1 x i64> @intrinsic_vnmsub_vx_nxv1i64_i64_nxv1i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i64> %2, iXLen %3) nounwind {284; RV32-LABEL: intrinsic_vnmsub_vx_nxv1i64_i64_nxv1i64:285; RV32: # %bb.0: # %entry286; RV32-NEXT: addi sp, sp, -16287; RV32-NEXT: sw a0, 8(sp)288; RV32-NEXT: sw a1, 12(sp)289; RV32-NEXT: addi a0, sp, 8290; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma291; RV32-NEXT: vlse64.v v10, (a0), zero292; RV32-NEXT: vnmsub.vv v8, v10, v9293; RV32-NEXT: addi sp, sp, 16294; RV32-NEXT: ret295;296; RV64-LABEL: intrinsic_vnmsub_vx_nxv1i64_i64_nxv1i64:297; RV64: # %bb.0: # %entry298; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma299; RV64-NEXT: vnmsub.vx v8, a0, v9300; RV64-NEXT: ret301entry:302 %a = call <vscale x 1 x i64> @llvm.riscv.vnmsub.nxv1i64.i64(303 <vscale x 1 x i64> %0,304 i64 %1,305 <vscale x 1 x i64> %2,306 iXLen %3, iXLen 1)307 308 ret <vscale x 1 x i64> %a309}310 311define <vscale x 1 x i16> @intrinsic_vwmacc_vv_nxv1i16_nxv1i8_nxv1i8(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {312; CHECK-LABEL: intrinsic_vwmacc_vv_nxv1i16_nxv1i8_nxv1i8:313; CHECK: # %bb.0: # %entry314; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma315; CHECK-NEXT: vwmacc.vv v8, v9, v10316; CHECK-NEXT: ret317entry:318 %a = call <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.nxv1i8(319 <vscale x 1 x i16> %0,320 <vscale x 1 x i8> %1,321 <vscale x 1 x i8> %2,322 iXLen %3, iXLen 1)323 324 ret <vscale x 1 x i16> %a325}326 327define <vscale x 1 x i16> @intrinsic_vwmaccsu_vv_nxv1i16_nxv1i8_nxv1i8(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {328; CHECK-LABEL: intrinsic_vwmaccsu_vv_nxv1i16_nxv1i8_nxv1i8:329; CHECK: # %bb.0: # %entry330; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma331; CHECK-NEXT: vwmaccsu.vv v8, v9, v10332; CHECK-NEXT: ret333entry:334 %a = call <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8(335 <vscale x 1 x i16> %0,336 <vscale x 1 x i8> %1,337 <vscale x 1 x i8> %2,338 iXLen %3, iXLen 1)339 340 ret <vscale x 1 x i16> %a341}342 343define <vscale x 1 x i16> @intrinsic_vwmaccu_vv_nxv1i16_nxv1i8_nxv1i8(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {344; CHECK-LABEL: intrinsic_vwmaccu_vv_nxv1i16_nxv1i8_nxv1i8:345; CHECK: # %bb.0: # %entry346; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma347; CHECK-NEXT: vwmaccu.vv v8, v9, v10348; CHECK-NEXT: ret349entry:350 %a = call <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.nxv1i8(351 <vscale x 1 x i16> %0,352 <vscale x 1 x i8> %1,353 <vscale x 1 x i8> %2,354 iXLen %3, iXLen 1)355 356 ret <vscale x 1 x i16> %a357}358 359define <vscale x 1 x i16> @intrinsic_vwmaccus_vx_nxv1i16_i8_nxv1i8(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {360; CHECK-LABEL: intrinsic_vwmaccus_vx_nxv1i16_i8_nxv1i8:361; CHECK: # %bb.0: # %entry362; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma363; CHECK-NEXT: vwmaccus.vx v8, a0, v9364; CHECK-NEXT: ret365entry:366 %a = call <vscale x 1 x i16> @llvm.riscv.vwmaccus.nxv1i16.i8(367 <vscale x 1 x i16> %0,368 i8 %1,369 <vscale x 1 x i8> %2,370 iXLen %3, iXLen 1)371 372 ret <vscale x 1 x i16> %a373}374 375define <vscale x 8 x i8> @intrinsic_vredsum_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 1 x i8> %0, <vscale x 8 x i8> %1, iXLen %2) nounwind {376; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv1i8_nxv8i8:377; CHECK: # %bb.0: # %entry378; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma379; CHECK-NEXT: vredsum.vs v8, v8, v9380; CHECK-NEXT: ret381entry:382 %a = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv1i8(383 <vscale x 8 x i8> poison,384 <vscale x 1 x i8> %0,385 <vscale x 8 x i8> %1,386 iXLen %2)387 388 ret <vscale x 8 x i8> %a389}390 391define <vscale x 8 x i8> @intrinsic_vredand_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 1 x i8> %0, <vscale x 8 x i8> %1, iXLen %2) nounwind {392; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv1i8_nxv8i8:393; CHECK: # %bb.0: # %entry394; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma395; CHECK-NEXT: vredand.vs v8, v8, v9396; CHECK-NEXT: ret397entry:398 %a = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv1i8(399 <vscale x 8 x i8> poison,400 <vscale x 1 x i8> %0,401 <vscale x 8 x i8> %1,402 iXLen %2)403 404 ret <vscale x 8 x i8> %a405}406 407define <vscale x 8 x i8> @intrinsic_vredor_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 1 x i8> %0, <vscale x 8 x i8> %1, iXLen %2) nounwind {408; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv1i8_nxv8i8:409; CHECK: # %bb.0: # %entry410; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma411; CHECK-NEXT: vredor.vs v8, v8, v9412; CHECK-NEXT: ret413entry:414 %a = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv1i8(415 <vscale x 8 x i8> poison,416 <vscale x 1 x i8> %0,417 <vscale x 8 x i8> %1,418 iXLen %2)419 420 ret <vscale x 8 x i8> %a421}422 423define <vscale x 8 x i8> @intrinsic_vredxor_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 1 x i8> %0, <vscale x 8 x i8> %1, iXLen %2) nounwind {424; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv1i8_nxv8i8:425; CHECK: # %bb.0: # %entry426; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma427; CHECK-NEXT: vredxor.vs v8, v8, v9428; CHECK-NEXT: ret429entry:430 %a = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv1i8(431 <vscale x 8 x i8> poison,432 <vscale x 1 x i8> %0,433 <vscale x 8 x i8> %1,434 iXLen %2)435 436 ret <vscale x 8 x i8> %a437}438 439define <vscale x 8 x i8> @intrinsic_vredminu_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 1 x i8> %0, <vscale x 8 x i8> %1, iXLen %2) nounwind {440; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv1i8_nxv8i8:441; CHECK: # %bb.0: # %entry442; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma443; CHECK-NEXT: vredminu.vs v8, v8, v9444; CHECK-NEXT: ret445entry:446 %a = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv1i8(447 <vscale x 8 x i8> poison,448 <vscale x 1 x i8> %0,449 <vscale x 8 x i8> %1,450 iXLen %2)451 452 ret <vscale x 8 x i8> %a453}454 455define <vscale x 8 x i8> @intrinsic_vredmin_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 1 x i8> %0, <vscale x 8 x i8> %1, iXLen %2) nounwind {456; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv1i8_nxv8i8:457; CHECK: # %bb.0: # %entry458; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma459; CHECK-NEXT: vredmin.vs v8, v8, v9460; CHECK-NEXT: ret461entry:462 %a = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv1i8(463 <vscale x 8 x i8> poison,464 <vscale x 1 x i8> %0,465 <vscale x 8 x i8> %1,466 iXLen %2)467 468 ret <vscale x 8 x i8> %a469}470 471define <vscale x 8 x i8> @intrinsic_vredmaxu_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 1 x i8> %0, <vscale x 8 x i8> %1, iXLen %2) nounwind {472; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv1i8_nxv8i8:473; CHECK: # %bb.0: # %entry474; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma475; CHECK-NEXT: vredmaxu.vs v8, v8, v9476; CHECK-NEXT: ret477entry:478 %a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv1i8(479 <vscale x 8 x i8> poison,480 <vscale x 1 x i8> %0,481 <vscale x 8 x i8> %1,482 iXLen %2)483 484 ret <vscale x 8 x i8> %a485}486 487define <vscale x 8 x i8> @intrinsic_vredmax_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 1 x i8> %0, <vscale x 8 x i8> %1, iXLen %2) nounwind {488; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv1i8_nxv8i8:489; CHECK: # %bb.0: # %entry490; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma491; CHECK-NEXT: vredmax.vs v8, v8, v9492; CHECK-NEXT: ret493entry:494 %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv1i8(495 <vscale x 8 x i8> poison,496 <vscale x 1 x i8> %0,497 <vscale x 8 x i8> %1,498 iXLen %2)499 500 ret <vscale x 8 x i8> %a501}502 503define <vscale x 4 x i16> @intrinsic_vwredsumu_vs_nxv4i16_nxv1i8_nxv4i16(<vscale x 1 x i8> %0, <vscale x 4 x i16> %1, iXLen %2) nounwind {504; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv4i16_nxv1i8_nxv4i16:505; CHECK: # %bb.0: # %entry506; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma507; CHECK-NEXT: vwredsumu.vs v8, v8, v9508; CHECK-NEXT: ret509entry:510 %a = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv1i8(511 <vscale x 4 x i16> poison,512 <vscale x 1 x i8> %0,513 <vscale x 4 x i16> %1,514 iXLen %2)515 516 ret <vscale x 4 x i16> %a517}518 519define <vscale x 4 x i16> @intrinsic_vwredsum_vs_nxv4i16_nxv1i8_nxv4i16(<vscale x 1 x i8> %0, <vscale x 4 x i16> %1, iXLen %2) nounwind {520; CHECK-LABEL: intrinsic_vwredsum_vs_nxv4i16_nxv1i8_nxv4i16:521; CHECK: # %bb.0: # %entry522; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma523; CHECK-NEXT: vwredsum.vs v8, v8, v9524; CHECK-NEXT: ret525entry:526 %a = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv1i8(527 <vscale x 4 x i16> poison,528 <vscale x 1 x i8> %0,529 <vscale x 4 x i16> %1,530 iXLen %2)531 532 ret <vscale x 4 x i16> %a533}534 535define <vscale x 4 x half> @intrinsic_vfredosum_vs_nxv4f16_nxv1f16_nxv4f16(<vscale x 1 x half> %0, <vscale x 4 x half> %1, iXLen %2) nounwind {536; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv1f16_nxv4f16:537; CHECK: # %bb.0: # %entry538; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma539; CHECK-NEXT: vfredosum.vs v8, v8, v9540; CHECK-NEXT: ret541entry:542 %a = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv1f16(543 <vscale x 4 x half> poison,544 <vscale x 1 x half> %0,545 <vscale x 4 x half> %1,546 iXLen 7, iXLen %2)547 548 ret <vscale x 4 x half> %a549}550 551define <vscale x 4 x half> @intrinsic_vfredusum_vs_nxv4f16_nxv1f16_nxv4f16(<vscale x 1 x half> %0, <vscale x 4 x half> %1, iXLen %2) nounwind {552; CHECK-LABEL: intrinsic_vfredusum_vs_nxv4f16_nxv1f16_nxv4f16:553; CHECK: # %bb.0: # %entry554; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma555; CHECK-NEXT: vfredusum.vs v8, v8, v9556; CHECK-NEXT: ret557entry:558 %a = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv1f16(559 <vscale x 4 x half> poison,560 <vscale x 1 x half> %0,561 <vscale x 4 x half> %1,562 iXLen 7, iXLen %2)563 564 ret <vscale x 4 x half> %a565}566 567define <vscale x 4 x half> @intrinsic_vfredmax_vs_nxv4f16_nxv1f16_nxv4f16(<vscale x 1 x half> %0, <vscale x 4 x half> %1, iXLen %2) nounwind {568; CHECK-LABEL: intrinsic_vfredmax_vs_nxv4f16_nxv1f16_nxv4f16:569; CHECK: # %bb.0: # %entry570; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma571; CHECK-NEXT: vfredmax.vs v8, v8, v9572; CHECK-NEXT: ret573entry:574 %a = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv1f16(575 <vscale x 4 x half> poison,576 <vscale x 1 x half> %0,577 <vscale x 4 x half> %1,578 iXLen %2)579 580 ret <vscale x 4 x half> %a581}582 583define <vscale x 4 x half> @intrinsic_vfredmin_vs_nxv4f16_nxv1f16_nxv4f16(<vscale x 1 x half> %0, <vscale x 4 x half> %1, iXLen %2) nounwind {584; CHECK-LABEL: intrinsic_vfredmin_vs_nxv4f16_nxv1f16_nxv4f16:585; CHECK: # %bb.0: # %entry586; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma587; CHECK-NEXT: vfredmin.vs v8, v8, v9588; CHECK-NEXT: ret589entry:590 %a = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv1f16(591 <vscale x 4 x half> poison,592 <vscale x 1 x half> %0,593 <vscale x 4 x half> %1,594 iXLen %2)595 596 ret <vscale x 4 x half> %a597}598 599define <vscale x 2 x float> @intrinsic_vfwredosum_vs_nxv2f32_nxv1f16_nxv2f32(<vscale x 1 x half> %0, <vscale x 2 x float> %1, iXLen %2) nounwind {600; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv2f32_nxv1f16_nxv2f32:601; CHECK: # %bb.0: # %entry602; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma603; CHECK-NEXT: vfwredosum.vs v8, v8, v9604; CHECK-NEXT: ret605entry:606 %a = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv1f16(607 <vscale x 2 x float> poison,608 <vscale x 1 x half> %0,609 <vscale x 2 x float> %1,610 iXLen 7, iXLen %2)611 612 ret <vscale x 2 x float> %a613}614 615define <vscale x 2 x float> @intrinsic_vfwredusum_vs_nxv2f32_nxv1f16_nxv2f32(<vscale x 1 x half> %0, <vscale x 2 x float> %1, iXLen %2) nounwind {616; CHECK-LABEL: intrinsic_vfwredusum_vs_nxv2f32_nxv1f16_nxv2f32:617; CHECK: # %bb.0: # %entry618; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma619; CHECK-NEXT: vfwredusum.vs v8, v8, v9620; CHECK-NEXT: ret621entry:622 %a = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv1f16(623 <vscale x 2 x float> poison,624 <vscale x 1 x half> %0,625 <vscale x 2 x float> %1,626 iXLen 7, iXLen %2)627 628 ret <vscale x 2 x float> %a629}630 631define <vscale x 1 x i8> @intrinsic_vslidedown_vx_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, iXLen %1, iXLen %2) nounwind {632; CHECK-LABEL: intrinsic_vslidedown_vx_nxv1i8_nxv1i8:633; CHECK: # %bb.0: # %entry634; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma635; CHECK-NEXT: vslidedown.vx v8, v8, a0636; CHECK-NEXT: ret637entry:638 %a = call <vscale x 1 x i8> @llvm.riscv.vslidedown.nxv1i8(639 <vscale x 1 x i8> poison,640 <vscale x 1 x i8> %0,641 iXLen %1,642 iXLen %2,643 iXLen 1)644 645 ret <vscale x 1 x i8> %a646}647 648define <vscale x 1 x i8> @intrinsic_vslideup_vx_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, iXLen %2, iXLen %3) nounwind {649; CHECK-LABEL: intrinsic_vslideup_vx_nxv1i8_nxv1i8:650; CHECK: # %bb.0: # %entry651; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma652; CHECK-NEXT: vslideup.vx v8, v9, a0653; CHECK-NEXT: ret654entry:655 %a = call <vscale x 1 x i8> @llvm.riscv.vslideup.nxv1i8(656 <vscale x 1 x i8> %0,657 <vscale x 1 x i8> %1,658 iXLen %2,659 iXLen %3,660 iXLen 1)661 662 ret <vscale x 1 x i8> %a663}664 665define <vscale x 1 x i64> @intrinsic_vmv.s.x_x_nxv1i64(i64 %0, iXLen %1) nounwind {666; RV32-LABEL: intrinsic_vmv.s.x_x_nxv1i64:667; RV32: # %bb.0: # %entry668; RV32-NEXT: addi sp, sp, -16669; RV32-NEXT: sw a0, 8(sp)670; RV32-NEXT: sw a1, 12(sp)671; RV32-NEXT: addi a0, sp, 8672; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma673; RV32-NEXT: vlse64.v v8, (a0), zero674; RV32-NEXT: addi sp, sp, 16675; RV32-NEXT: ret676;677; RV64-LABEL: intrinsic_vmv.s.x_x_nxv1i64:678; RV64: # %bb.0: # %entry679; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma680; RV64-NEXT: vmv.s.x v8, a0681; RV64-NEXT: ret682entry:683 %a = call <vscale x 1 x i64> @llvm.riscv.vmv.s.x.nxv1i64(<vscale x 1 x i64> poison, i64 %0, iXLen %1)684 ret <vscale x 1 x i64> %a685}686 687define <vscale x 1 x half> @intrinsic_vfmv.s.f_f_nxv1f16(half %0, iXLen %1) nounwind {688; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv1f16:689; CHECK: # %bb.0: # %entry690; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma691; CHECK-NEXT: vfmv.s.f v8, fa0692; CHECK-NEXT: ret693entry:694 %a = call <vscale x 1 x half> @llvm.riscv.vfmv.s.f.nxv1f16(<vscale x 1 x half> poison, half %0, iXLen %1)695 ret <vscale x 1 x half> %a696}697 698define <vscale x 1 x i8> @intrinsic_vcompress_um_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {699; CHECK-LABEL: intrinsic_vcompress_um_nxv1i8_nxv1i8:700; CHECK: # %bb.0: # %entry701; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma702; CHECK-NEXT: vcompress.vm v9, v8, v0703; CHECK-NEXT: vmv1r.v v8, v9704; CHECK-NEXT: ret705entry:706 %a = call <vscale x 1 x i8> @llvm.riscv.vcompress.nxv1i8(707 <vscale x 1 x i8> poison,708 <vscale x 1 x i8> %0,709 <vscale x 1 x i1> %1,710 iXLen %2)711 712 ret <vscale x 1 x i8> %a713}714