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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \3; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s --check-prefixes=CHECK,RV324; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \5; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s --check-prefixes=CHECK,RV646 7define <vscale x 1 x i8> @intrinsic_vle_v_tu_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, ptr %1, iXLen %2) nounwind {8; CHECK-LABEL: intrinsic_vle_v_tu_nxv1i8_nxv1i8:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, ma11; CHECK-NEXT: vle8.v v8, (a0)12; CHECK-NEXT: ret13entry:14 %a = call <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8(15 <vscale x 1 x i8> %0,16 ptr %1,17 iXLen %2)18 19 ret <vscale x 1 x i8> %a20}21 22define <vscale x 1 x i8> @intrinsic_vlse_v_tu(<vscale x 1 x i8> %0, ptr %1, iXLen %2, iXLen %3) nounwind {23; CHECK-LABEL: intrinsic_vlse_v_tu:24; CHECK: # %bb.0: # %entry25; CHECK-NEXT: vsetvli zero, a2, e8, mf8, tu, ma26; CHECK-NEXT: vlse8.v v8, (a0), a127; CHECK-NEXT: ret28entry:29 %a = call <vscale x 1 x i8> @llvm.riscv.vlse(30 <vscale x 1 x i8> %0,31 ptr %1,32 iXLen %2,33 iXLen %3)34 35 ret <vscale x 1 x i8> %a36}37 38define <vscale x 1 x i8> @intrinsic_vleff_v_tu(<vscale x 1 x i8> %0, ptr %1, iXLen %2, ptr %3) nounwind {39; RV32-LABEL: intrinsic_vleff_v_tu:40; RV32: # %bb.0: # %entry41; RV32-NEXT: vsetvli zero, a1, e8, mf8, tu, ma42; RV32-NEXT: vle8ff.v v8, (a0)43; RV32-NEXT: csrr a0, vl44; RV32-NEXT: sw a0, 0(a2)45; RV32-NEXT: ret46;47; RV64-LABEL: intrinsic_vleff_v_tu:48; RV64: # %bb.0: # %entry49; RV64-NEXT: vsetvli zero, a1, e8, mf8, tu, ma50; RV64-NEXT: vle8ff.v v8, (a0)51; RV64-NEXT: csrr a0, vl52; RV64-NEXT: sd a0, 0(a2)53; RV64-NEXT: ret54entry:55 %a = call { <vscale x 1 x i8>, iXLen } @llvm.riscv.vleff(56 <vscale x 1 x i8> %0,57 ptr %1,58 iXLen %2)59 %b = extractvalue { <vscale x 1 x i8>, iXLen } %a, 060 %c = extractvalue { <vscale x 1 x i8>, iXLen } %a, 161 store iXLen %c, ptr %362 ret <vscale x 1 x i8> %b63}64 65define <vscale x 1 x i8> @intrinsic_vloxei_v_tu_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, ptr %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {66; CHECK-LABEL: intrinsic_vloxei_v_tu_nxv1i8_nxv1i8:67; CHECK: # %bb.0: # %entry68; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, ma69; CHECK-NEXT: vloxei8.v v8, (a0), v970; CHECK-NEXT: ret71entry:72 %a = call <vscale x 1 x i8> @llvm.riscv.vloxei.nxv1i8(73 <vscale x 1 x i8> %0,74 ptr %1,75 <vscale x 1 x i8> %2,76 iXLen %3)77 78 ret <vscale x 1 x i8> %a79}80 81define <vscale x 1 x i8> @intrinsic_vaadd_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {82; CHECK-LABEL: intrinsic_vaadd_vv_nxv1i8_nxv1i8_nxv1i8:83; CHECK: # %bb.0: # %entry84; CHECK-NEXT: csrwi vxrm, 085; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma86; CHECK-NEXT: vaadd.vv v8, v9, v1087; CHECK-NEXT: ret88entry:89 %a = call <vscale x 1 x i8> @llvm.riscv.vaadd.rm.nxv1i8.nxv1i8(90 <vscale x 1 x i8> %0,91 <vscale x 1 x i8> %1,92 <vscale x 1 x i8> %2,93 iXLen 0, iXLen %3)94 95 ret <vscale x 1 x i8> %a96}97 98define <vscale x 1 x i8> @intrinsic_vaaddu_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {99; CHECK-LABEL: intrinsic_vaaddu_vv_nxv1i8_nxv1i8_nxv1i8:100; CHECK: # %bb.0: # %entry101; CHECK-NEXT: csrwi vxrm, 0102; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma103; CHECK-NEXT: vaaddu.vv v8, v9, v10104; CHECK-NEXT: ret105entry:106 %a = call <vscale x 1 x i8> @llvm.riscv.vaaddu.rm.nxv1i8.nxv1i8(107 <vscale x 1 x i8> %0,108 <vscale x 1 x i8> %1,109 <vscale x 1 x i8> %2,110 iXLen 0, iXLen %3)111 112 ret <vscale x 1 x i8> %a113}114 115define <vscale x 1 x i8> @intrinsic_vadd_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {116; CHECK-LABEL: intrinsic_vadd_vv_nxv1i8_nxv1i8_nxv1i8:117; CHECK: # %bb.0: # %entry118; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma119; CHECK-NEXT: vadd.vv v8, v9, v10120; CHECK-NEXT: ret121entry:122 %a = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8(123 <vscale x 1 x i8> %0,124 <vscale x 1 x i8> %1,125 <vscale x 1 x i8> %2,126 iXLen %3)127 128 ret <vscale x 1 x i8> %a129}130 131define <vscale x 1 x i8> @intrinsic_vand_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {132; CHECK-LABEL: intrinsic_vand_vv_nxv1i8_nxv1i8_nxv1i8:133; CHECK: # %bb.0: # %entry134; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma135; CHECK-NEXT: vand.vv v8, v9, v10136; CHECK-NEXT: ret137entry:138 %a = call <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.nxv1i8(139 <vscale x 1 x i8> %0,140 <vscale x 1 x i8> %1,141 <vscale x 1 x i8> %2,142 iXLen %3)143 144 ret <vscale x 1 x i8> %a145}146 147define <vscale x 1 x i8> @intrinsic_vasub_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {148; CHECK-LABEL: intrinsic_vasub_vv_nxv1i8_nxv1i8_nxv1i8:149; CHECK: # %bb.0: # %entry150; CHECK-NEXT: csrwi vxrm, 0151; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma152; CHECK-NEXT: vasub.vv v8, v9, v10153; CHECK-NEXT: ret154entry:155 %a = call <vscale x 1 x i8> @llvm.riscv.vasub.rm.nxv1i8.nxv1i8(156 <vscale x 1 x i8> %0,157 <vscale x 1 x i8> %1,158 <vscale x 1 x i8> %2,159 iXLen 0, iXLen %3)160 161 ret <vscale x 1 x i8> %a162}163 164define <vscale x 1 x i8> @intrinsic_vasubu_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {165; CHECK-LABEL: intrinsic_vasubu_vv_nxv1i8_nxv1i8_nxv1i8:166; CHECK: # %bb.0: # %entry167; CHECK-NEXT: csrwi vxrm, 0168; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma169; CHECK-NEXT: vasubu.vv v8, v9, v10170; CHECK-NEXT: ret171entry:172 %a = call <vscale x 1 x i8> @llvm.riscv.vasubu.rm.nxv1i8.nxv1i8(173 <vscale x 1 x i8> %0,174 <vscale x 1 x i8> %1,175 <vscale x 1 x i8> %2,176 iXLen 0, iXLen %3)177 178 ret <vscale x 1 x i8> %a179}180 181define <vscale x 1 x i8> @intrinsic_vdiv_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {182; CHECK-LABEL: intrinsic_vdiv_vv_nxv1i8_nxv1i8_nxv1i8:183; CHECK: # %bb.0: # %entry184; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma185; CHECK-NEXT: vdiv.vv v8, v9, v10186; CHECK-NEXT: ret187entry:188 %a = call <vscale x 1 x i8> @llvm.riscv.vdiv.nxv1i8.nxv1i8(189 <vscale x 1 x i8> %0,190 <vscale x 1 x i8> %1,191 <vscale x 1 x i8> %2,192 iXLen %3)193 194 ret <vscale x 1 x i8> %a195}196 197define <vscale x 1 x i8> @intrinsic_vdivu_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {198; CHECK-LABEL: intrinsic_vdivu_vv_nxv1i8_nxv1i8_nxv1i8:199; CHECK: # %bb.0: # %entry200; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma201; CHECK-NEXT: vdivu.vv v8, v9, v10202; CHECK-NEXT: ret203entry:204 %a = call <vscale x 1 x i8> @llvm.riscv.vdivu.nxv1i8.nxv1i8(205 <vscale x 1 x i8> %0,206 <vscale x 1 x i8> %1,207 <vscale x 1 x i8> %2,208 iXLen %3)209 210 ret <vscale x 1 x i8> %a211}212 213define <vscale x 1 x half> @intrinsic_vfadd_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, iXLen %3) nounwind {214; CHECK-LABEL: intrinsic_vfadd_vv_nxv1f16_nxv1f16_nxv1f16:215; CHECK: # %bb.0: # %entry216; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma217; CHECK-NEXT: vfadd.vv v8, v9, v10218; CHECK-NEXT: ret219entry:220 %a = call <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.nxv1f16(221 <vscale x 1 x half> %0,222 <vscale x 1 x half> %1,223 <vscale x 1 x half> %2,224 iXLen 7, iXLen %3)225 226 ret <vscale x 1 x half> %a227}228 229define <vscale x 1 x half> @intrinsic_vfdiv_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, iXLen %3) nounwind {230; CHECK-LABEL: intrinsic_vfdiv_vv_nxv1f16_nxv1f16_nxv1f16:231; CHECK: # %bb.0: # %entry232; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma233; CHECK-NEXT: vfdiv.vv v8, v9, v10234; CHECK-NEXT: ret235entry:236 %a = call <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.nxv1f16(237 <vscale x 1 x half> %0,238 <vscale x 1 x half> %1,239 <vscale x 1 x half> %2,240 iXLen 7, iXLen %3)241 242 ret <vscale x 1 x half> %a243}244 245define <vscale x 1 x half> @intrinsic_vfmax_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, iXLen %3) nounwind {246; CHECK-LABEL: intrinsic_vfmax_vv_nxv1f16_nxv1f16_nxv1f16:247; CHECK: # %bb.0: # %entry248; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma249; CHECK-NEXT: vfmax.vv v8, v9, v10250; CHECK-NEXT: ret251entry:252 %a = call <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.nxv1f16(253 <vscale x 1 x half> %0,254 <vscale x 1 x half> %1,255 <vscale x 1 x half> %2,256 iXLen %3)257 258 ret <vscale x 1 x half> %a259}260 261define <vscale x 1 x half> @intrinsic_vfmin_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, iXLen %3) nounwind {262; CHECK-LABEL: intrinsic_vfmin_vv_nxv1f16_nxv1f16_nxv1f16:263; CHECK: # %bb.0: # %entry264; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma265; CHECK-NEXT: vfmin.vv v8, v9, v10266; CHECK-NEXT: ret267entry:268 %a = call <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.nxv1f16(269 <vscale x 1 x half> %0,270 <vscale x 1 x half> %1,271 <vscale x 1 x half> %2,272 iXLen %3)273 274 ret <vscale x 1 x half> %a275}276 277define <vscale x 1 x half> @intrinsic_vfmul_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, iXLen %3) nounwind {278; CHECK-LABEL: intrinsic_vfmul_vv_nxv1f16_nxv1f16_nxv1f16:279; CHECK: # %bb.0: # %entry280; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma281; CHECK-NEXT: vfmul.vv v8, v9, v10282; CHECK-NEXT: ret283entry:284 %a = call <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.nxv1f16(285 <vscale x 1 x half> %0,286 <vscale x 1 x half> %1,287 <vscale x 1 x half> %2,288 iXLen 7, iXLen %3)289 290 ret <vscale x 1 x half> %a291}292 293define <vscale x 1 x half> @intrinsic_vfrdiv_vf_nxv1f16_nxv1f16_f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, iXLen %3) nounwind {294; CHECK-LABEL: intrinsic_vfrdiv_vf_nxv1f16_nxv1f16_f16:295; CHECK: # %bb.0: # %entry296; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma297; CHECK-NEXT: vfrdiv.vf v8, v9, fa0298; CHECK-NEXT: ret299entry:300 %a = call <vscale x 1 x half> @llvm.riscv.vfrdiv.nxv1f16.f16(301 <vscale x 1 x half> %0,302 <vscale x 1 x half> %1,303 half %2,304 iXLen 7, iXLen %3)305 306 ret <vscale x 1 x half> %a307}308 309define <vscale x 1 x half> @intrinsic_vfsgnj_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, iXLen %3) nounwind {310; CHECK-LABEL: intrinsic_vfsgnj_vv_nxv1f16_nxv1f16_nxv1f16:311; CHECK: # %bb.0: # %entry312; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma313; CHECK-NEXT: vfsgnj.vv v8, v9, v10314; CHECK-NEXT: ret315entry:316 %a = call <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.nxv1f16(317 <vscale x 1 x half> %0,318 <vscale x 1 x half> %1,319 <vscale x 1 x half> %2,320 iXLen %3)321 322 ret <vscale x 1 x half> %a323}324 325define <vscale x 1 x half> @intrinsic_vfsgnjn_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, iXLen %3) nounwind {326; CHECK-LABEL: intrinsic_vfsgnjn_vv_nxv1f16_nxv1f16_nxv1f16:327; CHECK: # %bb.0: # %entry328; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma329; CHECK-NEXT: vfsgnjn.vv v8, v9, v10330; CHECK-NEXT: ret331entry:332 %a = call <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16(333 <vscale x 1 x half> %0,334 <vscale x 1 x half> %1,335 <vscale x 1 x half> %2,336 iXLen %3)337 338 ret <vscale x 1 x half> %a339}340 341define <vscale x 1 x half> @intrinsic_vfsgnjx_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, iXLen %3) nounwind {342; CHECK-LABEL: intrinsic_vfsgnjx_vv_nxv1f16_nxv1f16_nxv1f16:343; CHECK: # %bb.0: # %entry344; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma345; CHECK-NEXT: vfsgnjx.vv v8, v9, v10346; CHECK-NEXT: ret347entry:348 %a = call <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16(349 <vscale x 1 x half> %0,350 <vscale x 1 x half> %1,351 <vscale x 1 x half> %2,352 iXLen %3)353 354 ret <vscale x 1 x half> %a355}356 357define <vscale x 1 x half> @intrinsic_vfrsub_vf_nxv1f16_nxv1f16_f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, iXLen %3) nounwind {358; CHECK-LABEL: intrinsic_vfrsub_vf_nxv1f16_nxv1f16_f16:359; CHECK: # %bb.0: # %entry360; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma361; CHECK-NEXT: vfrsub.vf v8, v9, fa0362; CHECK-NEXT: ret363entry:364 %a = call <vscale x 1 x half> @llvm.riscv.vfrsub.nxv1f16.f16(365 <vscale x 1 x half> %0,366 <vscale x 1 x half> %1,367 half %2,368 iXLen 7, iXLen %3)369 370 ret <vscale x 1 x half> %a371}372 373define <vscale x 1 x half> @intrinsic_vfslide1down_vf_nxv1f16_nxv1f16_f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, iXLen %3) nounwind {374; CHECK-LABEL: intrinsic_vfslide1down_vf_nxv1f16_nxv1f16_f16:375; CHECK: # %bb.0: # %entry376; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma377; CHECK-NEXT: vfslide1down.vf v8, v9, fa0378; CHECK-NEXT: ret379entry:380 %a = call <vscale x 1 x half> @llvm.riscv.vfslide1down.nxv1f16.f16(381 <vscale x 1 x half> %0,382 <vscale x 1 x half> %1,383 half %2,384 iXLen %3)385 386 ret <vscale x 1 x half> %a387}388 389define <vscale x 1 x half> @intrinsic_vfslide1up_vf_nxv1f16_nxv1f16_f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, iXLen %3) nounwind {390; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv1f16_nxv1f16_f16:391; CHECK: # %bb.0: # %entry392; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma393; CHECK-NEXT: vfslide1up.vf v8, v9, fa0394; CHECK-NEXT: ret395entry:396 %a = call <vscale x 1 x half> @llvm.riscv.vfslide1up.nxv1f16.f16(397 <vscale x 1 x half> %0,398 <vscale x 1 x half> %1,399 half %2,400 iXLen %3)401 402 ret <vscale x 1 x half> %a403}404 405define <vscale x 1 x float> @intrinsic_vfwsub_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, iXLen %3) nounwind {406; CHECK-LABEL: intrinsic_vfwsub_vv_nxv1f32_nxv1f16_nxv1f16:407; CHECK: # %bb.0: # %entry408; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma409; CHECK-NEXT: vfwsub.vv v8, v9, v10410; CHECK-NEXT: ret411entry:412 %a = call <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16(413 <vscale x 1 x float> %0,414 <vscale x 1 x half> %1,415 <vscale x 1 x half> %2,416 iXLen 7, iXLen %3)417 418 ret <vscale x 1 x float> %a419}420 421define <vscale x 1 x float> @intrinsic_vfwsub.w_wv_nxv1f32_nxv1f32_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x half> %2, iXLen %3) nounwind {422; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv1f32_nxv1f32_nxv1f16:423; CHECK: # %bb.0: # %entry424; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma425; CHECK-NEXT: vfwsub.wv v8, v9, v10426; CHECK-NEXT: ret427entry:428 %a = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16(429 <vscale x 1 x float> %0,430 <vscale x 1 x float> %1,431 <vscale x 1 x half> %2,432 iXLen 7, iXLen %3)433 434 ret <vscale x 1 x float> %a435}436 437define <vscale x 16 x float> @intrinsic_vfwsub.w_wv_nxv16f32_nxv16f32_nxv16f16(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x half> %2, iXLen %3) nounwind {438; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv16f32_nxv16f32_nxv16f16:439; CHECK: # %bb.0: # %entry440; CHECK-NEXT: vl4re16.v v24, (a0)441; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, ma442; CHECK-NEXT: vfwsub.wv v8, v16, v24443; CHECK-NEXT: ret444entry:445 %a = call <vscale x 16 x float> @llvm.riscv.vfwsub.w.nxv16f32.nxv16f16(446 <vscale x 16 x float> %0,447 <vscale x 16 x float> %1,448 <vscale x 16 x half> %2,449 iXLen 7, iXLen %3)450 451 ret <vscale x 16 x float> %a452}453 454define <vscale x 1 x float> @intrinsic_vfwmul_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, iXLen %3) nounwind {455; CHECK-LABEL: intrinsic_vfwmul_vv_nxv1f32_nxv1f16_nxv1f16:456; CHECK: # %bb.0: # %entry457; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma458; CHECK-NEXT: vfwmul.vv v8, v9, v10459; CHECK-NEXT: ret460entry:461 %a = call <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16(462 <vscale x 1 x float> %0,463 <vscale x 1 x half> %1,464 <vscale x 1 x half> %2,465 iXLen 7, iXLen %3)466 467 ret <vscale x 1 x float> %a468}469 470define <vscale x 1 x float> @intrinsic_vfwadd.w_wv_nxv1f32_nxv1f32_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x half> %2, iXLen %3) nounwind {471; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv1f32_nxv1f32_nxv1f16:472; CHECK: # %bb.0: # %entry473; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma474; CHECK-NEXT: vfwadd.wv v8, v9, v10475; CHECK-NEXT: ret476entry:477 %a = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16(478 <vscale x 1 x float> %0,479 <vscale x 1 x float> %1,480 <vscale x 1 x half> %2,481 iXLen 7, iXLen %3)482 483 ret <vscale x 1 x float> %a484}485 486define <vscale x 1 x float> @intrinsic_vfwadd_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, iXLen %3) nounwind {487; CHECK-LABEL: intrinsic_vfwadd_vv_nxv1f32_nxv1f16_nxv1f16:488; CHECK: # %bb.0: # %entry489; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma490; CHECK-NEXT: vfwadd.vv v8, v9, v10491; CHECK-NEXT: ret492entry:493 %a = call <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16(494 <vscale x 1 x float> %0,495 <vscale x 1 x half> %1,496 <vscale x 1 x half> %2,497 iXLen 7, iXLen %3)498 499 ret <vscale x 1 x float> %a500}501 502define <vscale x 1 x half> @intrinsic_vfsub_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, iXLen %3) nounwind {503; CHECK-LABEL: intrinsic_vfsub_vv_nxv1f16_nxv1f16_nxv1f16:504; CHECK: # %bb.0: # %entry505; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma506; CHECK-NEXT: vfsub.vv v8, v9, v10507; CHECK-NEXT: ret508entry:509 %a = call <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.nxv1f16(510 <vscale x 1 x half> %0,511 <vscale x 1 x half> %1,512 <vscale x 1 x half> %2,513 iXLen 7, iXLen %3)514 515 ret <vscale x 1 x half> %a516}517 518define <vscale x 1 x i64> @intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, iXLen %3) nounwind {519; RV32-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64:520; RV32: # %bb.0: # %entry521; RV32-NEXT: vsetvli a2, a2, e64, m1, ta, ma522; RV32-NEXT: slli a2, a2, 1523; RV32-NEXT: vmv1r.v v10, v8524; RV32-NEXT: vsetvli zero, a2, e32, m1, tu, ma525; RV32-NEXT: vslide1down.vx v10, v9, a0526; RV32-NEXT: vslide1down.vx v8, v10, a1527; RV32-NEXT: ret528;529; RV64-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64:530; RV64: # %bb.0: # %entry531; RV64-NEXT: vsetvli zero, a1, e64, m1, tu, ma532; RV64-NEXT: vslide1down.vx v8, v9, a0533; RV64-NEXT: ret534entry:535 %a = call <vscale x 1 x i64> @llvm.riscv.vslide1down.nxv1i64(536 <vscale x 1 x i64> %0,537 <vscale x 1 x i64> %1,538 i64 %2,539 iXLen %3)540 541 ret <vscale x 1 x i64> %a542}543 544define <vscale x 1 x i64> @intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, iXLen %3) nounwind {545; RV32-LABEL: intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64:546; RV32: # %bb.0: # %entry547; RV32-NEXT: vsetvli a2, a2, e64, m1, ta, ma548; RV32-NEXT: slli a2, a2, 1549; RV32-NEXT: vmv1r.v v10, v8550; RV32-NEXT: vsetvli zero, a2, e32, m1, tu, ma551; RV32-NEXT: vslide1up.vx v10, v9, a1552; RV32-NEXT: vslide1up.vx v8, v10, a0553; RV32-NEXT: ret554;555; RV64-LABEL: intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64:556; RV64: # %bb.0: # %entry557; RV64-NEXT: vsetvli zero, a1, e64, m1, tu, ma558; RV64-NEXT: vslide1up.vx v8, v9, a0559; RV64-NEXT: ret560entry:561 %a = call <vscale x 1 x i64> @llvm.riscv.vslide1up.nxv1i64.i64(562 <vscale x 1 x i64> %0,563 <vscale x 1 x i64> %1,564 i64 %2,565 iXLen %3)566 567 ret <vscale x 1 x i64> %a568}569 570define <vscale x 1 x i8> @intrinsic_vmax_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {571; CHECK-LABEL: intrinsic_vmax_vv_nxv1i8_nxv1i8_nxv1i8:572; CHECK: # %bb.0: # %entry573; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma574; CHECK-NEXT: vmax.vv v8, v9, v10575; CHECK-NEXT: ret576entry:577 %a = call <vscale x 1 x i8> @llvm.riscv.vmax.nxv1i8.nxv1i8(578 <vscale x 1 x i8> %0,579 <vscale x 1 x i8> %1,580 <vscale x 1 x i8> %2,581 iXLen %3)582 583 ret <vscale x 1 x i8> %a584}585 586define <vscale x 1 x i8> @intrinsic_vmaxu_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {587; CHECK-LABEL: intrinsic_vmaxu_vv_nxv1i8_nxv1i8_nxv1i8:588; CHECK: # %bb.0: # %entry589; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma590; CHECK-NEXT: vmaxu.vv v8, v9, v10591; CHECK-NEXT: ret592entry:593 %a = call <vscale x 1 x i8> @llvm.riscv.vmaxu.nxv1i8.nxv1i8(594 <vscale x 1 x i8> %0,595 <vscale x 1 x i8> %1,596 <vscale x 1 x i8> %2,597 iXLen %3)598 599 ret <vscale x 1 x i8> %a600}601 602define <vscale x 1 x i8> @intrinsic_vmin_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {603; CHECK-LABEL: intrinsic_vmin_vv_nxv1i8_nxv1i8_nxv1i8:604; CHECK: # %bb.0: # %entry605; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma606; CHECK-NEXT: vmin.vv v8, v9, v10607; CHECK-NEXT: ret608entry:609 %a = call <vscale x 1 x i8> @llvm.riscv.vmin.nxv1i8.nxv1i8(610 <vscale x 1 x i8> %0,611 <vscale x 1 x i8> %1,612 <vscale x 1 x i8> %2,613 iXLen %3)614 615 ret <vscale x 1 x i8> %a616}617 618define <vscale x 1 x i8> @intrinsic_vminu_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {619; CHECK-LABEL: intrinsic_vminu_vv_nxv1i8_nxv1i8_nxv1i8:620; CHECK: # %bb.0: # %entry621; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma622; CHECK-NEXT: vminu.vv v8, v9, v10623; CHECK-NEXT: ret624entry:625 %a = call <vscale x 1 x i8> @llvm.riscv.vminu.nxv1i8.nxv1i8(626 <vscale x 1 x i8> %0,627 <vscale x 1 x i8> %1,628 <vscale x 1 x i8> %2,629 iXLen %3)630 631 ret <vscale x 1 x i8> %a632}633 634define <vscale x 1 x i8> @intrinsic_vmul_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {635; CHECK-LABEL: intrinsic_vmul_vv_nxv1i8_nxv1i8_nxv1i8:636; CHECK: # %bb.0: # %entry637; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma638; CHECK-NEXT: vmul.vv v8, v9, v10639; CHECK-NEXT: ret640entry:641 %a = call <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.nxv1i8(642 <vscale x 1 x i8> %0,643 <vscale x 1 x i8> %1,644 <vscale x 1 x i8> %2,645 iXLen %3)646 647 ret <vscale x 1 x i8> %a648}649 650define <vscale x 1 x i8> @intrinsic_vmulh_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {651; CHECK-LABEL: intrinsic_vmulh_vv_nxv1i8_nxv1i8_nxv1i8:652; CHECK: # %bb.0: # %entry653; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma654; CHECK-NEXT: vmulh.vv v8, v9, v10655; CHECK-NEXT: ret656entry:657 %a = call <vscale x 1 x i8> @llvm.riscv.vmulh.nxv1i8.nxv1i8(658 <vscale x 1 x i8> %0,659 <vscale x 1 x i8> %1,660 <vscale x 1 x i8> %2,661 iXLen %3)662 663 ret <vscale x 1 x i8> %a664}665 666define <vscale x 1 x i8> @intrinsic_vmulhsu_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {667; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv1i8_nxv1i8_nxv1i8:668; CHECK: # %bb.0: # %entry669; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma670; CHECK-NEXT: vmulhsu.vv v8, v9, v10671; CHECK-NEXT: ret672entry:673 %a = call <vscale x 1 x i8> @llvm.riscv.vmulhsu.nxv1i8.nxv1i8(674 <vscale x 1 x i8> %0,675 <vscale x 1 x i8> %1,676 <vscale x 1 x i8> %2,677 iXLen %3)678 679 ret <vscale x 1 x i8> %a680}681 682define <vscale x 1 x i8> @intrinsic_vmulhu_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {683; CHECK-LABEL: intrinsic_vmulhu_vv_nxv1i8_nxv1i8_nxv1i8:684; CHECK: # %bb.0: # %entry685; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma686; CHECK-NEXT: vmulhu.vv v8, v9, v10687; CHECK-NEXT: ret688entry:689 %a = call <vscale x 1 x i8> @llvm.riscv.vmulhu.nxv1i8.nxv1i8(690 <vscale x 1 x i8> %0,691 <vscale x 1 x i8> %1,692 <vscale x 1 x i8> %2,693 iXLen %3)694 695 ret <vscale x 1 x i8> %a696}697 698define <vscale x 1 x i8> @intrinsic_vnclip_wv_nxv1i8_nxv1i16_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {699; CHECK-LABEL: intrinsic_vnclip_wv_nxv1i8_nxv1i16_nxv1i8:700; CHECK: # %bb.0: # %entry701; CHECK-NEXT: csrwi vxrm, 0702; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma703; CHECK-NEXT: vnclip.wv v8, v9, v10704; CHECK-NEXT: ret705entry:706 %a = call <vscale x 1 x i8> @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8(707 <vscale x 1 x i8> %0,708 <vscale x 1 x i16> %1,709 <vscale x 1 x i8> %2,710 iXLen 0, iXLen %3)711 712 ret <vscale x 1 x i8> %a713}714 715define <vscale x 1 x i8> @intrinsic_vnclipu_wv_nxv1i8_nxv1i16_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {716; CHECK-LABEL: intrinsic_vnclipu_wv_nxv1i8_nxv1i16_nxv1i8:717; CHECK: # %bb.0: # %entry718; CHECK-NEXT: csrwi vxrm, 0719; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma720; CHECK-NEXT: vnclipu.wv v8, v9, v10721; CHECK-NEXT: ret722entry:723 %a = call <vscale x 1 x i8> @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8(724 <vscale x 1 x i8> %0,725 <vscale x 1 x i16> %1,726 <vscale x 1 x i8> %2,727 iXLen 0, iXLen %3)728 729 ret <vscale x 1 x i8> %a730}731 732define <vscale x 1 x i8> @intrinsic_vnsra_wv_nxv1i8_nxv1i16_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {733; CHECK-LABEL: intrinsic_vnsra_wv_nxv1i8_nxv1i16_nxv1i8:734; CHECK: # %bb.0: # %entry735; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma736; CHECK-NEXT: vnsra.wv v8, v9, v10737; CHECK-NEXT: ret738entry:739 %a = call <vscale x 1 x i8> @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8(740 <vscale x 1 x i8> %0,741 <vscale x 1 x i16> %1,742 <vscale x 1 x i8> %2,743 iXLen %3)744 745 ret <vscale x 1 x i8> %a746}747 748define <vscale x 1 x i8> @intrinsic_vnsrl_wv_nxv1i8_nxv1i16_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {749; CHECK-LABEL: intrinsic_vnsrl_wv_nxv1i8_nxv1i16_nxv1i8:750; CHECK: # %bb.0: # %entry751; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma752; CHECK-NEXT: vnsrl.wv v8, v9, v10753; CHECK-NEXT: ret754entry:755 %a = call <vscale x 1 x i8> @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8(756 <vscale x 1 x i8> %0,757 <vscale x 1 x i16> %1,758 <vscale x 1 x i8> %2,759 iXLen %3)760 761 ret <vscale x 1 x i8> %a762}763 764define <vscale x 1 x i8> @intrinsic_vor_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {765; CHECK-LABEL: intrinsic_vor_vv_nxv1i8_nxv1i8_nxv1i8:766; CHECK: # %bb.0: # %entry767; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma768; CHECK-NEXT: vor.vv v8, v9, v10769; CHECK-NEXT: ret770entry:771 %a = call <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.nxv1i8(772 <vscale x 1 x i8> %0,773 <vscale x 1 x i8> %1,774 <vscale x 1 x i8> %2,775 iXLen %3)776 777 ret <vscale x 1 x i8> %a778}779 780define <vscale x 1 x i8> @intrinsic_vrem_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {781; CHECK-LABEL: intrinsic_vrem_vv_nxv1i8_nxv1i8_nxv1i8:782; CHECK: # %bb.0: # %entry783; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma784; CHECK-NEXT: vrem.vv v8, v9, v10785; CHECK-NEXT: ret786entry:787 %a = call <vscale x 1 x i8> @llvm.riscv.vrem.nxv1i8.nxv1i8(788 <vscale x 1 x i8> %0,789 <vscale x 1 x i8> %1,790 <vscale x 1 x i8> %2,791 iXLen %3)792 793 ret <vscale x 1 x i8> %a794}795 796define <vscale x 1 x i8> @intrinsic_vrgather_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {797; CHECK-LABEL: intrinsic_vrgather_vv_nxv1i8_nxv1i8_nxv1i8:798; CHECK: # %bb.0: # %entry799; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma800; CHECK-NEXT: vrgather.vv v8, v9, v10801; CHECK-NEXT: ret802entry:803 %a = call <vscale x 1 x i8> @llvm.riscv.vrgather.vv.nxv1i8.i32(804 <vscale x 1 x i8> %0,805 <vscale x 1 x i8> %1,806 <vscale x 1 x i8> %2,807 iXLen %3)808 809 ret <vscale x 1 x i8> %a810}811 812define <vscale x 1 x i8> @intrinsic_vrgather_vx_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, iXLen %2, iXLen %3) nounwind {813; CHECK-LABEL: intrinsic_vrgather_vx_nxv1i8_nxv1i8:814; CHECK: # %bb.0: # %entry815; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, ma816; CHECK-NEXT: vrgather.vx v8, v9, a0817; CHECK-NEXT: ret818entry:819 %a = call <vscale x 1 x i8> @llvm.riscv.vrgather.vx.nxv1i8(820 <vscale x 1 x i8> %0,821 <vscale x 1 x i8> %1,822 iXLen %2,823 iXLen %3)824 825 ret <vscale x 1 x i8> %a826}827 828define <vscale x 1 x i8> @intrinsic_vrgatherei16_vv_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i16> %2, iXLen %3) nounwind {829; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv1i8_nxv1i8:830; CHECK: # %bb.0: # %entry831; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma832; CHECK-NEXT: vrgatherei16.vv v8, v9, v10833; CHECK-NEXT: ret834entry:835 %a = call <vscale x 1 x i8> @llvm.riscv.vrgatherei16.vv.nxv1i8(836 <vscale x 1 x i8> %0,837 <vscale x 1 x i8> %1,838 <vscale x 1 x i16> %2,839 iXLen %3)840 841 ret <vscale x 1 x i8> %a842}843 844define <vscale x 1 x i64> @intrinsic_vrsub_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, iXLen %3) nounwind {845; RV32-LABEL: intrinsic_vrsub_vx_nxv1i64_nxv1i64_i64:846; RV32: # %bb.0: # %entry847; RV32-NEXT: addi sp, sp, -16848; RV32-NEXT: sw a0, 8(sp)849; RV32-NEXT: sw a1, 12(sp)850; RV32-NEXT: addi a0, sp, 8851; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma852; RV32-NEXT: vlse64.v v10, (a0), zero853; RV32-NEXT: vsetvli zero, zero, e64, m1, tu, ma854; RV32-NEXT: vsub.vv v8, v10, v9855; RV32-NEXT: addi sp, sp, 16856; RV32-NEXT: ret857;858; RV64-LABEL: intrinsic_vrsub_vx_nxv1i64_nxv1i64_i64:859; RV64: # %bb.0: # %entry860; RV64-NEXT: vsetvli zero, a1, e64, m1, tu, ma861; RV64-NEXT: vrsub.vx v8, v9, a0862; RV64-NEXT: ret863entry:864 %a = call <vscale x 1 x i64> @llvm.riscv.vrsub.nxv1i64.i64(865 <vscale x 1 x i64> %0,866 <vscale x 1 x i64> %1,867 i64 %2,868 iXLen %3)869 870 ret <vscale x 1 x i64> %a871}872 873define <vscale x 1 x i64> @intrinsic_vsadd_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, iXLen %3) nounwind {874; RV32-LABEL: intrinsic_vsadd_vx_nxv1i64_nxv1i64_i64:875; RV32: # %bb.0: # %entry876; RV32-NEXT: addi sp, sp, -16877; RV32-NEXT: sw a0, 8(sp)878; RV32-NEXT: sw a1, 12(sp)879; RV32-NEXT: addi a0, sp, 8880; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma881; RV32-NEXT: vlse64.v v10, (a0), zero882; RV32-NEXT: vsetvli zero, zero, e64, m1, tu, ma883; RV32-NEXT: vsadd.vv v8, v9, v10884; RV32-NEXT: addi sp, sp, 16885; RV32-NEXT: ret886;887; RV64-LABEL: intrinsic_vsadd_vx_nxv1i64_nxv1i64_i64:888; RV64: # %bb.0: # %entry889; RV64-NEXT: vsetvli zero, a1, e64, m1, tu, ma890; RV64-NEXT: vsadd.vx v8, v9, a0891; RV64-NEXT: ret892entry:893 %a = call <vscale x 1 x i64> @llvm.riscv.vsadd.nxv1i64.i64(894 <vscale x 1 x i64> %0,895 <vscale x 1 x i64> %1,896 i64 %2,897 iXLen %3)898 899 ret <vscale x 1 x i64> %a900}901 902define <vscale x 1 x i8> @intrinsic_vsaddu_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {903; CHECK-LABEL: intrinsic_vsaddu_vv_nxv1i8_nxv1i8_nxv1i8:904; CHECK: # %bb.0: # %entry905; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma906; CHECK-NEXT: vsaddu.vv v8, v9, v10907; CHECK-NEXT: ret908entry:909 %a = call <vscale x 1 x i8> @llvm.riscv.vsaddu.nxv1i8.nxv1i8(910 <vscale x 1 x i8> %0,911 <vscale x 1 x i8> %1,912 <vscale x 1 x i8> %2,913 iXLen %3)914 915 ret <vscale x 1 x i8> %a916}917 918define <vscale x 1 x i8> @intrinsic_vsll_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {919; CHECK-LABEL: intrinsic_vsll_vv_nxv1i8_nxv1i8_nxv1i8:920; CHECK: # %bb.0: # %entry921; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma922; CHECK-NEXT: vsll.vv v8, v9, v10923; CHECK-NEXT: ret924entry:925 %a = call <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8.nxv1i8(926 <vscale x 1 x i8> %0,927 <vscale x 1 x i8> %1,928 <vscale x 1 x i8> %2,929 iXLen %3)930 931 ret <vscale x 1 x i8> %a932}933 934define <vscale x 1 x i8> @intrinsic_vsmul_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {935; CHECK-LABEL: intrinsic_vsmul_vv_nxv1i8_nxv1i8_nxv1i8:936; CHECK: # %bb.0: # %entry937; CHECK-NEXT: csrwi vxrm, 0938; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma939; CHECK-NEXT: vsmul.vv v8, v9, v10940; CHECK-NEXT: ret941entry:942 %a = call <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.nxv1i8(943 <vscale x 1 x i8> %0,944 <vscale x 1 x i8> %1,945 <vscale x 1 x i8> %2,946 iXLen 0, iXLen %3)947 948 ret <vscale x 1 x i8> %a949}950 951define <vscale x 1 x i64> @intrinsic_vsmul_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, iXLen %3) nounwind {952; RV32-LABEL: intrinsic_vsmul_vx_nxv1i64_nxv1i64_i64:953; RV32: # %bb.0: # %entry954; RV32-NEXT: addi sp, sp, -16955; RV32-NEXT: sw a0, 8(sp)956; RV32-NEXT: sw a1, 12(sp)957; RV32-NEXT: addi a0, sp, 8958; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma959; RV32-NEXT: vlse64.v v10, (a0), zero960; RV32-NEXT: csrwi vxrm, 0961; RV32-NEXT: vsetvli zero, zero, e64, m1, tu, ma962; RV32-NEXT: vsmul.vv v8, v9, v10963; RV32-NEXT: addi sp, sp, 16964; RV32-NEXT: ret965;966; RV64-LABEL: intrinsic_vsmul_vx_nxv1i64_nxv1i64_i64:967; RV64: # %bb.0: # %entry968; RV64-NEXT: csrwi vxrm, 0969; RV64-NEXT: vsetvli zero, a1, e64, m1, tu, ma970; RV64-NEXT: vsmul.vx v8, v9, a0971; RV64-NEXT: ret972entry:973 %a = call <vscale x 1 x i64> @llvm.riscv.vsmul.nxv1i64.i64(974 <vscale x 1 x i64> %0,975 <vscale x 1 x i64> %1,976 i64 %2,977 iXLen 0, iXLen %3)978 979 ret <vscale x 1 x i64> %a980}981 982define <vscale x 1 x i8> @intrinsic_vsra_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {983; CHECK-LABEL: intrinsic_vsra_vv_nxv1i8_nxv1i8_nxv1i8:984; CHECK: # %bb.0: # %entry985; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma986; CHECK-NEXT: vsra.vv v8, v9, v10987; CHECK-NEXT: ret988entry:989 %a = call <vscale x 1 x i8> @llvm.riscv.vsra.nxv1i8.nxv1i8(990 <vscale x 1 x i8> %0,991 <vscale x 1 x i8> %1,992 <vscale x 1 x i8> %2,993 iXLen %3)994 995 ret <vscale x 1 x i8> %a996}997 998define <vscale x 1 x i8> @intrinsic_vsrl_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {999; CHECK-LABEL: intrinsic_vsrl_vv_nxv1i8_nxv1i8_nxv1i8:1000; CHECK: # %bb.0: # %entry1001; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma1002; CHECK-NEXT: vsrl.vv v8, v9, v101003; CHECK-NEXT: ret1004entry:1005 %a = call <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.nxv1i8(1006 <vscale x 1 x i8> %0,1007 <vscale x 1 x i8> %1,1008 <vscale x 1 x i8> %2,1009 iXLen %3)1010 1011 ret <vscale x 1 x i8> %a1012}1013 1014define <vscale x 1 x i8> @intrinsic_vssra_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {1015; CHECK-LABEL: intrinsic_vssra_vv_nxv1i8_nxv1i8_nxv1i8:1016; CHECK: # %bb.0: # %entry1017; CHECK-NEXT: csrwi vxrm, 01018; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma1019; CHECK-NEXT: vssra.vv v8, v9, v101020; CHECK-NEXT: ret1021entry:1022 %a = call <vscale x 1 x i8> @llvm.riscv.vssra.nxv1i8.nxv1i8(1023 <vscale x 1 x i8> %0,1024 <vscale x 1 x i8> %1,1025 <vscale x 1 x i8> %2,1026 iXLen 0, iXLen %3)1027 1028 ret <vscale x 1 x i8> %a1029}1030 1031define <vscale x 1 x i8> @intrinsic_vssrl_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {1032; CHECK-LABEL: intrinsic_vssrl_vv_nxv1i8_nxv1i8_nxv1i8:1033; CHECK: # %bb.0: # %entry1034; CHECK-NEXT: csrwi vxrm, 01035; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma1036; CHECK-NEXT: vssrl.vv v8, v9, v101037; CHECK-NEXT: ret1038entry:1039 %a = call <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.nxv1i8(1040 <vscale x 1 x i8> %0,1041 <vscale x 1 x i8> %1,1042 <vscale x 1 x i8> %2,1043 iXLen 0, iXLen %3)1044 1045 ret <vscale x 1 x i8> %a1046}1047 1048define <vscale x 1 x i8> @intrinsic_vssub_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {1049; CHECK-LABEL: intrinsic_vssub_vv_nxv1i8_nxv1i8_nxv1i8:1050; CHECK: # %bb.0: # %entry1051; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma1052; CHECK-NEXT: vssub.vv v8, v9, v101053; CHECK-NEXT: ret1054entry:1055 %a = call <vscale x 1 x i8> @llvm.riscv.vssub.nxv1i8.nxv1i8(1056 <vscale x 1 x i8> %0,1057 <vscale x 1 x i8> %1,1058 <vscale x 1 x i8> %2,1059 iXLen %3)1060 1061 ret <vscale x 1 x i8> %a1062}1063 1064define <vscale x 1 x i8> @intrinsic_vssubu_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {1065; CHECK-LABEL: intrinsic_vssubu_vv_nxv1i8_nxv1i8_nxv1i8:1066; CHECK: # %bb.0: # %entry1067; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma1068; CHECK-NEXT: vssubu.vv v8, v9, v101069; CHECK-NEXT: ret1070entry:1071 %a = call <vscale x 1 x i8> @llvm.riscv.vssubu.nxv1i8.nxv1i8(1072 <vscale x 1 x i8> %0,1073 <vscale x 1 x i8> %1,1074 <vscale x 1 x i8> %2,1075 iXLen %3)1076 1077 ret <vscale x 1 x i8> %a1078}1079 1080define <vscale x 1 x i64> @intrinsic_vssub_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, iXLen %3) nounwind {1081; RV32-LABEL: intrinsic_vssub_vx_nxv1i64_nxv1i64_i64:1082; RV32: # %bb.0: # %entry1083; RV32-NEXT: addi sp, sp, -161084; RV32-NEXT: sw a0, 8(sp)1085; RV32-NEXT: sw a1, 12(sp)1086; RV32-NEXT: addi a0, sp, 81087; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma1088; RV32-NEXT: vlse64.v v10, (a0), zero1089; RV32-NEXT: vsetvli zero, zero, e64, m1, tu, ma1090; RV32-NEXT: vssub.vv v8, v9, v101091; RV32-NEXT: addi sp, sp, 161092; RV32-NEXT: ret1093;1094; RV64-LABEL: intrinsic_vssub_vx_nxv1i64_nxv1i64_i64:1095; RV64: # %bb.0: # %entry1096; RV64-NEXT: vsetvli zero, a1, e64, m1, tu, ma1097; RV64-NEXT: vssub.vx v8, v9, a01098; RV64-NEXT: ret1099entry:1100 %a = call <vscale x 1 x i64> @llvm.riscv.vssub.nxv1i64.i64(1101 <vscale x 1 x i64> %0,1102 <vscale x 1 x i64> %1,1103 i64 %2,1104 iXLen %3)1105 1106 ret <vscale x 1 x i64> %a1107}1108 1109define <vscale x 1 x i64> @intrinsic_vssubu_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, iXLen %3) nounwind {1110; RV32-LABEL: intrinsic_vssubu_vx_nxv1i64_nxv1i64_i64:1111; RV32: # %bb.0: # %entry1112; RV32-NEXT: addi sp, sp, -161113; RV32-NEXT: sw a0, 8(sp)1114; RV32-NEXT: sw a1, 12(sp)1115; RV32-NEXT: addi a0, sp, 81116; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma1117; RV32-NEXT: vlse64.v v10, (a0), zero1118; RV32-NEXT: vsetvli zero, zero, e64, m1, tu, ma1119; RV32-NEXT: vssubu.vv v8, v9, v101120; RV32-NEXT: addi sp, sp, 161121; RV32-NEXT: ret1122;1123; RV64-LABEL: intrinsic_vssubu_vx_nxv1i64_nxv1i64_i64:1124; RV64: # %bb.0: # %entry1125; RV64-NEXT: vsetvli zero, a1, e64, m1, tu, ma1126; RV64-NEXT: vssubu.vx v8, v9, a01127; RV64-NEXT: ret1128entry:1129 %a = call <vscale x 1 x i64> @llvm.riscv.vssubu.nxv1i64.i64(1130 <vscale x 1 x i64> %0,1131 <vscale x 1 x i64> %1,1132 i64 %2,1133 iXLen %3)1134 1135 ret <vscale x 1 x i64> %a1136}1137 1138define <vscale x 1 x i8> @intrinsic_vsub_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {1139; CHECK-LABEL: intrinsic_vsub_vv_nxv1i8_nxv1i8_nxv1i8:1140; CHECK: # %bb.0: # %entry1141; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma1142; CHECK-NEXT: vsub.vv v8, v9, v101143; CHECK-NEXT: ret1144entry:1145 %a = call <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.nxv1i8(1146 <vscale x 1 x i8> %0,1147 <vscale x 1 x i8> %1,1148 <vscale x 1 x i8> %2,1149 iXLen %3)1150 1151 ret <vscale x 1 x i8> %a1152}1153 1154define <vscale x 1 x i16> @intrinsic_vwadd_vv_nxv1i16_nxv1i8_nxv1i8(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {1155; CHECK-LABEL: intrinsic_vwadd_vv_nxv1i16_nxv1i8_nxv1i8:1156; CHECK: # %bb.0: # %entry1157; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma1158; CHECK-NEXT: vwadd.vv v8, v9, v101159; CHECK-NEXT: ret1160entry:1161 %a = call <vscale x 1 x i16> @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8(1162 <vscale x 1 x i16> %0,1163 <vscale x 1 x i8> %1,1164 <vscale x 1 x i8> %2,1165 iXLen %3)1166 1167 ret <vscale x 1 x i16> %a1168}1169 1170define <vscale x 1 x i16> @intrinsic_vwadd.w_wv_nxv1i16_nxv1i16_nxv1i8(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {1171; CHECK-LABEL: intrinsic_vwadd.w_wv_nxv1i16_nxv1i16_nxv1i8:1172; CHECK: # %bb.0: # %entry1173; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma1174; CHECK-NEXT: vwadd.wv v8, v9, v101175; CHECK-NEXT: ret1176entry:1177 %a = call <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.nxv1i8(1178 <vscale x 1 x i16> %0,1179 <vscale x 1 x i16> %1,1180 <vscale x 1 x i8> %2,1181 iXLen %3)1182 1183 ret <vscale x 1 x i16> %a1184}1185 1186define <vscale x 1 x i16> @intrinsic_vwaddu_vv_nxv1i16_nxv1i8_nxv1i8(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {1187; CHECK-LABEL: intrinsic_vwaddu_vv_nxv1i16_nxv1i8_nxv1i8:1188; CHECK: # %bb.0: # %entry1189; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma1190; CHECK-NEXT: vwaddu.vv v8, v9, v101191; CHECK-NEXT: ret1192entry:1193 %a = call <vscale x 1 x i16> @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8(1194 <vscale x 1 x i16> %0,1195 <vscale x 1 x i8> %1,1196 <vscale x 1 x i8> %2,1197 iXLen %3)1198 1199 ret <vscale x 1 x i16> %a1200}1201 1202define <vscale x 1 x i16> @intrinsic_vwmul_vv_nxv1i16_nxv1i8_nxv1i8(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {1203; CHECK-LABEL: intrinsic_vwmul_vv_nxv1i16_nxv1i8_nxv1i8:1204; CHECK: # %bb.0: # %entry1205; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma1206; CHECK-NEXT: vwmul.vv v8, v9, v101207; CHECK-NEXT: ret1208entry:1209 %a = call <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8(1210 <vscale x 1 x i16> %0,1211 <vscale x 1 x i8> %1,1212 <vscale x 1 x i8> %2,1213 iXLen %3)1214 1215 ret <vscale x 1 x i16> %a1216}1217 1218define <vscale x 1 x i16> @intrinsic_vwmulu_vv_nxv1i16_nxv1i8_nxv1i8(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {1219; CHECK-LABEL: intrinsic_vwmulu_vv_nxv1i16_nxv1i8_nxv1i8:1220; CHECK: # %bb.0: # %entry1221; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma1222; CHECK-NEXT: vwmulu.vv v8, v9, v101223; CHECK-NEXT: ret1224entry:1225 %a = call <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8(1226 <vscale x 1 x i16> %0,1227 <vscale x 1 x i8> %1,1228 <vscale x 1 x i8> %2,1229 iXLen %3)1230 1231 ret <vscale x 1 x i16> %a1232}1233 1234define <vscale x 1 x i16> @intrinsic_vwmulsu_vv_nxv1i16_nxv1i8_nxv1i8(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {1235; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv1i16_nxv1i8_nxv1i8:1236; CHECK: # %bb.0: # %entry1237; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma1238; CHECK-NEXT: vwmulsu.vv v8, v9, v101239; CHECK-NEXT: ret1240entry:1241 %a = call <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8(1242 <vscale x 1 x i16> %0,1243 <vscale x 1 x i8> %1,1244 <vscale x 1 x i8> %2,1245 iXLen %3)1246 1247 ret <vscale x 1 x i16> %a1248}1249 1250define <vscale x 1 x i16> @intrinsic_vwsub_vv_nxv1i16_nxv1i8_nxv1i8(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {1251; CHECK-LABEL: intrinsic_vwsub_vv_nxv1i16_nxv1i8_nxv1i8:1252; CHECK: # %bb.0: # %entry1253; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma1254; CHECK-NEXT: vwsub.vv v8, v9, v101255; CHECK-NEXT: ret1256entry:1257 %a = call <vscale x 1 x i16> @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8(1258 <vscale x 1 x i16> %0,1259 <vscale x 1 x i8> %1,1260 <vscale x 1 x i8> %2,1261 iXLen %3)1262 1263 ret <vscale x 1 x i16> %a1264}1265 1266define <vscale x 1 x i16> @intrinsic_vwsub.w_wv_nxv1i16_nxv1i16_nxv1i8(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {1267; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv1i16_nxv1i16_nxv1i8:1268; CHECK: # %bb.0: # %entry1269; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma1270; CHECK-NEXT: vwsub.wv v8, v9, v101271; CHECK-NEXT: ret1272entry:1273 %a = call <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.nxv1i8(1274 <vscale x 1 x i16> %0,1275 <vscale x 1 x i16> %1,1276 <vscale x 1 x i8> %2,1277 iXLen %3)1278 1279 ret <vscale x 1 x i16> %a1280}1281 1282define <vscale x 1 x i16> @intrinsic_vwsub.w_wv_nxv1i16_nxv1i16_nxv1i8_tied(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {1283; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv1i16_nxv1i16_nxv1i8_tied:1284; CHECK: # %bb.0: # %entry1285; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma1286; CHECK-NEXT: vwsub.wv v8, v8, v91287; CHECK-NEXT: ret1288entry:1289 %a = call <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.nxv1i8(1290 <vscale x 1 x i16> %0,1291 <vscale x 1 x i16> %0,1292 <vscale x 1 x i8> %1,1293 iXLen %2)1294 1295 ret <vscale x 1 x i16> %a1296}1297 1298define <vscale x 1 x i16> @intrinsic_vwsubu_vv_nxv1i16_nxv1i8_nxv1i8(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {1299; CHECK-LABEL: intrinsic_vwsubu_vv_nxv1i16_nxv1i8_nxv1i8:1300; CHECK: # %bb.0: # %entry1301; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma1302; CHECK-NEXT: vwsubu.vv v8, v9, v101303; CHECK-NEXT: ret1304entry:1305 %a = call <vscale x 1 x i16> @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8(1306 <vscale x 1 x i16> %0,1307 <vscale x 1 x i8> %1,1308 <vscale x 1 x i8> %2,1309 iXLen %3)1310 1311 ret <vscale x 1 x i16> %a1312}1313 1314define <vscale x 1 x i16> @intrinsic_vwsubu.w_wv_nxv1i16_nxv1i16_nxv1i8(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {1315; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv1i16_nxv1i16_nxv1i8:1316; CHECK: # %bb.0: # %entry1317; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma1318; CHECK-NEXT: vwsubu.wv v8, v9, v101319; CHECK-NEXT: ret1320entry:1321 %a = call <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8(1322 <vscale x 1 x i16> %0,1323 <vscale x 1 x i16> %1,1324 <vscale x 1 x i8> %2,1325 iXLen %3)1326 1327 ret <vscale x 1 x i16> %a1328}1329 1330define <vscale x 1 x i8> @intrinsic_vxor_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {1331; CHECK-LABEL: intrinsic_vxor_vv_nxv1i8_nxv1i8_nxv1i8:1332; CHECK: # %bb.0: # %entry1333; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma1334; CHECK-NEXT: vxor.vv v8, v9, v101335; CHECK-NEXT: ret1336entry:1337 %a = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.nxv1i8(1338 <vscale x 1 x i8> %0,1339 <vscale x 1 x i8> %1,1340 <vscale x 1 x i8> %2,1341 iXLen %3)1342 1343 ret <vscale x 1 x i8> %a1344}1345 1346define <vscale x 1 x i64> @intrinsic_vsext_vf8_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {1347; CHECK-LABEL: intrinsic_vsext_vf8_nxv1i64:1348; CHECK: # %bb.0: # %entry1349; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma1350; CHECK-NEXT: vsext.vf8 v8, v91351; CHECK-NEXT: ret1352entry:1353 %a = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i8(1354 <vscale x 1 x i64> %0,1355 <vscale x 1 x i8> %1,1356 iXLen %2)1357 1358 ret <vscale x 1 x i64> %a1359}1360 1361define <vscale x 1 x i64> @intrinsic_vzext_vf8_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {1362; CHECK-LABEL: intrinsic_vzext_vf8_nxv1i64:1363; CHECK: # %bb.0: # %entry1364; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma1365; CHECK-NEXT: vzext.vf8 v8, v91366; CHECK-NEXT: ret1367entry:1368 %a = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i8(1369 <vscale x 1 x i64> %0,1370 <vscale x 1 x i8> %1,1371 iXLen %2)1372 1373 ret <vscale x 1 x i64> %a1374}1375 1376define <vscale x 2 x i16> @intrinsic_vfncvt_x.f.w_nxv2i16_nxv2f32( <vscale x 2 x i16> %0, <vscale x 2 x float> %1, iXLen %2) nounwind {1377; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv2i16_nxv2f32:1378; CHECK: # %bb.0: # %entry1379; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma1380; CHECK-NEXT: vfncvt.x.f.w v8, v91381; CHECK-NEXT: ret1382entry:1383 %a = call <vscale x 2 x i16> @llvm.riscv.vfncvt.x.f.w.nxv2i16.nxv2f32(1384 <vscale x 2 x i16> %0,1385 <vscale x 2 x float> %1,1386 iXLen 7, iXLen %2)1387 1388 ret <vscale x 2 x i16> %a1389}1390 1391define <vscale x 1 x i8> @intrinsic_vid_v_nxv1i8(<vscale x 1 x i8> %0, iXLen %1) nounwind {1392; CHECK-LABEL: intrinsic_vid_v_nxv1i8:1393; CHECK: # %bb.0: # %entry1394; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma1395; CHECK-NEXT: vid.v v81396; CHECK-NEXT: ret1397entry:1398 %a = call <vscale x 1 x i8> @llvm.riscv.vid.nxv1i8(1399 <vscale x 1 x i8> %0,1400 iXLen %1)1401 1402 ret <vscale x 1 x i8> %a1403}1404 1405define <vscale x 1 x i16> @intrinsic_vfclass_v_nxv1i16_nxv1f16(1406; CHECK-LABEL: intrinsic_vfclass_v_nxv1i16_nxv1f16:1407; CHECK: # %bb.0: # %entry1408; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma1409; CHECK-NEXT: vfclass.v v8, v91410; CHECK-NEXT: ret1411 <vscale x 1 x i16> %0,1412 <vscale x 1 x half> %1,1413 iXLen %2) nounwind {1414entry:1415 %a = call <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1i16(1416 <vscale x 1 x i16> %0,1417 <vscale x 1 x half> %1,1418 iXLen %2)1419 1420 ret <vscale x 1 x i16> %a1421}1422 1423define <vscale x 1 x half> @intrinsic_vfcvt_f.x.v_nxv1f16_nxv1i16(<vscale x 1 x half> %0, <vscale x 1 x i16> %1, iXLen %2) nounwind {1424; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv1f16_nxv1i16:1425; CHECK: # %bb.0: # %entry1426; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma1427; CHECK-NEXT: vfcvt.f.x.v v8, v91428; CHECK-NEXT: ret1429entry:1430 %a = call <vscale x 1 x half> @llvm.riscv.vfcvt.f.x.v.nxv1f16.nxv1i16(1431 <vscale x 1 x half> %0,1432 <vscale x 1 x i16> %1,1433 iXLen 7, iXLen %2)1434 1435 ret <vscale x 1 x half> %a1436}1437 1438define <vscale x 1 x half> @intrinsic_vfcvt_f.xu.v_nxv1f16_nxv1i16(<vscale x 1 x half> %0, <vscale x 1 x i16> %1, iXLen %2) nounwind {1439; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv1f16_nxv1i16:1440; CHECK: # %bb.0: # %entry1441; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma1442; CHECK-NEXT: vfcvt.f.xu.v v8, v91443; CHECK-NEXT: ret1444entry:1445 %a = call <vscale x 1 x half> @llvm.riscv.vfcvt.f.xu.v.nxv1f16.nxv1i16(1446 <vscale x 1 x half> %0,1447 <vscale x 1 x i16> %1,1448 iXLen 7, iXLen %2)1449 1450 ret <vscale x 1 x half> %a1451}1452 1453define <vscale x 1 x i16> @intrinsic_vfcvt_rtz.x.f.v_nxv1i16_nxv1f16(<vscale x 1 x i16> %0, <vscale x 1 x half> %1, iXLen %2) nounwind {1454; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv1i16_nxv1f16:1455; CHECK: # %bb.0: # %entry1456; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma1457; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v91458; CHECK-NEXT: ret1459entry:1460 %a = call <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16(1461 <vscale x 1 x i16> %0,1462 <vscale x 1 x half> %1,1463 iXLen %2)1464 1465 ret <vscale x 1 x i16> %a1466}1467 1468define <vscale x 1 x i16> @intrinsic_vfcvt_rtz.xu.f.v_nxv1i16_nxv1f16(<vscale x 1 x i16> %0, <vscale x 1 x half> %1, iXLen %2) nounwind {1469; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv1i16_nxv1f16:1470; CHECK: # %bb.0: # %entry1471; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma1472; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v91473; CHECK-NEXT: ret1474entry:1475 %a = call <vscale x 1 x i16> @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16(1476 <vscale x 1 x i16> %0,1477 <vscale x 1 x half> %1,1478 iXLen %2)1479 1480 ret <vscale x 1 x i16> %a1481}1482 1483define <vscale x 1 x i16> @intrinsic_vfcvt_x.f.v_nxv1i16_nxv1f16(<vscale x 1 x i16> %0, <vscale x 1 x half> %1, iXLen %2) nounwind {1484; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv1i16_nxv1f16:1485; CHECK: # %bb.0: # %entry1486; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma1487; CHECK-NEXT: vfcvt.x.f.v v8, v91488; CHECK-NEXT: ret1489entry:1490 %a = call <vscale x 1 x i16> @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16(1491 <vscale x 1 x i16> %0,1492 <vscale x 1 x half> %1,1493 iXLen 7, iXLen %2)1494 1495 ret <vscale x 1 x i16> %a1496}1497 1498define <vscale x 1 x half> @intrinsic_vfncvt_f.f.w_nxv1f16_nxv1f32(<vscale x 1 x half> %0, <vscale x 1 x float> %1, iXLen %2) nounwind {1499; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv1f16_nxv1f32:1500; CHECK: # %bb.0: # %entry1501; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma1502; CHECK-NEXT: vfncvt.f.f.w v8, v91503; CHECK-NEXT: ret1504entry:1505 %a = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32(1506 <vscale x 1 x half> %0,1507 <vscale x 1 x float> %1,1508 iXLen 7, iXLen %2)1509 1510 ret <vscale x 1 x half> %a1511}1512 1513define <vscale x 1 x i16> @intrinsic_vfcvt_xu.f.v_nxv1i16_nxv1f16(<vscale x 1 x i16> %0, <vscale x 1 x half> %1, iXLen %2) nounwind {1514; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv1i16_nxv1f16:1515; CHECK: # %bb.0: # %entry1516; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma1517; CHECK-NEXT: vfcvt.xu.f.v v8, v91518; CHECK-NEXT: ret1519entry:1520 %a = call <vscale x 1 x i16> @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16(1521 <vscale x 1 x i16> %0,1522 <vscale x 1 x half> %1,1523 iXLen 7, iXLen %2)1524 1525 ret <vscale x 1 x i16> %a1526}1527 1528define <vscale x 1 x half> @intrinsic_vfncvt_f.x.w_nxv1f16_nxv1i32(<vscale x 1 x half> %0, <vscale x 1 x i32> %1, iXLen %2) nounwind {1529; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv1f16_nxv1i32:1530; CHECK: # %bb.0: # %entry1531; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma1532; CHECK-NEXT: vfncvt.f.x.w v8, v91533; CHECK-NEXT: ret1534entry:1535 %a = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.x.w.nxv1f16.nxv1i32(1536 <vscale x 1 x half> %0,1537 <vscale x 1 x i32> %1,1538 iXLen 7, iXLen %2)1539 1540 ret <vscale x 1 x half> %a1541}1542 1543define <vscale x 1 x half> @intrinsic_vfncvt_f.xu.w_nxv1f16_nxv1i32(<vscale x 1 x half> %0, <vscale x 1 x i32> %1, iXLen %2) nounwind {1544; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv1f16_nxv1i32:1545; CHECK: # %bb.0: # %entry1546; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma1547; CHECK-NEXT: vfncvt.f.xu.w v8, v91548; CHECK-NEXT: ret1549entry:1550 %a = call <vscale x 1 x half> @llvm.riscv.vfncvt.f.xu.w.nxv1f16.nxv1i32(1551 <vscale x 1 x half> %0,1552 <vscale x 1 x i32> %1,1553 iXLen 7, iXLen %2)1554 1555 ret <vscale x 1 x half> %a1556}1557 1558define <vscale x 1 x half> @intrinsic_vfncvt_rod.f.f.w_nxv1f16_nxv1f32(<vscale x 1 x half> %0, <vscale x 1 x float> %1, iXLen %2) nounwind {1559; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv1f16_nxv1f32:1560; CHECK: # %bb.0: # %entry1561; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma1562; CHECK-NEXT: vfncvt.rod.f.f.w v8, v91563; CHECK-NEXT: ret1564entry:1565 %a = call <vscale x 1 x half> @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32(1566 <vscale x 1 x half> %0,1567 <vscale x 1 x float> %1,1568 iXLen %2)1569 1570 ret <vscale x 1 x half> %a1571}1572 1573define <vscale x 1 x i8> @intrinsic_vfncvt_rtz.x.f.w_nxv1i8_nxv1f16(<vscale x 1 x i8> %0, <vscale x 1 x half> %1, iXLen %2) nounwind {1574; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv1i8_nxv1f16:1575; CHECK: # %bb.0: # %entry1576; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma1577; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v91578; CHECK-NEXT: ret1579entry:1580 %a = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16(1581 <vscale x 1 x i8> %0,1582 <vscale x 1 x half> %1,1583 iXLen %2)1584 1585 ret <vscale x 1 x i8> %a1586}1587 1588define <vscale x 1 x i8> @intrinsic_vfncvt_rtz.xu.f.w_nxv1i8_nxv1f16(<vscale x 1 x i8> %0, <vscale x 1 x half> %1, iXLen %2) nounwind {1589; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv1i8_nxv1f16:1590; CHECK: # %bb.0: # %entry1591; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma1592; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v91593; CHECK-NEXT: ret1594entry:1595 %a = call <vscale x 1 x i8> @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16(1596 <vscale x 1 x i8> %0,1597 <vscale x 1 x half> %1,1598 iXLen %2)1599 1600 ret <vscale x 1 x i8> %a1601}1602 1603define <vscale x 1 x i8> @intrinsic_vfncvt_x.f.w_nxv1i8_nxv1f16(<vscale x 1 x i8> %0, <vscale x 1 x half> %1, iXLen %2) nounwind {1604; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv1i8_nxv1f16:1605; CHECK: # %bb.0: # %entry1606; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma1607; CHECK-NEXT: vfncvt.x.f.w v8, v91608; CHECK-NEXT: ret1609entry:1610 %a = call <vscale x 1 x i8> @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16(1611 <vscale x 1 x i8> %0,1612 <vscale x 1 x half> %1,1613 iXLen 7, iXLen %2)1614 1615 ret <vscale x 1 x i8> %a1616}1617 1618define <vscale x 1 x i8> @intrinsic_vfncvt_xu.f.w_nxv1i8_nxv1f16(<vscale x 1 x i8> %0, <vscale x 1 x half> %1, iXLen %2) nounwind {1619; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv1i8_nxv1f16:1620; CHECK: # %bb.0: # %entry1621; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma1622; CHECK-NEXT: vfncvt.xu.f.w v8, v91623; CHECK-NEXT: ret1624entry:1625 %a = call <vscale x 1 x i8> @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16(1626 <vscale x 1 x i8> %0,1627 <vscale x 1 x half> %1,1628 iXLen 7, iXLen %2)1629 1630 ret <vscale x 1 x i8> %a1631}1632 1633define <vscale x 1 x half> @intrinsic_vfrec7_v_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, iXLen %2) nounwind {1634; CHECK-LABEL: intrinsic_vfrec7_v_nxv1f16_nxv1f16:1635; CHECK: # %bb.0: # %entry1636; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma1637; CHECK-NEXT: vfrec7.v v8, v91638; CHECK-NEXT: ret1639entry:1640 %a = call <vscale x 1 x half> @llvm.riscv.vfrec7.nxv1f16(1641 <vscale x 1 x half> %0,1642 <vscale x 1 x half> %1,1643 iXLen 7, iXLen %2)1644 1645 ret <vscale x 1 x half> %a1646}1647 1648define <vscale x 1 x half> @intrinsic_vfrsqrt7_v_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, iXLen %2) nounwind {1649; CHECK-LABEL: intrinsic_vfrsqrt7_v_nxv1f16_nxv1f16:1650; CHECK: # %bb.0: # %entry1651; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma1652; CHECK-NEXT: vfrsqrt7.v v8, v91653; CHECK-NEXT: ret1654entry:1655 %a = call <vscale x 1 x half> @llvm.riscv.vfrsqrt7.nxv1f16(1656 <vscale x 1 x half> %0,1657 <vscale x 1 x half> %1,1658 iXLen %2)1659 1660 ret <vscale x 1 x half> %a1661}1662 1663define <vscale x 1 x half> @intrinsic_vfsqrt_v_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, iXLen %2) nounwind {1664; CHECK-LABEL: intrinsic_vfsqrt_v_nxv1f16_nxv1f16:1665; CHECK: # %bb.0: # %entry1666; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma1667; CHECK-NEXT: vfsqrt.v v8, v91668; CHECK-NEXT: ret1669entry:1670 %a = call <vscale x 1 x half> @llvm.riscv.vfsqrt.nxv1f16(1671 <vscale x 1 x half> %0,1672 <vscale x 1 x half> %1,1673 iXLen 7, iXLen %2)1674 1675 ret <vscale x 1 x half> %a1676}1677 1678define <vscale x 1 x float> @intrinsic_vfwcvt_f.f.v_nxv1f32_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, iXLen %2) nounwind {1679; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv1f32_nxv1f16:1680; CHECK: # %bb.0: # %entry1681; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma1682; CHECK-NEXT: vfwcvt.f.f.v v8, v91683; CHECK-NEXT: ret1684entry:1685 %a = call <vscale x 1 x float> @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16(1686 <vscale x 1 x float> %0,1687 <vscale x 1 x half> %1,1688 iXLen %2)1689 1690 ret <vscale x 1 x float> %a1691}1692 1693define <vscale x 1 x half> @intrinsic_vfwcvt_f.x.v_nxv1f16_nxv1i8(<vscale x 1 x half> %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {1694; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv1f16_nxv1i8:1695; CHECK: # %bb.0: # %entry1696; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma1697; CHECK-NEXT: vfwcvt.f.x.v v8, v91698; CHECK-NEXT: ret1699entry:1700 %a = call <vscale x 1 x half> @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8(1701 <vscale x 1 x half> %0,1702 <vscale x 1 x i8> %1,1703 iXLen %2)1704 1705 ret <vscale x 1 x half> %a1706}1707 1708define <vscale x 1 x half> @intrinsic_vfwcvt_f.xu.v_nxv1f16_nxv1i8(<vscale x 1 x half> %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {1709; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv1f16_nxv1i8:1710; CHECK: # %bb.0: # %entry1711; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma1712; CHECK-NEXT: vfwcvt.f.xu.v v8, v91713; CHECK-NEXT: ret1714entry:1715 %a = call <vscale x 1 x half> @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8(1716 <vscale x 1 x half> %0,1717 <vscale x 1 x i8> %1,1718 iXLen %2)1719 1720 ret <vscale x 1 x half> %a1721}1722 1723define <vscale x 1 x i32> @intrinsic_vfwcvt_rtz.x.f.v_nxv1i32_nxv1f16(<vscale x 1 x i32> %0, <vscale x 1 x half> %1, iXLen %2) nounwind {1724; CHECK-LABEL: intrinsic_vfwcvt_rtz.x.f.v_nxv1i32_nxv1f16:1725; CHECK: # %bb.0: # %entry1726; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma1727; CHECK-NEXT: vfwcvt.rtz.x.f.v v8, v91728; CHECK-NEXT: ret1729entry:1730 %a = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16(1731 <vscale x 1 x i32> %0,1732 <vscale x 1 x half> %1,1733 iXLen %2)1734 1735 ret <vscale x 1 x i32> %a1736}1737 1738define <vscale x 1 x i32> @intrinsic_vfwcvt_rtz.xu.f.v_nxv1i32_nxv1f16(<vscale x 1 x i32> %0, <vscale x 1 x half> %1, iXLen %2) nounwind {1739; CHECK-LABEL: intrinsic_vfwcvt_rtz.xu.f.v_nxv1i32_nxv1f16:1740; CHECK: # %bb.0: # %entry1741; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma1742; CHECK-NEXT: vfwcvt.rtz.xu.f.v v8, v91743; CHECK-NEXT: ret1744entry:1745 %a = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16(1746 <vscale x 1 x i32> %0,1747 <vscale x 1 x half> %1,1748 iXLen %2)1749 1750 ret <vscale x 1 x i32> %a1751}1752 1753define <vscale x 1 x i32> @intrinsic_vfwcvt_x.f.v_nxv1i32_nxv1f16(<vscale x 1 x i32> %0, <vscale x 1 x half> %1, iXLen %2) nounwind {1754; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv1i32_nxv1f16:1755; CHECK: # %bb.0: # %entry1756; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma1757; CHECK-NEXT: vfwcvt.x.f.v v8, v91758; CHECK-NEXT: ret1759entry:1760 %a = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.x.f.v.nxv1i32.nxv1f16(1761 <vscale x 1 x i32> %0,1762 <vscale x 1 x half> %1,1763 iXLen 7, iXLen %2)1764 1765 ret <vscale x 1 x i32> %a1766}1767 1768define <vscale x 1 x i32> @intrinsic_vfwcvt_xu.f.v_nxv1i32_nxv1f16(<vscale x 1 x i32> %0, <vscale x 1 x half> %1, iXLen %2) nounwind {1769; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv1i32_nxv1f16:1770; CHECK: # %bb.0: # %entry1771; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma1772; CHECK-NEXT: vfwcvt.xu.f.v v8, v91773; CHECK-NEXT: ret1774entry:1775 %a = call <vscale x 1 x i32> @llvm.riscv.vfwcvt.xu.f.v.nxv1i32.nxv1f16(1776 <vscale x 1 x i32> %0,1777 <vscale x 1 x half> %1,1778 iXLen 7, iXLen %2)1779 1780 ret <vscale x 1 x i32> %a1781}1782 1783define <vscale x 1 x i8> @intrinsic_viota_m_nxv1i8_nxv1i1(<vscale x 1 x i8> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {1784; CHECK-LABEL: intrinsic_viota_m_nxv1i8_nxv1i1:1785; CHECK: # %bb.0: # %entry1786; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma1787; CHECK-NEXT: viota.m v8, v01788; CHECK-NEXT: ret1789entry:1790 %a = call <vscale x 1 x i8> @llvm.riscv.viota.nxv1i8(1791 <vscale x 1 x i8> %0,1792 <vscale x 1 x i1> %1,1793 iXLen %2)1794 1795 ret <vscale x 1 x i8> %a1796}1797 1798define <vscale x 1 x i8> @intrinsic_vadc_vvm_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {1799; CHECK-LABEL: intrinsic_vadc_vvm_nxv1i8_nxv1i8_nxv1i8:1800; CHECK: # %bb.0: # %entry1801; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma1802; CHECK-NEXT: vadc.vvm v8, v9, v10, v01803; CHECK-NEXT: ret1804entry:1805 %a = call <vscale x 1 x i8> @llvm.riscv.vadc.nxv1i8.nxv1i8(1806 <vscale x 1 x i8> %0,1807 <vscale x 1 x i8> %1,1808 <vscale x 1 x i8> %2,1809 <vscale x 1 x i1> %3,1810 iXLen %4)1811 1812 ret <vscale x 1 x i8> %a1813}1814 1815define <vscale x 1 x i8> @intrinsic_vsbc_vvm_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {1816; CHECK-LABEL: intrinsic_vsbc_vvm_nxv1i8_nxv1i8_nxv1i8:1817; CHECK: # %bb.0: # %entry1818; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma1819; CHECK-NEXT: vsbc.vvm v8, v9, v10, v01820; CHECK-NEXT: ret1821entry:1822 %a = call <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.nxv1i8(1823 <vscale x 1 x i8> %0,1824 <vscale x 1 x i8> %1,1825 <vscale x 1 x i8> %2,1826 <vscale x 1 x i1> %3,1827 iXLen %4)1828 1829 ret <vscale x 1 x i8> %a1830}1831 1832define <vscale x 1 x i8> @intrinsic_vmerge_vvm_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {1833; CHECK-LABEL: intrinsic_vmerge_vvm_nxv1i8_nxv1i8_nxv1i8:1834; CHECK: # %bb.0: # %entry1835; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma1836; CHECK-NEXT: vmerge.vvm v8, v9, v10, v01837; CHECK-NEXT: ret1838entry:1839 %a = call <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.nxv1i8(1840 <vscale x 1 x i8> %0,1841 <vscale x 1 x i8> %1,1842 <vscale x 1 x i8> %2,1843 <vscale x 1 x i1> %3,1844 iXLen %4)1845 1846 ret <vscale x 1 x i8> %a1847}1848 1849define <vscale x 8 x i64> @intrinsic_vmerge_vxm_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {1850; RV32-LABEL: intrinsic_vmerge_vxm_nxv8i64_nxv8i64_i64:1851; RV32: # %bb.0: # %entry1852; RV32-NEXT: addi sp, sp, -161853; RV32-NEXT: sw a0, 8(sp)1854; RV32-NEXT: sw a1, 12(sp)1855; RV32-NEXT: addi a0, sp, 81856; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma1857; RV32-NEXT: vlse64.v v24, (a0), zero1858; RV32-NEXT: vsetvli zero, zero, e64, m8, tu, ma1859; RV32-NEXT: vmerge.vvm v8, v16, v24, v01860; RV32-NEXT: addi sp, sp, 161861; RV32-NEXT: ret1862;1863; RV64-LABEL: intrinsic_vmerge_vxm_nxv8i64_nxv8i64_i64:1864; RV64: # %bb.0: # %entry1865; RV64-NEXT: vsetvli zero, a1, e64, m8, tu, ma1866; RV64-NEXT: vmerge.vxm v8, v16, a0, v01867; RV64-NEXT: ret1868entry:1869 %a = call <vscale x 8 x i64> @llvm.riscv.vmerge.nxv8i64.i64(1870 <vscale x 8 x i64> %0,1871 <vscale x 8 x i64> %1,1872 i64 %2,1873 <vscale x 8 x i1> %3,1874 iXLen %4)1875 1876 ret <vscale x 8 x i64> %a1877}1878 1879define <vscale x 8 x i64> @intrinsic_vmerge_vim_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {1880; RV32-LABEL: intrinsic_vmerge_vim_nxv8i64_nxv8i64_i64:1881; RV32: # %bb.0: # %entry1882; RV32-NEXT: addi sp, sp, -161883; RV32-NEXT: li a1, 151884; RV32-NEXT: li a2, -11885; RV32-NEXT: sw a2, 8(sp)1886; RV32-NEXT: sw a1, 12(sp)1887; RV32-NEXT: addi a1, sp, 81888; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma1889; RV32-NEXT: vlse64.v v24, (a1), zero1890; RV32-NEXT: vsetvli zero, zero, e64, m8, tu, ma1891; RV32-NEXT: vmerge.vvm v8, v16, v24, v01892; RV32-NEXT: addi sp, sp, 161893; RV32-NEXT: ret1894;1895; RV64-LABEL: intrinsic_vmerge_vim_nxv8i64_nxv8i64_i64:1896; RV64: # %bb.0: # %entry1897; RV64-NEXT: li a1, -11898; RV64-NEXT: srli a1, a1, 281899; RV64-NEXT: vsetvli zero, a0, e64, m8, tu, ma1900; RV64-NEXT: vmerge.vxm v8, v16, a1, v01901; RV64-NEXT: ret1902entry:1903 %a = call <vscale x 8 x i64> @llvm.riscv.vmerge.nxv8i64.i64(1904 <vscale x 8 x i64> %0,1905 <vscale x 8 x i64> %1,1906 i64 68719476735,1907 <vscale x 8 x i1> %2,1908 iXLen %3)1909 1910 ret <vscale x 8 x i64> %a1911}1912 1913define <vscale x 8 x double> @intrinsic_vfmerge_vfm_nxv8f64_nxv8f64_f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, double %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {1914; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv8f64_nxv8f64_f64:1915; CHECK: # %bb.0: # %entry1916; CHECK-NEXT: vsetvli zero, a0, e64, m8, tu, ma1917; CHECK-NEXT: vfmerge.vfm v8, v16, fa0, v01918; CHECK-NEXT: ret1919entry:1920 %a = call <vscale x 8 x double> @llvm.riscv.vfmerge.nxv8f64.f64(1921 <vscale x 8 x double> %0,1922 <vscale x 8 x double> %1,1923 double %2,1924 <vscale x 8 x i1> %3,1925 iXLen %4)1926 1927 ret <vscale x 8 x double> %a1928}1929 1930define <vscale x 1 x half> @intrinsic_vmerge_vvm_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {1931; CHECK-LABEL: intrinsic_vmerge_vvm_nxv1f16_nxv1f16_nxv1f16:1932; CHECK: # %bb.0: # %entry1933; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma1934; CHECK-NEXT: vmerge.vvm v8, v9, v10, v01935; CHECK-NEXT: ret1936entry:1937 %a = call <vscale x 1 x half> @llvm.riscv.vmerge.nxv1f16.nxv1f16(1938 <vscale x 1 x half> %0,1939 <vscale x 1 x half> %1,1940 <vscale x 1 x half> %2,1941 <vscale x 1 x i1> %3,1942 iXLen %4)1943 1944 ret <vscale x 1 x half> %a1945}1946 1947define <vscale x 1 x half> @intrinsic_vfmerge_vzm_nxv1f16_nxv1f16_f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {1948; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv1f16_nxv1f16_f16:1949; CHECK: # %bb.0: # %entry1950; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma1951; CHECK-NEXT: vmerge.vim v8, v9, 0, v01952; CHECK-NEXT: ret1953entry:1954 %a = call <vscale x 1 x half> @llvm.riscv.vfmerge.nxv1f16.f16(1955 <vscale x 1 x half> %0,1956 <vscale x 1 x half> %1,1957 half zeroinitializer,1958 <vscale x 1 x i1> %2,1959 iXLen %3)1960 1961 ret <vscale x 1 x half> %a1962}1963 1964define <vscale x 1 x i8> @intrinsic_vmv.v.v_v_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {1965; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1i8_nxv1i8:1966; CHECK: # %bb.0: # %entry1967; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma1968; CHECK-NEXT: vmv.v.v v8, v91969; CHECK-NEXT: ret1970entry:1971 %a = call <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8(1972 <vscale x 1 x i8> %0,1973 <vscale x 1 x i8> %1,1974 iXLen %2)1975 1976 ret <vscale x 1 x i8> %a1977}1978 1979define <vscale x 1 x float> @intrinsic_vmv.v.v_v_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, iXLen %2) nounwind {1980; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1f32_nxv1f32:1981; CHECK: # %bb.0: # %entry1982; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma1983; CHECK-NEXT: vmv.v.v v8, v91984; CHECK-NEXT: ret1985entry:1986 %a = call <vscale x 1 x float> @llvm.riscv.vmv.v.v.nxv1f32(1987 <vscale x 1 x float> %0,1988 <vscale x 1 x float> %1,1989 iXLen %2)1990 1991 ret <vscale x 1 x float> %a1992}1993 1994define <vscale x 1 x i64> @intrinsic_vmv.v.x_x_nxv1i64(<vscale x 1 x i64> %0, i64 %1, iXLen %2) nounwind {1995; RV32-LABEL: intrinsic_vmv.v.x_x_nxv1i64:1996; RV32: # %bb.0: # %entry1997; RV32-NEXT: addi sp, sp, -161998; RV32-NEXT: sw a0, 8(sp)1999; RV32-NEXT: sw a1, 12(sp)2000; RV32-NEXT: addi a0, sp, 82001; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, ma2002; RV32-NEXT: vlse64.v v8, (a0), zero2003; RV32-NEXT: addi sp, sp, 162004; RV32-NEXT: ret2005;2006; RV64-LABEL: intrinsic_vmv.v.x_x_nxv1i64:2007; RV64: # %bb.0: # %entry2008; RV64-NEXT: vsetvli zero, a1, e64, m1, tu, ma2009; RV64-NEXT: vmv.v.x v8, a02010; RV64-NEXT: ret2011entry:2012 %a = call <vscale x 1 x i64> @llvm.riscv.vmv.v.x.nxv1i64(2013 <vscale x 1 x i64> %0,2014 i64 %1,2015 iXLen %2)2016 2017 ret <vscale x 1 x i64> %a2018}2019 2020define <vscale x 1 x float> @intrinsic_vfmv.v.f_f_nxv1f32(<vscale x 1 x float> %0, float %1, iXLen %2) nounwind {2021; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv1f32:2022; CHECK: # %bb.0: # %entry2023; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma2024; CHECK-NEXT: vfmv.v.f v8, fa02025; CHECK-NEXT: ret2026entry:2027 %a = call <vscale x 1 x float> @llvm.riscv.vfmv.v.f.nxv1f32(2028 <vscale x 1 x float> %0,2029 float %1,2030 iXLen %2)2031 2032 ret <vscale x 1 x float> %a2033}2034