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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+m,+v < %s | FileCheck %s --check-prefix=RV323; RUN: llc -mtriple=riscv64 -mattr=+m,+v < %s | FileCheck %s --check-prefix=RV644 5define <vscale x 1 x i16> @test_urem_vec_even_divisor_eq0(<vscale x 1 x i16> %x) nounwind {6; RV32-LABEL: test_urem_vec_even_divisor_eq0:7; RV32: # %bb.0:8; RV32-NEXT: lui a0, 10485719; RV32-NEXT: addi a0, a0, -136510; RV32-NEXT: vsetvli a1, zero, e16, mf4, ta, ma11; RV32-NEXT: vmul.vx v8, v8, a012; RV32-NEXT: lui a0, 313; RV32-NEXT: addi a0, a0, -136614; RV32-NEXT: vsll.vi v9, v8, 1515; RV32-NEXT: vsrl.vi v8, v8, 116; RV32-NEXT: vor.vv v8, v8, v917; RV32-NEXT: vmsgtu.vx v0, v8, a018; RV32-NEXT: vmv.v.i v8, 019; RV32-NEXT: vmerge.vim v8, v8, -1, v020; RV32-NEXT: ret21;22; RV64-LABEL: test_urem_vec_even_divisor_eq0:23; RV64: # %bb.0:24; RV64-NEXT: lui a0, 104857125; RV64-NEXT: addi a0, a0, -136526; RV64-NEXT: vsetvli a1, zero, e16, mf4, ta, ma27; RV64-NEXT: vmul.vx v8, v8, a028; RV64-NEXT: lui a0, 329; RV64-NEXT: addi a0, a0, -136630; RV64-NEXT: vsll.vi v9, v8, 1531; RV64-NEXT: vsrl.vi v8, v8, 132; RV64-NEXT: vor.vv v8, v8, v933; RV64-NEXT: vmsgtu.vx v0, v8, a034; RV64-NEXT: vmv.v.i v8, 035; RV64-NEXT: vmerge.vim v8, v8, -1, v036; RV64-NEXT: ret37 %urem = urem <vscale x 1 x i16> %x, splat (i16 6)38 %cmp = icmp ne <vscale x 1 x i16> %urem, splat (i16 0)39 %ext = sext <vscale x 1 x i1> %cmp to <vscale x 1 x i16>40 ret <vscale x 1 x i16> %ext41}42 43define <vscale x 1 x i16> @test_urem_vec_odd_divisor_eq0(<vscale x 1 x i16> %x) nounwind {44; RV32-LABEL: test_urem_vec_odd_divisor_eq0:45; RV32: # %bb.0:46; RV32-NEXT: lui a0, 104857347; RV32-NEXT: addi a0, a0, -81948; RV32-NEXT: vsetvli a1, zero, e16, mf4, ta, ma49; RV32-NEXT: vmul.vx v8, v8, a050; RV32-NEXT: lui a0, 351; RV32-NEXT: addi a0, a0, 81952; RV32-NEXT: vmsgtu.vx v0, v8, a053; RV32-NEXT: vmv.v.i v8, 054; RV32-NEXT: vmerge.vim v8, v8, -1, v055; RV32-NEXT: ret56;57; RV64-LABEL: test_urem_vec_odd_divisor_eq0:58; RV64: # %bb.0:59; RV64-NEXT: lui a0, 104857360; RV64-NEXT: addi a0, a0, -81961; RV64-NEXT: vsetvli a1, zero, e16, mf4, ta, ma62; RV64-NEXT: vmul.vx v8, v8, a063; RV64-NEXT: lui a0, 364; RV64-NEXT: addi a0, a0, 81965; RV64-NEXT: vmsgtu.vx v0, v8, a066; RV64-NEXT: vmv.v.i v8, 067; RV64-NEXT: vmerge.vim v8, v8, -1, v068; RV64-NEXT: ret69 %urem = urem <vscale x 1 x i16> %x, splat (i16 5)70 %cmp = icmp ne <vscale x 1 x i16> %urem, splat (i16 0)71 %ext = sext <vscale x 1 x i1> %cmp to <vscale x 1 x i16>72 ret <vscale x 1 x i16> %ext73}74 75define <vscale x 1 x i16> @test_urem_vec_even_divisor_eq1(<vscale x 1 x i16> %x) nounwind {76; RV32-LABEL: test_urem_vec_even_divisor_eq1:77; RV32: # %bb.0:78; RV32-NEXT: vsetvli a0, zero, e16, mf4, ta, ma79; RV32-NEXT: vadd.vi v8, v8, -180; RV32-NEXT: lui a0, 104857181; RV32-NEXT: addi a0, a0, -136582; RV32-NEXT: vmul.vx v8, v8, a083; RV32-NEXT: lui a0, 384; RV32-NEXT: addi a0, a0, -136685; RV32-NEXT: vsll.vi v9, v8, 1586; RV32-NEXT: vsrl.vi v8, v8, 187; RV32-NEXT: vor.vv v8, v8, v988; RV32-NEXT: vmsgtu.vx v0, v8, a089; RV32-NEXT: vmv.v.i v8, 090; RV32-NEXT: vmerge.vim v8, v8, -1, v091; RV32-NEXT: ret92;93; RV64-LABEL: test_urem_vec_even_divisor_eq1:94; RV64: # %bb.0:95; RV64-NEXT: vsetvli a0, zero, e16, mf4, ta, ma96; RV64-NEXT: vadd.vi v8, v8, -197; RV64-NEXT: lui a0, 104857198; RV64-NEXT: addi a0, a0, -136599; RV64-NEXT: vmul.vx v8, v8, a0100; RV64-NEXT: lui a0, 3101; RV64-NEXT: addi a0, a0, -1366102; RV64-NEXT: vsll.vi v9, v8, 15103; RV64-NEXT: vsrl.vi v8, v8, 1104; RV64-NEXT: vor.vv v8, v8, v9105; RV64-NEXT: vmsgtu.vx v0, v8, a0106; RV64-NEXT: vmv.v.i v8, 0107; RV64-NEXT: vmerge.vim v8, v8, -1, v0108; RV64-NEXT: ret109 %urem = urem <vscale x 1 x i16> %x, splat (i16 6)110 %cmp = icmp ne <vscale x 1 x i16> %urem, splat (i16 1)111 %ext = sext <vscale x 1 x i1> %cmp to <vscale x 1 x i16>112 ret <vscale x 1 x i16> %ext113}114 115define <vscale x 1 x i16> @test_urem_vec_odd_divisor_eq1(<vscale x 1 x i16> %x) nounwind {116; RV32-LABEL: test_urem_vec_odd_divisor_eq1:117; RV32: # %bb.0:118; RV32-NEXT: vsetvli a0, zero, e16, mf4, ta, ma119; RV32-NEXT: vadd.vi v8, v8, -1120; RV32-NEXT: lui a0, 1048573121; RV32-NEXT: addi a0, a0, -819122; RV32-NEXT: vmul.vx v8, v8, a0123; RV32-NEXT: lui a0, 3124; RV32-NEXT: addi a0, a0, 818125; RV32-NEXT: vmsgtu.vx v0, v8, a0126; RV32-NEXT: vmv.v.i v8, 0127; RV32-NEXT: vmerge.vim v8, v8, -1, v0128; RV32-NEXT: ret129;130; RV64-LABEL: test_urem_vec_odd_divisor_eq1:131; RV64: # %bb.0:132; RV64-NEXT: vsetvli a0, zero, e16, mf4, ta, ma133; RV64-NEXT: vadd.vi v8, v8, -1134; RV64-NEXT: lui a0, 1048573135; RV64-NEXT: addi a0, a0, -819136; RV64-NEXT: vmul.vx v8, v8, a0137; RV64-NEXT: lui a0, 3138; RV64-NEXT: addi a0, a0, 818139; RV64-NEXT: vmsgtu.vx v0, v8, a0140; RV64-NEXT: vmv.v.i v8, 0141; RV64-NEXT: vmerge.vim v8, v8, -1, v0142; RV64-NEXT: ret143 %urem = urem <vscale x 1 x i16> %x, splat (i16 5)144 %cmp = icmp ne <vscale x 1 x i16> %urem, splat (i16 1)145 %ext = sext <vscale x 1 x i1> %cmp to <vscale x 1 x i16>146 ret <vscale x 1 x i16> %ext147}148