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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=riscv64 -mattr=+v | FileCheck %s3 4define <2 x i64> @vec_v2i64(<2 x i64> %x, <2 x i64> %y) nounwind {5; CHECK-LABEL: vec_v2i64:6; CHECK: # %bb.0:7; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma8; CHECK-NEXT: vsll.vv v10, v8, v99; CHECK-NEXT: vsrl.vv v9, v10, v910; CHECK-NEXT: vmsne.vv v0, v8, v911; CHECK-NEXT: vmerge.vim v8, v10, -1, v012; CHECK-NEXT: ret13 %tmp = call <2 x i64> @llvm.ushl.sat.v2i64(<2 x i64> %x, <2 x i64> %y)14 ret <2 x i64> %tmp15}16 17define <4 x i32> @vec_v4i32(<4 x i32> %x, <4 x i32> %y) nounwind {18; CHECK-LABEL: vec_v4i32:19; CHECK: # %bb.0:20; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma21; CHECK-NEXT: vsll.vv v10, v8, v922; CHECK-NEXT: vsrl.vv v9, v10, v923; CHECK-NEXT: vmsne.vv v0, v8, v924; CHECK-NEXT: vmerge.vim v8, v10, -1, v025; CHECK-NEXT: ret26 %tmp = call <4 x i32> @llvm.ushl.sat.v4i32(<4 x i32> %x, <4 x i32> %y)27 ret <4 x i32> %tmp28}29 30define <8 x i16> @vec_v8i16(<8 x i16> %x, <8 x i16> %y) nounwind {31; CHECK-LABEL: vec_v8i16:32; CHECK: # %bb.0:33; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma34; CHECK-NEXT: vsll.vv v10, v8, v935; CHECK-NEXT: vsrl.vv v9, v10, v936; CHECK-NEXT: vmsne.vv v0, v8, v937; CHECK-NEXT: vmerge.vim v8, v10, -1, v038; CHECK-NEXT: ret39 %tmp = call <8 x i16> @llvm.ushl.sat.v8i16(<8 x i16> %x, <8 x i16> %y)40 ret <8 x i16> %tmp41}42 43define <16 x i8> @vec_v16i8(<16 x i8> %x, <16 x i8> %y) nounwind {44; CHECK-LABEL: vec_v16i8:45; CHECK: # %bb.0:46; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma47; CHECK-NEXT: vsll.vv v10, v8, v948; CHECK-NEXT: vsrl.vv v9, v10, v949; CHECK-NEXT: vmsne.vv v0, v8, v950; CHECK-NEXT: vmerge.vim v8, v10, -1, v051; CHECK-NEXT: ret52 %tmp = call <16 x i8> @llvm.ushl.sat.v16i8(<16 x i8> %x, <16 x i8> %y)53 ret <16 x i8> %tmp54}55 56define <vscale x 2 x i64> @vec_nxv2i64(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y) nounwind {57; CHECK-LABEL: vec_nxv2i64:58; CHECK: # %bb.0:59; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma60; CHECK-NEXT: vsll.vv v12, v8, v1061; CHECK-NEXT: vsrl.vv v10, v12, v1062; CHECK-NEXT: vmsne.vv v0, v8, v1063; CHECK-NEXT: vmerge.vim v8, v12, -1, v064; CHECK-NEXT: ret65 %tmp = call <vscale x 2 x i64> @llvm.ushl.sat.nxv2i64(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y)66 ret <vscale x 2 x i64> %tmp67}68 69define <vscale x 4 x i32> @vec_nxv4i32(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y) nounwind {70; CHECK-LABEL: vec_nxv4i32:71; CHECK: # %bb.0:72; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma73; CHECK-NEXT: vsll.vv v12, v8, v1074; CHECK-NEXT: vsrl.vv v10, v12, v1075; CHECK-NEXT: vmsne.vv v0, v8, v1076; CHECK-NEXT: vmerge.vim v8, v12, -1, v077; CHECK-NEXT: ret78 %tmp = call <vscale x 4 x i32> @llvm.ushl.sat.nxv4i32(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y)79 ret <vscale x 4 x i32> %tmp80}81 82define <vscale x 8 x i16> @vec_nxv8i16(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y) nounwind {83; CHECK-LABEL: vec_nxv8i16:84; CHECK: # %bb.0:85; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma86; CHECK-NEXT: vsll.vv v12, v8, v1087; CHECK-NEXT: vsrl.vv v10, v12, v1088; CHECK-NEXT: vmsne.vv v0, v8, v1089; CHECK-NEXT: vmerge.vim v8, v12, -1, v090; CHECK-NEXT: ret91 %tmp = call <vscale x 8 x i16> @llvm.ushl.sat.nxv8i16(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y)92 ret <vscale x 8 x i16> %tmp93}94 95define <vscale x 16 x i8> @vec_nxv16i8(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y) nounwind {96; CHECK-LABEL: vec_nxv16i8:97; CHECK: # %bb.0:98; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma99; CHECK-NEXT: vsll.vv v12, v8, v10100; CHECK-NEXT: vsrl.vv v10, v12, v10101; CHECK-NEXT: vmsne.vv v0, v8, v10102; CHECK-NEXT: vmerge.vim v8, v12, -1, v0103; CHECK-NEXT: ret104 %tmp = call <vscale x 16 x i8> @llvm.ushl.sat.nxv16i8(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y)105 ret <vscale x 16 x i8> %tmp106}107