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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV323; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV644 5define <vscale x 8 x i8> @vaaddu_vv_nxv8i8_floor(<vscale x 8 x i8> %x, <vscale x 8 x i8> %y) {6; CHECK-LABEL: vaaddu_vv_nxv8i8_floor:7; CHECK: # %bb.0:8; CHECK-NEXT: csrwi vxrm, 29; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma10; CHECK-NEXT: vaaddu.vv v8, v8, v911; CHECK-NEXT: ret12 %xzv = zext <vscale x 8 x i8> %x to <vscale x 8 x i16>13 %yzv = zext <vscale x 8 x i8> %y to <vscale x 8 x i16>14 %add = add nuw nsw <vscale x 8 x i16> %xzv, %yzv15 %div = lshr <vscale x 8 x i16> %add, splat (i16 1)16 %ret = trunc <vscale x 8 x i16> %div to <vscale x 8 x i8>17 ret <vscale x 8 x i8> %ret18}19 20define <vscale x 8 x i8> @vaaddu_vx_nxv8i8_floor(<vscale x 8 x i8> %x, i8 %y) {21; CHECK-LABEL: vaaddu_vx_nxv8i8_floor:22; CHECK: # %bb.0:23; CHECK-NEXT: csrwi vxrm, 224; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma25; CHECK-NEXT: vaaddu.vx v8, v8, a026; CHECK-NEXT: ret27 %xzv = zext <vscale x 8 x i8> %x to <vscale x 8 x i16>28 %yhead = insertelement <vscale x 8 x i8> poison, i8 %y, i32 029 %ysplat = shufflevector <vscale x 8 x i8> %yhead, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer30 %yzv = zext <vscale x 8 x i8> %ysplat to <vscale x 8 x i16>31 %add = add nuw nsw <vscale x 8 x i16> %xzv, %yzv32 %div = lshr <vscale x 8 x i16> %add, splat (i16 1)33 %ret = trunc <vscale x 8 x i16> %div to <vscale x 8 x i8>34 ret <vscale x 8 x i8> %ret35}36 37define <vscale x 8 x i8> @vaaddu_vv_nxv8i8_floor_sexti16(<vscale x 8 x i8> %x, <vscale x 8 x i8> %y) {38; CHECK-LABEL: vaaddu_vv_nxv8i8_floor_sexti16:39; CHECK: # %bb.0:40; CHECK-NEXT: csrwi vxrm, 241; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma42; CHECK-NEXT: vaadd.vv v8, v8, v943; CHECK-NEXT: ret44 %xzv = sext <vscale x 8 x i8> %x to <vscale x 8 x i16>45 %yzv = sext <vscale x 8 x i8> %y to <vscale x 8 x i16>46 %add = add nuw nsw <vscale x 8 x i16> %xzv, %yzv47 %div = lshr <vscale x 8 x i16> %add, splat (i16 1)48 %ret = trunc <vscale x 8 x i16> %div to <vscale x 8 x i8>49 ret <vscale x 8 x i8> %ret50}51 52define <vscale x 8 x i8> @vaaddu_vv_nxv8i8_floor_zexti32(<vscale x 8 x i8> %x, <vscale x 8 x i8> %y) {53; CHECK-LABEL: vaaddu_vv_nxv8i8_floor_zexti32:54; CHECK: # %bb.0:55; CHECK-NEXT: csrwi vxrm, 256; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma57; CHECK-NEXT: vaaddu.vv v8, v8, v958; CHECK-NEXT: ret59 %xzv = zext <vscale x 8 x i8> %x to <vscale x 8 x i32>60 %yzv = zext <vscale x 8 x i8> %y to <vscale x 8 x i32>61 %add = add nuw nsw <vscale x 8 x i32> %xzv, %yzv62 %div = lshr <vscale x 8 x i32> %add, splat (i32 1)63 %ret = trunc <vscale x 8 x i32> %div to <vscale x 8 x i8>64 ret <vscale x 8 x i8> %ret65}66 67define <vscale x 8 x i8> @vaaddu_vv_nxv8i8_floor_lshr2(<vscale x 8 x i8> %x, <vscale x 8 x i8> %y) {68; CHECK-LABEL: vaaddu_vv_nxv8i8_floor_lshr2:69; CHECK: # %bb.0:70; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma71; CHECK-NEXT: vwaddu.vv v10, v8, v972; CHECK-NEXT: vnsrl.wi v8, v10, 273; CHECK-NEXT: ret74 %xzv = zext <vscale x 8 x i8> %x to <vscale x 8 x i16>75 %yzv = zext <vscale x 8 x i8> %y to <vscale x 8 x i16>76 %add = add nuw nsw <vscale x 8 x i16> %xzv, %yzv77 %div = lshr <vscale x 8 x i16> %add, splat (i16 2)78 %ret = trunc <vscale x 8 x i16> %div to <vscale x 8 x i8>79 ret <vscale x 8 x i8> %ret80}81 82define <vscale x 8 x i16> @vaaddu_vv_nxv8i16_floor(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y) {83; CHECK-LABEL: vaaddu_vv_nxv8i16_floor:84; CHECK: # %bb.0:85; CHECK-NEXT: csrwi vxrm, 286; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma87; CHECK-NEXT: vaaddu.vv v8, v8, v1088; CHECK-NEXT: ret89 %xzv = zext <vscale x 8 x i16> %x to <vscale x 8 x i32>90 %yzv = zext <vscale x 8 x i16> %y to <vscale x 8 x i32>91 %add = add nuw nsw <vscale x 8 x i32> %xzv, %yzv92 %div = lshr <vscale x 8 x i32> %add, splat (i32 1)93 %ret = trunc <vscale x 8 x i32> %div to <vscale x 8 x i16>94 ret <vscale x 8 x i16> %ret95}96 97define <vscale x 8 x i16> @vaaddu_vx_nxv8i16_floor(<vscale x 8 x i16> %x, i16 %y) {98; CHECK-LABEL: vaaddu_vx_nxv8i16_floor:99; CHECK: # %bb.0:100; CHECK-NEXT: csrwi vxrm, 2101; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma102; CHECK-NEXT: vaaddu.vx v8, v8, a0103; CHECK-NEXT: ret104 %xzv = zext <vscale x 8 x i16> %x to <vscale x 8 x i32>105 %yhead = insertelement <vscale x 8 x i16> poison, i16 %y, i16 0106 %ysplat = shufflevector <vscale x 8 x i16> %yhead, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer107 %yzv = zext <vscale x 8 x i16> %ysplat to <vscale x 8 x i32>108 %add = add nuw nsw <vscale x 8 x i32> %xzv, %yzv109 %div = lshr <vscale x 8 x i32> %add, splat (i32 1)110 %ret = trunc <vscale x 8 x i32> %div to <vscale x 8 x i16>111 ret <vscale x 8 x i16> %ret112}113 114define <vscale x 8 x i32> @vaaddu_vv_nxv8i32_floor(<vscale x 8 x i32> %x, <vscale x 8 x i32> %y) {115; CHECK-LABEL: vaaddu_vv_nxv8i32_floor:116; CHECK: # %bb.0:117; CHECK-NEXT: csrwi vxrm, 2118; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma119; CHECK-NEXT: vaaddu.vv v8, v8, v12120; CHECK-NEXT: ret121 %xzv = zext <vscale x 8 x i32> %x to <vscale x 8 x i64>122 %yzv = zext <vscale x 8 x i32> %y to <vscale x 8 x i64>123 %add = add nuw nsw <vscale x 8 x i64> %xzv, %yzv124 %div = lshr <vscale x 8 x i64> %add, splat (i64 1)125 %ret = trunc <vscale x 8 x i64> %div to <vscale x 8 x i32>126 ret <vscale x 8 x i32> %ret127}128 129define <vscale x 8 x i32> @vaaddu_vx_nxv8i32_floor(<vscale x 8 x i32> %x, i32 %y) {130; CHECK-LABEL: vaaddu_vx_nxv8i32_floor:131; CHECK: # %bb.0:132; CHECK-NEXT: csrwi vxrm, 2133; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma134; CHECK-NEXT: vaaddu.vx v8, v8, a0135; CHECK-NEXT: ret136 %xzv = zext <vscale x 8 x i32> %x to <vscale x 8 x i64>137 %yhead = insertelement <vscale x 8 x i32> poison, i32 %y, i32 0138 %ysplat = shufflevector <vscale x 8 x i32> %yhead, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer139 %yzv = zext <vscale x 8 x i32> %ysplat to <vscale x 8 x i64>140 %add = add nuw nsw <vscale x 8 x i64> %xzv, %yzv141 %div = lshr <vscale x 8 x i64> %add, splat (i64 1)142 %ret = trunc <vscale x 8 x i64> %div to <vscale x 8 x i32>143 ret <vscale x 8 x i32> %ret144}145 146define <vscale x 8 x i64> @vaaddu_vv_nxv8i64_floor(<vscale x 8 x i64> %x, <vscale x 8 x i64> %y) {147; CHECK-LABEL: vaaddu_vv_nxv8i64_floor:148; CHECK: # %bb.0:149; CHECK-NEXT: csrwi vxrm, 2150; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma151; CHECK-NEXT: vaaddu.vv v8, v8, v16152; CHECK-NEXT: ret153 %xzv = zext <vscale x 8 x i64> %x to <vscale x 8 x i128>154 %yzv = zext <vscale x 8 x i64> %y to <vscale x 8 x i128>155 %add = add nuw nsw <vscale x 8 x i128> %xzv, %yzv156 %div = lshr <vscale x 8 x i128> %add, splat (i128 1)157 %ret = trunc <vscale x 8 x i128> %div to <vscale x 8 x i64>158 ret <vscale x 8 x i64> %ret159}160 161define <vscale x 8 x i64> @vaaddu_vx_nxv8i64_floor(<vscale x 8 x i64> %x, i64 %y) {162; RV32-LABEL: vaaddu_vx_nxv8i64_floor:163; RV32: # %bb.0:164; RV32-NEXT: addi sp, sp, -16165; RV32-NEXT: .cfi_def_cfa_offset 16166; RV32-NEXT: sw a0, 8(sp)167; RV32-NEXT: sw a1, 12(sp)168; RV32-NEXT: addi a0, sp, 8169; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma170; RV32-NEXT: vlse64.v v16, (a0), zero171; RV32-NEXT: csrwi vxrm, 2172; RV32-NEXT: vaaddu.vv v8, v8, v16173; RV32-NEXT: addi sp, sp, 16174; RV32-NEXT: .cfi_def_cfa_offset 0175; RV32-NEXT: ret176;177; RV64-LABEL: vaaddu_vx_nxv8i64_floor:178; RV64: # %bb.0:179; RV64-NEXT: csrwi vxrm, 2180; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma181; RV64-NEXT: vaaddu.vx v8, v8, a0182; RV64-NEXT: ret183 %xzv = zext <vscale x 8 x i64> %x to <vscale x 8 x i128>184 %yhead = insertelement <vscale x 8 x i64> poison, i64 %y, i64 0185 %ysplat = shufflevector <vscale x 8 x i64> %yhead, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer186 %yzv = zext <vscale x 8 x i64> %ysplat to <vscale x 8 x i128>187 %add = add nuw nsw <vscale x 8 x i128> %xzv, %yzv188 %div = lshr <vscale x 8 x i128> %add, splat (i128 1)189 %ret = trunc <vscale x 8 x i128> %div to <vscale x 8 x i64>190 ret <vscale x 8 x i64> %ret191}192 193define <vscale x 8 x i8> @vaaddu_vv_nxv8i8_ceil(<vscale x 8 x i8> %x, <vscale x 8 x i8> %y) {194; CHECK-LABEL: vaaddu_vv_nxv8i8_ceil:195; CHECK: # %bb.0:196; CHECK-NEXT: csrwi vxrm, 0197; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma198; CHECK-NEXT: vaaddu.vv v8, v8, v9199; CHECK-NEXT: ret200 %xzv = zext <vscale x 8 x i8> %x to <vscale x 8 x i16>201 %yzv = zext <vscale x 8 x i8> %y to <vscale x 8 x i16>202 %add = add nuw nsw <vscale x 8 x i16> %xzv, %yzv203 %add1 = add nuw nsw <vscale x 8 x i16> %add, splat (i16 1)204 %div = lshr <vscale x 8 x i16> %add1, splat (i16 1)205 %ret = trunc <vscale x 8 x i16> %div to <vscale x 8 x i8>206 ret <vscale x 8 x i8> %ret207}208 209define <vscale x 8 x i8> @vaaddu_vx_nxv8i8_ceil(<vscale x 8 x i8> %x, i8 %y) {210; CHECK-LABEL: vaaddu_vx_nxv8i8_ceil:211; CHECK: # %bb.0:212; CHECK-NEXT: csrwi vxrm, 0213; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma214; CHECK-NEXT: vaaddu.vx v8, v8, a0215; CHECK-NEXT: ret216 %xzv = zext <vscale x 8 x i8> %x to <vscale x 8 x i16>217 %yhead = insertelement <vscale x 8 x i8> poison, i8 %y, i32 0218 %ysplat = shufflevector <vscale x 8 x i8> %yhead, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer219 %yzv = zext <vscale x 8 x i8> %ysplat to <vscale x 8 x i16>220 %add = add nuw nsw <vscale x 8 x i16> %xzv, %yzv221 %add1 = add nuw nsw <vscale x 8 x i16> %add, splat (i16 1)222 %div = lshr <vscale x 8 x i16> %add1, splat (i16 1)223 %ret = trunc <vscale x 8 x i16> %div to <vscale x 8 x i8>224 ret <vscale x 8 x i8> %ret225}226 227define <vscale x 8 x i8> @vaaddu_vv_nxv8i8_ceil_sexti16(<vscale x 8 x i8> %x, <vscale x 8 x i8> %y) {228; CHECK-LABEL: vaaddu_vv_nxv8i8_ceil_sexti16:229; CHECK: # %bb.0:230; CHECK-NEXT: csrwi vxrm, 0231; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma232; CHECK-NEXT: vaadd.vv v8, v8, v9233; CHECK-NEXT: ret234 %xzv = sext <vscale x 8 x i8> %x to <vscale x 8 x i16>235 %yzv = sext <vscale x 8 x i8> %y to <vscale x 8 x i16>236 %add = add nuw nsw <vscale x 8 x i16> %xzv, %yzv237 %add1 = add nuw nsw <vscale x 8 x i16> %add, splat (i16 1)238 %div = lshr <vscale x 8 x i16> %add1, splat (i16 1)239 %ret = trunc <vscale x 8 x i16> %div to <vscale x 8 x i8>240 ret <vscale x 8 x i8> %ret241}242 243define <vscale x 8 x i8> @vaaddu_vv_nxv8i8_ceil_zexti32(<vscale x 8 x i8> %x, <vscale x 8 x i8> %y) {244; CHECK-LABEL: vaaddu_vv_nxv8i8_ceil_zexti32:245; CHECK: # %bb.0:246; CHECK-NEXT: csrwi vxrm, 0247; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma248; CHECK-NEXT: vaaddu.vv v8, v8, v9249; CHECK-NEXT: ret250 %xzv = zext <vscale x 8 x i8> %x to <vscale x 8 x i32>251 %yzv = zext <vscale x 8 x i8> %y to <vscale x 8 x i32>252 %add = add nuw nsw <vscale x 8 x i32> %xzv, %yzv253 %add1 = add nuw nsw <vscale x 8 x i32> %add, splat (i32 1)254 %div = lshr <vscale x 8 x i32> %add1, splat (i32 1)255 %ret = trunc <vscale x 8 x i32> %div to <vscale x 8 x i8>256 ret <vscale x 8 x i8> %ret257}258 259define <vscale x 8 x i8> @vaaddu_vv_nxv8i8_ceil_lshr2(<vscale x 8 x i8> %x, <vscale x 8 x i8> %y) {260; CHECK-LABEL: vaaddu_vv_nxv8i8_ceil_lshr2:261; CHECK: # %bb.0:262; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma263; CHECK-NEXT: vwaddu.vv v10, v8, v9264; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma265; CHECK-NEXT: vadd.vi v10, v10, 2266; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma267; CHECK-NEXT: vnsrl.wi v8, v10, 2268; CHECK-NEXT: ret269 %xzv = zext <vscale x 8 x i8> %x to <vscale x 8 x i16>270 %yzv = zext <vscale x 8 x i8> %y to <vscale x 8 x i16>271 %add = add nuw nsw <vscale x 8 x i16> %xzv, %yzv272 %add1 = add nuw nsw <vscale x 8 x i16> %add, splat (i16 2)273 %div = lshr <vscale x 8 x i16> %add1, splat (i16 2)274 %ret = trunc <vscale x 8 x i16> %div to <vscale x 8 x i8>275 ret <vscale x 8 x i8> %ret276}277 278define <vscale x 8 x i8> @vaaddu_vv_nxv8i8_ceil_add2(<vscale x 8 x i8> %x, <vscale x 8 x i8> %y) {279; CHECK-LABEL: vaaddu_vv_nxv8i8_ceil_add2:280; CHECK: # %bb.0:281; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma282; CHECK-NEXT: vwaddu.vv v10, v8, v9283; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma284; CHECK-NEXT: vadd.vi v10, v10, 2285; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma286; CHECK-NEXT: vnsrl.wi v8, v10, 2287; CHECK-NEXT: ret288 %xzv = zext <vscale x 8 x i8> %x to <vscale x 8 x i16>289 %yzv = zext <vscale x 8 x i8> %y to <vscale x 8 x i16>290 %add = add nuw nsw <vscale x 8 x i16> %xzv, %yzv291 %add2 = add nuw nsw <vscale x 8 x i16> %add, splat (i16 2)292 %div = lshr <vscale x 8 x i16> %add2, splat (i16 2)293 %ret = trunc <vscale x 8 x i16> %div to <vscale x 8 x i8>294 ret <vscale x 8 x i8> %ret295}296 297define <vscale x 8 x i16> @vaaddu_vv_nxv8i16_ceil(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y) {298; CHECK-LABEL: vaaddu_vv_nxv8i16_ceil:299; CHECK: # %bb.0:300; CHECK-NEXT: csrwi vxrm, 0301; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma302; CHECK-NEXT: vaaddu.vv v8, v8, v10303; CHECK-NEXT: ret304 %xzv = zext <vscale x 8 x i16> %x to <vscale x 8 x i32>305 %yzv = zext <vscale x 8 x i16> %y to <vscale x 8 x i32>306 %add = add nuw nsw <vscale x 8 x i32> %xzv, %yzv307 %add1 = add nuw nsw <vscale x 8 x i32> %add, splat (i32 1)308 %div = lshr <vscale x 8 x i32> %add1, splat (i32 1)309 %ret = trunc <vscale x 8 x i32> %div to <vscale x 8 x i16>310 ret <vscale x 8 x i16> %ret311}312 313define <vscale x 8 x i16> @vaaddu_vx_nxv8i16_ceil(<vscale x 8 x i16> %x, i16 %y) {314; CHECK-LABEL: vaaddu_vx_nxv8i16_ceil:315; CHECK: # %bb.0:316; CHECK-NEXT: csrwi vxrm, 0317; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma318; CHECK-NEXT: vaaddu.vx v8, v8, a0319; CHECK-NEXT: ret320 %xzv = zext <vscale x 8 x i16> %x to <vscale x 8 x i32>321 %yhead = insertelement <vscale x 8 x i16> poison, i16 %y, i16 0322 %ysplat = shufflevector <vscale x 8 x i16> %yhead, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer323 %yzv = zext <vscale x 8 x i16> %ysplat to <vscale x 8 x i32>324 %add = add nuw nsw <vscale x 8 x i32> %xzv, %yzv325 %add1 = add nuw nsw <vscale x 8 x i32> %add, splat (i32 1)326 %div = lshr <vscale x 8 x i32> %add1, splat (i32 1)327 %ret = trunc <vscale x 8 x i32> %div to <vscale x 8 x i16>328 ret <vscale x 8 x i16> %ret329}330 331define <vscale x 8 x i32> @vaaddu_vv_nxv8i32_ceil(<vscale x 8 x i32> %x, <vscale x 8 x i32> %y) {332; CHECK-LABEL: vaaddu_vv_nxv8i32_ceil:333; CHECK: # %bb.0:334; CHECK-NEXT: csrwi vxrm, 0335; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma336; CHECK-NEXT: vaaddu.vv v8, v8, v12337; CHECK-NEXT: ret338 %xzv = zext <vscale x 8 x i32> %x to <vscale x 8 x i64>339 %yzv = zext <vscale x 8 x i32> %y to <vscale x 8 x i64>340 %add = add nuw nsw <vscale x 8 x i64> %xzv, %yzv341 %add1 = add nuw nsw <vscale x 8 x i64> %add, splat (i64 1)342 %div = lshr <vscale x 8 x i64> %add1, splat (i64 1)343 %ret = trunc <vscale x 8 x i64> %div to <vscale x 8 x i32>344 ret <vscale x 8 x i32> %ret345}346 347define <vscale x 8 x i32> @vaaddu_vx_nxv8i32_ceil(<vscale x 8 x i32> %x, i32 %y) {348; CHECK-LABEL: vaaddu_vx_nxv8i32_ceil:349; CHECK: # %bb.0:350; CHECK-NEXT: csrwi vxrm, 0351; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma352; CHECK-NEXT: vaaddu.vx v8, v8, a0353; CHECK-NEXT: ret354 %xzv = zext <vscale x 8 x i32> %x to <vscale x 8 x i64>355 %yhead = insertelement <vscale x 8 x i32> poison, i32 %y, i32 0356 %ysplat = shufflevector <vscale x 8 x i32> %yhead, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer357 %yzv = zext <vscale x 8 x i32> %ysplat to <vscale x 8 x i64>358 %add = add nuw nsw <vscale x 8 x i64> %xzv, %yzv359 %add1 = add nuw nsw <vscale x 8 x i64> %add, splat (i64 1)360 %div = lshr <vscale x 8 x i64> %add1, splat (i64 1)361 %ret = trunc <vscale x 8 x i64> %div to <vscale x 8 x i32>362 ret <vscale x 8 x i32> %ret363}364 365define <vscale x 8 x i64> @vaaddu_vv_nxv8i64_ceil(<vscale x 8 x i64> %x, <vscale x 8 x i64> %y) {366; CHECK-LABEL: vaaddu_vv_nxv8i64_ceil:367; CHECK: # %bb.0:368; CHECK-NEXT: csrwi vxrm, 0369; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma370; CHECK-NEXT: vaaddu.vv v8, v8, v16371; CHECK-NEXT: ret372 %xzv = zext <vscale x 8 x i64> %x to <vscale x 8 x i128>373 %yzv = zext <vscale x 8 x i64> %y to <vscale x 8 x i128>374 %add = add nuw nsw <vscale x 8 x i128> %xzv, %yzv375 %add1 = add nuw nsw <vscale x 8 x i128> %add, splat (i128 1)376 %div = lshr <vscale x 8 x i128> %add1, splat (i128 1)377 %ret = trunc <vscale x 8 x i128> %div to <vscale x 8 x i64>378 ret <vscale x 8 x i64> %ret379}380 381define <vscale x 8 x i64> @vaaddu_vx_nxv8i64_ceil(<vscale x 8 x i64> %x, i64 %y) {382; RV32-LABEL: vaaddu_vx_nxv8i64_ceil:383; RV32: # %bb.0:384; RV32-NEXT: addi sp, sp, -16385; RV32-NEXT: .cfi_def_cfa_offset 16386; RV32-NEXT: sw a0, 8(sp)387; RV32-NEXT: sw a1, 12(sp)388; RV32-NEXT: addi a0, sp, 8389; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma390; RV32-NEXT: vlse64.v v16, (a0), zero391; RV32-NEXT: csrwi vxrm, 0392; RV32-NEXT: vaaddu.vv v8, v8, v16393; RV32-NEXT: addi sp, sp, 16394; RV32-NEXT: .cfi_def_cfa_offset 0395; RV32-NEXT: ret396;397; RV64-LABEL: vaaddu_vx_nxv8i64_ceil:398; RV64: # %bb.0:399; RV64-NEXT: csrwi vxrm, 0400; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma401; RV64-NEXT: vaaddu.vx v8, v8, a0402; RV64-NEXT: ret403 %xzv = zext <vscale x 8 x i64> %x to <vscale x 8 x i128>404 %yhead = insertelement <vscale x 8 x i64> poison, i64 %y, i64 0405 %ysplat = shufflevector <vscale x 8 x i64> %yhead, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer406 %yzv = zext <vscale x 8 x i64> %ysplat to <vscale x 8 x i128>407 %add = add nuw nsw <vscale x 8 x i128> %xzv, %yzv408 %add1 = add nuw nsw <vscale x 8 x i128> %add, splat (i128 1)409 %div = lshr <vscale x 8 x i128> %add1, splat (i128 1)410 %ret = trunc <vscale x 8 x i128> %div to <vscale x 8 x i64>411 ret <vscale x 8 x i64> %ret412}413