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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV323; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV644 5define <vscale x 1 x i8> @vadd_vx_nxv1i8(<vscale x 1 x i8> %va, i8 signext %b) {6; CHECK-LABEL: vadd_vx_nxv1i8:7; CHECK: # %bb.0:8; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma9; CHECK-NEXT: vadd.vx v8, v8, a010; CHECK-NEXT: ret11 %head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 012 %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer13 %vc = add <vscale x 1 x i8> %va, %splat14 ret <vscale x 1 x i8> %vc15}16 17define <vscale x 1 x i8> @vadd_vx_nxv1i8_0(<vscale x 1 x i8> %va) {18; CHECK-LABEL: vadd_vx_nxv1i8_0:19; CHECK: # %bb.0:20; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma21; CHECK-NEXT: vadd.vi v8, v8, -122; CHECK-NEXT: ret23 %vc = add <vscale x 1 x i8> %va, splat (i8 -1)24 ret <vscale x 1 x i8> %vc25}26 27define <vscale x 1 x i8> @vadd_vx_nxv1i8_1(<vscale x 1 x i8> %va) {28; CHECK-LABEL: vadd_vx_nxv1i8_1:29; CHECK: # %bb.0:30; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma31; CHECK-NEXT: vadd.vi v8, v8, 232; CHECK-NEXT: ret33 %vc = add <vscale x 1 x i8> %va, splat (i8 2)34 ret <vscale x 1 x i8> %vc35}36 37; Test constant adds to see if we can optimize them away for scalable vectors.38define <vscale x 1 x i8> @vadd_ii_nxv1i8_1() {39; CHECK-LABEL: vadd_ii_nxv1i8_1:40; CHECK: # %bb.0:41; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma42; CHECK-NEXT: vmv.v.i v8, 543; CHECK-NEXT: ret44 %vc = add <vscale x 1 x i8> splat (i8 2), splat (i8 3)45 ret <vscale x 1 x i8> %vc46}47 48define <vscale x 2 x i8> @vadd_vx_nxv2i8(<vscale x 2 x i8> %va, i8 signext %b) {49; CHECK-LABEL: vadd_vx_nxv2i8:50; CHECK: # %bb.0:51; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma52; CHECK-NEXT: vadd.vx v8, v8, a053; CHECK-NEXT: ret54 %head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 055 %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer56 %vc = add <vscale x 2 x i8> %va, %splat57 ret <vscale x 2 x i8> %vc58}59 60define <vscale x 2 x i8> @vadd_vx_nxv2i8_0(<vscale x 2 x i8> %va) {61; CHECK-LABEL: vadd_vx_nxv2i8_0:62; CHECK: # %bb.0:63; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma64; CHECK-NEXT: vadd.vi v8, v8, -165; CHECK-NEXT: ret66 %vc = add <vscale x 2 x i8> %va, splat (i8 -1)67 ret <vscale x 2 x i8> %vc68}69 70define <vscale x 2 x i8> @vadd_vx_nxv2i8_1(<vscale x 2 x i8> %va) {71; CHECK-LABEL: vadd_vx_nxv2i8_1:72; CHECK: # %bb.0:73; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma74; CHECK-NEXT: vadd.vi v8, v8, 275; CHECK-NEXT: ret76 %vc = add <vscale x 2 x i8> %va, splat (i8 2)77 ret <vscale x 2 x i8> %vc78}79 80define <vscale x 4 x i8> @vadd_vx_nxv4i8(<vscale x 4 x i8> %va, i8 signext %b) {81; CHECK-LABEL: vadd_vx_nxv4i8:82; CHECK: # %bb.0:83; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma84; CHECK-NEXT: vadd.vx v8, v8, a085; CHECK-NEXT: ret86 %head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 087 %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer88 %vc = add <vscale x 4 x i8> %va, %splat89 ret <vscale x 4 x i8> %vc90}91 92define <vscale x 4 x i8> @vadd_vx_nxv4i8_0(<vscale x 4 x i8> %va) {93; CHECK-LABEL: vadd_vx_nxv4i8_0:94; CHECK: # %bb.0:95; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma96; CHECK-NEXT: vadd.vi v8, v8, -197; CHECK-NEXT: ret98 %vc = add <vscale x 4 x i8> %va, splat (i8 -1)99 ret <vscale x 4 x i8> %vc100}101 102define <vscale x 4 x i8> @vadd_vx_nxv4i8_1(<vscale x 4 x i8> %va) {103; CHECK-LABEL: vadd_vx_nxv4i8_1:104; CHECK: # %bb.0:105; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma106; CHECK-NEXT: vadd.vi v8, v8, 2107; CHECK-NEXT: ret108 %vc = add <vscale x 4 x i8> %va, splat (i8 2)109 ret <vscale x 4 x i8> %vc110}111 112define <vscale x 8 x i8> @vadd_vx_nxv8i8(<vscale x 8 x i8> %va, i8 signext %b) {113; CHECK-LABEL: vadd_vx_nxv8i8:114; CHECK: # %bb.0:115; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma116; CHECK-NEXT: vadd.vx v8, v8, a0117; CHECK-NEXT: ret118 %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0119 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer120 %vc = add <vscale x 8 x i8> %va, %splat121 ret <vscale x 8 x i8> %vc122}123 124define <vscale x 8 x i8> @vadd_vx_nxv8i8_0(<vscale x 8 x i8> %va) {125; CHECK-LABEL: vadd_vx_nxv8i8_0:126; CHECK: # %bb.0:127; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma128; CHECK-NEXT: vadd.vi v8, v8, -1129; CHECK-NEXT: ret130 %vc = add <vscale x 8 x i8> %va, splat (i8 -1)131 ret <vscale x 8 x i8> %vc132}133 134define <vscale x 8 x i8> @vadd_vx_nxv8i8_1(<vscale x 8 x i8> %va) {135; CHECK-LABEL: vadd_vx_nxv8i8_1:136; CHECK: # %bb.0:137; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma138; CHECK-NEXT: vadd.vi v8, v8, 2139; CHECK-NEXT: ret140 %vc = add <vscale x 8 x i8> %va, splat (i8 2)141 ret <vscale x 8 x i8> %vc142}143 144define <vscale x 16 x i8> @vadd_vx_nxv16i8(<vscale x 16 x i8> %va, i8 signext %b) {145; CHECK-LABEL: vadd_vx_nxv16i8:146; CHECK: # %bb.0:147; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma148; CHECK-NEXT: vadd.vx v8, v8, a0149; CHECK-NEXT: ret150 %head = insertelement <vscale x 16 x i8> poison, i8 %b, i32 0151 %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer152 %vc = add <vscale x 16 x i8> %va, %splat153 ret <vscale x 16 x i8> %vc154}155 156define <vscale x 16 x i8> @vadd_vx_nxv16i8_0(<vscale x 16 x i8> %va) {157; CHECK-LABEL: vadd_vx_nxv16i8_0:158; CHECK: # %bb.0:159; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma160; CHECK-NEXT: vadd.vi v8, v8, -1161; CHECK-NEXT: ret162 %vc = add <vscale x 16 x i8> %va, splat (i8 -1)163 ret <vscale x 16 x i8> %vc164}165 166define <vscale x 16 x i8> @vadd_vx_nxv16i8_1(<vscale x 16 x i8> %va) {167; CHECK-LABEL: vadd_vx_nxv16i8_1:168; CHECK: # %bb.0:169; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma170; CHECK-NEXT: vadd.vi v8, v8, 2171; CHECK-NEXT: ret172 %vc = add <vscale x 16 x i8> %va, splat (i8 2)173 ret <vscale x 16 x i8> %vc174}175 176define <vscale x 32 x i8> @vadd_vx_nxv32i8(<vscale x 32 x i8> %va, i8 signext %b) {177; CHECK-LABEL: vadd_vx_nxv32i8:178; CHECK: # %bb.0:179; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma180; CHECK-NEXT: vadd.vx v8, v8, a0181; CHECK-NEXT: ret182 %head = insertelement <vscale x 32 x i8> poison, i8 %b, i32 0183 %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer184 %vc = add <vscale x 32 x i8> %va, %splat185 ret <vscale x 32 x i8> %vc186}187 188define <vscale x 32 x i8> @vadd_vx_nxv32i8_0(<vscale x 32 x i8> %va) {189; CHECK-LABEL: vadd_vx_nxv32i8_0:190; CHECK: # %bb.0:191; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma192; CHECK-NEXT: vadd.vi v8, v8, -1193; CHECK-NEXT: ret194 %vc = add <vscale x 32 x i8> %va, splat (i8 -1)195 ret <vscale x 32 x i8> %vc196}197 198define <vscale x 32 x i8> @vadd_vx_nxv32i8_1(<vscale x 32 x i8> %va) {199; CHECK-LABEL: vadd_vx_nxv32i8_1:200; CHECK: # %bb.0:201; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma202; CHECK-NEXT: vadd.vi v8, v8, 2203; CHECK-NEXT: ret204 %vc = add <vscale x 32 x i8> %va, splat (i8 2)205 ret <vscale x 32 x i8> %vc206}207 208define <vscale x 64 x i8> @vadd_vx_nxv64i8(<vscale x 64 x i8> %va, i8 signext %b) {209; CHECK-LABEL: vadd_vx_nxv64i8:210; CHECK: # %bb.0:211; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma212; CHECK-NEXT: vadd.vx v8, v8, a0213; CHECK-NEXT: ret214 %head = insertelement <vscale x 64 x i8> poison, i8 %b, i32 0215 %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer216 %vc = add <vscale x 64 x i8> %va, %splat217 ret <vscale x 64 x i8> %vc218}219 220define <vscale x 64 x i8> @vadd_vx_nxv64i8_0(<vscale x 64 x i8> %va) {221; CHECK-LABEL: vadd_vx_nxv64i8_0:222; CHECK: # %bb.0:223; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma224; CHECK-NEXT: vadd.vi v8, v8, -1225; CHECK-NEXT: ret226 %vc = add <vscale x 64 x i8> %va, splat (i8 -1)227 ret <vscale x 64 x i8> %vc228}229 230define <vscale x 64 x i8> @vadd_vx_nxv64i8_1(<vscale x 64 x i8> %va) {231; CHECK-LABEL: vadd_vx_nxv64i8_1:232; CHECK: # %bb.0:233; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma234; CHECK-NEXT: vadd.vi v8, v8, 2235; CHECK-NEXT: ret236 %vc = add <vscale x 64 x i8> %va, splat (i8 2)237 ret <vscale x 64 x i8> %vc238}239 240define <vscale x 1 x i16> @vadd_vx_nxv1i16(<vscale x 1 x i16> %va, i16 signext %b) {241; CHECK-LABEL: vadd_vx_nxv1i16:242; CHECK: # %bb.0:243; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma244; CHECK-NEXT: vadd.vx v8, v8, a0245; CHECK-NEXT: ret246 %head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0247 %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer248 %vc = add <vscale x 1 x i16> %va, %splat249 ret <vscale x 1 x i16> %vc250}251 252define <vscale x 1 x i16> @vadd_vx_nxv1i16_0(<vscale x 1 x i16> %va) {253; CHECK-LABEL: vadd_vx_nxv1i16_0:254; CHECK: # %bb.0:255; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma256; CHECK-NEXT: vadd.vi v8, v8, -1257; CHECK-NEXT: ret258 %vc = add <vscale x 1 x i16> %va, splat (i16 -1)259 ret <vscale x 1 x i16> %vc260}261 262define <vscale x 1 x i16> @vadd_vx_nxv1i16_1(<vscale x 1 x i16> %va) {263; CHECK-LABEL: vadd_vx_nxv1i16_1:264; CHECK: # %bb.0:265; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma266; CHECK-NEXT: vadd.vi v8, v8, 2267; CHECK-NEXT: ret268 %vc = add <vscale x 1 x i16> %va, splat (i16 2)269 ret <vscale x 1 x i16> %vc270}271 272define <vscale x 2 x i16> @vadd_vx_nxv2i16(<vscale x 2 x i16> %va, i16 signext %b) {273; CHECK-LABEL: vadd_vx_nxv2i16:274; CHECK: # %bb.0:275; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma276; CHECK-NEXT: vadd.vx v8, v8, a0277; CHECK-NEXT: ret278 %head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0279 %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer280 %vc = add <vscale x 2 x i16> %va, %splat281 ret <vscale x 2 x i16> %vc282}283 284define <vscale x 2 x i16> @vadd_vx_nxv2i16_0(<vscale x 2 x i16> %va) {285; CHECK-LABEL: vadd_vx_nxv2i16_0:286; CHECK: # %bb.0:287; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma288; CHECK-NEXT: vadd.vi v8, v8, -1289; CHECK-NEXT: ret290 %vc = add <vscale x 2 x i16> %va, splat (i16 -1)291 ret <vscale x 2 x i16> %vc292}293 294define <vscale x 2 x i16> @vadd_vx_nxv2i16_1(<vscale x 2 x i16> %va) {295; CHECK-LABEL: vadd_vx_nxv2i16_1:296; CHECK: # %bb.0:297; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma298; CHECK-NEXT: vadd.vi v8, v8, 2299; CHECK-NEXT: ret300 %vc = add <vscale x 2 x i16> %va, splat (i16 2)301 ret <vscale x 2 x i16> %vc302}303 304define <vscale x 4 x i16> @vadd_vx_nxv4i16(<vscale x 4 x i16> %va, i16 signext %b) {305; CHECK-LABEL: vadd_vx_nxv4i16:306; CHECK: # %bb.0:307; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma308; CHECK-NEXT: vadd.vx v8, v8, a0309; CHECK-NEXT: ret310 %head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0311 %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer312 %vc = add <vscale x 4 x i16> %va, %splat313 ret <vscale x 4 x i16> %vc314}315 316define <vscale x 4 x i16> @vadd_vx_nxv4i16_0(<vscale x 4 x i16> %va) {317; CHECK-LABEL: vadd_vx_nxv4i16_0:318; CHECK: # %bb.0:319; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma320; CHECK-NEXT: vadd.vi v8, v8, -1321; CHECK-NEXT: ret322 %vc = add <vscale x 4 x i16> %va, splat (i16 -1)323 ret <vscale x 4 x i16> %vc324}325 326define <vscale x 4 x i16> @vadd_vx_nxv4i16_1(<vscale x 4 x i16> %va) {327; CHECK-LABEL: vadd_vx_nxv4i16_1:328; CHECK: # %bb.0:329; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma330; CHECK-NEXT: vadd.vi v8, v8, 2331; CHECK-NEXT: ret332 %vc = add <vscale x 4 x i16> %va, splat (i16 2)333 ret <vscale x 4 x i16> %vc334}335 336define <vscale x 8 x i16> @vadd_vx_nxv8i16(<vscale x 8 x i16> %va, i16 signext %b) {337; CHECK-LABEL: vadd_vx_nxv8i16:338; CHECK: # %bb.0:339; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma340; CHECK-NEXT: vadd.vx v8, v8, a0341; CHECK-NEXT: ret342 %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0343 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer344 %vc = add <vscale x 8 x i16> %va, %splat345 ret <vscale x 8 x i16> %vc346}347 348define <vscale x 8 x i16> @vadd_vx_nxv8i16_0(<vscale x 8 x i16> %va) {349; CHECK-LABEL: vadd_vx_nxv8i16_0:350; CHECK: # %bb.0:351; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma352; CHECK-NEXT: vadd.vi v8, v8, -1353; CHECK-NEXT: ret354 %vc = add <vscale x 8 x i16> %va, splat (i16 -1)355 ret <vscale x 8 x i16> %vc356}357 358define <vscale x 8 x i16> @vadd_vx_nxv8i16_1(<vscale x 8 x i16> %va) {359; CHECK-LABEL: vadd_vx_nxv8i16_1:360; CHECK: # %bb.0:361; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma362; CHECK-NEXT: vadd.vi v8, v8, 2363; CHECK-NEXT: ret364 %vc = add <vscale x 8 x i16> %va, splat (i16 2)365 ret <vscale x 8 x i16> %vc366}367 368define <vscale x 16 x i16> @vadd_vx_nxv16i16(<vscale x 16 x i16> %va, i16 signext %b) {369; CHECK-LABEL: vadd_vx_nxv16i16:370; CHECK: # %bb.0:371; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma372; CHECK-NEXT: vadd.vx v8, v8, a0373; CHECK-NEXT: ret374 %head = insertelement <vscale x 16 x i16> poison, i16 %b, i32 0375 %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer376 %vc = add <vscale x 16 x i16> %va, %splat377 ret <vscale x 16 x i16> %vc378}379 380define <vscale x 16 x i16> @vadd_vx_nxv16i16_0(<vscale x 16 x i16> %va) {381; CHECK-LABEL: vadd_vx_nxv16i16_0:382; CHECK: # %bb.0:383; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma384; CHECK-NEXT: vadd.vi v8, v8, -1385; CHECK-NEXT: ret386 %vc = add <vscale x 16 x i16> %va, splat (i16 -1)387 ret <vscale x 16 x i16> %vc388}389 390define <vscale x 16 x i16> @vadd_vx_nxv16i16_1(<vscale x 16 x i16> %va) {391; CHECK-LABEL: vadd_vx_nxv16i16_1:392; CHECK: # %bb.0:393; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma394; CHECK-NEXT: vadd.vi v8, v8, 2395; CHECK-NEXT: ret396 %vc = add <vscale x 16 x i16> %va, splat (i16 2)397 ret <vscale x 16 x i16> %vc398}399 400define <vscale x 32 x i16> @vadd_vx_nxv32i16(<vscale x 32 x i16> %va, i16 signext %b) {401; CHECK-LABEL: vadd_vx_nxv32i16:402; CHECK: # %bb.0:403; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma404; CHECK-NEXT: vadd.vx v8, v8, a0405; CHECK-NEXT: ret406 %head = insertelement <vscale x 32 x i16> poison, i16 %b, i32 0407 %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer408 %vc = add <vscale x 32 x i16> %va, %splat409 ret <vscale x 32 x i16> %vc410}411 412define <vscale x 32 x i16> @vadd_vx_nxv32i16_0(<vscale x 32 x i16> %va) {413; CHECK-LABEL: vadd_vx_nxv32i16_0:414; CHECK: # %bb.0:415; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma416; CHECK-NEXT: vadd.vi v8, v8, -1417; CHECK-NEXT: ret418 %vc = add <vscale x 32 x i16> %va, splat (i16 -1)419 ret <vscale x 32 x i16> %vc420}421 422define <vscale x 32 x i16> @vadd_vx_nxv32i16_1(<vscale x 32 x i16> %va) {423; CHECK-LABEL: vadd_vx_nxv32i16_1:424; CHECK: # %bb.0:425; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma426; CHECK-NEXT: vadd.vi v8, v8, 2427; CHECK-NEXT: ret428 %vc = add <vscale x 32 x i16> %va, splat (i16 2)429 ret <vscale x 32 x i16> %vc430}431 432define <vscale x 1 x i32> @vadd_vx_nxv1i32(<vscale x 1 x i32> %va, i32 signext %b) {433; CHECK-LABEL: vadd_vx_nxv1i32:434; CHECK: # %bb.0:435; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma436; CHECK-NEXT: vadd.vx v8, v8, a0437; CHECK-NEXT: ret438 %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0439 %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer440 %vc = add <vscale x 1 x i32> %va, %splat441 ret <vscale x 1 x i32> %vc442}443 444define <vscale x 1 x i32> @vadd_vx_nxv1i32_0(<vscale x 1 x i32> %va) {445; CHECK-LABEL: vadd_vx_nxv1i32_0:446; CHECK: # %bb.0:447; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma448; CHECK-NEXT: vadd.vi v8, v8, -1449; CHECK-NEXT: ret450 %vc = add <vscale x 1 x i32> %va, splat (i32 -1)451 ret <vscale x 1 x i32> %vc452}453 454define <vscale x 1 x i32> @vadd_vx_nxv1i32_1(<vscale x 1 x i32> %va) {455; CHECK-LABEL: vadd_vx_nxv1i32_1:456; CHECK: # %bb.0:457; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma458; CHECK-NEXT: vadd.vi v8, v8, 2459; CHECK-NEXT: ret460 %vc = add <vscale x 1 x i32> %va, splat (i32 2)461 ret <vscale x 1 x i32> %vc462}463 464define <vscale x 2 x i32> @vadd_vx_nxv2i32(<vscale x 2 x i32> %va, i32 signext %b) {465; CHECK-LABEL: vadd_vx_nxv2i32:466; CHECK: # %bb.0:467; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma468; CHECK-NEXT: vadd.vx v8, v8, a0469; CHECK-NEXT: ret470 %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0471 %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer472 %vc = add <vscale x 2 x i32> %va, %splat473 ret <vscale x 2 x i32> %vc474}475 476define <vscale x 2 x i32> @vadd_vx_nxv2i32_0(<vscale x 2 x i32> %va) {477; CHECK-LABEL: vadd_vx_nxv2i32_0:478; CHECK: # %bb.0:479; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma480; CHECK-NEXT: vadd.vi v8, v8, -1481; CHECK-NEXT: ret482 %vc = add <vscale x 2 x i32> %va, splat (i32 -1)483 ret <vscale x 2 x i32> %vc484}485 486define <vscale x 2 x i32> @vadd_vx_nxv2i32_1(<vscale x 2 x i32> %va) {487; CHECK-LABEL: vadd_vx_nxv2i32_1:488; CHECK: # %bb.0:489; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma490; CHECK-NEXT: vadd.vi v8, v8, 2491; CHECK-NEXT: ret492 %vc = add <vscale x 2 x i32> %va, splat (i32 2)493 ret <vscale x 2 x i32> %vc494}495 496define <vscale x 4 x i32> @vadd_vx_nxv4i32(<vscale x 4 x i32> %va, i32 signext %b) {497; CHECK-LABEL: vadd_vx_nxv4i32:498; CHECK: # %bb.0:499; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma500; CHECK-NEXT: vadd.vx v8, v8, a0501; CHECK-NEXT: ret502 %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0503 %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer504 %vc = add <vscale x 4 x i32> %va, %splat505 ret <vscale x 4 x i32> %vc506}507 508define <vscale x 4 x i32> @vadd_vx_nxv4i32_0(<vscale x 4 x i32> %va) {509; CHECK-LABEL: vadd_vx_nxv4i32_0:510; CHECK: # %bb.0:511; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma512; CHECK-NEXT: vadd.vi v8, v8, -1513; CHECK-NEXT: ret514 %vc = add <vscale x 4 x i32> %va, splat (i32 -1)515 ret <vscale x 4 x i32> %vc516}517 518define <vscale x 4 x i32> @vadd_vx_nxv4i32_1(<vscale x 4 x i32> %va) {519; CHECK-LABEL: vadd_vx_nxv4i32_1:520; CHECK: # %bb.0:521; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma522; CHECK-NEXT: vadd.vi v8, v8, 2523; CHECK-NEXT: ret524 %vc = add <vscale x 4 x i32> %va, splat (i32 2)525 ret <vscale x 4 x i32> %vc526}527 528define <vscale x 8 x i32> @vadd_vx_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b) {529; CHECK-LABEL: vadd_vx_nxv8i32:530; CHECK: # %bb.0:531; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma532; CHECK-NEXT: vadd.vx v8, v8, a0533; CHECK-NEXT: ret534 %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0535 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer536 %vc = add <vscale x 8 x i32> %va, %splat537 ret <vscale x 8 x i32> %vc538}539 540define <vscale x 8 x i32> @vadd_vx_nxv8i32_0(<vscale x 8 x i32> %va) {541; CHECK-LABEL: vadd_vx_nxv8i32_0:542; CHECK: # %bb.0:543; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma544; CHECK-NEXT: vadd.vi v8, v8, -1545; CHECK-NEXT: ret546 %vc = add <vscale x 8 x i32> %va, splat (i32 -1)547 ret <vscale x 8 x i32> %vc548}549 550define <vscale x 8 x i32> @vadd_vx_nxv8i32_1(<vscale x 8 x i32> %va) {551; CHECK-LABEL: vadd_vx_nxv8i32_1:552; CHECK: # %bb.0:553; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma554; CHECK-NEXT: vadd.vi v8, v8, 2555; CHECK-NEXT: ret556 %vc = add <vscale x 8 x i32> %va, splat (i32 2)557 ret <vscale x 8 x i32> %vc558}559 560define <vscale x 16 x i32> @vadd_vx_nxv16i32(<vscale x 16 x i32> %va, i32 signext %b) {561; CHECK-LABEL: vadd_vx_nxv16i32:562; CHECK: # %bb.0:563; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma564; CHECK-NEXT: vadd.vx v8, v8, a0565; CHECK-NEXT: ret566 %head = insertelement <vscale x 16 x i32> poison, i32 %b, i32 0567 %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer568 %vc = add <vscale x 16 x i32> %va, %splat569 ret <vscale x 16 x i32> %vc570}571 572define <vscale x 16 x i32> @vadd_vx_nxv16i32_0(<vscale x 16 x i32> %va) {573; CHECK-LABEL: vadd_vx_nxv16i32_0:574; CHECK: # %bb.0:575; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma576; CHECK-NEXT: vadd.vi v8, v8, -1577; CHECK-NEXT: ret578 %vc = add <vscale x 16 x i32> %va, splat (i32 -1)579 ret <vscale x 16 x i32> %vc580}581 582define <vscale x 16 x i32> @vadd_vx_nxv16i32_1(<vscale x 16 x i32> %va) {583; CHECK-LABEL: vadd_vx_nxv16i32_1:584; CHECK: # %bb.0:585; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma586; CHECK-NEXT: vadd.vi v8, v8, 2587; CHECK-NEXT: ret588 %vc = add <vscale x 16 x i32> %va, splat (i32 2)589 ret <vscale x 16 x i32> %vc590}591 592define <vscale x 1 x i64> @vadd_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {593; RV32-LABEL: vadd_vx_nxv1i64:594; RV32: # %bb.0:595; RV32-NEXT: addi sp, sp, -16596; RV32-NEXT: .cfi_def_cfa_offset 16597; RV32-NEXT: sw a0, 8(sp)598; RV32-NEXT: sw a1, 12(sp)599; RV32-NEXT: addi a0, sp, 8600; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma601; RV32-NEXT: vlse64.v v9, (a0), zero602; RV32-NEXT: vadd.vv v8, v8, v9603; RV32-NEXT: addi sp, sp, 16604; RV32-NEXT: .cfi_def_cfa_offset 0605; RV32-NEXT: ret606;607; RV64-LABEL: vadd_vx_nxv1i64:608; RV64: # %bb.0:609; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, ma610; RV64-NEXT: vadd.vx v8, v8, a0611; RV64-NEXT: ret612 %head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0613 %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer614 %vc = add <vscale x 1 x i64> %va, %splat615 ret <vscale x 1 x i64> %vc616}617 618define <vscale x 1 x i64> @vadd_vx_nxv1i64_0(<vscale x 1 x i64> %va) {619; CHECK-LABEL: vadd_vx_nxv1i64_0:620; CHECK: # %bb.0:621; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma622; CHECK-NEXT: vadd.vi v8, v8, -1623; CHECK-NEXT: ret624 %vc = add <vscale x 1 x i64> %va, splat (i64 -1)625 ret <vscale x 1 x i64> %vc626}627 628define <vscale x 1 x i64> @vadd_vx_nxv1i64_1(<vscale x 1 x i64> %va) {629; CHECK-LABEL: vadd_vx_nxv1i64_1:630; CHECK: # %bb.0:631; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma632; CHECK-NEXT: vadd.vi v8, v8, 2633; CHECK-NEXT: ret634 %vc = add <vscale x 1 x i64> %va, splat (i64 2)635 ret <vscale x 1 x i64> %vc636}637 638define <vscale x 2 x i64> @vadd_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {639; RV32-LABEL: vadd_vx_nxv2i64:640; RV32: # %bb.0:641; RV32-NEXT: addi sp, sp, -16642; RV32-NEXT: .cfi_def_cfa_offset 16643; RV32-NEXT: sw a0, 8(sp)644; RV32-NEXT: sw a1, 12(sp)645; RV32-NEXT: addi a0, sp, 8646; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma647; RV32-NEXT: vlse64.v v10, (a0), zero648; RV32-NEXT: vadd.vv v8, v8, v10649; RV32-NEXT: addi sp, sp, 16650; RV32-NEXT: .cfi_def_cfa_offset 0651; RV32-NEXT: ret652;653; RV64-LABEL: vadd_vx_nxv2i64:654; RV64: # %bb.0:655; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, ma656; RV64-NEXT: vadd.vx v8, v8, a0657; RV64-NEXT: ret658 %head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0659 %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer660 %vc = add <vscale x 2 x i64> %va, %splat661 ret <vscale x 2 x i64> %vc662}663 664define <vscale x 2 x i64> @vadd_vx_nxv2i64_0(<vscale x 2 x i64> %va) {665; CHECK-LABEL: vadd_vx_nxv2i64_0:666; CHECK: # %bb.0:667; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma668; CHECK-NEXT: vadd.vi v8, v8, -1669; CHECK-NEXT: ret670 %vc = add <vscale x 2 x i64> %va, splat (i64 -1)671 ret <vscale x 2 x i64> %vc672}673 674define <vscale x 2 x i64> @vadd_vx_nxv2i64_1(<vscale x 2 x i64> %va) {675; CHECK-LABEL: vadd_vx_nxv2i64_1:676; CHECK: # %bb.0:677; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma678; CHECK-NEXT: vadd.vi v8, v8, 2679; CHECK-NEXT: ret680 %vc = add <vscale x 2 x i64> %va, splat (i64 2)681 ret <vscale x 2 x i64> %vc682}683 684define <vscale x 4 x i64> @vadd_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {685; RV32-LABEL: vadd_vx_nxv4i64:686; RV32: # %bb.0:687; RV32-NEXT: addi sp, sp, -16688; RV32-NEXT: .cfi_def_cfa_offset 16689; RV32-NEXT: sw a0, 8(sp)690; RV32-NEXT: sw a1, 12(sp)691; RV32-NEXT: addi a0, sp, 8692; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma693; RV32-NEXT: vlse64.v v12, (a0), zero694; RV32-NEXT: vadd.vv v8, v8, v12695; RV32-NEXT: addi sp, sp, 16696; RV32-NEXT: .cfi_def_cfa_offset 0697; RV32-NEXT: ret698;699; RV64-LABEL: vadd_vx_nxv4i64:700; RV64: # %bb.0:701; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, ma702; RV64-NEXT: vadd.vx v8, v8, a0703; RV64-NEXT: ret704 %head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0705 %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer706 %vc = add <vscale x 4 x i64> %va, %splat707 ret <vscale x 4 x i64> %vc708}709 710define <vscale x 4 x i64> @vadd_vx_nxv4i64_0(<vscale x 4 x i64> %va) {711; CHECK-LABEL: vadd_vx_nxv4i64_0:712; CHECK: # %bb.0:713; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma714; CHECK-NEXT: vadd.vi v8, v8, -1715; CHECK-NEXT: ret716 %vc = add <vscale x 4 x i64> %va, splat (i64 -1)717 ret <vscale x 4 x i64> %vc718}719 720define <vscale x 4 x i64> @vadd_vx_nxv4i64_1(<vscale x 4 x i64> %va) {721; CHECK-LABEL: vadd_vx_nxv4i64_1:722; CHECK: # %bb.0:723; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma724; CHECK-NEXT: vadd.vi v8, v8, 2725; CHECK-NEXT: ret726 %vc = add <vscale x 4 x i64> %va, splat (i64 2)727 ret <vscale x 4 x i64> %vc728}729 730define <vscale x 8 x i64> @vadd_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {731; RV32-LABEL: vadd_vx_nxv8i64:732; RV32: # %bb.0:733; RV32-NEXT: addi sp, sp, -16734; RV32-NEXT: .cfi_def_cfa_offset 16735; RV32-NEXT: sw a0, 8(sp)736; RV32-NEXT: sw a1, 12(sp)737; RV32-NEXT: addi a0, sp, 8738; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma739; RV32-NEXT: vlse64.v v16, (a0), zero740; RV32-NEXT: vadd.vv v8, v8, v16741; RV32-NEXT: addi sp, sp, 16742; RV32-NEXT: .cfi_def_cfa_offset 0743; RV32-NEXT: ret744;745; RV64-LABEL: vadd_vx_nxv8i64:746; RV64: # %bb.0:747; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma748; RV64-NEXT: vadd.vx v8, v8, a0749; RV64-NEXT: ret750 %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0751 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer752 %vc = add <vscale x 8 x i64> %va, %splat753 ret <vscale x 8 x i64> %vc754}755 756define <vscale x 8 x i64> @vadd_vx_nxv8i64_0(<vscale x 8 x i64> %va) {757; CHECK-LABEL: vadd_vx_nxv8i64_0:758; CHECK: # %bb.0:759; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma760; CHECK-NEXT: vadd.vi v8, v8, -1761; CHECK-NEXT: ret762 %vc = add <vscale x 8 x i64> %va, splat (i64 -1)763 ret <vscale x 8 x i64> %vc764}765 766define <vscale x 8 x i64> @vadd_vx_nxv8i64_1(<vscale x 8 x i64> %va) {767; CHECK-LABEL: vadd_vx_nxv8i64_1:768; CHECK: # %bb.0:769; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma770; CHECK-NEXT: vadd.vi v8, v8, 2771; CHECK-NEXT: ret772 %vc = add <vscale x 8 x i64> %va, splat (i64 2)773 ret <vscale x 8 x i64> %vc774}775 776define <vscale x 8 x i64> @vadd_xx_nxv8i64(i64 %a, i64 %b) nounwind {777; RV32-LABEL: vadd_xx_nxv8i64:778; RV32: # %bb.0:779; RV32-NEXT: addi sp, sp, -16780; RV32-NEXT: add a2, a0, a2781; RV32-NEXT: add a1, a1, a3782; RV32-NEXT: sltu a0, a2, a0783; RV32-NEXT: add a0, a1, a0784; RV32-NEXT: sw a2, 8(sp)785; RV32-NEXT: sw a0, 12(sp)786; RV32-NEXT: addi a0, sp, 8787; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma788; RV32-NEXT: vlse64.v v8, (a0), zero789; RV32-NEXT: addi sp, sp, 16790; RV32-NEXT: ret791;792; RV64-LABEL: vadd_xx_nxv8i64:793; RV64: # %bb.0:794; RV64-NEXT: add a0, a0, a1795; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma796; RV64-NEXT: vmv.v.x v8, a0797; RV64-NEXT: ret798 %head1 = insertelement <vscale x 8 x i64> poison, i64 %a, i32 0799 %splat1 = shufflevector <vscale x 8 x i64> %head1, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer800 %head2 = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0801 %splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer802 %v = add <vscale x 8 x i64> %splat1, %splat2803 ret <vscale x 8 x i64> %v804}805 806define <vscale x 8 x i32> @vadd_vv_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {807; CHECK-LABEL: vadd_vv_mask_nxv8i32:808; CHECK: # %bb.0:809; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu810; CHECK-NEXT: vadd.vv v8, v8, v12, v0.t811; CHECK-NEXT: ret812 %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> zeroinitializer813 %vc = add <vscale x 8 x i32> %va, %vs814 ret <vscale x 8 x i32> %vc815}816 817define <vscale x 8 x i32> @vadd_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {818; CHECK-LABEL: vadd_vx_mask_nxv8i32:819; CHECK: # %bb.0:820; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu821; CHECK-NEXT: vadd.vx v8, v8, a0, v0.t822; CHECK-NEXT: ret823 %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0824 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer825 %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer826 %vc = add <vscale x 8 x i32> %va, %vs827 ret <vscale x 8 x i32> %vc828}829 830define <vscale x 8 x i32> @vadd_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {831; CHECK-LABEL: vadd_vi_mask_nxv8i32:832; CHECK: # %bb.0:833; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu834; CHECK-NEXT: vadd.vi v8, v8, 7, v0.t835; CHECK-NEXT: ret836 %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> splat (i32 7), <vscale x 8 x i32> zeroinitializer837 %vc = add <vscale x 8 x i32> %va, %vs838 ret <vscale x 8 x i32> %vc839}840 841define <vscale x 8 x i32> @vadd_vv_mask_negative0_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {842; CHECK-LABEL: vadd_vv_mask_negative0_nxv8i32:843; CHECK: # %bb.0:844; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma845; CHECK-NEXT: vmv.v.i v16, 1846; CHECK-NEXT: vmerge.vvm v12, v16, v12, v0847; CHECK-NEXT: vadd.vv v8, v8, v12848; CHECK-NEXT: ret849 %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> splat (i32 1)850 %vc = add <vscale x 8 x i32> %va, %vs851 ret <vscale x 8 x i32> %vc852}853 854define <vscale x 8 x i32> @vadd_vv_mask_negative1_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {855; CHECK-LABEL: vadd_vv_mask_negative1_nxv8i32:856; CHECK: # %bb.0:857; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma858; CHECK-NEXT: vmv.v.i v16, 0859; CHECK-NEXT: vmerge.vvm v12, v16, v12, v0860; CHECK-NEXT: vadd.vv v8, v8, v12861; CHECK-NEXT: vadd.vv v8, v8, v12862; CHECK-NEXT: ret863 %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> zeroinitializer864 %vc = add <vscale x 8 x i32> %va, %vs865 %vd = add <vscale x 8 x i32> %vc, %vs866 ret <vscale x 8 x i32> %vd867}868 869define <vscale x 1 x i64> @vadd_vx_imm64_to_sub(<vscale x 1 x i64> %va) nounwind {870; RV32-LABEL: vadd_vx_imm64_to_sub:871; RV32: # %bb.0:872; RV32-NEXT: addi sp, sp, -16873; RV32-NEXT: li a0, -256874; RV32-NEXT: li a1, 1875; RV32-NEXT: sw a1, 8(sp)876; RV32-NEXT: sw a0, 12(sp)877; RV32-NEXT: addi a0, sp, 8878; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma879; RV32-NEXT: vlse64.v v9, (a0), zero880; RV32-NEXT: vadd.vv v8, v8, v9881; RV32-NEXT: addi sp, sp, 16882; RV32-NEXT: ret883;884; RV64-LABEL: vadd_vx_imm64_to_sub:885; RV64: # %bb.0:886; RV64-NEXT: li a0, -1887; RV64-NEXT: srli a0, a0, 24888; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, ma889; RV64-NEXT: vsub.vx v8, v8, a0890; RV64-NEXT: ret891 %vc = add <vscale x 1 x i64> splat (i64 -1099511627775), %va892 ret <vscale x 1 x i64> %vc893}894 895define <vscale x 1 x i64> @vadd_vx_imm64_to_sub_swapped(<vscale x 1 x i64> %va) nounwind {896; RV32-LABEL: vadd_vx_imm64_to_sub_swapped:897; RV32: # %bb.0:898; RV32-NEXT: addi sp, sp, -16899; RV32-NEXT: li a0, -256900; RV32-NEXT: li a1, 1901; RV32-NEXT: sw a1, 8(sp)902; RV32-NEXT: sw a0, 12(sp)903; RV32-NEXT: addi a0, sp, 8904; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma905; RV32-NEXT: vlse64.v v9, (a0), zero906; RV32-NEXT: vadd.vv v8, v8, v9907; RV32-NEXT: addi sp, sp, 16908; RV32-NEXT: ret909;910; RV64-LABEL: vadd_vx_imm64_to_sub_swapped:911; RV64: # %bb.0:912; RV64-NEXT: li a0, -1913; RV64-NEXT: srli a0, a0, 24914; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, ma915; RV64-NEXT: vsub.vx v8, v8, a0916; RV64-NEXT: ret917 %vc = add <vscale x 1 x i64> %va, splat (i64 -1099511627775)918 ret <vscale x 1 x i64> %vc919}920