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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s \3; RUN: | FileCheck %s --check-prefixes=CHECK4; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \5; RUN: | FileCheck %s --check-prefixes=CHECK6 7define <vscale x 2 x i1> @vadd_vv_nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {8; CHECK-LABEL: vadd_vv_nxv2i1:9; CHECK: # %bb.0:10; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma11; CHECK-NEXT: vmxor.mm v0, v0, v812; CHECK-NEXT: ret13 %v = call <vscale x 2 x i1> @llvm.vp.add.nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %b, <vscale x 2 x i1> %m, i32 %evl)14 ret <vscale x 2 x i1> %v15}16 17define <vscale x 4 x i1> @vadd_vv_nxv4i1(<vscale x 4 x i1> %va, <vscale x 4 x i1> %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {18; CHECK-LABEL: vadd_vv_nxv4i1:19; CHECK: # %bb.0:20; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma21; CHECK-NEXT: vmxor.mm v0, v0, v822; CHECK-NEXT: ret23 %v = call <vscale x 4 x i1> @llvm.vp.add.nxv4i1(<vscale x 4 x i1> %va, <vscale x 4 x i1> %b, <vscale x 4 x i1> %m, i32 %evl)24 ret <vscale x 4 x i1> %v25}26 27define <vscale x 8 x i1> @vadd_vv_nxv8i1(<vscale x 8 x i1> %va, <vscale x 8 x i1> %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {28; CHECK-LABEL: vadd_vv_nxv8i1:29; CHECK: # %bb.0:30; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma31; CHECK-NEXT: vmxor.mm v0, v0, v832; CHECK-NEXT: ret33 %v = call <vscale x 8 x i1> @llvm.vp.add.nxv8i1(<vscale x 8 x i1> %va, <vscale x 8 x i1> %b, <vscale x 8 x i1> %m, i32 %evl)34 ret <vscale x 8 x i1> %v35}36 37define <vscale x 16 x i1> @vadd_vv_nxv16i1(<vscale x 16 x i1> %va, <vscale x 16 x i1> %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {38; CHECK-LABEL: vadd_vv_nxv16i1:39; CHECK: # %bb.0:40; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma41; CHECK-NEXT: vmxor.mm v0, v0, v842; CHECK-NEXT: ret43 %v = call <vscale x 16 x i1> @llvm.vp.add.nxv16i1(<vscale x 16 x i1> %va, <vscale x 16 x i1> %b, <vscale x 16 x i1> %m, i32 %evl)44 ret <vscale x 16 x i1> %v45}46 47define <vscale x 32 x i1> @vadd_vv_nxv32i1(<vscale x 32 x i1> %va, <vscale x 32 x i1> %b, <vscale x 32 x i1> %m, i32 zeroext %evl) {48; CHECK-LABEL: vadd_vv_nxv32i1:49; CHECK: # %bb.0:50; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma51; CHECK-NEXT: vmxor.mm v0, v0, v852; CHECK-NEXT: ret53 %v = call <vscale x 32 x i1> @llvm.vp.add.nxv32i1(<vscale x 32 x i1> %va, <vscale x 32 x i1> %b, <vscale x 32 x i1> %m, i32 %evl)54 ret <vscale x 32 x i1> %v55}56