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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s \3; RUN:   | FileCheck %s --check-prefixes=CHECK,RV324; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \5; RUN:   | FileCheck %s --check-prefixes=CHECK,RV646 7define <vscale x 8 x i7> @vadd_vx_nxv8i7(<vscale x 8 x i7> %a, i7 signext %b, <vscale x 8 x i1> %mask, i32 zeroext %evl) {8; CHECK-LABEL: vadd_vx_nxv8i7:9; CHECK:       # %bb.0:10; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma11; CHECK-NEXT:    vadd.vx v8, v8, a0, v0.t12; CHECK-NEXT:    ret13  %elt.head = insertelement <vscale x 8 x i7> poison, i7 %b, i32 014  %vb = shufflevector <vscale x 8 x i7> %elt.head, <vscale x 8 x i7> poison, <vscale x 8 x i32> zeroinitializer15  %v = call <vscale x 8 x i7> @llvm.vp.add.nxv8i7(<vscale x 8 x i7> %a, <vscale x 8 x i7> %vb, <vscale x 8 x i1> %mask, i32 %evl)16  ret <vscale x 8 x i7> %v17}18 19define <vscale x 1 x i8> @vadd_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {20; CHECK-LABEL: vadd_vv_nxv1i8:21; CHECK:       # %bb.0:22; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma23; CHECK-NEXT:    vadd.vv v8, v8, v9, v0.t24; CHECK-NEXT:    ret25  %v = call <vscale x 1 x i8> @llvm.vp.add.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %b, <vscale x 1 x i1> %m, i32 %evl)26  ret <vscale x 1 x i8> %v27}28 29define <vscale x 1 x i8> @vadd_vv_nxv1i8_unmasked(<vscale x 1 x i8> %va, <vscale x 1 x i8> %b, i32 zeroext %evl) {30; CHECK-LABEL: vadd_vv_nxv1i8_unmasked:31; CHECK:       # %bb.0:32; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma33; CHECK-NEXT:    vadd.vv v8, v8, v934; CHECK-NEXT:    ret35  %v = call <vscale x 1 x i8> @llvm.vp.add.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %b, <vscale x 1 x i1> splat (i1 true), i32 %evl)36  ret <vscale x 1 x i8> %v37}38 39define <vscale x 1 x i8> @vadd_vx_nxv1i8(<vscale x 1 x i8> %va, i8 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {40; CHECK-LABEL: vadd_vx_nxv1i8:41; CHECK:       # %bb.0:42; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma43; CHECK-NEXT:    vadd.vx v8, v8, a0, v0.t44; CHECK-NEXT:    ret45  %elt.head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 046  %vb = shufflevector <vscale x 1 x i8> %elt.head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer47  %v = call <vscale x 1 x i8> @llvm.vp.add.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb, <vscale x 1 x i1> %m, i32 %evl)48  ret <vscale x 1 x i8> %v49}50 51define <vscale x 1 x i8> @vadd_vx_nxv1i8_commute(<vscale x 1 x i8> %va, i8 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {52; CHECK-LABEL: vadd_vx_nxv1i8_commute:53; CHECK:       # %bb.0:54; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma55; CHECK-NEXT:    vadd.vx v8, v8, a0, v0.t56; CHECK-NEXT:    ret57  %elt.head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 058  %vb = shufflevector <vscale x 1 x i8> %elt.head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer59  %v = call <vscale x 1 x i8> @llvm.vp.add.nxv1i8(<vscale x 1 x i8> %vb, <vscale x 1 x i8> %va, <vscale x 1 x i1> %m, i32 %evl)60  ret <vscale x 1 x i8> %v61}62 63define <vscale x 1 x i8> @vadd_vx_nxv1i8_unmasked(<vscale x 1 x i8> %va, i8 %b, i32 zeroext %evl) {64; CHECK-LABEL: vadd_vx_nxv1i8_unmasked:65; CHECK:       # %bb.0:66; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma67; CHECK-NEXT:    vadd.vx v8, v8, a068; CHECK-NEXT:    ret69  %elt.head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 070  %vb = shufflevector <vscale x 1 x i8> %elt.head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer71  %v = call <vscale x 1 x i8> @llvm.vp.add.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb, <vscale x 1 x i1> splat (i1 true), i32 %evl)72  ret <vscale x 1 x i8> %v73}74 75define <vscale x 1 x i8> @vadd_vi_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {76; CHECK-LABEL: vadd_vi_nxv1i8:77; CHECK:       # %bb.0:78; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma79; CHECK-NEXT:    vadd.vi v8, v8, -1, v0.t80; CHECK-NEXT:    ret81  %v = call <vscale x 1 x i8> @llvm.vp.add.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> splat (i8 -1), <vscale x 1 x i1> %m, i32 %evl)82  ret <vscale x 1 x i8> %v83}84 85define <vscale x 1 x i8> @vadd_vi_nxv1i8_unmasked(<vscale x 1 x i8> %va, i32 zeroext %evl) {86; CHECK-LABEL: vadd_vi_nxv1i8_unmasked:87; CHECK:       # %bb.0:88; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma89; CHECK-NEXT:    vadd.vi v8, v8, -190; CHECK-NEXT:    ret91  %v = call <vscale x 1 x i8> @llvm.vp.add.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> splat (i8 -1), <vscale x 1 x i1> splat (i1 true), i32 %evl)92  ret <vscale x 1 x i8> %v93}94 95define <vscale x 2 x i8> @vadd_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {96; CHECK-LABEL: vadd_vv_nxv2i8:97; CHECK:       # %bb.0:98; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma99; CHECK-NEXT:    vadd.vv v8, v8, v9, v0.t100; CHECK-NEXT:    ret101  %v = call <vscale x 2 x i8> @llvm.vp.add.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %b, <vscale x 2 x i1> %m, i32 %evl)102  ret <vscale x 2 x i8> %v103}104 105define <vscale x 2 x i8> @vadd_vv_nxv2i8_unmasked(<vscale x 2 x i8> %va, <vscale x 2 x i8> %b, i32 zeroext %evl) {106; CHECK-LABEL: vadd_vv_nxv2i8_unmasked:107; CHECK:       # %bb.0:108; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma109; CHECK-NEXT:    vadd.vv v8, v8, v9110; CHECK-NEXT:    ret111  %v = call <vscale x 2 x i8> @llvm.vp.add.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %b, <vscale x 2 x i1> splat (i1 true), i32 %evl)112  ret <vscale x 2 x i8> %v113}114 115define <vscale x 2 x i8> @vadd_vx_nxv2i8(<vscale x 2 x i8> %va, i8 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {116; CHECK-LABEL: vadd_vx_nxv2i8:117; CHECK:       # %bb.0:118; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma119; CHECK-NEXT:    vadd.vx v8, v8, a0, v0.t120; CHECK-NEXT:    ret121  %elt.head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0122  %vb = shufflevector <vscale x 2 x i8> %elt.head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer123  %v = call <vscale x 2 x i8> @llvm.vp.add.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb, <vscale x 2 x i1> %m, i32 %evl)124  ret <vscale x 2 x i8> %v125}126 127define <vscale x 2 x i8> @vadd_vx_nxv2i8_unmasked(<vscale x 2 x i8> %va, i8 %b, i32 zeroext %evl) {128; CHECK-LABEL: vadd_vx_nxv2i8_unmasked:129; CHECK:       # %bb.0:130; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma131; CHECK-NEXT:    vadd.vx v8, v8, a0132; CHECK-NEXT:    ret133  %elt.head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0134  %vb = shufflevector <vscale x 2 x i8> %elt.head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer135  %v = call <vscale x 2 x i8> @llvm.vp.add.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb, <vscale x 2 x i1> splat (i1 true), i32 %evl)136  ret <vscale x 2 x i8> %v137}138 139define <vscale x 2 x i8> @vadd_vi_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {140; CHECK-LABEL: vadd_vi_nxv2i8:141; CHECK:       # %bb.0:142; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma143; CHECK-NEXT:    vadd.vi v8, v8, -1, v0.t144; CHECK-NEXT:    ret145  %v = call <vscale x 2 x i8> @llvm.vp.add.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> splat (i8 -1), <vscale x 2 x i1> %m, i32 %evl)146  ret <vscale x 2 x i8> %v147}148 149define <vscale x 2 x i8> @vadd_vi_nxv2i8_unmasked(<vscale x 2 x i8> %va, i32 zeroext %evl) {150; CHECK-LABEL: vadd_vi_nxv2i8_unmasked:151; CHECK:       # %bb.0:152; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma153; CHECK-NEXT:    vadd.vi v8, v8, -1154; CHECK-NEXT:    ret155  %v = call <vscale x 2 x i8> @llvm.vp.add.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> splat (i8 -1), <vscale x 2 x i1> splat (i1 true), i32 %evl)156  ret <vscale x 2 x i8> %v157}158 159define <vscale x 3 x i8> @vadd_vv_nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> %b, <vscale x 3 x i1> %m, i32 zeroext %evl) {160; CHECK-LABEL: vadd_vv_nxv3i8:161; CHECK:       # %bb.0:162; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma163; CHECK-NEXT:    vadd.vv v8, v8, v9, v0.t164; CHECK-NEXT:    ret165  %v = call <vscale x 3 x i8> @llvm.vp.add.nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> %b, <vscale x 3 x i1> %m, i32 %evl)166  ret <vscale x 3 x i8> %v167}168 169define <vscale x 3 x i8> @vadd_vv_nxv3i8_unmasked(<vscale x 3 x i8> %va, <vscale x 3 x i8> %b, i32 zeroext %evl) {170; CHECK-LABEL: vadd_vv_nxv3i8_unmasked:171; CHECK:       # %bb.0:172; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma173; CHECK-NEXT:    vadd.vv v8, v8, v9174; CHECK-NEXT:    ret175  %v = call <vscale x 3 x i8> @llvm.vp.add.nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> %b, <vscale x 3 x i1> splat (i1 true), i32 %evl)176  ret <vscale x 3 x i8> %v177}178 179define <vscale x 3 x i8> @vadd_vx_nxv3i8(<vscale x 3 x i8> %va, i8 %b, <vscale x 3 x i1> %m, i32 zeroext %evl) {180; CHECK-LABEL: vadd_vx_nxv3i8:181; CHECK:       # %bb.0:182; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma183; CHECK-NEXT:    vadd.vx v8, v8, a0, v0.t184; CHECK-NEXT:    ret185  %elt.head = insertelement <vscale x 3 x i8> poison, i8 %b, i32 0186  %vb = shufflevector <vscale x 3 x i8> %elt.head, <vscale x 3 x i8> poison, <vscale x 3 x i32> zeroinitializer187  %v = call <vscale x 3 x i8> @llvm.vp.add.nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> %vb, <vscale x 3 x i1> %m, i32 %evl)188  ret <vscale x 3 x i8> %v189}190 191define <vscale x 3 x i8> @vadd_vx_nxv3i8_unmasked(<vscale x 3 x i8> %va, i8 %b, i32 zeroext %evl) {192; CHECK-LABEL: vadd_vx_nxv3i8_unmasked:193; CHECK:       # %bb.0:194; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma195; CHECK-NEXT:    vadd.vx v8, v8, a0196; CHECK-NEXT:    ret197  %elt.head = insertelement <vscale x 3 x i8> poison, i8 %b, i32 0198  %vb = shufflevector <vscale x 3 x i8> %elt.head, <vscale x 3 x i8> poison, <vscale x 3 x i32> zeroinitializer199  %v = call <vscale x 3 x i8> @llvm.vp.add.nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> %vb, <vscale x 3 x i1> splat (i1 true), i32 %evl)200  ret <vscale x 3 x i8> %v201}202 203define <vscale x 3 x i8> @vadd_vi_nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i1> %m, i32 zeroext %evl) {204; CHECK-LABEL: vadd_vi_nxv3i8:205; CHECK:       # %bb.0:206; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma207; CHECK-NEXT:    vadd.vi v8, v8, -1, v0.t208; CHECK-NEXT:    ret209  %v = call <vscale x 3 x i8> @llvm.vp.add.nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> splat (i8 -1), <vscale x 3 x i1> %m, i32 %evl)210  ret <vscale x 3 x i8> %v211}212 213define <vscale x 3 x i8> @vadd_vi_nxv3i8_unmasked(<vscale x 3 x i8> %va, i32 zeroext %evl) {214; CHECK-LABEL: vadd_vi_nxv3i8_unmasked:215; CHECK:       # %bb.0:216; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma217; CHECK-NEXT:    vadd.vi v8, v8, -1218; CHECK-NEXT:    ret219  %v = call <vscale x 3 x i8> @llvm.vp.add.nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> splat (i8 -1), <vscale x 3 x i1> splat (i1 true), i32 %evl)220  ret <vscale x 3 x i8> %v221}222 223define <vscale x 4 x i8> @vadd_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {224; CHECK-LABEL: vadd_vv_nxv4i8:225; CHECK:       # %bb.0:226; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma227; CHECK-NEXT:    vadd.vv v8, v8, v9, v0.t228; CHECK-NEXT:    ret229  %v = call <vscale x 4 x i8> @llvm.vp.add.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %b, <vscale x 4 x i1> %m, i32 %evl)230  ret <vscale x 4 x i8> %v231}232 233define <vscale x 4 x i8> @vadd_vv_nxv4i8_unmasked(<vscale x 4 x i8> %va, <vscale x 4 x i8> %b, i32 zeroext %evl) {234; CHECK-LABEL: vadd_vv_nxv4i8_unmasked:235; CHECK:       # %bb.0:236; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma237; CHECK-NEXT:    vadd.vv v8, v8, v9238; CHECK-NEXT:    ret239  %v = call <vscale x 4 x i8> @llvm.vp.add.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %b, <vscale x 4 x i1> splat (i1 true), i32 %evl)240  ret <vscale x 4 x i8> %v241}242 243define <vscale x 4 x i8> @vadd_vx_nxv4i8(<vscale x 4 x i8> %va, i8 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {244; CHECK-LABEL: vadd_vx_nxv4i8:245; CHECK:       # %bb.0:246; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma247; CHECK-NEXT:    vadd.vx v8, v8, a0, v0.t248; CHECK-NEXT:    ret249  %elt.head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0250  %vb = shufflevector <vscale x 4 x i8> %elt.head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer251  %v = call <vscale x 4 x i8> @llvm.vp.add.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb, <vscale x 4 x i1> %m, i32 %evl)252  ret <vscale x 4 x i8> %v253}254 255define <vscale x 4 x i8> @vadd_vx_nxv4i8_unmasked(<vscale x 4 x i8> %va, i8 %b, i32 zeroext %evl) {256; CHECK-LABEL: vadd_vx_nxv4i8_unmasked:257; CHECK:       # %bb.0:258; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma259; CHECK-NEXT:    vadd.vx v8, v8, a0260; CHECK-NEXT:    ret261  %elt.head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0262  %vb = shufflevector <vscale x 4 x i8> %elt.head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer263  %v = call <vscale x 4 x i8> @llvm.vp.add.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb, <vscale x 4 x i1> splat (i1 true), i32 %evl)264  ret <vscale x 4 x i8> %v265}266 267define <vscale x 4 x i8> @vadd_vi_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {268; CHECK-LABEL: vadd_vi_nxv4i8:269; CHECK:       # %bb.0:270; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma271; CHECK-NEXT:    vadd.vi v8, v8, -1, v0.t272; CHECK-NEXT:    ret273  %v = call <vscale x 4 x i8> @llvm.vp.add.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> splat (i8 -1), <vscale x 4 x i1> %m, i32 %evl)274  ret <vscale x 4 x i8> %v275}276 277define <vscale x 4 x i8> @vadd_vi_nxv4i8_unmasked(<vscale x 4 x i8> %va, i32 zeroext %evl) {278; CHECK-LABEL: vadd_vi_nxv4i8_unmasked:279; CHECK:       # %bb.0:280; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma281; CHECK-NEXT:    vadd.vi v8, v8, -1282; CHECK-NEXT:    ret283  %v = call <vscale x 4 x i8> @llvm.vp.add.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> splat (i8 -1), <vscale x 4 x i1> splat (i1 true), i32 %evl)284  ret <vscale x 4 x i8> %v285}286 287define <vscale x 8 x i8> @vadd_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {288; CHECK-LABEL: vadd_vv_nxv8i8:289; CHECK:       # %bb.0:290; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma291; CHECK-NEXT:    vadd.vv v8, v8, v9, v0.t292; CHECK-NEXT:    ret293  %v = call <vscale x 8 x i8> @llvm.vp.add.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %b, <vscale x 8 x i1> %m, i32 %evl)294  ret <vscale x 8 x i8> %v295}296 297define <vscale x 8 x i8> @vadd_vv_nxv8i8_unmasked(<vscale x 8 x i8> %va, <vscale x 8 x i8> %b, i32 zeroext %evl) {298; CHECK-LABEL: vadd_vv_nxv8i8_unmasked:299; CHECK:       # %bb.0:300; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma301; CHECK-NEXT:    vadd.vv v8, v8, v9302; CHECK-NEXT:    ret303  %v = call <vscale x 8 x i8> @llvm.vp.add.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %b, <vscale x 8 x i1> splat (i1 true), i32 %evl)304  ret <vscale x 8 x i8> %v305}306 307define <vscale x 8 x i8> @vadd_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {308; CHECK-LABEL: vadd_vx_nxv8i8:309; CHECK:       # %bb.0:310; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma311; CHECK-NEXT:    vadd.vx v8, v8, a0, v0.t312; CHECK-NEXT:    ret313  %elt.head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0314  %vb = shufflevector <vscale x 8 x i8> %elt.head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer315  %v = call <vscale x 8 x i8> @llvm.vp.add.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb, <vscale x 8 x i1> %m, i32 %evl)316  ret <vscale x 8 x i8> %v317}318 319define <vscale x 8 x i8> @vadd_vx_nxv8i8_unmasked(<vscale x 8 x i8> %va, i8 %b, i32 zeroext %evl) {320; CHECK-LABEL: vadd_vx_nxv8i8_unmasked:321; CHECK:       # %bb.0:322; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma323; CHECK-NEXT:    vadd.vx v8, v8, a0324; CHECK-NEXT:    ret325  %elt.head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0326  %vb = shufflevector <vscale x 8 x i8> %elt.head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer327  %v = call <vscale x 8 x i8> @llvm.vp.add.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb, <vscale x 8 x i1> splat (i1 true), i32 %evl)328  ret <vscale x 8 x i8> %v329}330 331define <vscale x 8 x i8> @vadd_vi_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {332; CHECK-LABEL: vadd_vi_nxv8i8:333; CHECK:       # %bb.0:334; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma335; CHECK-NEXT:    vadd.vi v8, v8, -1, v0.t336; CHECK-NEXT:    ret337  %v = call <vscale x 8 x i8> @llvm.vp.add.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> splat (i8 -1), <vscale x 8 x i1> %m, i32 %evl)338  ret <vscale x 8 x i8> %v339}340 341define <vscale x 8 x i8> @vadd_vi_nxv8i8_unmasked(<vscale x 8 x i8> %va, i32 zeroext %evl) {342; CHECK-LABEL: vadd_vi_nxv8i8_unmasked:343; CHECK:       # %bb.0:344; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma345; CHECK-NEXT:    vadd.vi v8, v8, -1346; CHECK-NEXT:    ret347  %v = call <vscale x 8 x i8> @llvm.vp.add.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> splat (i8 -1), <vscale x 8 x i1> splat (i1 true), i32 %evl)348  ret <vscale x 8 x i8> %v349}350 351define <vscale x 16 x i8> @vadd_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {352; CHECK-LABEL: vadd_vv_nxv16i8:353; CHECK:       # %bb.0:354; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma355; CHECK-NEXT:    vadd.vv v8, v8, v10, v0.t356; CHECK-NEXT:    ret357  %v = call <vscale x 16 x i8> @llvm.vp.add.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %b, <vscale x 16 x i1> %m, i32 %evl)358  ret <vscale x 16 x i8> %v359}360 361define <vscale x 16 x i8> @vadd_vv_nxv16i8_unmasked(<vscale x 16 x i8> %va, <vscale x 16 x i8> %b, i32 zeroext %evl) {362; CHECK-LABEL: vadd_vv_nxv16i8_unmasked:363; CHECK:       # %bb.0:364; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma365; CHECK-NEXT:    vadd.vv v8, v8, v10366; CHECK-NEXT:    ret367  %v = call <vscale x 16 x i8> @llvm.vp.add.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %b, <vscale x 16 x i1> splat (i1 true), i32 %evl)368  ret <vscale x 16 x i8> %v369}370 371define <vscale x 16 x i8> @vadd_vx_nxv16i8(<vscale x 16 x i8> %va, i8 %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {372; CHECK-LABEL: vadd_vx_nxv16i8:373; CHECK:       # %bb.0:374; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma375; CHECK-NEXT:    vadd.vx v8, v8, a0, v0.t376; CHECK-NEXT:    ret377  %elt.head = insertelement <vscale x 16 x i8> poison, i8 %b, i32 0378  %vb = shufflevector <vscale x 16 x i8> %elt.head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer379  %v = call <vscale x 16 x i8> @llvm.vp.add.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb, <vscale x 16 x i1> %m, i32 %evl)380  ret <vscale x 16 x i8> %v381}382 383define <vscale x 16 x i8> @vadd_vx_nxv16i8_unmasked(<vscale x 16 x i8> %va, i8 %b, i32 zeroext %evl) {384; CHECK-LABEL: vadd_vx_nxv16i8_unmasked:385; CHECK:       # %bb.0:386; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma387; CHECK-NEXT:    vadd.vx v8, v8, a0388; CHECK-NEXT:    ret389  %elt.head = insertelement <vscale x 16 x i8> poison, i8 %b, i32 0390  %vb = shufflevector <vscale x 16 x i8> %elt.head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer391  %v = call <vscale x 16 x i8> @llvm.vp.add.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb, <vscale x 16 x i1> splat (i1 true), i32 %evl)392  ret <vscale x 16 x i8> %v393}394 395define <vscale x 16 x i8> @vadd_vi_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {396; CHECK-LABEL: vadd_vi_nxv16i8:397; CHECK:       # %bb.0:398; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma399; CHECK-NEXT:    vadd.vi v8, v8, -1, v0.t400; CHECK-NEXT:    ret401  %v = call <vscale x 16 x i8> @llvm.vp.add.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> splat (i8 -1), <vscale x 16 x i1> %m, i32 %evl)402  ret <vscale x 16 x i8> %v403}404 405define <vscale x 16 x i8> @vadd_vi_nxv16i8_unmasked(<vscale x 16 x i8> %va, i32 zeroext %evl) {406; CHECK-LABEL: vadd_vi_nxv16i8_unmasked:407; CHECK:       # %bb.0:408; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma409; CHECK-NEXT:    vadd.vi v8, v8, -1410; CHECK-NEXT:    ret411  %v = call <vscale x 16 x i8> @llvm.vp.add.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> splat (i8 -1), <vscale x 16 x i1> splat (i1 true), i32 %evl)412  ret <vscale x 16 x i8> %v413}414 415define <vscale x 32 x i8> @vadd_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %b, <vscale x 32 x i1> %m, i32 zeroext %evl) {416; CHECK-LABEL: vadd_vv_nxv32i8:417; CHECK:       # %bb.0:418; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma419; CHECK-NEXT:    vadd.vv v8, v8, v12, v0.t420; CHECK-NEXT:    ret421  %v = call <vscale x 32 x i8> @llvm.vp.add.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %b, <vscale x 32 x i1> %m, i32 %evl)422  ret <vscale x 32 x i8> %v423}424 425define <vscale x 32 x i8> @vadd_vv_nxv32i8_unmasked(<vscale x 32 x i8> %va, <vscale x 32 x i8> %b, i32 zeroext %evl) {426; CHECK-LABEL: vadd_vv_nxv32i8_unmasked:427; CHECK:       # %bb.0:428; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma429; CHECK-NEXT:    vadd.vv v8, v8, v12430; CHECK-NEXT:    ret431  %v = call <vscale x 32 x i8> @llvm.vp.add.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %b, <vscale x 32 x i1> splat (i1 true), i32 %evl)432  ret <vscale x 32 x i8> %v433}434 435define <vscale x 32 x i8> @vadd_vx_nxv32i8(<vscale x 32 x i8> %va, i8 %b, <vscale x 32 x i1> %m, i32 zeroext %evl) {436; CHECK-LABEL: vadd_vx_nxv32i8:437; CHECK:       # %bb.0:438; CHECK-NEXT:    vsetvli zero, a1, e8, m4, ta, ma439; CHECK-NEXT:    vadd.vx v8, v8, a0, v0.t440; CHECK-NEXT:    ret441  %elt.head = insertelement <vscale x 32 x i8> poison, i8 %b, i32 0442  %vb = shufflevector <vscale x 32 x i8> %elt.head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer443  %v = call <vscale x 32 x i8> @llvm.vp.add.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb, <vscale x 32 x i1> %m, i32 %evl)444  ret <vscale x 32 x i8> %v445}446 447define <vscale x 32 x i8> @vadd_vx_nxv32i8_unmasked(<vscale x 32 x i8> %va, i8 %b, i32 zeroext %evl) {448; CHECK-LABEL: vadd_vx_nxv32i8_unmasked:449; CHECK:       # %bb.0:450; CHECK-NEXT:    vsetvli zero, a1, e8, m4, ta, ma451; CHECK-NEXT:    vadd.vx v8, v8, a0452; CHECK-NEXT:    ret453  %elt.head = insertelement <vscale x 32 x i8> poison, i8 %b, i32 0454  %vb = shufflevector <vscale x 32 x i8> %elt.head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer455  %v = call <vscale x 32 x i8> @llvm.vp.add.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb, <vscale x 32 x i1> splat (i1 true), i32 %evl)456  ret <vscale x 32 x i8> %v457}458 459define <vscale x 32 x i8> @vadd_vi_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {460; CHECK-LABEL: vadd_vi_nxv32i8:461; CHECK:       # %bb.0:462; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma463; CHECK-NEXT:    vadd.vi v8, v8, -1, v0.t464; CHECK-NEXT:    ret465  %v = call <vscale x 32 x i8> @llvm.vp.add.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> splat (i8 -1), <vscale x 32 x i1> %m, i32 %evl)466  ret <vscale x 32 x i8> %v467}468 469define <vscale x 32 x i8> @vadd_vi_nxv32i8_unmasked(<vscale x 32 x i8> %va, i32 zeroext %evl) {470; CHECK-LABEL: vadd_vi_nxv32i8_unmasked:471; CHECK:       # %bb.0:472; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma473; CHECK-NEXT:    vadd.vi v8, v8, -1474; CHECK-NEXT:    ret475  %v = call <vscale x 32 x i8> @llvm.vp.add.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> splat (i8 -1), <vscale x 32 x i1> splat (i1 true), i32 %evl)476  ret <vscale x 32 x i8> %v477}478 479define <vscale x 64 x i8> @vadd_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %b, <vscale x 64 x i1> %m, i32 zeroext %evl) {480; CHECK-LABEL: vadd_vv_nxv64i8:481; CHECK:       # %bb.0:482; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma483; CHECK-NEXT:    vadd.vv v8, v8, v16, v0.t484; CHECK-NEXT:    ret485  %v = call <vscale x 64 x i8> @llvm.vp.add.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %b, <vscale x 64 x i1> %m, i32 %evl)486  ret <vscale x 64 x i8> %v487}488 489define <vscale x 64 x i8> @vadd_vv_nxv64i8_unmasked(<vscale x 64 x i8> %va, <vscale x 64 x i8> %b, i32 zeroext %evl) {490; CHECK-LABEL: vadd_vv_nxv64i8_unmasked:491; CHECK:       # %bb.0:492; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma493; CHECK-NEXT:    vadd.vv v8, v8, v16494; CHECK-NEXT:    ret495  %v = call <vscale x 64 x i8> @llvm.vp.add.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %b, <vscale x 64 x i1> splat (i1 true), i32 %evl)496  ret <vscale x 64 x i8> %v497}498 499define <vscale x 64 x i8> @vadd_vx_nxv64i8(<vscale x 64 x i8> %va, i8 %b, <vscale x 64 x i1> %m, i32 zeroext %evl) {500; CHECK-LABEL: vadd_vx_nxv64i8:501; CHECK:       # %bb.0:502; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, ma503; CHECK-NEXT:    vadd.vx v8, v8, a0, v0.t504; CHECK-NEXT:    ret505  %elt.head = insertelement <vscale x 64 x i8> poison, i8 %b, i32 0506  %vb = shufflevector <vscale x 64 x i8> %elt.head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer507  %v = call <vscale x 64 x i8> @llvm.vp.add.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb, <vscale x 64 x i1> %m, i32 %evl)508  ret <vscale x 64 x i8> %v509}510 511define <vscale x 64 x i8> @vadd_vx_nxv64i8_unmasked(<vscale x 64 x i8> %va, i8 %b, i32 zeroext %evl) {512; CHECK-LABEL: vadd_vx_nxv64i8_unmasked:513; CHECK:       # %bb.0:514; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, ma515; CHECK-NEXT:    vadd.vx v8, v8, a0516; CHECK-NEXT:    ret517  %elt.head = insertelement <vscale x 64 x i8> poison, i8 %b, i32 0518  %vb = shufflevector <vscale x 64 x i8> %elt.head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer519  %v = call <vscale x 64 x i8> @llvm.vp.add.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb, <vscale x 64 x i1> splat (i1 true), i32 %evl)520  ret <vscale x 64 x i8> %v521}522 523define <vscale x 64 x i8> @vadd_vi_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i1> %m, i32 zeroext %evl) {524; CHECK-LABEL: vadd_vi_nxv64i8:525; CHECK:       # %bb.0:526; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma527; CHECK-NEXT:    vadd.vi v8, v8, -1, v0.t528; CHECK-NEXT:    ret529  %v = call <vscale x 64 x i8> @llvm.vp.add.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> splat (i8 -1), <vscale x 64 x i1> %m, i32 %evl)530  ret <vscale x 64 x i8> %v531}532 533define <vscale x 64 x i8> @vadd_vi_nxv64i8_unmasked(<vscale x 64 x i8> %va, i32 zeroext %evl) {534; CHECK-LABEL: vadd_vi_nxv64i8_unmasked:535; CHECK:       # %bb.0:536; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma537; CHECK-NEXT:    vadd.vi v8, v8, -1538; CHECK-NEXT:    ret539  %v = call <vscale x 64 x i8> @llvm.vp.add.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> splat (i8 -1), <vscale x 64 x i1> splat (i1 true), i32 %evl)540  ret <vscale x 64 x i8> %v541}542 543; Test that split-legalization works when the mask itself needs splitting.544 545define <vscale x 128 x i8> @vadd_vi_nxv128i8(<vscale x 128 x i8> %va, <vscale x 128 x i1> %m, i32 zeroext %evl) {546; CHECK-LABEL: vadd_vi_nxv128i8:547; CHECK:       # %bb.0:548; CHECK-NEXT:    vsetvli a2, zero, e8, m8, ta, ma549; CHECK-NEXT:    vmv1r.v v24, v0550; CHECK-NEXT:    vlm.v v0, (a0)551; CHECK-NEXT:    csrr a0, vlenb552; CHECK-NEXT:    slli a0, a0, 3553; CHECK-NEXT:    sub a2, a1, a0554; CHECK-NEXT:    sltu a3, a1, a2555; CHECK-NEXT:    addi a3, a3, -1556; CHECK-NEXT:    and a2, a3, a2557; CHECK-NEXT:    vsetvli zero, a2, e8, m8, ta, ma558; CHECK-NEXT:    vadd.vi v16, v16, -1, v0.t559; CHECK-NEXT:    bltu a1, a0, .LBB50_2560; CHECK-NEXT:  # %bb.1:561; CHECK-NEXT:    mv a1, a0562; CHECK-NEXT:  .LBB50_2:563; CHECK-NEXT:    vmv1r.v v0, v24564; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, ma565; CHECK-NEXT:    vadd.vi v8, v8, -1, v0.t566; CHECK-NEXT:    ret567  %v = call <vscale x 128 x i8> @llvm.vp.add.nxv128i8(<vscale x 128 x i8> %va, <vscale x 128 x i8> splat (i8 -1), <vscale x 128 x i1> %m, i32 %evl)568  ret <vscale x 128 x i8> %v569}570 571define <vscale x 128 x i8> @vadd_vi_nxv128i8_unmasked(<vscale x 128 x i8> %va, i32 zeroext %evl) {572; CHECK-LABEL: vadd_vi_nxv128i8_unmasked:573; CHECK:       # %bb.0:574; CHECK-NEXT:    csrr a1, vlenb575; CHECK-NEXT:    slli a1, a1, 3576; CHECK-NEXT:    sub a2, a0, a1577; CHECK-NEXT:    sltu a3, a0, a2578; CHECK-NEXT:    addi a3, a3, -1579; CHECK-NEXT:    and a2, a3, a2580; CHECK-NEXT:    vsetvli zero, a2, e8, m8, ta, ma581; CHECK-NEXT:    vadd.vi v16, v16, -1582; CHECK-NEXT:    bltu a0, a1, .LBB51_2583; CHECK-NEXT:  # %bb.1:584; CHECK-NEXT:    mv a0, a1585; CHECK-NEXT:  .LBB51_2:586; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma587; CHECK-NEXT:    vadd.vi v8, v8, -1588; CHECK-NEXT:    ret589  %v = call <vscale x 128 x i8> @llvm.vp.add.nxv128i8(<vscale x 128 x i8> %va, <vscale x 128 x i8> splat (i8 -1), <vscale x 128 x i1> splat (i1 true), i32 %evl)590  ret <vscale x 128 x i8> %v591}592 593define <vscale x 1 x i16> @vadd_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {594; CHECK-LABEL: vadd_vv_nxv1i16:595; CHECK:       # %bb.0:596; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma597; CHECK-NEXT:    vadd.vv v8, v8, v9, v0.t598; CHECK-NEXT:    ret599  %v = call <vscale x 1 x i16> @llvm.vp.add.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %b, <vscale x 1 x i1> %m, i32 %evl)600  ret <vscale x 1 x i16> %v601}602 603define <vscale x 1 x i16> @vadd_vv_nxv1i16_unmasked(<vscale x 1 x i16> %va, <vscale x 1 x i16> %b, i32 zeroext %evl) {604; CHECK-LABEL: vadd_vv_nxv1i16_unmasked:605; CHECK:       # %bb.0:606; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma607; CHECK-NEXT:    vadd.vv v8, v8, v9608; CHECK-NEXT:    ret609  %v = call <vscale x 1 x i16> @llvm.vp.add.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %b, <vscale x 1 x i1> splat (i1 true), i32 %evl)610  ret <vscale x 1 x i16> %v611}612 613define <vscale x 1 x i16> @vadd_vx_nxv1i16(<vscale x 1 x i16> %va, i16 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {614; CHECK-LABEL: vadd_vx_nxv1i16:615; CHECK:       # %bb.0:616; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma617; CHECK-NEXT:    vadd.vx v8, v8, a0, v0.t618; CHECK-NEXT:    ret619  %elt.head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0620  %vb = shufflevector <vscale x 1 x i16> %elt.head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer621  %v = call <vscale x 1 x i16> @llvm.vp.add.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb, <vscale x 1 x i1> %m, i32 %evl)622  ret <vscale x 1 x i16> %v623}624 625define <vscale x 1 x i16> @vadd_vx_nxv1i16_unmasked(<vscale x 1 x i16> %va, i16 %b, i32 zeroext %evl) {626; CHECK-LABEL: vadd_vx_nxv1i16_unmasked:627; CHECK:       # %bb.0:628; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma629; CHECK-NEXT:    vadd.vx v8, v8, a0630; CHECK-NEXT:    ret631  %elt.head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0632  %vb = shufflevector <vscale x 1 x i16> %elt.head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer633  %v = call <vscale x 1 x i16> @llvm.vp.add.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb, <vscale x 1 x i1> splat (i1 true), i32 %evl)634  ret <vscale x 1 x i16> %v635}636 637define <vscale x 1 x i16> @vadd_vi_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {638; CHECK-LABEL: vadd_vi_nxv1i16:639; CHECK:       # %bb.0:640; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma641; CHECK-NEXT:    vadd.vi v8, v8, -1, v0.t642; CHECK-NEXT:    ret643  %v = call <vscale x 1 x i16> @llvm.vp.add.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> splat (i16 -1), <vscale x 1 x i1> %m, i32 %evl)644  ret <vscale x 1 x i16> %v645}646 647define <vscale x 1 x i16> @vadd_vi_nxv1i16_unmasked(<vscale x 1 x i16> %va, i32 zeroext %evl) {648; CHECK-LABEL: vadd_vi_nxv1i16_unmasked:649; CHECK:       # %bb.0:650; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma651; CHECK-NEXT:    vadd.vi v8, v8, -1652; CHECK-NEXT:    ret653  %v = call <vscale x 1 x i16> @llvm.vp.add.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> splat (i16 -1), <vscale x 1 x i1> splat (i1 true), i32 %evl)654  ret <vscale x 1 x i16> %v655}656 657define <vscale x 2 x i16> @vadd_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {658; CHECK-LABEL: vadd_vv_nxv2i16:659; CHECK:       # %bb.0:660; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma661; CHECK-NEXT:    vadd.vv v8, v8, v9, v0.t662; CHECK-NEXT:    ret663  %v = call <vscale x 2 x i16> @llvm.vp.add.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %b, <vscale x 2 x i1> %m, i32 %evl)664  ret <vscale x 2 x i16> %v665}666 667define <vscale x 2 x i16> @vadd_vv_nxv2i16_unmasked(<vscale x 2 x i16> %va, <vscale x 2 x i16> %b, i32 zeroext %evl) {668; CHECK-LABEL: vadd_vv_nxv2i16_unmasked:669; CHECK:       # %bb.0:670; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma671; CHECK-NEXT:    vadd.vv v8, v8, v9672; CHECK-NEXT:    ret673  %v = call <vscale x 2 x i16> @llvm.vp.add.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %b, <vscale x 2 x i1> splat (i1 true), i32 %evl)674  ret <vscale x 2 x i16> %v675}676 677define <vscale x 2 x i16> @vadd_vx_nxv2i16(<vscale x 2 x i16> %va, i16 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {678; CHECK-LABEL: vadd_vx_nxv2i16:679; CHECK:       # %bb.0:680; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma681; CHECK-NEXT:    vadd.vx v8, v8, a0, v0.t682; CHECK-NEXT:    ret683  %elt.head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0684  %vb = shufflevector <vscale x 2 x i16> %elt.head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer685  %v = call <vscale x 2 x i16> @llvm.vp.add.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb, <vscale x 2 x i1> %m, i32 %evl)686  ret <vscale x 2 x i16> %v687}688 689define <vscale x 2 x i16> @vadd_vx_nxv2i16_unmasked(<vscale x 2 x i16> %va, i16 %b, i32 zeroext %evl) {690; CHECK-LABEL: vadd_vx_nxv2i16_unmasked:691; CHECK:       # %bb.0:692; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma693; CHECK-NEXT:    vadd.vx v8, v8, a0694; CHECK-NEXT:    ret695  %elt.head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0696  %vb = shufflevector <vscale x 2 x i16> %elt.head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer697  %v = call <vscale x 2 x i16> @llvm.vp.add.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb, <vscale x 2 x i1> splat (i1 true), i32 %evl)698  ret <vscale x 2 x i16> %v699}700 701define <vscale x 2 x i16> @vadd_vi_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {702; CHECK-LABEL: vadd_vi_nxv2i16:703; CHECK:       # %bb.0:704; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma705; CHECK-NEXT:    vadd.vi v8, v8, -1, v0.t706; CHECK-NEXT:    ret707  %v = call <vscale x 2 x i16> @llvm.vp.add.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> splat (i16 -1), <vscale x 2 x i1> %m, i32 %evl)708  ret <vscale x 2 x i16> %v709}710 711define <vscale x 2 x i16> @vadd_vi_nxv2i16_unmasked(<vscale x 2 x i16> %va, i32 zeroext %evl) {712; CHECK-LABEL: vadd_vi_nxv2i16_unmasked:713; CHECK:       # %bb.0:714; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma715; CHECK-NEXT:    vadd.vi v8, v8, -1716; CHECK-NEXT:    ret717  %v = call <vscale x 2 x i16> @llvm.vp.add.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> splat (i16 -1), <vscale x 2 x i1> splat (i1 true), i32 %evl)718  ret <vscale x 2 x i16> %v719}720 721define <vscale x 4 x i16> @vadd_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {722; CHECK-LABEL: vadd_vv_nxv4i16:723; CHECK:       # %bb.0:724; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma725; CHECK-NEXT:    vadd.vv v8, v8, v9, v0.t726; CHECK-NEXT:    ret727  %v = call <vscale x 4 x i16> @llvm.vp.add.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %b, <vscale x 4 x i1> %m, i32 %evl)728  ret <vscale x 4 x i16> %v729}730 731define <vscale x 4 x i16> @vadd_vv_nxv4i16_unmasked(<vscale x 4 x i16> %va, <vscale x 4 x i16> %b, i32 zeroext %evl) {732; CHECK-LABEL: vadd_vv_nxv4i16_unmasked:733; CHECK:       # %bb.0:734; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma735; CHECK-NEXT:    vadd.vv v8, v8, v9736; CHECK-NEXT:    ret737  %v = call <vscale x 4 x i16> @llvm.vp.add.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %b, <vscale x 4 x i1> splat (i1 true), i32 %evl)738  ret <vscale x 4 x i16> %v739}740 741define <vscale x 4 x i16> @vadd_vx_nxv4i16(<vscale x 4 x i16> %va, i16 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {742; CHECK-LABEL: vadd_vx_nxv4i16:743; CHECK:       # %bb.0:744; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma745; CHECK-NEXT:    vadd.vx v8, v8, a0, v0.t746; CHECK-NEXT:    ret747  %elt.head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0748  %vb = shufflevector <vscale x 4 x i16> %elt.head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer749  %v = call <vscale x 4 x i16> @llvm.vp.add.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb, <vscale x 4 x i1> %m, i32 %evl)750  ret <vscale x 4 x i16> %v751}752 753define <vscale x 4 x i16> @vadd_vx_nxv4i16_unmasked(<vscale x 4 x i16> %va, i16 %b, i32 zeroext %evl) {754; CHECK-LABEL: vadd_vx_nxv4i16_unmasked:755; CHECK:       # %bb.0:756; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma757; CHECK-NEXT:    vadd.vx v8, v8, a0758; CHECK-NEXT:    ret759  %elt.head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0760  %vb = shufflevector <vscale x 4 x i16> %elt.head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer761  %v = call <vscale x 4 x i16> @llvm.vp.add.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb, <vscale x 4 x i1> splat (i1 true), i32 %evl)762  ret <vscale x 4 x i16> %v763}764 765define <vscale x 4 x i16> @vadd_vi_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {766; CHECK-LABEL: vadd_vi_nxv4i16:767; CHECK:       # %bb.0:768; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma769; CHECK-NEXT:    vadd.vi v8, v8, -1, v0.t770; CHECK-NEXT:    ret771  %v = call <vscale x 4 x i16> @llvm.vp.add.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> splat (i16 -1), <vscale x 4 x i1> %m, i32 %evl)772  ret <vscale x 4 x i16> %v773}774 775define <vscale x 4 x i16> @vadd_vi_nxv4i16_unmasked(<vscale x 4 x i16> %va, i32 zeroext %evl) {776; CHECK-LABEL: vadd_vi_nxv4i16_unmasked:777; CHECK:       # %bb.0:778; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma779; CHECK-NEXT:    vadd.vi v8, v8, -1780; CHECK-NEXT:    ret781  %v = call <vscale x 4 x i16> @llvm.vp.add.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> splat (i16 -1), <vscale x 4 x i1> splat (i1 true), i32 %evl)782  ret <vscale x 4 x i16> %v783}784 785define <vscale x 8 x i16> @vadd_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {786; CHECK-LABEL: vadd_vv_nxv8i16:787; CHECK:       # %bb.0:788; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma789; CHECK-NEXT:    vadd.vv v8, v8, v10, v0.t790; CHECK-NEXT:    ret791  %v = call <vscale x 8 x i16> @llvm.vp.add.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %b, <vscale x 8 x i1> %m, i32 %evl)792  ret <vscale x 8 x i16> %v793}794 795define <vscale x 8 x i16> @vadd_vv_nxv8i16_unmasked(<vscale x 8 x i16> %va, <vscale x 8 x i16> %b, i32 zeroext %evl) {796; CHECK-LABEL: vadd_vv_nxv8i16_unmasked:797; CHECK:       # %bb.0:798; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma799; CHECK-NEXT:    vadd.vv v8, v8, v10800; CHECK-NEXT:    ret801  %v = call <vscale x 8 x i16> @llvm.vp.add.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %b, <vscale x 8 x i1> splat (i1 true), i32 %evl)802  ret <vscale x 8 x i16> %v803}804 805define <vscale x 8 x i16> @vadd_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {806; CHECK-LABEL: vadd_vx_nxv8i16:807; CHECK:       # %bb.0:808; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma809; CHECK-NEXT:    vadd.vx v8, v8, a0, v0.t810; CHECK-NEXT:    ret811  %elt.head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0812  %vb = shufflevector <vscale x 8 x i16> %elt.head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer813  %v = call <vscale x 8 x i16> @llvm.vp.add.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb, <vscale x 8 x i1> %m, i32 %evl)814  ret <vscale x 8 x i16> %v815}816 817define <vscale x 8 x i16> @vadd_vx_nxv8i16_unmasked(<vscale x 8 x i16> %va, i16 %b, i32 zeroext %evl) {818; CHECK-LABEL: vadd_vx_nxv8i16_unmasked:819; CHECK:       # %bb.0:820; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma821; CHECK-NEXT:    vadd.vx v8, v8, a0822; CHECK-NEXT:    ret823  %elt.head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0824  %vb = shufflevector <vscale x 8 x i16> %elt.head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer825  %v = call <vscale x 8 x i16> @llvm.vp.add.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb, <vscale x 8 x i1> splat (i1 true), i32 %evl)826  ret <vscale x 8 x i16> %v827}828 829define <vscale x 8 x i16> @vadd_vi_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {830; CHECK-LABEL: vadd_vi_nxv8i16:831; CHECK:       # %bb.0:832; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma833; CHECK-NEXT:    vadd.vi v8, v8, -1, v0.t834; CHECK-NEXT:    ret835  %v = call <vscale x 8 x i16> @llvm.vp.add.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> splat (i16 -1), <vscale x 8 x i1> %m, i32 %evl)836  ret <vscale x 8 x i16> %v837}838 839define <vscale x 8 x i16> @vadd_vi_nxv8i16_unmasked(<vscale x 8 x i16> %va, i32 zeroext %evl) {840; CHECK-LABEL: vadd_vi_nxv8i16_unmasked:841; CHECK:       # %bb.0:842; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma843; CHECK-NEXT:    vadd.vi v8, v8, -1844; CHECK-NEXT:    ret845  %v = call <vscale x 8 x i16> @llvm.vp.add.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> splat (i16 -1), <vscale x 8 x i1> splat (i1 true), i32 %evl)846  ret <vscale x 8 x i16> %v847}848 849define <vscale x 16 x i16> @vadd_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {850; CHECK-LABEL: vadd_vv_nxv16i16:851; CHECK:       # %bb.0:852; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma853; CHECK-NEXT:    vadd.vv v8, v8, v12, v0.t854; CHECK-NEXT:    ret855  %v = call <vscale x 16 x i16> @llvm.vp.add.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %b, <vscale x 16 x i1> %m, i32 %evl)856  ret <vscale x 16 x i16> %v857}858 859define <vscale x 16 x i16> @vadd_vv_nxv16i16_unmasked(<vscale x 16 x i16> %va, <vscale x 16 x i16> %b, i32 zeroext %evl) {860; CHECK-LABEL: vadd_vv_nxv16i16_unmasked:861; CHECK:       # %bb.0:862; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma863; CHECK-NEXT:    vadd.vv v8, v8, v12864; CHECK-NEXT:    ret865  %v = call <vscale x 16 x i16> @llvm.vp.add.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %b, <vscale x 16 x i1> splat (i1 true), i32 %evl)866  ret <vscale x 16 x i16> %v867}868 869define <vscale x 16 x i16> @vadd_vx_nxv16i16(<vscale x 16 x i16> %va, i16 %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {870; CHECK-LABEL: vadd_vx_nxv16i16:871; CHECK:       # %bb.0:872; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma873; CHECK-NEXT:    vadd.vx v8, v8, a0, v0.t874; CHECK-NEXT:    ret875  %elt.head = insertelement <vscale x 16 x i16> poison, i16 %b, i32 0876  %vb = shufflevector <vscale x 16 x i16> %elt.head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer877  %v = call <vscale x 16 x i16> @llvm.vp.add.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb, <vscale x 16 x i1> %m, i32 %evl)878  ret <vscale x 16 x i16> %v879}880 881define <vscale x 16 x i16> @vadd_vx_nxv16i16_unmasked(<vscale x 16 x i16> %va, i16 %b, i32 zeroext %evl) {882; CHECK-LABEL: vadd_vx_nxv16i16_unmasked:883; CHECK:       # %bb.0:884; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma885; CHECK-NEXT:    vadd.vx v8, v8, a0886; CHECK-NEXT:    ret887  %elt.head = insertelement <vscale x 16 x i16> poison, i16 %b, i32 0888  %vb = shufflevector <vscale x 16 x i16> %elt.head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer889  %v = call <vscale x 16 x i16> @llvm.vp.add.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb, <vscale x 16 x i1> splat (i1 true), i32 %evl)890  ret <vscale x 16 x i16> %v891}892 893define <vscale x 16 x i16> @vadd_vi_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {894; CHECK-LABEL: vadd_vi_nxv16i16:895; CHECK:       # %bb.0:896; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma897; CHECK-NEXT:    vadd.vi v8, v8, -1, v0.t898; CHECK-NEXT:    ret899  %v = call <vscale x 16 x i16> @llvm.vp.add.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> splat (i16 -1), <vscale x 16 x i1> %m, i32 %evl)900  ret <vscale x 16 x i16> %v901}902 903define <vscale x 16 x i16> @vadd_vi_nxv16i16_unmasked(<vscale x 16 x i16> %va, i32 zeroext %evl) {904; CHECK-LABEL: vadd_vi_nxv16i16_unmasked:905; CHECK:       # %bb.0:906; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma907; CHECK-NEXT:    vadd.vi v8, v8, -1908; CHECK-NEXT:    ret909  %v = call <vscale x 16 x i16> @llvm.vp.add.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> splat (i16 -1), <vscale x 16 x i1> splat (i1 true), i32 %evl)910  ret <vscale x 16 x i16> %v911}912 913define <vscale x 32 x i16> @vadd_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %b, <vscale x 32 x i1> %m, i32 zeroext %evl) {914; CHECK-LABEL: vadd_vv_nxv32i16:915; CHECK:       # %bb.0:916; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, ma917; CHECK-NEXT:    vadd.vv v8, v8, v16, v0.t918; CHECK-NEXT:    ret919  %v = call <vscale x 32 x i16> @llvm.vp.add.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %b, <vscale x 32 x i1> %m, i32 %evl)920  ret <vscale x 32 x i16> %v921}922 923define <vscale x 32 x i16> @vadd_vv_nxv32i16_unmasked(<vscale x 32 x i16> %va, <vscale x 32 x i16> %b, i32 zeroext %evl) {924; CHECK-LABEL: vadd_vv_nxv32i16_unmasked:925; CHECK:       # %bb.0:926; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, ma927; CHECK-NEXT:    vadd.vv v8, v8, v16928; CHECK-NEXT:    ret929  %v = call <vscale x 32 x i16> @llvm.vp.add.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %b, <vscale x 32 x i1> splat (i1 true), i32 %evl)930  ret <vscale x 32 x i16> %v931}932 933define <vscale x 32 x i16> @vadd_vx_nxv32i16(<vscale x 32 x i16> %va, i16 %b, <vscale x 32 x i1> %m, i32 zeroext %evl) {934; CHECK-LABEL: vadd_vx_nxv32i16:935; CHECK:       # %bb.0:936; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, ma937; CHECK-NEXT:    vadd.vx v8, v8, a0, v0.t938; CHECK-NEXT:    ret939  %elt.head = insertelement <vscale x 32 x i16> poison, i16 %b, i32 0940  %vb = shufflevector <vscale x 32 x i16> %elt.head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer941  %v = call <vscale x 32 x i16> @llvm.vp.add.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb, <vscale x 32 x i1> %m, i32 %evl)942  ret <vscale x 32 x i16> %v943}944 945define <vscale x 32 x i16> @vadd_vx_nxv32i16_unmasked(<vscale x 32 x i16> %va, i16 %b, i32 zeroext %evl) {946; CHECK-LABEL: vadd_vx_nxv32i16_unmasked:947; CHECK:       # %bb.0:948; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, ma949; CHECK-NEXT:    vadd.vx v8, v8, a0950; CHECK-NEXT:    ret951  %elt.head = insertelement <vscale x 32 x i16> poison, i16 %b, i32 0952  %vb = shufflevector <vscale x 32 x i16> %elt.head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer953  %v = call <vscale x 32 x i16> @llvm.vp.add.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb, <vscale x 32 x i1> splat (i1 true), i32 %evl)954  ret <vscale x 32 x i16> %v955}956 957define <vscale x 32 x i16> @vadd_vi_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {958; CHECK-LABEL: vadd_vi_nxv32i16:959; CHECK:       # %bb.0:960; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, ma961; CHECK-NEXT:    vadd.vi v8, v8, -1, v0.t962; CHECK-NEXT:    ret963  %v = call <vscale x 32 x i16> @llvm.vp.add.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> splat (i16 -1), <vscale x 32 x i1> %m, i32 %evl)964  ret <vscale x 32 x i16> %v965}966 967define <vscale x 32 x i16> @vadd_vi_nxv32i16_unmasked(<vscale x 32 x i16> %va, i32 zeroext %evl) {968; CHECK-LABEL: vadd_vi_nxv32i16_unmasked:969; CHECK:       # %bb.0:970; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, ma971; CHECK-NEXT:    vadd.vi v8, v8, -1972; CHECK-NEXT:    ret973  %v = call <vscale x 32 x i16> @llvm.vp.add.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> splat (i16 -1), <vscale x 32 x i1> splat (i1 true), i32 %evl)974  ret <vscale x 32 x i16> %v975}976 977define <vscale x 1 x i32> @vadd_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {978; CHECK-LABEL: vadd_vv_nxv1i32:979; CHECK:       # %bb.0:980; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma981; CHECK-NEXT:    vadd.vv v8, v8, v9, v0.t982; CHECK-NEXT:    ret983  %v = call <vscale x 1 x i32> @llvm.vp.add.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %b, <vscale x 1 x i1> %m, i32 %evl)984  ret <vscale x 1 x i32> %v985}986 987define <vscale x 1 x i32> @vadd_vv_nxv1i32_unmasked(<vscale x 1 x i32> %va, <vscale x 1 x i32> %b, i32 zeroext %evl) {988; CHECK-LABEL: vadd_vv_nxv1i32_unmasked:989; CHECK:       # %bb.0:990; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma991; CHECK-NEXT:    vadd.vv v8, v8, v9992; CHECK-NEXT:    ret993  %v = call <vscale x 1 x i32> @llvm.vp.add.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %b, <vscale x 1 x i1> splat (i1 true), i32 %evl)994  ret <vscale x 1 x i32> %v995}996 997define <vscale x 1 x i32> @vadd_vx_nxv1i32(<vscale x 1 x i32> %va, i32 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {998; CHECK-LABEL: vadd_vx_nxv1i32:999; CHECK:       # %bb.0:1000; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma1001; CHECK-NEXT:    vadd.vx v8, v8, a0, v0.t1002; CHECK-NEXT:    ret1003  %elt.head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 01004  %vb = shufflevector <vscale x 1 x i32> %elt.head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer1005  %v = call <vscale x 1 x i32> @llvm.vp.add.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb, <vscale x 1 x i1> %m, i32 %evl)1006  ret <vscale x 1 x i32> %v1007}1008 1009define <vscale x 1 x i32> @vadd_vx_nxv1i32_unmasked(<vscale x 1 x i32> %va, i32 %b, i32 zeroext %evl) {1010; CHECK-LABEL: vadd_vx_nxv1i32_unmasked:1011; CHECK:       # %bb.0:1012; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma1013; CHECK-NEXT:    vadd.vx v8, v8, a01014; CHECK-NEXT:    ret1015  %elt.head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 01016  %vb = shufflevector <vscale x 1 x i32> %elt.head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer1017  %v = call <vscale x 1 x i32> @llvm.vp.add.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb, <vscale x 1 x i1> splat (i1 true), i32 %evl)1018  ret <vscale x 1 x i32> %v1019}1020 1021define <vscale x 1 x i32> @vadd_vi_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {1022; CHECK-LABEL: vadd_vi_nxv1i32:1023; CHECK:       # %bb.0:1024; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma1025; CHECK-NEXT:    vadd.vi v8, v8, -1, v0.t1026; CHECK-NEXT:    ret1027  %v = call <vscale x 1 x i32> @llvm.vp.add.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> splat (i32 -1), <vscale x 1 x i1> %m, i32 %evl)1028  ret <vscale x 1 x i32> %v1029}1030 1031define <vscale x 1 x i32> @vadd_vi_nxv1i32_unmasked(<vscale x 1 x i32> %va, i32 zeroext %evl) {1032; CHECK-LABEL: vadd_vi_nxv1i32_unmasked:1033; CHECK:       # %bb.0:1034; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma1035; CHECK-NEXT:    vadd.vi v8, v8, -11036; CHECK-NEXT:    ret1037  %v = call <vscale x 1 x i32> @llvm.vp.add.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> splat (i32 -1), <vscale x 1 x i1> splat (i1 true), i32 %evl)1038  ret <vscale x 1 x i32> %v1039}1040 1041define <vscale x 2 x i32> @vadd_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {1042; CHECK-LABEL: vadd_vv_nxv2i32:1043; CHECK:       # %bb.0:1044; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma1045; CHECK-NEXT:    vadd.vv v8, v8, v9, v0.t1046; CHECK-NEXT:    ret1047  %v = call <vscale x 2 x i32> @llvm.vp.add.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %b, <vscale x 2 x i1> %m, i32 %evl)1048  ret <vscale x 2 x i32> %v1049}1050 1051define <vscale x 2 x i32> @vadd_vv_nxv2i32_unmasked(<vscale x 2 x i32> %va, <vscale x 2 x i32> %b, i32 zeroext %evl) {1052; CHECK-LABEL: vadd_vv_nxv2i32_unmasked:1053; CHECK:       # %bb.0:1054; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma1055; CHECK-NEXT:    vadd.vv v8, v8, v91056; CHECK-NEXT:    ret1057  %v = call <vscale x 2 x i32> @llvm.vp.add.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %b, <vscale x 2 x i1> splat (i1 true), i32 %evl)1058  ret <vscale x 2 x i32> %v1059}1060 1061define <vscale x 2 x i32> @vadd_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {1062; CHECK-LABEL: vadd_vx_nxv2i32:1063; CHECK:       # %bb.0:1064; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma1065; CHECK-NEXT:    vadd.vx v8, v8, a0, v0.t1066; CHECK-NEXT:    ret1067  %elt.head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 01068  %vb = shufflevector <vscale x 2 x i32> %elt.head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer1069  %v = call <vscale x 2 x i32> @llvm.vp.add.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb, <vscale x 2 x i1> %m, i32 %evl)1070  ret <vscale x 2 x i32> %v1071}1072 1073define <vscale x 2 x i32> @vadd_vx_nxv2i32_unmasked(<vscale x 2 x i32> %va, i32 %b, i32 zeroext %evl) {1074; CHECK-LABEL: vadd_vx_nxv2i32_unmasked:1075; CHECK:       # %bb.0:1076; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma1077; CHECK-NEXT:    vadd.vx v8, v8, a01078; CHECK-NEXT:    ret1079  %elt.head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 01080  %vb = shufflevector <vscale x 2 x i32> %elt.head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer1081  %v = call <vscale x 2 x i32> @llvm.vp.add.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb, <vscale x 2 x i1> splat (i1 true), i32 %evl)1082  ret <vscale x 2 x i32> %v1083}1084 1085define <vscale x 2 x i32> @vadd_vi_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {1086; CHECK-LABEL: vadd_vi_nxv2i32:1087; CHECK:       # %bb.0:1088; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma1089; CHECK-NEXT:    vadd.vi v8, v8, -1, v0.t1090; CHECK-NEXT:    ret1091  %v = call <vscale x 2 x i32> @llvm.vp.add.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> splat (i32 -1), <vscale x 2 x i1> %m, i32 %evl)1092  ret <vscale x 2 x i32> %v1093}1094 1095define <vscale x 2 x i32> @vadd_vi_nxv2i32_unmasked(<vscale x 2 x i32> %va, i32 zeroext %evl) {1096; CHECK-LABEL: vadd_vi_nxv2i32_unmasked:1097; CHECK:       # %bb.0:1098; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma1099; CHECK-NEXT:    vadd.vi v8, v8, -11100; CHECK-NEXT:    ret1101  %v = call <vscale x 2 x i32> @llvm.vp.add.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> splat (i32 -1), <vscale x 2 x i1> splat (i1 true), i32 %evl)1102  ret <vscale x 2 x i32> %v1103}1104 1105define <vscale x 4 x i32> @vadd_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {1106; CHECK-LABEL: vadd_vv_nxv4i32:1107; CHECK:       # %bb.0:1108; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma1109; CHECK-NEXT:    vadd.vv v8, v8, v10, v0.t1110; CHECK-NEXT:    ret1111  %v = call <vscale x 4 x i32> @llvm.vp.add.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %b, <vscale x 4 x i1> %m, i32 %evl)1112  ret <vscale x 4 x i32> %v1113}1114 1115define <vscale x 4 x i32> @vadd_vv_nxv4i32_unmasked(<vscale x 4 x i32> %va, <vscale x 4 x i32> %b, i32 zeroext %evl) {1116; CHECK-LABEL: vadd_vv_nxv4i32_unmasked:1117; CHECK:       # %bb.0:1118; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma1119; CHECK-NEXT:    vadd.vv v8, v8, v101120; CHECK-NEXT:    ret1121  %v = call <vscale x 4 x i32> @llvm.vp.add.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %b, <vscale x 4 x i1> splat (i1 true), i32 %evl)1122  ret <vscale x 4 x i32> %v1123}1124 1125define <vscale x 4 x i32> @vadd_vx_nxv4i32(<vscale x 4 x i32> %va, i32 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {1126; CHECK-LABEL: vadd_vx_nxv4i32:1127; CHECK:       # %bb.0:1128; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma1129; CHECK-NEXT:    vadd.vx v8, v8, a0, v0.t1130; CHECK-NEXT:    ret1131  %elt.head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 01132  %vb = shufflevector <vscale x 4 x i32> %elt.head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer1133  %v = call <vscale x 4 x i32> @llvm.vp.add.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb, <vscale x 4 x i1> %m, i32 %evl)1134  ret <vscale x 4 x i32> %v1135}1136 1137define <vscale x 4 x i32> @vadd_vx_nxv4i32_unmasked(<vscale x 4 x i32> %va, i32 %b, i32 zeroext %evl) {1138; CHECK-LABEL: vadd_vx_nxv4i32_unmasked:1139; CHECK:       # %bb.0:1140; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma1141; CHECK-NEXT:    vadd.vx v8, v8, a01142; CHECK-NEXT:    ret1143  %elt.head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 01144  %vb = shufflevector <vscale x 4 x i32> %elt.head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer1145  %v = call <vscale x 4 x i32> @llvm.vp.add.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb, <vscale x 4 x i1> splat (i1 true), i32 %evl)1146  ret <vscale x 4 x i32> %v1147}1148 1149define <vscale x 4 x i32> @vadd_vi_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {1150; CHECK-LABEL: vadd_vi_nxv4i32:1151; CHECK:       # %bb.0:1152; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma1153; CHECK-NEXT:    vadd.vi v8, v8, -1, v0.t1154; CHECK-NEXT:    ret1155  %v = call <vscale x 4 x i32> @llvm.vp.add.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> splat (i32 -1), <vscale x 4 x i1> %m, i32 %evl)1156  ret <vscale x 4 x i32> %v1157}1158 1159define <vscale x 4 x i32> @vadd_vi_nxv4i32_unmasked(<vscale x 4 x i32> %va, i32 zeroext %evl) {1160; CHECK-LABEL: vadd_vi_nxv4i32_unmasked:1161; CHECK:       # %bb.0:1162; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma1163; CHECK-NEXT:    vadd.vi v8, v8, -11164; CHECK-NEXT:    ret1165  %v = call <vscale x 4 x i32> @llvm.vp.add.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> splat (i32 -1), <vscale x 4 x i1> splat (i1 true), i32 %evl)1166  ret <vscale x 4 x i32> %v1167}1168 1169define <vscale x 8 x i32> @vadd_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {1170; CHECK-LABEL: vadd_vv_nxv8i32:1171; CHECK:       # %bb.0:1172; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma1173; CHECK-NEXT:    vadd.vv v8, v8, v12, v0.t1174; CHECK-NEXT:    ret1175  %v = call <vscale x 8 x i32> @llvm.vp.add.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %b, <vscale x 8 x i1> %m, i32 %evl)1176  ret <vscale x 8 x i32> %v1177}1178 1179define <vscale x 8 x i32> @vadd_vv_nxv8i32_unmasked(<vscale x 8 x i32> %va, <vscale x 8 x i32> %b, i32 zeroext %evl) {1180; CHECK-LABEL: vadd_vv_nxv8i32_unmasked:1181; CHECK:       # %bb.0:1182; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma1183; CHECK-NEXT:    vadd.vv v8, v8, v121184; CHECK-NEXT:    ret1185  %v = call <vscale x 8 x i32> @llvm.vp.add.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %b, <vscale x 8 x i1> splat (i1 true), i32 %evl)1186  ret <vscale x 8 x i32> %v1187}1188 1189define <vscale x 8 x i32> @vadd_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {1190; CHECK-LABEL: vadd_vx_nxv8i32:1191; CHECK:       # %bb.0:1192; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma1193; CHECK-NEXT:    vadd.vx v8, v8, a0, v0.t1194; CHECK-NEXT:    ret1195  %elt.head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 01196  %vb = shufflevector <vscale x 8 x i32> %elt.head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer1197  %v = call <vscale x 8 x i32> @llvm.vp.add.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %m, i32 %evl)1198  ret <vscale x 8 x i32> %v1199}1200 1201define <vscale x 8 x i32> @vadd_vx_nxv8i32_unmasked(<vscale x 8 x i32> %va, i32 %b, i32 zeroext %evl) {1202; CHECK-LABEL: vadd_vx_nxv8i32_unmasked:1203; CHECK:       # %bb.0:1204; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma1205; CHECK-NEXT:    vadd.vx v8, v8, a01206; CHECK-NEXT:    ret1207  %elt.head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 01208  %vb = shufflevector <vscale x 8 x i32> %elt.head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer1209  %v = call <vscale x 8 x i32> @llvm.vp.add.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> splat (i1 true), i32 %evl)1210  ret <vscale x 8 x i32> %v1211}1212 1213define <vscale x 8 x i32> @vadd_vi_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {1214; CHECK-LABEL: vadd_vi_nxv8i32:1215; CHECK:       # %bb.0:1216; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma1217; CHECK-NEXT:    vadd.vi v8, v8, -1, v0.t1218; CHECK-NEXT:    ret1219  %v = call <vscale x 8 x i32> @llvm.vp.add.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> splat (i32 -1), <vscale x 8 x i1> %m, i32 %evl)1220  ret <vscale x 8 x i32> %v1221}1222 1223define <vscale x 8 x i32> @vadd_vi_nxv8i32_unmasked(<vscale x 8 x i32> %va, i32 zeroext %evl) {1224; CHECK-LABEL: vadd_vi_nxv8i32_unmasked:1225; CHECK:       # %bb.0:1226; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma1227; CHECK-NEXT:    vadd.vi v8, v8, -11228; CHECK-NEXT:    ret1229  %v = call <vscale x 8 x i32> @llvm.vp.add.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> splat (i32 -1), <vscale x 8 x i1> splat (i1 true), i32 %evl)1230  ret <vscale x 8 x i32> %v1231}1232 1233define <vscale x 16 x i32> @vadd_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {1234; CHECK-LABEL: vadd_vv_nxv16i32:1235; CHECK:       # %bb.0:1236; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma1237; CHECK-NEXT:    vadd.vv v8, v8, v16, v0.t1238; CHECK-NEXT:    ret1239  %v = call <vscale x 16 x i32> @llvm.vp.add.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %b, <vscale x 16 x i1> %m, i32 %evl)1240  ret <vscale x 16 x i32> %v1241}1242 1243define <vscale x 16 x i32> @vadd_vv_nxv16i32_unmasked(<vscale x 16 x i32> %va, <vscale x 16 x i32> %b, i32 zeroext %evl) {1244; CHECK-LABEL: vadd_vv_nxv16i32_unmasked:1245; CHECK:       # %bb.0:1246; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma1247; CHECK-NEXT:    vadd.vv v8, v8, v161248; CHECK-NEXT:    ret1249  %v = call <vscale x 16 x i32> @llvm.vp.add.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %b, <vscale x 16 x i1> splat (i1 true), i32 %evl)1250  ret <vscale x 16 x i32> %v1251}1252 1253define <vscale x 16 x i32> @vadd_vx_nxv16i32(<vscale x 16 x i32> %va, i32 %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {1254; CHECK-LABEL: vadd_vx_nxv16i32:1255; CHECK:       # %bb.0:1256; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, ma1257; CHECK-NEXT:    vadd.vx v8, v8, a0, v0.t1258; CHECK-NEXT:    ret1259  %elt.head = insertelement <vscale x 16 x i32> poison, i32 %b, i32 01260  %vb = shufflevector <vscale x 16 x i32> %elt.head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer1261  %v = call <vscale x 16 x i32> @llvm.vp.add.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb, <vscale x 16 x i1> %m, i32 %evl)1262  ret <vscale x 16 x i32> %v1263}1264 1265define <vscale x 16 x i32> @vadd_vx_nxv16i32_unmasked(<vscale x 16 x i32> %va, i32 %b, i32 zeroext %evl) {1266; CHECK-LABEL: vadd_vx_nxv16i32_unmasked:1267; CHECK:       # %bb.0:1268; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, ma1269; CHECK-NEXT:    vadd.vx v8, v8, a01270; CHECK-NEXT:    ret1271  %elt.head = insertelement <vscale x 16 x i32> poison, i32 %b, i32 01272  %vb = shufflevector <vscale x 16 x i32> %elt.head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer1273  %v = call <vscale x 16 x i32> @llvm.vp.add.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb, <vscale x 16 x i1> splat (i1 true), i32 %evl)1274  ret <vscale x 16 x i32> %v1275}1276 1277define <vscale x 16 x i32> @vadd_vi_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {1278; CHECK-LABEL: vadd_vi_nxv16i32:1279; CHECK:       # %bb.0:1280; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma1281; CHECK-NEXT:    vadd.vi v8, v8, -1, v0.t1282; CHECK-NEXT:    ret1283  %v = call <vscale x 16 x i32> @llvm.vp.add.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> splat (i32 -1), <vscale x 16 x i1> %m, i32 %evl)1284  ret <vscale x 16 x i32> %v1285}1286 1287define <vscale x 16 x i32> @vadd_vi_nxv16i32_unmasked(<vscale x 16 x i32> %va, i32 zeroext %evl) {1288; CHECK-LABEL: vadd_vi_nxv16i32_unmasked:1289; CHECK:       # %bb.0:1290; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma1291; CHECK-NEXT:    vadd.vi v8, v8, -11292; CHECK-NEXT:    ret1293  %v = call <vscale x 16 x i32> @llvm.vp.add.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> splat (i32 -1), <vscale x 16 x i1> splat (i1 true), i32 %evl)1294  ret <vscale x 16 x i32> %v1295}1296 1297; Test that split-legalization works then the mask needs manual splitting.1298 1299define <vscale x 32 x i32> @vadd_vi_nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {1300; CHECK-LABEL: vadd_vi_nxv32i32:1301; CHECK:       # %bb.0:1302; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma1303; CHECK-NEXT:    vmv1r.v v24, v01304; CHECK-NEXT:    csrr a1, vlenb1305; CHECK-NEXT:    srli a2, a1, 21306; CHECK-NEXT:    slli a1, a1, 11307; CHECK-NEXT:    vslidedown.vx v0, v0, a21308; CHECK-NEXT:    sub a2, a0, a11309; CHECK-NEXT:    sltu a3, a0, a21310; CHECK-NEXT:    addi a3, a3, -11311; CHECK-NEXT:    and a2, a3, a21312; CHECK-NEXT:    vsetvli zero, a2, e32, m8, ta, ma1313; CHECK-NEXT:    vadd.vi v16, v16, -1, v0.t1314; CHECK-NEXT:    bltu a0, a1, .LBB118_21315; CHECK-NEXT:  # %bb.1:1316; CHECK-NEXT:    mv a0, a11317; CHECK-NEXT:  .LBB118_2:1318; CHECK-NEXT:    vmv1r.v v0, v241319; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma1320; CHECK-NEXT:    vadd.vi v8, v8, -1, v0.t1321; CHECK-NEXT:    ret1322  %v = call <vscale x 32 x i32> @llvm.vp.add.nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i32> splat (i32 -1), <vscale x 32 x i1> %m, i32 %evl)1323  ret <vscale x 32 x i32> %v1324}1325 1326define <vscale x 32 x i32> @vadd_vi_nxv32i32_unmasked(<vscale x 32 x i32> %va, i32 zeroext %evl) {1327; CHECK-LABEL: vadd_vi_nxv32i32_unmasked:1328; CHECK:       # %bb.0:1329; CHECK-NEXT:    csrr a1, vlenb1330; CHECK-NEXT:    slli a1, a1, 11331; CHECK-NEXT:    sub a2, a0, a11332; CHECK-NEXT:    sltu a3, a0, a21333; CHECK-NEXT:    addi a3, a3, -11334; CHECK-NEXT:    and a2, a3, a21335; CHECK-NEXT:    vsetvli zero, a2, e32, m8, ta, ma1336; CHECK-NEXT:    vadd.vi v16, v16, -11337; CHECK-NEXT:    bltu a0, a1, .LBB119_21338; CHECK-NEXT:  # %bb.1:1339; CHECK-NEXT:    mv a0, a11340; CHECK-NEXT:  .LBB119_2:1341; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma1342; CHECK-NEXT:    vadd.vi v8, v8, -11343; CHECK-NEXT:    ret1344  %v = call <vscale x 32 x i32> @llvm.vp.add.nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i32> splat (i32 -1), <vscale x 32 x i1> splat (i1 true), i32 %evl)1345  ret <vscale x 32 x i32> %v1346}1347 1348; Test splitting when the %evl is a constant (albeit an unknown one).1349 1350define <vscale x 32 x i32> @vadd_vi_nxv32i32_evl_nx8(<vscale x 32 x i32> %va, <vscale x 32 x i1> %m) {1351; RV32-LABEL: vadd_vi_nxv32i32_evl_nx8:1352; RV32:       # %bb.0:1353; RV32-NEXT:    csrr a0, vlenb1354; RV32-NEXT:    srli a1, a0, 21355; RV32-NEXT:    vsetvli zero, a0, e32, m8, ta, ma1356; RV32-NEXT:    vadd.vi v8, v8, -1, v0.t1357; RV32-NEXT:    vsetvli a2, zero, e8, mf2, ta, ma1358; RV32-NEXT:    vslidedown.vx v0, v0, a11359; RV32-NEXT:    slli a1, a0, 11360; RV32-NEXT:    sub a1, a0, a11361; RV32-NEXT:    sltu a0, a0, a11362; RV32-NEXT:    addi a0, a0, -11363; RV32-NEXT:    and a0, a0, a11364; RV32-NEXT:    vsetvli zero, a0, e32, m8, ta, ma1365; RV32-NEXT:    vadd.vi v16, v16, -1, v0.t1366; RV32-NEXT:    ret1367;1368; RV64-LABEL: vadd_vi_nxv32i32_evl_nx8:1369; RV64:       # %bb.0:1370; RV64-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma1371; RV64-NEXT:    vmv1r.v v24, v01372; RV64-NEXT:    csrr a0, vlenb1373; RV64-NEXT:    srli a2, a0, 21374; RV64-NEXT:    slli a1, a0, 11375; RV64-NEXT:    vslidedown.vx v0, v0, a21376; RV64-NEXT:    sub a2, a0, a11377; RV64-NEXT:    sltu a3, a0, a21378; RV64-NEXT:    addi a3, a3, -11379; RV64-NEXT:    and a2, a3, a21380; RV64-NEXT:    vsetvli zero, a2, e32, m8, ta, ma1381; RV64-NEXT:    vadd.vi v16, v16, -1, v0.t1382; RV64-NEXT:    bltu a0, a1, .LBB120_21383; RV64-NEXT:  # %bb.1:1384; RV64-NEXT:    mv a0, a11385; RV64-NEXT:  .LBB120_2:1386; RV64-NEXT:    vmv1r.v v0, v241387; RV64-NEXT:    vsetvli zero, a0, e32, m8, ta, ma1388; RV64-NEXT:    vadd.vi v8, v8, -1, v0.t1389; RV64-NEXT:    ret1390  %evl = call i32 @llvm.vscale.i32()1391  %evl0 = mul i32 %evl, 81392  %v = call <vscale x 32 x i32> @llvm.vp.add.nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i32> splat (i32 -1), <vscale x 32 x i1> %m, i32 %evl0)1393  ret <vscale x 32 x i32> %v1394}1395 1396; The attribute vscale_range(2,1024) given here can remove the zero_extend for1397; the i32 %evl to i64 on RV64 through KnownBits analysis.1398 1399define <vscale x 32 x i32> @vadd_vi_nxv32i32_evl_nx16(<vscale x 32 x i32> %va, <vscale x 32 x i1> %m) vscale_range(2,1024) {1400; CHECK-LABEL: vadd_vi_nxv32i32_evl_nx16:1401; CHECK:       # %bb.0:1402; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, ma1403; CHECK-NEXT:    vadd.vi v8, v8, -1, v0.t1404; CHECK-NEXT:    ret1405  %evl = call i32 @llvm.vscale.i32()1406  %evl0 = mul i32 %evl, 161407  %v = call <vscale x 32 x i32> @llvm.vp.add.nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i32> splat (i32 -1), <vscale x 32 x i1> %m, i32 %evl0)1408  ret <vscale x 32 x i32> %v1409}1410 1411define <vscale x 1 x i64> @vadd_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {1412; CHECK-LABEL: vadd_vv_nxv1i64:1413; CHECK:       # %bb.0:1414; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma1415; CHECK-NEXT:    vadd.vv v8, v8, v9, v0.t1416; CHECK-NEXT:    ret1417  %v = call <vscale x 1 x i64> @llvm.vp.add.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %b, <vscale x 1 x i1> %m, i32 %evl)1418  ret <vscale x 1 x i64> %v1419}1420 1421define <vscale x 1 x i64> @vadd_vv_nxv1i64_unmasked(<vscale x 1 x i64> %va, <vscale x 1 x i64> %b, i32 zeroext %evl) {1422; CHECK-LABEL: vadd_vv_nxv1i64_unmasked:1423; CHECK:       # %bb.0:1424; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma1425; CHECK-NEXT:    vadd.vv v8, v8, v91426; CHECK-NEXT:    ret1427  %v = call <vscale x 1 x i64> @llvm.vp.add.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %b, <vscale x 1 x i1> splat (i1 true), i32 %evl)1428  ret <vscale x 1 x i64> %v1429}1430 1431define <vscale x 1 x i64> @vadd_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {1432; RV32-LABEL: vadd_vx_nxv1i64:1433; RV32:       # %bb.0:1434; RV32-NEXT:    addi sp, sp, -161435; RV32-NEXT:    .cfi_def_cfa_offset 161436; RV32-NEXT:    sw a0, 8(sp)1437; RV32-NEXT:    sw a1, 12(sp)1438; RV32-NEXT:    addi a0, sp, 81439; RV32-NEXT:    vsetvli zero, a2, e64, m1, ta, ma1440; RV32-NEXT:    vlse64.v v9, (a0), zero1441; RV32-NEXT:    vadd.vv v8, v8, v9, v0.t1442; RV32-NEXT:    addi sp, sp, 161443; RV32-NEXT:    .cfi_def_cfa_offset 01444; RV32-NEXT:    ret1445;1446; RV64-LABEL: vadd_vx_nxv1i64:1447; RV64:       # %bb.0:1448; RV64-NEXT:    vsetvli zero, a1, e64, m1, ta, ma1449; RV64-NEXT:    vadd.vx v8, v8, a0, v0.t1450; RV64-NEXT:    ret1451  %elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 01452  %vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer1453  %v = call <vscale x 1 x i64> @llvm.vp.add.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, <vscale x 1 x i1> %m, i32 %evl)1454  ret <vscale x 1 x i64> %v1455}1456 1457define <vscale x 1 x i64> @vadd_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64 %b, i32 zeroext %evl) {1458; RV32-LABEL: vadd_vx_nxv1i64_unmasked:1459; RV32:       # %bb.0:1460; RV32-NEXT:    addi sp, sp, -161461; RV32-NEXT:    .cfi_def_cfa_offset 161462; RV32-NEXT:    sw a0, 8(sp)1463; RV32-NEXT:    sw a1, 12(sp)1464; RV32-NEXT:    addi a0, sp, 81465; RV32-NEXT:    vsetvli zero, a2, e64, m1, ta, ma1466; RV32-NEXT:    vlse64.v v9, (a0), zero1467; RV32-NEXT:    vadd.vv v8, v8, v91468; RV32-NEXT:    addi sp, sp, 161469; RV32-NEXT:    .cfi_def_cfa_offset 01470; RV32-NEXT:    ret1471;1472; RV64-LABEL: vadd_vx_nxv1i64_unmasked:1473; RV64:       # %bb.0:1474; RV64-NEXT:    vsetvli zero, a1, e64, m1, ta, ma1475; RV64-NEXT:    vadd.vx v8, v8, a01476; RV64-NEXT:    ret1477  %elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 01478  %vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer1479  %v = call <vscale x 1 x i64> @llvm.vp.add.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, <vscale x 1 x i1> splat (i1 true), i32 %evl)1480  ret <vscale x 1 x i64> %v1481}1482 1483define <vscale x 1 x i64> @vadd_vi_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {1484; CHECK-LABEL: vadd_vi_nxv1i64:1485; CHECK:       # %bb.0:1486; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma1487; CHECK-NEXT:    vadd.vi v8, v8, -1, v0.t1488; CHECK-NEXT:    ret1489  %v = call <vscale x 1 x i64> @llvm.vp.add.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> splat (i64 -1), <vscale x 1 x i1> %m, i32 %evl)1490  ret <vscale x 1 x i64> %v1491}1492 1493define <vscale x 1 x i64> @vadd_vi_nxv1i64_unmasked(<vscale x 1 x i64> %va, i32 zeroext %evl) {1494; CHECK-LABEL: vadd_vi_nxv1i64_unmasked:1495; CHECK:       # %bb.0:1496; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma1497; CHECK-NEXT:    vadd.vi v8, v8, -11498; CHECK-NEXT:    ret1499  %v = call <vscale x 1 x i64> @llvm.vp.add.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> splat (i64 -1), <vscale x 1 x i1> splat (i1 true), i32 %evl)1500  ret <vscale x 1 x i64> %v1501}1502 1503define <vscale x 2 x i64> @vadd_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {1504; CHECK-LABEL: vadd_vv_nxv2i64:1505; CHECK:       # %bb.0:1506; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma1507; CHECK-NEXT:    vadd.vv v8, v8, v10, v0.t1508; CHECK-NEXT:    ret1509  %v = call <vscale x 2 x i64> @llvm.vp.add.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %b, <vscale x 2 x i1> %m, i32 %evl)1510  ret <vscale x 2 x i64> %v1511}1512 1513define <vscale x 2 x i64> @vadd_vv_nxv2i64_unmasked(<vscale x 2 x i64> %va, <vscale x 2 x i64> %b, i32 zeroext %evl) {1514; CHECK-LABEL: vadd_vv_nxv2i64_unmasked:1515; CHECK:       # %bb.0:1516; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma1517; CHECK-NEXT:    vadd.vv v8, v8, v101518; CHECK-NEXT:    ret1519  %v = call <vscale x 2 x i64> @llvm.vp.add.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %b, <vscale x 2 x i1> splat (i1 true), i32 %evl)1520  ret <vscale x 2 x i64> %v1521}1522 1523define <vscale x 2 x i64> @vadd_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {1524; RV32-LABEL: vadd_vx_nxv2i64:1525; RV32:       # %bb.0:1526; RV32-NEXT:    addi sp, sp, -161527; RV32-NEXT:    .cfi_def_cfa_offset 161528; RV32-NEXT:    sw a0, 8(sp)1529; RV32-NEXT:    sw a1, 12(sp)1530; RV32-NEXT:    addi a0, sp, 81531; RV32-NEXT:    vsetvli zero, a2, e64, m2, ta, ma1532; RV32-NEXT:    vlse64.v v10, (a0), zero1533; RV32-NEXT:    vadd.vv v8, v8, v10, v0.t1534; RV32-NEXT:    addi sp, sp, 161535; RV32-NEXT:    .cfi_def_cfa_offset 01536; RV32-NEXT:    ret1537;1538; RV64-LABEL: vadd_vx_nxv2i64:1539; RV64:       # %bb.0:1540; RV64-NEXT:    vsetvli zero, a1, e64, m2, ta, ma1541; RV64-NEXT:    vadd.vx v8, v8, a0, v0.t1542; RV64-NEXT:    ret1543  %elt.head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 01544  %vb = shufflevector <vscale x 2 x i64> %elt.head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer1545  %v = call <vscale x 2 x i64> @llvm.vp.add.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, <vscale x 2 x i1> %m, i32 %evl)1546  ret <vscale x 2 x i64> %v1547}1548 1549define <vscale x 2 x i64> @vadd_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64 %b, i32 zeroext %evl) {1550; RV32-LABEL: vadd_vx_nxv2i64_unmasked:1551; RV32:       # %bb.0:1552; RV32-NEXT:    addi sp, sp, -161553; RV32-NEXT:    .cfi_def_cfa_offset 161554; RV32-NEXT:    sw a0, 8(sp)1555; RV32-NEXT:    sw a1, 12(sp)1556; RV32-NEXT:    addi a0, sp, 81557; RV32-NEXT:    vsetvli zero, a2, e64, m2, ta, ma1558; RV32-NEXT:    vlse64.v v10, (a0), zero1559; RV32-NEXT:    vadd.vv v8, v8, v101560; RV32-NEXT:    addi sp, sp, 161561; RV32-NEXT:    .cfi_def_cfa_offset 01562; RV32-NEXT:    ret1563;1564; RV64-LABEL: vadd_vx_nxv2i64_unmasked:1565; RV64:       # %bb.0:1566; RV64-NEXT:    vsetvli zero, a1, e64, m2, ta, ma1567; RV64-NEXT:    vadd.vx v8, v8, a01568; RV64-NEXT:    ret1569  %elt.head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 01570  %vb = shufflevector <vscale x 2 x i64> %elt.head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer1571  %v = call <vscale x 2 x i64> @llvm.vp.add.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, <vscale x 2 x i1> splat (i1 true), i32 %evl)1572  ret <vscale x 2 x i64> %v1573}1574 1575define <vscale x 2 x i64> @vadd_vi_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {1576; CHECK-LABEL: vadd_vi_nxv2i64:1577; CHECK:       # %bb.0:1578; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma1579; CHECK-NEXT:    vadd.vi v8, v8, -1, v0.t1580; CHECK-NEXT:    ret1581  %v = call <vscale x 2 x i64> @llvm.vp.add.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> splat (i64 -1), <vscale x 2 x i1> %m, i32 %evl)1582  ret <vscale x 2 x i64> %v1583}1584 1585define <vscale x 2 x i64> @vadd_vi_nxv2i64_unmasked(<vscale x 2 x i64> %va, i32 zeroext %evl) {1586; CHECK-LABEL: vadd_vi_nxv2i64_unmasked:1587; CHECK:       # %bb.0:1588; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma1589; CHECK-NEXT:    vadd.vi v8, v8, -11590; CHECK-NEXT:    ret1591  %v = call <vscale x 2 x i64> @llvm.vp.add.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> splat (i64 -1), <vscale x 2 x i1> splat (i1 true), i32 %evl)1592  ret <vscale x 2 x i64> %v1593}1594 1595define <vscale x 4 x i64> @vadd_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {1596; CHECK-LABEL: vadd_vv_nxv4i64:1597; CHECK:       # %bb.0:1598; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma1599; CHECK-NEXT:    vadd.vv v8, v8, v12, v0.t1600; CHECK-NEXT:    ret1601  %v = call <vscale x 4 x i64> @llvm.vp.add.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %b, <vscale x 4 x i1> %m, i32 %evl)1602  ret <vscale x 4 x i64> %v1603}1604 1605define <vscale x 4 x i64> @vadd_vv_nxv4i64_unmasked(<vscale x 4 x i64> %va, <vscale x 4 x i64> %b, i32 zeroext %evl) {1606; CHECK-LABEL: vadd_vv_nxv4i64_unmasked:1607; CHECK:       # %bb.0:1608; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma1609; CHECK-NEXT:    vadd.vv v8, v8, v121610; CHECK-NEXT:    ret1611  %v = call <vscale x 4 x i64> @llvm.vp.add.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %b, <vscale x 4 x i1> splat (i1 true), i32 %evl)1612  ret <vscale x 4 x i64> %v1613}1614 1615define <vscale x 4 x i64> @vadd_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {1616; RV32-LABEL: vadd_vx_nxv4i64:1617; RV32:       # %bb.0:1618; RV32-NEXT:    addi sp, sp, -161619; RV32-NEXT:    .cfi_def_cfa_offset 161620; RV32-NEXT:    sw a0, 8(sp)1621; RV32-NEXT:    sw a1, 12(sp)1622; RV32-NEXT:    addi a0, sp, 81623; RV32-NEXT:    vsetvli zero, a2, e64, m4, ta, ma1624; RV32-NEXT:    vlse64.v v12, (a0), zero1625; RV32-NEXT:    vadd.vv v8, v8, v12, v0.t1626; RV32-NEXT:    addi sp, sp, 161627; RV32-NEXT:    .cfi_def_cfa_offset 01628; RV32-NEXT:    ret1629;1630; RV64-LABEL: vadd_vx_nxv4i64:1631; RV64:       # %bb.0:1632; RV64-NEXT:    vsetvli zero, a1, e64, m4, ta, ma1633; RV64-NEXT:    vadd.vx v8, v8, a0, v0.t1634; RV64-NEXT:    ret1635  %elt.head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 01636  %vb = shufflevector <vscale x 4 x i64> %elt.head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer1637  %v = call <vscale x 4 x i64> @llvm.vp.add.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb, <vscale x 4 x i1> %m, i32 %evl)1638  ret <vscale x 4 x i64> %v1639}1640 1641define <vscale x 4 x i64> @vadd_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64 %b, i32 zeroext %evl) {1642; RV32-LABEL: vadd_vx_nxv4i64_unmasked:1643; RV32:       # %bb.0:1644; RV32-NEXT:    addi sp, sp, -161645; RV32-NEXT:    .cfi_def_cfa_offset 161646; RV32-NEXT:    sw a0, 8(sp)1647; RV32-NEXT:    sw a1, 12(sp)1648; RV32-NEXT:    addi a0, sp, 81649; RV32-NEXT:    vsetvli zero, a2, e64, m4, ta, ma1650; RV32-NEXT:    vlse64.v v12, (a0), zero1651; RV32-NEXT:    vadd.vv v8, v8, v121652; RV32-NEXT:    addi sp, sp, 161653; RV32-NEXT:    .cfi_def_cfa_offset 01654; RV32-NEXT:    ret1655;1656; RV64-LABEL: vadd_vx_nxv4i64_unmasked:1657; RV64:       # %bb.0:1658; RV64-NEXT:    vsetvli zero, a1, e64, m4, ta, ma1659; RV64-NEXT:    vadd.vx v8, v8, a01660; RV64-NEXT:    ret1661  %elt.head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 01662  %vb = shufflevector <vscale x 4 x i64> %elt.head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer1663  %v = call <vscale x 4 x i64> @llvm.vp.add.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb, <vscale x 4 x i1> splat (i1 true), i32 %evl)1664  ret <vscale x 4 x i64> %v1665}1666 1667define <vscale x 4 x i64> @vadd_vi_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {1668; CHECK-LABEL: vadd_vi_nxv4i64:1669; CHECK:       # %bb.0:1670; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma1671; CHECK-NEXT:    vadd.vi v8, v8, -1, v0.t1672; CHECK-NEXT:    ret1673  %v = call <vscale x 4 x i64> @llvm.vp.add.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> splat (i64 -1), <vscale x 4 x i1> %m, i32 %evl)1674  ret <vscale x 4 x i64> %v1675}1676 1677define <vscale x 4 x i64> @vadd_vi_nxv4i64_unmasked(<vscale x 4 x i64> %va, i32 zeroext %evl) {1678; CHECK-LABEL: vadd_vi_nxv4i64_unmasked:1679; CHECK:       # %bb.0:1680; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma1681; CHECK-NEXT:    vadd.vi v8, v8, -11682; CHECK-NEXT:    ret1683  %v = call <vscale x 4 x i64> @llvm.vp.add.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> splat (i64 -1), <vscale x 4 x i1> splat (i1 true), i32 %evl)1684  ret <vscale x 4 x i64> %v1685}1686 1687define <vscale x 8 x i64> @vadd_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {1688; CHECK-LABEL: vadd_vv_nxv8i64:1689; CHECK:       # %bb.0:1690; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma1691; CHECK-NEXT:    vadd.vv v8, v8, v16, v0.t1692; CHECK-NEXT:    ret1693  %v = call <vscale x 8 x i64> @llvm.vp.add.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %b, <vscale x 8 x i1> %m, i32 %evl)1694  ret <vscale x 8 x i64> %v1695}1696 1697define <vscale x 8 x i64> @vadd_vv_nxv8i64_unmasked(<vscale x 8 x i64> %va, <vscale x 8 x i64> %b, i32 zeroext %evl) {1698; CHECK-LABEL: vadd_vv_nxv8i64_unmasked:1699; CHECK:       # %bb.0:1700; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma1701; CHECK-NEXT:    vadd.vv v8, v8, v161702; CHECK-NEXT:    ret1703  %v = call <vscale x 8 x i64> @llvm.vp.add.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %b, <vscale x 8 x i1> splat (i1 true), i32 %evl)1704  ret <vscale x 8 x i64> %v1705}1706 1707define <vscale x 8 x i64> @vadd_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {1708; RV32-LABEL: vadd_vx_nxv8i64:1709; RV32:       # %bb.0:1710; RV32-NEXT:    addi sp, sp, -161711; RV32-NEXT:    .cfi_def_cfa_offset 161712; RV32-NEXT:    sw a0, 8(sp)1713; RV32-NEXT:    sw a1, 12(sp)1714; RV32-NEXT:    addi a0, sp, 81715; RV32-NEXT:    vsetvli zero, a2, e64, m8, ta, ma1716; RV32-NEXT:    vlse64.v v16, (a0), zero1717; RV32-NEXT:    vadd.vv v8, v8, v16, v0.t1718; RV32-NEXT:    addi sp, sp, 161719; RV32-NEXT:    .cfi_def_cfa_offset 01720; RV32-NEXT:    ret1721;1722; RV64-LABEL: vadd_vx_nxv8i64:1723; RV64:       # %bb.0:1724; RV64-NEXT:    vsetvli zero, a1, e64, m8, ta, ma1725; RV64-NEXT:    vadd.vx v8, v8, a0, v0.t1726; RV64-NEXT:    ret1727  %elt.head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 01728  %vb = shufflevector <vscale x 8 x i64> %elt.head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer1729  %v = call <vscale x 8 x i64> @llvm.vp.add.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb, <vscale x 8 x i1> %m, i32 %evl)1730  ret <vscale x 8 x i64> %v1731}1732 1733define <vscale x 8 x i64> @vadd_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64 %b, i32 zeroext %evl) {1734; RV32-LABEL: vadd_vx_nxv8i64_unmasked:1735; RV32:       # %bb.0:1736; RV32-NEXT:    addi sp, sp, -161737; RV32-NEXT:    .cfi_def_cfa_offset 161738; RV32-NEXT:    sw a0, 8(sp)1739; RV32-NEXT:    sw a1, 12(sp)1740; RV32-NEXT:    addi a0, sp, 81741; RV32-NEXT:    vsetvli zero, a2, e64, m8, ta, ma1742; RV32-NEXT:    vlse64.v v16, (a0), zero1743; RV32-NEXT:    vadd.vv v8, v8, v161744; RV32-NEXT:    addi sp, sp, 161745; RV32-NEXT:    .cfi_def_cfa_offset 01746; RV32-NEXT:    ret1747;1748; RV64-LABEL: vadd_vx_nxv8i64_unmasked:1749; RV64:       # %bb.0:1750; RV64-NEXT:    vsetvli zero, a1, e64, m8, ta, ma1751; RV64-NEXT:    vadd.vx v8, v8, a01752; RV64-NEXT:    ret1753  %elt.head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 01754  %vb = shufflevector <vscale x 8 x i64> %elt.head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer1755  %v = call <vscale x 8 x i64> @llvm.vp.add.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb, <vscale x 8 x i1> splat (i1 true), i32 %evl)1756  ret <vscale x 8 x i64> %v1757}1758 1759define <vscale x 8 x i64> @vadd_vi_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {1760; CHECK-LABEL: vadd_vi_nxv8i64:1761; CHECK:       # %bb.0:1762; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma1763; CHECK-NEXT:    vadd.vi v8, v8, -1, v0.t1764; CHECK-NEXT:    ret1765  %v = call <vscale x 8 x i64> @llvm.vp.add.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> splat (i64 -1), <vscale x 8 x i1> %m, i32 %evl)1766  ret <vscale x 8 x i64> %v1767}1768 1769define <vscale x 8 x i64> @vadd_vi_nxv8i64_unmasked(<vscale x 8 x i64> %va, i32 zeroext %evl) {1770; CHECK-LABEL: vadd_vi_nxv8i64_unmasked:1771; CHECK:       # %bb.0:1772; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma1773; CHECK-NEXT:    vadd.vi v8, v8, -11774; CHECK-NEXT:    ret1775  %v = call <vscale x 8 x i64> @llvm.vp.add.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> splat (i64 -1), <vscale x 8 x i1> splat (i1 true), i32 %evl)1776  ret <vscale x 8 x i64> %v1777}1778