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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \3; RUN:   -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV324; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \5; RUN:   -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV646 7define <vscale x 1 x i8> @intrinsic_vadd_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {8; CHECK-LABEL: intrinsic_vadd_vv_nxv1i8_nxv1i8_nxv1i8:9; CHECK:       # %bb.0: # %entry10; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma11; CHECK-NEXT:    vadd.vv v8, v8, v912; CHECK-NEXT:    ret13entry:14  %a = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8(15    <vscale x 1 x i8> poison,16    <vscale x 1 x i8> %0,17    <vscale x 1 x i8> %1,18    iXLen %2)19 20  ret <vscale x 1 x i8> %a21}22 23define <vscale x 1 x i8> @intrinsic_vadd_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {24; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv1i8_nxv1i8_nxv1i8:25; CHECK:       # %bb.0: # %entry26; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, mu27; CHECK-NEXT:    vadd.vv v8, v9, v10, v0.t28; CHECK-NEXT:    ret29entry:30  %a = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8(31    <vscale x 1 x i8> %0,32    <vscale x 1 x i8> %1,33    <vscale x 1 x i8> %2,34    <vscale x 1 x i1> %3,35    iXLen %4, iXLen 1)36 37  ret <vscale x 1 x i8> %a38}39 40define <vscale x 2 x i8> @intrinsic_vadd_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, iXLen %2) nounwind {41; CHECK-LABEL: intrinsic_vadd_vv_nxv2i8_nxv2i8_nxv2i8:42; CHECK:       # %bb.0: # %entry43; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma44; CHECK-NEXT:    vadd.vv v8, v8, v945; CHECK-NEXT:    ret46entry:47  %a = call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.nxv2i8(48    <vscale x 2 x i8> poison,49    <vscale x 2 x i8> %0,50    <vscale x 2 x i8> %1,51    iXLen %2)52 53  ret <vscale x 2 x i8> %a54}55 56define <vscale x 2 x i8> @intrinsic_vadd_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {57; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv2i8_nxv2i8_nxv2i8:58; CHECK:       # %bb.0: # %entry59; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, mu60; CHECK-NEXT:    vadd.vv v8, v9, v10, v0.t61; CHECK-NEXT:    ret62entry:63  %a = call <vscale x 2 x i8> @llvm.riscv.vadd.mask.nxv2i8.nxv2i8(64    <vscale x 2 x i8> %0,65    <vscale x 2 x i8> %1,66    <vscale x 2 x i8> %2,67    <vscale x 2 x i1> %3,68    iXLen %4, iXLen 1)69 70  ret <vscale x 2 x i8> %a71}72 73define <vscale x 4 x i8> @intrinsic_vadd_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, iXLen %2) nounwind {74; CHECK-LABEL: intrinsic_vadd_vv_nxv4i8_nxv4i8_nxv4i8:75; CHECK:       # %bb.0: # %entry76; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma77; CHECK-NEXT:    vadd.vv v8, v8, v978; CHECK-NEXT:    ret79entry:80  %a = call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.nxv4i8(81    <vscale x 4 x i8> poison,82    <vscale x 4 x i8> %0,83    <vscale x 4 x i8> %1,84    iXLen %2)85 86  ret <vscale x 4 x i8> %a87}88 89define <vscale x 4 x i8> @intrinsic_vadd_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {90; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv4i8_nxv4i8_nxv4i8:91; CHECK:       # %bb.0: # %entry92; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, mu93; CHECK-NEXT:    vadd.vv v8, v9, v10, v0.t94; CHECK-NEXT:    ret95entry:96  %a = call <vscale x 4 x i8> @llvm.riscv.vadd.mask.nxv4i8.nxv4i8(97    <vscale x 4 x i8> %0,98    <vscale x 4 x i8> %1,99    <vscale x 4 x i8> %2,100    <vscale x 4 x i1> %3,101    iXLen %4, iXLen 1)102 103  ret <vscale x 4 x i8> %a104}105 106define <vscale x 8 x i8> @intrinsic_vadd_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, iXLen %2) nounwind {107; CHECK-LABEL: intrinsic_vadd_vv_nxv8i8_nxv8i8_nxv8i8:108; CHECK:       # %bb.0: # %entry109; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma110; CHECK-NEXT:    vadd.vv v8, v8, v9111; CHECK-NEXT:    ret112entry:113  %a = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.nxv8i8(114    <vscale x 8 x i8> poison,115    <vscale x 8 x i8> %0,116    <vscale x 8 x i8> %1,117    iXLen %2)118 119  ret <vscale x 8 x i8> %a120}121 122define <vscale x 8 x i8> @intrinsic_vadd_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {123; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv8i8_nxv8i8_nxv8i8:124; CHECK:       # %bb.0: # %entry125; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, mu126; CHECK-NEXT:    vadd.vv v8, v9, v10, v0.t127; CHECK-NEXT:    ret128entry:129  %a = call <vscale x 8 x i8> @llvm.riscv.vadd.mask.nxv8i8.nxv8i8(130    <vscale x 8 x i8> %0,131    <vscale x 8 x i8> %1,132    <vscale x 8 x i8> %2,133    <vscale x 8 x i1> %3,134    iXLen %4, iXLen 1)135 136  ret <vscale x 8 x i8> %a137}138 139define <vscale x 16 x i8> @intrinsic_vadd_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, iXLen %2) nounwind {140; CHECK-LABEL: intrinsic_vadd_vv_nxv16i8_nxv16i8_nxv16i8:141; CHECK:       # %bb.0: # %entry142; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma143; CHECK-NEXT:    vadd.vv v8, v8, v10144; CHECK-NEXT:    ret145entry:146  %a = call <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.nxv16i8(147    <vscale x 16 x i8> poison,148    <vscale x 16 x i8> %0,149    <vscale x 16 x i8> %1,150    iXLen %2)151 152  ret <vscale x 16 x i8> %a153}154 155define <vscale x 16 x i8> @intrinsic_vadd_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {156; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv16i8_nxv16i8_nxv16i8:157; CHECK:       # %bb.0: # %entry158; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, mu159; CHECK-NEXT:    vadd.vv v8, v10, v12, v0.t160; CHECK-NEXT:    ret161entry:162  %a = call <vscale x 16 x i8> @llvm.riscv.vadd.mask.nxv16i8.nxv16i8(163    <vscale x 16 x i8> %0,164    <vscale x 16 x i8> %1,165    <vscale x 16 x i8> %2,166    <vscale x 16 x i1> %3,167    iXLen %4, iXLen 1)168 169  ret <vscale x 16 x i8> %a170}171 172define <vscale x 32 x i8> @intrinsic_vadd_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, iXLen %2) nounwind {173; CHECK-LABEL: intrinsic_vadd_vv_nxv32i8_nxv32i8_nxv32i8:174; CHECK:       # %bb.0: # %entry175; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma176; CHECK-NEXT:    vadd.vv v8, v8, v12177; CHECK-NEXT:    ret178entry:179  %a = call <vscale x 32 x i8> @llvm.riscv.vadd.nxv32i8.nxv32i8(180    <vscale x 32 x i8> poison,181    <vscale x 32 x i8> %0,182    <vscale x 32 x i8> %1,183    iXLen %2)184 185  ret <vscale x 32 x i8> %a186}187 188define <vscale x 32 x i8> @intrinsic_vadd_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {189; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv32i8_nxv32i8_nxv32i8:190; CHECK:       # %bb.0: # %entry191; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, mu192; CHECK-NEXT:    vadd.vv v8, v12, v16, v0.t193; CHECK-NEXT:    ret194entry:195  %a = call <vscale x 32 x i8> @llvm.riscv.vadd.mask.nxv32i8.nxv32i8(196    <vscale x 32 x i8> %0,197    <vscale x 32 x i8> %1,198    <vscale x 32 x i8> %2,199    <vscale x 32 x i1> %3,200    iXLen %4, iXLen 1)201 202  ret <vscale x 32 x i8> %a203}204 205define <vscale x 64 x i8> @intrinsic_vadd_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, iXLen %2) nounwind {206; CHECK-LABEL: intrinsic_vadd_vv_nxv64i8_nxv64i8_nxv64i8:207; CHECK:       # %bb.0: # %entry208; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma209; CHECK-NEXT:    vadd.vv v8, v8, v16210; CHECK-NEXT:    ret211entry:212  %a = call <vscale x 64 x i8> @llvm.riscv.vadd.nxv64i8.nxv64i8(213    <vscale x 64 x i8> poison,214    <vscale x 64 x i8> %0,215    <vscale x 64 x i8> %1,216    iXLen %2)217 218  ret <vscale x 64 x i8> %a219}220 221define <vscale x 64 x i8> @intrinsic_vadd_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, iXLen %4) nounwind {222; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv64i8_nxv64i8_nxv64i8:223; CHECK:       # %bb.0: # %entry224; CHECK-NEXT:    vl8r.v v24, (a0)225; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, mu226; CHECK-NEXT:    vadd.vv v8, v16, v24, v0.t227; CHECK-NEXT:    ret228entry:229  %a = call <vscale x 64 x i8> @llvm.riscv.vadd.mask.nxv64i8.nxv64i8(230    <vscale x 64 x i8> %0,231    <vscale x 64 x i8> %1,232    <vscale x 64 x i8> %2,233    <vscale x 64 x i1> %3,234    iXLen %4, iXLen 1)235 236  ret <vscale x 64 x i8> %a237}238 239define <vscale x 1 x i16> @intrinsic_vadd_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, iXLen %2) nounwind {240; CHECK-LABEL: intrinsic_vadd_vv_nxv1i16_nxv1i16_nxv1i16:241; CHECK:       # %bb.0: # %entry242; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma243; CHECK-NEXT:    vadd.vv v8, v8, v9244; CHECK-NEXT:    ret245entry:246  %a = call <vscale x 1 x i16> @llvm.riscv.vadd.nxv1i16.nxv1i16(247    <vscale x 1 x i16> poison,248    <vscale x 1 x i16> %0,249    <vscale x 1 x i16> %1,250    iXLen %2)251 252  ret <vscale x 1 x i16> %a253}254 255define <vscale x 1 x i16> @intrinsic_vadd_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {256; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv1i16_nxv1i16_nxv1i16:257; CHECK:       # %bb.0: # %entry258; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, mu259; CHECK-NEXT:    vadd.vv v8, v9, v10, v0.t260; CHECK-NEXT:    ret261entry:262  %a = call <vscale x 1 x i16> @llvm.riscv.vadd.mask.nxv1i16.nxv1i16(263    <vscale x 1 x i16> %0,264    <vscale x 1 x i16> %1,265    <vscale x 1 x i16> %2,266    <vscale x 1 x i1> %3,267    iXLen %4, iXLen 1)268 269  ret <vscale x 1 x i16> %a270}271 272define <vscale x 2 x i16> @intrinsic_vadd_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, iXLen %2) nounwind {273; CHECK-LABEL: intrinsic_vadd_vv_nxv2i16_nxv2i16_nxv2i16:274; CHECK:       # %bb.0: # %entry275; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma276; CHECK-NEXT:    vadd.vv v8, v8, v9277; CHECK-NEXT:    ret278entry:279  %a = call <vscale x 2 x i16> @llvm.riscv.vadd.nxv2i16.nxv2i16(280    <vscale x 2 x i16> poison,281    <vscale x 2 x i16> %0,282    <vscale x 2 x i16> %1,283    iXLen %2)284 285  ret <vscale x 2 x i16> %a286}287 288define <vscale x 2 x i16> @intrinsic_vadd_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {289; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv2i16_nxv2i16_nxv2i16:290; CHECK:       # %bb.0: # %entry291; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, mu292; CHECK-NEXT:    vadd.vv v8, v9, v10, v0.t293; CHECK-NEXT:    ret294entry:295  %a = call <vscale x 2 x i16> @llvm.riscv.vadd.mask.nxv2i16.nxv2i16(296    <vscale x 2 x i16> %0,297    <vscale x 2 x i16> %1,298    <vscale x 2 x i16> %2,299    <vscale x 2 x i1> %3,300    iXLen %4, iXLen 1)301 302  ret <vscale x 2 x i16> %a303}304 305define <vscale x 4 x i16> @intrinsic_vadd_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, iXLen %2) nounwind {306; CHECK-LABEL: intrinsic_vadd_vv_nxv4i16_nxv4i16_nxv4i16:307; CHECK:       # %bb.0: # %entry308; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma309; CHECK-NEXT:    vadd.vv v8, v8, v9310; CHECK-NEXT:    ret311entry:312  %a = call <vscale x 4 x i16> @llvm.riscv.vadd.nxv4i16.nxv4i16(313    <vscale x 4 x i16> poison,314    <vscale x 4 x i16> %0,315    <vscale x 4 x i16> %1,316    iXLen %2)317 318  ret <vscale x 4 x i16> %a319}320 321define <vscale x 4 x i16> @intrinsic_vadd_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {322; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv4i16_nxv4i16_nxv4i16:323; CHECK:       # %bb.0: # %entry324; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, mu325; CHECK-NEXT:    vadd.vv v8, v9, v10, v0.t326; CHECK-NEXT:    ret327entry:328  %a = call <vscale x 4 x i16> @llvm.riscv.vadd.mask.nxv4i16.nxv4i16(329    <vscale x 4 x i16> %0,330    <vscale x 4 x i16> %1,331    <vscale x 4 x i16> %2,332    <vscale x 4 x i1> %3,333    iXLen %4, iXLen 1)334 335  ret <vscale x 4 x i16> %a336}337 338define <vscale x 8 x i16> @intrinsic_vadd_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, iXLen %2) nounwind {339; CHECK-LABEL: intrinsic_vadd_vv_nxv8i16_nxv8i16_nxv8i16:340; CHECK:       # %bb.0: # %entry341; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma342; CHECK-NEXT:    vadd.vv v8, v8, v10343; CHECK-NEXT:    ret344entry:345  %a = call <vscale x 8 x i16> @llvm.riscv.vadd.nxv8i16.nxv8i16(346    <vscale x 8 x i16> poison,347    <vscale x 8 x i16> %0,348    <vscale x 8 x i16> %1,349    iXLen %2)350 351  ret <vscale x 8 x i16> %a352}353 354define <vscale x 8 x i16> @intrinsic_vadd_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {355; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv8i16_nxv8i16_nxv8i16:356; CHECK:       # %bb.0: # %entry357; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, mu358; CHECK-NEXT:    vadd.vv v8, v10, v12, v0.t359; CHECK-NEXT:    ret360entry:361  %a = call <vscale x 8 x i16> @llvm.riscv.vadd.mask.nxv8i16.nxv8i16(362    <vscale x 8 x i16> %0,363    <vscale x 8 x i16> %1,364    <vscale x 8 x i16> %2,365    <vscale x 8 x i1> %3,366    iXLen %4, iXLen 1)367 368  ret <vscale x 8 x i16> %a369}370 371define <vscale x 16 x i16> @intrinsic_vadd_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, iXLen %2) nounwind {372; CHECK-LABEL: intrinsic_vadd_vv_nxv16i16_nxv16i16_nxv16i16:373; CHECK:       # %bb.0: # %entry374; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma375; CHECK-NEXT:    vadd.vv v8, v8, v12376; CHECK-NEXT:    ret377entry:378  %a = call <vscale x 16 x i16> @llvm.riscv.vadd.nxv16i16.nxv16i16(379    <vscale x 16 x i16> poison,380    <vscale x 16 x i16> %0,381    <vscale x 16 x i16> %1,382    iXLen %2)383 384  ret <vscale x 16 x i16> %a385}386 387define <vscale x 16 x i16> @intrinsic_vadd_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {388; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv16i16_nxv16i16_nxv16i16:389; CHECK:       # %bb.0: # %entry390; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, mu391; CHECK-NEXT:    vadd.vv v8, v12, v16, v0.t392; CHECK-NEXT:    ret393entry:394  %a = call <vscale x 16 x i16> @llvm.riscv.vadd.mask.nxv16i16.nxv16i16(395    <vscale x 16 x i16> %0,396    <vscale x 16 x i16> %1,397    <vscale x 16 x i16> %2,398    <vscale x 16 x i1> %3,399    iXLen %4, iXLen 1)400 401  ret <vscale x 16 x i16> %a402}403 404define <vscale x 32 x i16> @intrinsic_vadd_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, iXLen %2) nounwind {405; CHECK-LABEL: intrinsic_vadd_vv_nxv32i16_nxv32i16_nxv32i16:406; CHECK:       # %bb.0: # %entry407; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, ma408; CHECK-NEXT:    vadd.vv v8, v8, v16409; CHECK-NEXT:    ret410entry:411  %a = call <vscale x 32 x i16> @llvm.riscv.vadd.nxv32i16.nxv32i16(412    <vscale x 32 x i16> poison,413    <vscale x 32 x i16> %0,414    <vscale x 32 x i16> %1,415    iXLen %2)416 417  ret <vscale x 32 x i16> %a418}419 420define <vscale x 32 x i16> @intrinsic_vadd_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {421; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv32i16_nxv32i16_nxv32i16:422; CHECK:       # %bb.0: # %entry423; CHECK-NEXT:    vl8re16.v v24, (a0)424; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, mu425; CHECK-NEXT:    vadd.vv v8, v16, v24, v0.t426; CHECK-NEXT:    ret427entry:428  %a = call <vscale x 32 x i16> @llvm.riscv.vadd.mask.nxv32i16.nxv32i16(429    <vscale x 32 x i16> %0,430    <vscale x 32 x i16> %1,431    <vscale x 32 x i16> %2,432    <vscale x 32 x i1> %3,433    iXLen %4, iXLen 1)434 435  ret <vscale x 32 x i16> %a436}437 438define <vscale x 1 x i32> @intrinsic_vadd_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, iXLen %2) nounwind {439; CHECK-LABEL: intrinsic_vadd_vv_nxv1i32_nxv1i32_nxv1i32:440; CHECK:       # %bb.0: # %entry441; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma442; CHECK-NEXT:    vadd.vv v8, v8, v9443; CHECK-NEXT:    ret444entry:445  %a = call <vscale x 1 x i32> @llvm.riscv.vadd.nxv1i32.nxv1i32(446    <vscale x 1 x i32> poison,447    <vscale x 1 x i32> %0,448    <vscale x 1 x i32> %1,449    iXLen %2)450 451  ret <vscale x 1 x i32> %a452}453 454define <vscale x 1 x i32> @intrinsic_vadd_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {455; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv1i32_nxv1i32_nxv1i32:456; CHECK:       # %bb.0: # %entry457; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, mu458; CHECK-NEXT:    vadd.vv v8, v9, v10, v0.t459; CHECK-NEXT:    ret460entry:461  %a = call <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.nxv1i32(462    <vscale x 1 x i32> %0,463    <vscale x 1 x i32> %1,464    <vscale x 1 x i32> %2,465    <vscale x 1 x i1> %3,466    iXLen %4, iXLen 1)467 468  ret <vscale x 1 x i32> %a469}470 471define <vscale x 2 x i32> @intrinsic_vadd_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, iXLen %2) nounwind {472; CHECK-LABEL: intrinsic_vadd_vv_nxv2i32_nxv2i32_nxv2i32:473; CHECK:       # %bb.0: # %entry474; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma475; CHECK-NEXT:    vadd.vv v8, v8, v9476; CHECK-NEXT:    ret477entry:478  %a = call <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32.nxv2i32(479    <vscale x 2 x i32> poison,480    <vscale x 2 x i32> %0,481    <vscale x 2 x i32> %1,482    iXLen %2)483 484  ret <vscale x 2 x i32> %a485}486 487define <vscale x 2 x i32> @intrinsic_vadd_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {488; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv2i32_nxv2i32_nxv2i32:489; CHECK:       # %bb.0: # %entry490; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, mu491; CHECK-NEXT:    vadd.vv v8, v9, v10, v0.t492; CHECK-NEXT:    ret493entry:494  %a = call <vscale x 2 x i32> @llvm.riscv.vadd.mask.nxv2i32.nxv2i32(495    <vscale x 2 x i32> %0,496    <vscale x 2 x i32> %1,497    <vscale x 2 x i32> %2,498    <vscale x 2 x i1> %3,499    iXLen %4, iXLen 1)500 501  ret <vscale x 2 x i32> %a502}503 504define <vscale x 4 x i32> @intrinsic_vadd_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, iXLen %2) nounwind {505; CHECK-LABEL: intrinsic_vadd_vv_nxv4i32_nxv4i32_nxv4i32:506; CHECK:       # %bb.0: # %entry507; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma508; CHECK-NEXT:    vadd.vv v8, v8, v10509; CHECK-NEXT:    ret510entry:511  %a = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(512    <vscale x 4 x i32> poison,513    <vscale x 4 x i32> %0,514    <vscale x 4 x i32> %1,515    iXLen %2)516 517  ret <vscale x 4 x i32> %a518}519 520define <vscale x 4 x i32> @intrinsic_vadd_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {521; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv4i32_nxv4i32_nxv4i32:522; CHECK:       # %bb.0: # %entry523; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, mu524; CHECK-NEXT:    vadd.vv v8, v10, v12, v0.t525; CHECK-NEXT:    ret526entry:527  %a = call <vscale x 4 x i32> @llvm.riscv.vadd.mask.nxv4i32.nxv4i32(528    <vscale x 4 x i32> %0,529    <vscale x 4 x i32> %1,530    <vscale x 4 x i32> %2,531    <vscale x 4 x i1> %3,532    iXLen %4, iXLen 1)533 534  ret <vscale x 4 x i32> %a535}536 537define <vscale x 8 x i32> @intrinsic_vadd_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, iXLen %2) nounwind {538; CHECK-LABEL: intrinsic_vadd_vv_nxv8i32_nxv8i32_nxv8i32:539; CHECK:       # %bb.0: # %entry540; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma541; CHECK-NEXT:    vadd.vv v8, v8, v12542; CHECK-NEXT:    ret543entry:544  %a = call <vscale x 8 x i32> @llvm.riscv.vadd.nxv8i32.nxv8i32(545    <vscale x 8 x i32> poison,546    <vscale x 8 x i32> %0,547    <vscale x 8 x i32> %1,548    iXLen %2)549 550  ret <vscale x 8 x i32> %a551}552 553define <vscale x 8 x i32> @intrinsic_vadd_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {554; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv8i32_nxv8i32_nxv8i32:555; CHECK:       # %bb.0: # %entry556; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, mu557; CHECK-NEXT:    vadd.vv v8, v12, v16, v0.t558; CHECK-NEXT:    ret559entry:560  %a = call <vscale x 8 x i32> @llvm.riscv.vadd.mask.nxv8i32.nxv8i32(561    <vscale x 8 x i32> %0,562    <vscale x 8 x i32> %1,563    <vscale x 8 x i32> %2,564    <vscale x 8 x i1> %3,565    iXLen %4, iXLen 1)566 567  ret <vscale x 8 x i32> %a568}569 570define <vscale x 16 x i32> @intrinsic_vadd_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, iXLen %2) nounwind {571; CHECK-LABEL: intrinsic_vadd_vv_nxv16i32_nxv16i32_nxv16i32:572; CHECK:       # %bb.0: # %entry573; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma574; CHECK-NEXT:    vadd.vv v8, v8, v16575; CHECK-NEXT:    ret576entry:577  %a = call <vscale x 16 x i32> @llvm.riscv.vadd.nxv16i32.nxv16i32(578    <vscale x 16 x i32> poison,579    <vscale x 16 x i32> %0,580    <vscale x 16 x i32> %1,581    iXLen %2)582 583  ret <vscale x 16 x i32> %a584}585 586define <vscale x 16 x i32> @intrinsic_vadd_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {587; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv16i32_nxv16i32_nxv16i32:588; CHECK:       # %bb.0: # %entry589; CHECK-NEXT:    vl8re32.v v24, (a0)590; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, mu591; CHECK-NEXT:    vadd.vv v8, v16, v24, v0.t592; CHECK-NEXT:    ret593entry:594  %a = call <vscale x 16 x i32> @llvm.riscv.vadd.mask.nxv16i32.nxv16i32(595    <vscale x 16 x i32> %0,596    <vscale x 16 x i32> %1,597    <vscale x 16 x i32> %2,598    <vscale x 16 x i1> %3,599    iXLen %4, iXLen 1)600 601  ret <vscale x 16 x i32> %a602}603 604define <vscale x 1 x i64> @intrinsic_vadd_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, iXLen %2) nounwind {605; CHECK-LABEL: intrinsic_vadd_vv_nxv1i64_nxv1i64_nxv1i64:606; CHECK:       # %bb.0: # %entry607; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma608; CHECK-NEXT:    vadd.vv v8, v8, v9609; CHECK-NEXT:    ret610entry:611  %a = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64(612    <vscale x 1 x i64> poison,613    <vscale x 1 x i64> %0,614    <vscale x 1 x i64> %1,615    iXLen %2)616 617  ret <vscale x 1 x i64> %a618}619 620define <vscale x 1 x i64> @intrinsic_vadd_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {621; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv1i64_nxv1i64_nxv1i64:622; CHECK:       # %bb.0: # %entry623; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, mu624; CHECK-NEXT:    vadd.vv v8, v9, v10, v0.t625; CHECK-NEXT:    ret626entry:627  %a = call <vscale x 1 x i64> @llvm.riscv.vadd.mask.nxv1i64.nxv1i64(628    <vscale x 1 x i64> %0,629    <vscale x 1 x i64> %1,630    <vscale x 1 x i64> %2,631    <vscale x 1 x i1> %3,632    iXLen %4, iXLen 1)633 634  ret <vscale x 1 x i64> %a635}636 637define <vscale x 2 x i64> @intrinsic_vadd_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, iXLen %2) nounwind {638; CHECK-LABEL: intrinsic_vadd_vv_nxv2i64_nxv2i64_nxv2i64:639; CHECK:       # %bb.0: # %entry640; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma641; CHECK-NEXT:    vadd.vv v8, v8, v10642; CHECK-NEXT:    ret643entry:644  %a = call <vscale x 2 x i64> @llvm.riscv.vadd.nxv2i64.nxv2i64(645    <vscale x 2 x i64> poison,646    <vscale x 2 x i64> %0,647    <vscale x 2 x i64> %1,648    iXLen %2)649 650  ret <vscale x 2 x i64> %a651}652 653define <vscale x 2 x i64> @intrinsic_vadd_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {654; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv2i64_nxv2i64_nxv2i64:655; CHECK:       # %bb.0: # %entry656; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, mu657; CHECK-NEXT:    vadd.vv v8, v10, v12, v0.t658; CHECK-NEXT:    ret659entry:660  %a = call <vscale x 2 x i64> @llvm.riscv.vadd.mask.nxv2i64.nxv2i64(661    <vscale x 2 x i64> %0,662    <vscale x 2 x i64> %1,663    <vscale x 2 x i64> %2,664    <vscale x 2 x i1> %3,665    iXLen %4, iXLen 1)666 667  ret <vscale x 2 x i64> %a668}669 670define <vscale x 4 x i64> @intrinsic_vadd_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, iXLen %2) nounwind {671; CHECK-LABEL: intrinsic_vadd_vv_nxv4i64_nxv4i64_nxv4i64:672; CHECK:       # %bb.0: # %entry673; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma674; CHECK-NEXT:    vadd.vv v8, v8, v12675; CHECK-NEXT:    ret676entry:677  %a = call <vscale x 4 x i64> @llvm.riscv.vadd.nxv4i64.nxv4i64(678    <vscale x 4 x i64> poison,679    <vscale x 4 x i64> %0,680    <vscale x 4 x i64> %1,681    iXLen %2)682 683  ret <vscale x 4 x i64> %a684}685 686define <vscale x 4 x i64> @intrinsic_vadd_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {687; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv4i64_nxv4i64_nxv4i64:688; CHECK:       # %bb.0: # %entry689; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, mu690; CHECK-NEXT:    vadd.vv v8, v12, v16, v0.t691; CHECK-NEXT:    ret692entry:693  %a = call <vscale x 4 x i64> @llvm.riscv.vadd.mask.nxv4i64.nxv4i64(694    <vscale x 4 x i64> %0,695    <vscale x 4 x i64> %1,696    <vscale x 4 x i64> %2,697    <vscale x 4 x i1> %3,698    iXLen %4, iXLen 1)699 700  ret <vscale x 4 x i64> %a701}702 703define <vscale x 8 x i64> @intrinsic_vadd_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, iXLen %2) nounwind {704; CHECK-LABEL: intrinsic_vadd_vv_nxv8i64_nxv8i64_nxv8i64:705; CHECK:       # %bb.0: # %entry706; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma707; CHECK-NEXT:    vadd.vv v8, v8, v16708; CHECK-NEXT:    ret709entry:710  %a = call <vscale x 8 x i64> @llvm.riscv.vadd.nxv8i64.nxv8i64(711    <vscale x 8 x i64> poison,712    <vscale x 8 x i64> %0,713    <vscale x 8 x i64> %1,714    iXLen %2)715 716  ret <vscale x 8 x i64> %a717}718 719define <vscale x 8 x i64> @intrinsic_vadd_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {720; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv8i64_nxv8i64_nxv8i64:721; CHECK:       # %bb.0: # %entry722; CHECK-NEXT:    vl8re64.v v24, (a0)723; CHECK-NEXT:    vsetvli zero, a1, e64, m8, ta, mu724; CHECK-NEXT:    vadd.vv v8, v16, v24, v0.t725; CHECK-NEXT:    ret726entry:727  %a = call <vscale x 8 x i64> @llvm.riscv.vadd.mask.nxv8i64.nxv8i64(728    <vscale x 8 x i64> %0,729    <vscale x 8 x i64> %1,730    <vscale x 8 x i64> %2,731    <vscale x 8 x i1> %3,732    iXLen %4, iXLen 1)733 734  ret <vscale x 8 x i64> %a735}736 737define <vscale x 1 x i8> @intrinsic_vadd_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, iXLen %2) nounwind {738; CHECK-LABEL: intrinsic_vadd_vx_nxv1i8_nxv1i8_i8:739; CHECK:       # %bb.0: # %entry740; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma741; CHECK-NEXT:    vadd.vx v8, v8, a0742; CHECK-NEXT:    ret743entry:744  %a = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8(745    <vscale x 1 x i8> poison,746    <vscale x 1 x i8> %0,747    i8 %1,748    iXLen %2)749 750  ret <vscale x 1 x i8> %a751}752 753define <vscale x 1 x i8> @intrinsic_vadd_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {754; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv1i8_nxv1i8_i8:755; CHECK:       # %bb.0: # %entry756; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, mu757; CHECK-NEXT:    vadd.vx v8, v9, a0, v0.t758; CHECK-NEXT:    ret759entry:760  %a = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.i8(761    <vscale x 1 x i8> %0,762    <vscale x 1 x i8> %1,763    i8 %2,764    <vscale x 1 x i1> %3,765    iXLen %4, iXLen 1)766 767  ret <vscale x 1 x i8> %a768}769 770define <vscale x 2 x i8> @intrinsic_vadd_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, iXLen %2) nounwind {771; CHECK-LABEL: intrinsic_vadd_vx_nxv2i8_nxv2i8_i8:772; CHECK:       # %bb.0: # %entry773; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma774; CHECK-NEXT:    vadd.vx v8, v8, a0775; CHECK-NEXT:    ret776entry:777  %a = call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.i8(778    <vscale x 2 x i8> poison,779    <vscale x 2 x i8> %0,780    i8 %1,781    iXLen %2)782 783  ret <vscale x 2 x i8> %a784}785 786define <vscale x 2 x i8> @intrinsic_vadd_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {787; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv2i8_nxv2i8_i8:788; CHECK:       # %bb.0: # %entry789; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, mu790; CHECK-NEXT:    vadd.vx v8, v9, a0, v0.t791; CHECK-NEXT:    ret792entry:793  %a = call <vscale x 2 x i8> @llvm.riscv.vadd.mask.nxv2i8.i8(794    <vscale x 2 x i8> %0,795    <vscale x 2 x i8> %1,796    i8 %2,797    <vscale x 2 x i1> %3,798    iXLen %4, iXLen 1)799 800  ret <vscale x 2 x i8> %a801}802 803define <vscale x 4 x i8> @intrinsic_vadd_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, iXLen %2) nounwind {804; CHECK-LABEL: intrinsic_vadd_vx_nxv4i8_nxv4i8_i8:805; CHECK:       # %bb.0: # %entry806; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma807; CHECK-NEXT:    vadd.vx v8, v8, a0808; CHECK-NEXT:    ret809entry:810  %a = call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.i8(811    <vscale x 4 x i8> poison,812    <vscale x 4 x i8> %0,813    i8 %1,814    iXLen %2)815 816  ret <vscale x 4 x i8> %a817}818 819define <vscale x 4 x i8> @intrinsic_vadd_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {820; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv4i8_nxv4i8_i8:821; CHECK:       # %bb.0: # %entry822; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, mu823; CHECK-NEXT:    vadd.vx v8, v9, a0, v0.t824; CHECK-NEXT:    ret825entry:826  %a = call <vscale x 4 x i8> @llvm.riscv.vadd.mask.nxv4i8.i8(827    <vscale x 4 x i8> %0,828    <vscale x 4 x i8> %1,829    i8 %2,830    <vscale x 4 x i1> %3,831    iXLen %4, iXLen 1)832 833  ret <vscale x 4 x i8> %a834}835 836define <vscale x 8 x i8> @intrinsic_vadd_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, iXLen %2) nounwind {837; CHECK-LABEL: intrinsic_vadd_vx_nxv8i8_nxv8i8_i8:838; CHECK:       # %bb.0: # %entry839; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma840; CHECK-NEXT:    vadd.vx v8, v8, a0841; CHECK-NEXT:    ret842entry:843  %a = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.i8(844    <vscale x 8 x i8> poison,845    <vscale x 8 x i8> %0,846    i8 %1,847    iXLen %2)848 849  ret <vscale x 8 x i8> %a850}851 852define <vscale x 8 x i8> @intrinsic_vadd_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {853; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv8i8_nxv8i8_i8:854; CHECK:       # %bb.0: # %entry855; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, mu856; CHECK-NEXT:    vadd.vx v8, v9, a0, v0.t857; CHECK-NEXT:    ret858entry:859  %a = call <vscale x 8 x i8> @llvm.riscv.vadd.mask.nxv8i8.i8(860    <vscale x 8 x i8> %0,861    <vscale x 8 x i8> %1,862    i8 %2,863    <vscale x 8 x i1> %3,864    iXLen %4, iXLen 1)865 866  ret <vscale x 8 x i8> %a867}868 869define <vscale x 16 x i8> @intrinsic_vadd_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, iXLen %2) nounwind {870; CHECK-LABEL: intrinsic_vadd_vx_nxv16i8_nxv16i8_i8:871; CHECK:       # %bb.0: # %entry872; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma873; CHECK-NEXT:    vadd.vx v8, v8, a0874; CHECK-NEXT:    ret875entry:876  %a = call <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.i8(877    <vscale x 16 x i8> poison,878    <vscale x 16 x i8> %0,879    i8 %1,880    iXLen %2)881 882  ret <vscale x 16 x i8> %a883}884 885define <vscale x 16 x i8> @intrinsic_vadd_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {886; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv16i8_nxv16i8_i8:887; CHECK:       # %bb.0: # %entry888; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, mu889; CHECK-NEXT:    vadd.vx v8, v10, a0, v0.t890; CHECK-NEXT:    ret891entry:892  %a = call <vscale x 16 x i8> @llvm.riscv.vadd.mask.nxv16i8.i8(893    <vscale x 16 x i8> %0,894    <vscale x 16 x i8> %1,895    i8 %2,896    <vscale x 16 x i1> %3,897    iXLen %4, iXLen 1)898 899  ret <vscale x 16 x i8> %a900}901 902define <vscale x 32 x i8> @intrinsic_vadd_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, iXLen %2) nounwind {903; CHECK-LABEL: intrinsic_vadd_vx_nxv32i8_nxv32i8_i8:904; CHECK:       # %bb.0: # %entry905; CHECK-NEXT:    vsetvli zero, a1, e8, m4, ta, ma906; CHECK-NEXT:    vadd.vx v8, v8, a0907; CHECK-NEXT:    ret908entry:909  %a = call <vscale x 32 x i8> @llvm.riscv.vadd.nxv32i8.i8(910    <vscale x 32 x i8> poison,911    <vscale x 32 x i8> %0,912    i8 %1,913    iXLen %2)914 915  ret <vscale x 32 x i8> %a916}917 918define <vscale x 32 x i8> @intrinsic_vadd_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {919; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv32i8_nxv32i8_i8:920; CHECK:       # %bb.0: # %entry921; CHECK-NEXT:    vsetvli zero, a1, e8, m4, ta, mu922; CHECK-NEXT:    vadd.vx v8, v12, a0, v0.t923; CHECK-NEXT:    ret924entry:925  %a = call <vscale x 32 x i8> @llvm.riscv.vadd.mask.nxv32i8.i8(926    <vscale x 32 x i8> %0,927    <vscale x 32 x i8> %1,928    i8 %2,929    <vscale x 32 x i1> %3,930    iXLen %4, iXLen 1)931 932  ret <vscale x 32 x i8> %a933}934 935define <vscale x 64 x i8> @intrinsic_vadd_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, iXLen %2) nounwind {936; CHECK-LABEL: intrinsic_vadd_vx_nxv64i8_nxv64i8_i8:937; CHECK:       # %bb.0: # %entry938; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, ma939; CHECK-NEXT:    vadd.vx v8, v8, a0940; CHECK-NEXT:    ret941entry:942  %a = call <vscale x 64 x i8> @llvm.riscv.vadd.nxv64i8.i8(943    <vscale x 64 x i8> poison,944    <vscale x 64 x i8> %0,945    i8 %1,946    iXLen %2)947 948  ret <vscale x 64 x i8> %a949}950 951define <vscale x 64 x i8> @intrinsic_vadd_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, iXLen %4) nounwind {952; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv64i8_nxv64i8_i8:953; CHECK:       # %bb.0: # %entry954; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, mu955; CHECK-NEXT:    vadd.vx v8, v16, a0, v0.t956; CHECK-NEXT:    ret957entry:958  %a = call <vscale x 64 x i8> @llvm.riscv.vadd.mask.nxv64i8.i8(959    <vscale x 64 x i8> %0,960    <vscale x 64 x i8> %1,961    i8 %2,962    <vscale x 64 x i1> %3,963    iXLen %4, iXLen 1)964 965  ret <vscale x 64 x i8> %a966}967 968define <vscale x 1 x i16> @intrinsic_vadd_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, iXLen %2) nounwind {969; CHECK-LABEL: intrinsic_vadd_vx_nxv1i16_nxv1i16_i16:970; CHECK:       # %bb.0: # %entry971; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma972; CHECK-NEXT:    vadd.vx v8, v8, a0973; CHECK-NEXT:    ret974entry:975  %a = call <vscale x 1 x i16> @llvm.riscv.vadd.nxv1i16.i16(976    <vscale x 1 x i16> poison,977    <vscale x 1 x i16> %0,978    i16 %1,979    iXLen %2)980 981  ret <vscale x 1 x i16> %a982}983 984define <vscale x 1 x i16> @intrinsic_vadd_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {985; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv1i16_nxv1i16_i16:986; CHECK:       # %bb.0: # %entry987; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, mu988; CHECK-NEXT:    vadd.vx v8, v9, a0, v0.t989; CHECK-NEXT:    ret990entry:991  %a = call <vscale x 1 x i16> @llvm.riscv.vadd.mask.nxv1i16.i16(992    <vscale x 1 x i16> %0,993    <vscale x 1 x i16> %1,994    i16 %2,995    <vscale x 1 x i1> %3,996    iXLen %4, iXLen 1)997 998  ret <vscale x 1 x i16> %a999}1000 1001define <vscale x 2 x i16> @intrinsic_vadd_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, iXLen %2) nounwind {1002; CHECK-LABEL: intrinsic_vadd_vx_nxv2i16_nxv2i16_i16:1003; CHECK:       # %bb.0: # %entry1004; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma1005; CHECK-NEXT:    vadd.vx v8, v8, a01006; CHECK-NEXT:    ret1007entry:1008  %a = call <vscale x 2 x i16> @llvm.riscv.vadd.nxv2i16.i16(1009    <vscale x 2 x i16> poison,1010    <vscale x 2 x i16> %0,1011    i16 %1,1012    iXLen %2)1013 1014  ret <vscale x 2 x i16> %a1015}1016 1017define <vscale x 2 x i16> @intrinsic_vadd_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {1018; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv2i16_nxv2i16_i16:1019; CHECK:       # %bb.0: # %entry1020; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, mu1021; CHECK-NEXT:    vadd.vx v8, v9, a0, v0.t1022; CHECK-NEXT:    ret1023entry:1024  %a = call <vscale x 2 x i16> @llvm.riscv.vadd.mask.nxv2i16.i16(1025    <vscale x 2 x i16> %0,1026    <vscale x 2 x i16> %1,1027    i16 %2,1028    <vscale x 2 x i1> %3,1029    iXLen %4, iXLen 1)1030 1031  ret <vscale x 2 x i16> %a1032}1033 1034define <vscale x 4 x i16> @intrinsic_vadd_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, iXLen %2) nounwind {1035; CHECK-LABEL: intrinsic_vadd_vx_nxv4i16_nxv4i16_i16:1036; CHECK:       # %bb.0: # %entry1037; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma1038; CHECK-NEXT:    vadd.vx v8, v8, a01039; CHECK-NEXT:    ret1040entry:1041  %a = call <vscale x 4 x i16> @llvm.riscv.vadd.nxv4i16.i16(1042    <vscale x 4 x i16> poison,1043    <vscale x 4 x i16> %0,1044    i16 %1,1045    iXLen %2)1046 1047  ret <vscale x 4 x i16> %a1048}1049 1050define <vscale x 4 x i16> @intrinsic_vadd_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1051; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv4i16_nxv4i16_i16:1052; CHECK:       # %bb.0: # %entry1053; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, mu1054; CHECK-NEXT:    vadd.vx v8, v9, a0, v0.t1055; CHECK-NEXT:    ret1056entry:1057  %a = call <vscale x 4 x i16> @llvm.riscv.vadd.mask.nxv4i16.i16(1058    <vscale x 4 x i16> %0,1059    <vscale x 4 x i16> %1,1060    i16 %2,1061    <vscale x 4 x i1> %3,1062    iXLen %4, iXLen 1)1063 1064  ret <vscale x 4 x i16> %a1065}1066 1067define <vscale x 8 x i16> @intrinsic_vadd_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, iXLen %2) nounwind {1068; CHECK-LABEL: intrinsic_vadd_vx_nxv8i16_nxv8i16_i16:1069; CHECK:       # %bb.0: # %entry1070; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma1071; CHECK-NEXT:    vadd.vx v8, v8, a01072; CHECK-NEXT:    ret1073entry:1074  %a = call <vscale x 8 x i16> @llvm.riscv.vadd.nxv8i16.i16(1075    <vscale x 8 x i16> poison,1076    <vscale x 8 x i16> %0,1077    i16 %1,1078    iXLen %2)1079 1080  ret <vscale x 8 x i16> %a1081}1082 1083define <vscale x 8 x i16> @intrinsic_vadd_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {1084; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv8i16_nxv8i16_i16:1085; CHECK:       # %bb.0: # %entry1086; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, mu1087; CHECK-NEXT:    vadd.vx v8, v10, a0, v0.t1088; CHECK-NEXT:    ret1089entry:1090  %a = call <vscale x 8 x i16> @llvm.riscv.vadd.mask.nxv8i16.i16(1091    <vscale x 8 x i16> %0,1092    <vscale x 8 x i16> %1,1093    i16 %2,1094    <vscale x 8 x i1> %3,1095    iXLen %4, iXLen 1)1096 1097  ret <vscale x 8 x i16> %a1098}1099 1100define <vscale x 16 x i16> @intrinsic_vadd_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, iXLen %2) nounwind {1101; CHECK-LABEL: intrinsic_vadd_vx_nxv16i16_nxv16i16_i16:1102; CHECK:       # %bb.0: # %entry1103; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma1104; CHECK-NEXT:    vadd.vx v8, v8, a01105; CHECK-NEXT:    ret1106entry:1107  %a = call <vscale x 16 x i16> @llvm.riscv.vadd.nxv16i16.i16(1108    <vscale x 16 x i16> poison,1109    <vscale x 16 x i16> %0,1110    i16 %1,1111    iXLen %2)1112 1113  ret <vscale x 16 x i16> %a1114}1115 1116define <vscale x 16 x i16> @intrinsic_vadd_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {1117; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv16i16_nxv16i16_i16:1118; CHECK:       # %bb.0: # %entry1119; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, mu1120; CHECK-NEXT:    vadd.vx v8, v12, a0, v0.t1121; CHECK-NEXT:    ret1122entry:1123  %a = call <vscale x 16 x i16> @llvm.riscv.vadd.mask.nxv16i16.i16(1124    <vscale x 16 x i16> %0,1125    <vscale x 16 x i16> %1,1126    i16 %2,1127    <vscale x 16 x i1> %3,1128    iXLen %4, iXLen 1)1129 1130  ret <vscale x 16 x i16> %a1131}1132 1133define <vscale x 32 x i16> @intrinsic_vadd_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, iXLen %2) nounwind {1134; CHECK-LABEL: intrinsic_vadd_vx_nxv32i16_nxv32i16_i16:1135; CHECK:       # %bb.0: # %entry1136; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, ma1137; CHECK-NEXT:    vadd.vx v8, v8, a01138; CHECK-NEXT:    ret1139entry:1140  %a = call <vscale x 32 x i16> @llvm.riscv.vadd.nxv32i16.i16(1141    <vscale x 32 x i16> poison,1142    <vscale x 32 x i16> %0,1143    i16 %1,1144    iXLen %2)1145 1146  ret <vscale x 32 x i16> %a1147}1148 1149define <vscale x 32 x i16> @intrinsic_vadd_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {1150; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv32i16_nxv32i16_i16:1151; CHECK:       # %bb.0: # %entry1152; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, mu1153; CHECK-NEXT:    vadd.vx v8, v16, a0, v0.t1154; CHECK-NEXT:    ret1155entry:1156  %a = call <vscale x 32 x i16> @llvm.riscv.vadd.mask.nxv32i16.i16(1157    <vscale x 32 x i16> %0,1158    <vscale x 32 x i16> %1,1159    i16 %2,1160    <vscale x 32 x i1> %3,1161    iXLen %4, iXLen 1)1162 1163  ret <vscale x 32 x i16> %a1164}1165 1166define <vscale x 1 x i32> @intrinsic_vadd_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, iXLen %2) nounwind {1167; CHECK-LABEL: intrinsic_vadd_vx_nxv1i32_nxv1i32_i32:1168; CHECK:       # %bb.0: # %entry1169; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma1170; CHECK-NEXT:    vadd.vx v8, v8, a01171; CHECK-NEXT:    ret1172entry:1173  %a = call <vscale x 1 x i32> @llvm.riscv.vadd.nxv1i32.i32(1174    <vscale x 1 x i32> poison,1175    <vscale x 1 x i32> %0,1176    i32 %1,1177    iXLen %2)1178 1179  ret <vscale x 1 x i32> %a1180}1181 1182define <vscale x 1 x i32> @intrinsic_vadd_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {1183; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv1i32_nxv1i32_i32:1184; CHECK:       # %bb.0: # %entry1185; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, mu1186; CHECK-NEXT:    vadd.vx v8, v9, a0, v0.t1187; CHECK-NEXT:    ret1188entry:1189  %a = call <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.i32(1190    <vscale x 1 x i32> %0,1191    <vscale x 1 x i32> %1,1192    i32 %2,1193    <vscale x 1 x i1> %3,1194    iXLen %4, iXLen 1)1195 1196  ret <vscale x 1 x i32> %a1197}1198 1199define <vscale x 2 x i32> @intrinsic_vadd_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, iXLen %2) nounwind {1200; CHECK-LABEL: intrinsic_vadd_vx_nxv2i32_nxv2i32_i32:1201; CHECK:       # %bb.0: # %entry1202; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma1203; CHECK-NEXT:    vadd.vx v8, v8, a01204; CHECK-NEXT:    ret1205entry:1206  %a = call <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32.i32(1207    <vscale x 2 x i32> poison,1208    <vscale x 2 x i32> %0,1209    i32 %1,1210    iXLen %2)1211 1212  ret <vscale x 2 x i32> %a1213}1214 1215define <vscale x 2 x i32> @intrinsic_vadd_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {1216; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv2i32_nxv2i32_i32:1217; CHECK:       # %bb.0: # %entry1218; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, mu1219; CHECK-NEXT:    vadd.vx v8, v9, a0, v0.t1220; CHECK-NEXT:    ret1221entry:1222  %a = call <vscale x 2 x i32> @llvm.riscv.vadd.mask.nxv2i32.i32(1223    <vscale x 2 x i32> %0,1224    <vscale x 2 x i32> %1,1225    i32 %2,1226    <vscale x 2 x i1> %3,1227    iXLen %4, iXLen 1)1228 1229  ret <vscale x 2 x i32> %a1230}1231 1232define <vscale x 4 x i32> @intrinsic_vadd_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, iXLen %2) nounwind {1233; CHECK-LABEL: intrinsic_vadd_vx_nxv4i32_nxv4i32_i32:1234; CHECK:       # %bb.0: # %entry1235; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma1236; CHECK-NEXT:    vadd.vx v8, v8, a01237; CHECK-NEXT:    ret1238entry:1239  %a = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.i32(1240    <vscale x 4 x i32> poison,1241    <vscale x 4 x i32> %0,1242    i32 %1,1243    iXLen %2)1244 1245  ret <vscale x 4 x i32> %a1246}1247 1248define <vscale x 4 x i32> @intrinsic_vadd_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1249; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv4i32_nxv4i32_i32:1250; CHECK:       # %bb.0: # %entry1251; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, mu1252; CHECK-NEXT:    vadd.vx v8, v10, a0, v0.t1253; CHECK-NEXT:    ret1254entry:1255  %a = call <vscale x 4 x i32> @llvm.riscv.vadd.mask.nxv4i32.i32(1256    <vscale x 4 x i32> %0,1257    <vscale x 4 x i32> %1,1258    i32 %2,1259    <vscale x 4 x i1> %3,1260    iXLen %4, iXLen 1)1261 1262  ret <vscale x 4 x i32> %a1263}1264 1265define <vscale x 8 x i32> @intrinsic_vadd_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, iXLen %2) nounwind {1266; CHECK-LABEL: intrinsic_vadd_vx_nxv8i32_nxv8i32_i32:1267; CHECK:       # %bb.0: # %entry1268; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma1269; CHECK-NEXT:    vadd.vx v8, v8, a01270; CHECK-NEXT:    ret1271entry:1272  %a = call <vscale x 8 x i32> @llvm.riscv.vadd.nxv8i32.i32(1273    <vscale x 8 x i32> poison,1274    <vscale x 8 x i32> %0,1275    i32 %1,1276    iXLen %2)1277 1278  ret <vscale x 8 x i32> %a1279}1280 1281define <vscale x 8 x i32> @intrinsic_vadd_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {1282; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv8i32_nxv8i32_i32:1283; CHECK:       # %bb.0: # %entry1284; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, mu1285; CHECK-NEXT:    vadd.vx v8, v12, a0, v0.t1286; CHECK-NEXT:    ret1287entry:1288  %a = call <vscale x 8 x i32> @llvm.riscv.vadd.mask.nxv8i32.i32(1289    <vscale x 8 x i32> %0,1290    <vscale x 8 x i32> %1,1291    i32 %2,1292    <vscale x 8 x i1> %3,1293    iXLen %4, iXLen 1)1294 1295  ret <vscale x 8 x i32> %a1296}1297 1298define <vscale x 16 x i32> @intrinsic_vadd_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, iXLen %2) nounwind {1299; CHECK-LABEL: intrinsic_vadd_vx_nxv16i32_nxv16i32_i32:1300; CHECK:       # %bb.0: # %entry1301; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, ma1302; CHECK-NEXT:    vadd.vx v8, v8, a01303; CHECK-NEXT:    ret1304entry:1305  %a = call <vscale x 16 x i32> @llvm.riscv.vadd.nxv16i32.i32(1306    <vscale x 16 x i32> poison,1307    <vscale x 16 x i32> %0,1308    i32 %1,1309    iXLen %2)1310 1311  ret <vscale x 16 x i32> %a1312}1313 1314define <vscale x 16 x i32> @intrinsic_vadd_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {1315; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv16i32_nxv16i32_i32:1316; CHECK:       # %bb.0: # %entry1317; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, mu1318; CHECK-NEXT:    vadd.vx v8, v16, a0, v0.t1319; CHECK-NEXT:    ret1320entry:1321  %a = call <vscale x 16 x i32> @llvm.riscv.vadd.mask.nxv16i32.i32(1322    <vscale x 16 x i32> %0,1323    <vscale x 16 x i32> %1,1324    i32 %2,1325    <vscale x 16 x i1> %3,1326    iXLen %4, iXLen 1)1327 1328  ret <vscale x 16 x i32> %a1329}1330 1331define <vscale x 1 x i64> @intrinsic_vadd_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, iXLen %2) nounwind {1332; RV32-LABEL: intrinsic_vadd_vx_nxv1i64_nxv1i64_i64:1333; RV32:       # %bb.0: # %entry1334; RV32-NEXT:    addi sp, sp, -161335; RV32-NEXT:    sw a0, 8(sp)1336; RV32-NEXT:    sw a1, 12(sp)1337; RV32-NEXT:    addi a0, sp, 81338; RV32-NEXT:    vsetvli zero, a2, e64, m1, ta, ma1339; RV32-NEXT:    vlse64.v v9, (a0), zero1340; RV32-NEXT:    vadd.vv v8, v8, v91341; RV32-NEXT:    addi sp, sp, 161342; RV32-NEXT:    ret1343;1344; RV64-LABEL: intrinsic_vadd_vx_nxv1i64_nxv1i64_i64:1345; RV64:       # %bb.0: # %entry1346; RV64-NEXT:    vsetvli zero, a1, e64, m1, ta, ma1347; RV64-NEXT:    vadd.vx v8, v8, a01348; RV64-NEXT:    ret1349entry:1350  %a = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.i64(1351    <vscale x 1 x i64> poison,1352    <vscale x 1 x i64> %0,1353    i64 %1,1354    iXLen %2)1355 1356  ret <vscale x 1 x i64> %a1357}1358 1359define <vscale x 1 x i64> @intrinsic_vadd_vx_sext_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i32 %1, iXLen %2) nounwind {1360; RV32-LABEL: intrinsic_vadd_vx_sext_nxv1i64_nxv1i64_i64:1361; RV32:       # %bb.0: # %entry1362; RV32-NEXT:    vsetvli zero, a1, e64, m1, ta, ma1363; RV32-NEXT:    vadd.vx v8, v8, a01364; RV32-NEXT:    ret1365;1366; RV64-LABEL: intrinsic_vadd_vx_sext_nxv1i64_nxv1i64_i64:1367; RV64:       # %bb.0: # %entry1368; RV64-NEXT:    sext.w a0, a01369; RV64-NEXT:    vsetvli zero, a1, e64, m1, ta, ma1370; RV64-NEXT:    vadd.vx v8, v8, a01371; RV64-NEXT:    ret1372entry:1373  %ext = sext i32 %1 to i641374  %a = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.i64(1375    <vscale x 1 x i64> poison,1376    <vscale x 1 x i64> %0,1377    i64 %ext,1378    iXLen %2)1379 1380  ret <vscale x 1 x i64> %a1381}1382 1383define <vscale x 1 x i64> @intrinsic_vadd_vx_sextload_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, ptr %1, iXLen %2) nounwind {1384; CHECK-LABEL: intrinsic_vadd_vx_sextload_nxv1i64_nxv1i64_i64:1385; CHECK:       # %bb.0: # %entry1386; CHECK-NEXT:    lw a0, 0(a0)1387; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma1388; CHECK-NEXT:    vadd.vx v8, v8, a01389; CHECK-NEXT:    ret1390entry:1391  %load = load i32, ptr %11392  %ext = sext i32 %load to i641393  %a = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.i64(1394    <vscale x 1 x i64> poison,1395    <vscale x 1 x i64> %0,1396    i64 %ext,1397    iXLen %2)1398 1399  ret <vscale x 1 x i64> %a1400}1401 1402define <vscale x 1 x i64> @intrinsic_vadd_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {1403; RV32-LABEL: intrinsic_vadd_mask_vx_nxv1i64_nxv1i64_i64:1404; RV32:       # %bb.0: # %entry1405; RV32-NEXT:    addi sp, sp, -161406; RV32-NEXT:    sw a0, 8(sp)1407; RV32-NEXT:    sw a1, 12(sp)1408; RV32-NEXT:    addi a0, sp, 81409; RV32-NEXT:    vsetvli zero, a2, e64, m1, ta, mu1410; RV32-NEXT:    vlse64.v v10, (a0), zero1411; RV32-NEXT:    vadd.vv v8, v9, v10, v0.t1412; RV32-NEXT:    addi sp, sp, 161413; RV32-NEXT:    ret1414;1415; RV64-LABEL: intrinsic_vadd_mask_vx_nxv1i64_nxv1i64_i64:1416; RV64:       # %bb.0: # %entry1417; RV64-NEXT:    vsetvli zero, a1, e64, m1, ta, mu1418; RV64-NEXT:    vadd.vx v8, v9, a0, v0.t1419; RV64-NEXT:    ret1420entry:1421  %a = call <vscale x 1 x i64> @llvm.riscv.vadd.mask.nxv1i64.i64(1422    <vscale x 1 x i64> %0,1423    <vscale x 1 x i64> %1,1424    i64 %2,1425    <vscale x 1 x i1> %3,1426    iXLen %4, iXLen 1)1427 1428  ret <vscale x 1 x i64> %a1429}1430 1431define <vscale x 2 x i64> @intrinsic_vadd_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, iXLen %2) nounwind {1432; RV32-LABEL: intrinsic_vadd_vx_nxv2i64_nxv2i64_i64:1433; RV32:       # %bb.0: # %entry1434; RV32-NEXT:    addi sp, sp, -161435; RV32-NEXT:    sw a0, 8(sp)1436; RV32-NEXT:    sw a1, 12(sp)1437; RV32-NEXT:    addi a0, sp, 81438; RV32-NEXT:    vsetvli zero, a2, e64, m2, ta, ma1439; RV32-NEXT:    vlse64.v v10, (a0), zero1440; RV32-NEXT:    vadd.vv v8, v8, v101441; RV32-NEXT:    addi sp, sp, 161442; RV32-NEXT:    ret1443;1444; RV64-LABEL: intrinsic_vadd_vx_nxv2i64_nxv2i64_i64:1445; RV64:       # %bb.0: # %entry1446; RV64-NEXT:    vsetvli zero, a1, e64, m2, ta, ma1447; RV64-NEXT:    vadd.vx v8, v8, a01448; RV64-NEXT:    ret1449entry:1450  %a = call <vscale x 2 x i64> @llvm.riscv.vadd.nxv2i64.i64(1451    <vscale x 2 x i64> poison,1452    <vscale x 2 x i64> %0,1453    i64 %1,1454    iXLen %2)1455 1456  ret <vscale x 2 x i64> %a1457}1458 1459define <vscale x 2 x i64> @intrinsic_vadd_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {1460; RV32-LABEL: intrinsic_vadd_mask_vx_nxv2i64_nxv2i64_i64:1461; RV32:       # %bb.0: # %entry1462; RV32-NEXT:    addi sp, sp, -161463; RV32-NEXT:    sw a0, 8(sp)1464; RV32-NEXT:    sw a1, 12(sp)1465; RV32-NEXT:    addi a0, sp, 81466; RV32-NEXT:    vsetvli zero, a2, e64, m2, ta, mu1467; RV32-NEXT:    vlse64.v v12, (a0), zero1468; RV32-NEXT:    vadd.vv v8, v10, v12, v0.t1469; RV32-NEXT:    addi sp, sp, 161470; RV32-NEXT:    ret1471;1472; RV64-LABEL: intrinsic_vadd_mask_vx_nxv2i64_nxv2i64_i64:1473; RV64:       # %bb.0: # %entry1474; RV64-NEXT:    vsetvli zero, a1, e64, m2, ta, mu1475; RV64-NEXT:    vadd.vx v8, v10, a0, v0.t1476; RV64-NEXT:    ret1477entry:1478  %a = call <vscale x 2 x i64> @llvm.riscv.vadd.mask.nxv2i64.i64(1479    <vscale x 2 x i64> %0,1480    <vscale x 2 x i64> %1,1481    i64 %2,1482    <vscale x 2 x i1> %3,1483    iXLen %4, iXLen 1)1484 1485  ret <vscale x 2 x i64> %a1486}1487 1488define <vscale x 4 x i64> @intrinsic_vadd_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, iXLen %2) nounwind {1489; RV32-LABEL: intrinsic_vadd_vx_nxv4i64_nxv4i64_i64:1490; RV32:       # %bb.0: # %entry1491; RV32-NEXT:    addi sp, sp, -161492; RV32-NEXT:    sw a0, 8(sp)1493; RV32-NEXT:    sw a1, 12(sp)1494; RV32-NEXT:    addi a0, sp, 81495; RV32-NEXT:    vsetvli zero, a2, e64, m4, ta, ma1496; RV32-NEXT:    vlse64.v v12, (a0), zero1497; RV32-NEXT:    vadd.vv v8, v8, v121498; RV32-NEXT:    addi sp, sp, 161499; RV32-NEXT:    ret1500;1501; RV64-LABEL: intrinsic_vadd_vx_nxv4i64_nxv4i64_i64:1502; RV64:       # %bb.0: # %entry1503; RV64-NEXT:    vsetvli zero, a1, e64, m4, ta, ma1504; RV64-NEXT:    vadd.vx v8, v8, a01505; RV64-NEXT:    ret1506entry:1507  %a = call <vscale x 4 x i64> @llvm.riscv.vadd.nxv4i64.i64(1508    <vscale x 4 x i64> poison,1509    <vscale x 4 x i64> %0,1510    i64 %1,1511    iXLen %2)1512 1513  ret <vscale x 4 x i64> %a1514}1515 1516define <vscale x 4 x i64> @intrinsic_vadd_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1517; RV32-LABEL: intrinsic_vadd_mask_vx_nxv4i64_nxv4i64_i64:1518; RV32:       # %bb.0: # %entry1519; RV32-NEXT:    addi sp, sp, -161520; RV32-NEXT:    sw a0, 8(sp)1521; RV32-NEXT:    sw a1, 12(sp)1522; RV32-NEXT:    addi a0, sp, 81523; RV32-NEXT:    vsetvli zero, a2, e64, m4, ta, mu1524; RV32-NEXT:    vlse64.v v16, (a0), zero1525; RV32-NEXT:    vadd.vv v8, v12, v16, v0.t1526; RV32-NEXT:    addi sp, sp, 161527; RV32-NEXT:    ret1528;1529; RV64-LABEL: intrinsic_vadd_mask_vx_nxv4i64_nxv4i64_i64:1530; RV64:       # %bb.0: # %entry1531; RV64-NEXT:    vsetvli zero, a1, e64, m4, ta, mu1532; RV64-NEXT:    vadd.vx v8, v12, a0, v0.t1533; RV64-NEXT:    ret1534entry:1535  %a = call <vscale x 4 x i64> @llvm.riscv.vadd.mask.nxv4i64.i64(1536    <vscale x 4 x i64> %0,1537    <vscale x 4 x i64> %1,1538    i64 %2,1539    <vscale x 4 x i1> %3,1540    iXLen %4, iXLen 1)1541 1542  ret <vscale x 4 x i64> %a1543}1544 1545define <vscale x 8 x i64> @intrinsic_vadd_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, iXLen %2) nounwind {1546; RV32-LABEL: intrinsic_vadd_vx_nxv8i64_nxv8i64_i64:1547; RV32:       # %bb.0: # %entry1548; RV32-NEXT:    addi sp, sp, -161549; RV32-NEXT:    sw a0, 8(sp)1550; RV32-NEXT:    sw a1, 12(sp)1551; RV32-NEXT:    addi a0, sp, 81552; RV32-NEXT:    vsetvli zero, a2, e64, m8, ta, ma1553; RV32-NEXT:    vlse64.v v16, (a0), zero1554; RV32-NEXT:    vadd.vv v8, v8, v161555; RV32-NEXT:    addi sp, sp, 161556; RV32-NEXT:    ret1557;1558; RV64-LABEL: intrinsic_vadd_vx_nxv8i64_nxv8i64_i64:1559; RV64:       # %bb.0: # %entry1560; RV64-NEXT:    vsetvli zero, a1, e64, m8, ta, ma1561; RV64-NEXT:    vadd.vx v8, v8, a01562; RV64-NEXT:    ret1563entry:1564  %a = call <vscale x 8 x i64> @llvm.riscv.vadd.nxv8i64.i64(1565    <vscale x 8 x i64> poison,1566    <vscale x 8 x i64> %0,1567    i64 %1,1568    iXLen %2)1569 1570  ret <vscale x 8 x i64> %a1571}1572 1573define <vscale x 8 x i64> @intrinsic_vadd_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {1574; RV32-LABEL: intrinsic_vadd_mask_vx_nxv8i64_nxv8i64_i64:1575; RV32:       # %bb.0: # %entry1576; RV32-NEXT:    addi sp, sp, -161577; RV32-NEXT:    sw a0, 8(sp)1578; RV32-NEXT:    sw a1, 12(sp)1579; RV32-NEXT:    addi a0, sp, 81580; RV32-NEXT:    vsetvli zero, a2, e64, m8, ta, mu1581; RV32-NEXT:    vlse64.v v24, (a0), zero1582; RV32-NEXT:    vadd.vv v8, v16, v24, v0.t1583; RV32-NEXT:    addi sp, sp, 161584; RV32-NEXT:    ret1585;1586; RV64-LABEL: intrinsic_vadd_mask_vx_nxv8i64_nxv8i64_i64:1587; RV64:       # %bb.0: # %entry1588; RV64-NEXT:    vsetvli zero, a1, e64, m8, ta, mu1589; RV64-NEXT:    vadd.vx v8, v16, a0, v0.t1590; RV64-NEXT:    ret1591entry:1592  %a = call <vscale x 8 x i64> @llvm.riscv.vadd.mask.nxv8i64.i64(1593    <vscale x 8 x i64> %0,1594    <vscale x 8 x i64> %1,1595    i64 %2,1596    <vscale x 8 x i1> %3,1597    iXLen %4, iXLen 1)1598 1599  ret <vscale x 8 x i64> %a1600}1601 1602define <vscale x 1 x i8> @intrinsic_vadd_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, iXLen %1) nounwind {1603; CHECK-LABEL: intrinsic_vadd_vi_nxv1i8_nxv1i8_i8:1604; CHECK:       # %bb.0: # %entry1605; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma1606; CHECK-NEXT:    vadd.vi v8, v8, 91607; CHECK-NEXT:    ret1608entry:1609  %a = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8(1610    <vscale x 1 x i8> poison,1611    <vscale x 1 x i8> %0,1612    i8 9,1613    iXLen %1)1614 1615  ret <vscale x 1 x i8> %a1616}1617 1618define <vscale x 1 x i8> @intrinsic_vadd_mask_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {1619; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv1i8_nxv1i8_i8:1620; CHECK:       # %bb.0: # %entry1621; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, mu1622; CHECK-NEXT:    vadd.vi v8, v9, -9, v0.t1623; CHECK-NEXT:    ret1624entry:1625  %a = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.i8(1626    <vscale x 1 x i8> %0,1627    <vscale x 1 x i8> %1,1628    i8 -9,1629    <vscale x 1 x i1> %2,1630    iXLen %3, iXLen 1)1631 1632  ret <vscale x 1 x i8> %a1633}1634 1635define <vscale x 2 x i8> @intrinsic_vadd_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, iXLen %1) nounwind {1636; CHECK-LABEL: intrinsic_vadd_vi_nxv2i8_nxv2i8_i8:1637; CHECK:       # %bb.0: # %entry1638; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma1639; CHECK-NEXT:    vadd.vi v8, v8, 91640; CHECK-NEXT:    ret1641entry:1642  %a = call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.i8(1643    <vscale x 2 x i8> poison,1644    <vscale x 2 x i8> %0,1645    i8 9,1646    iXLen %1)1647 1648  ret <vscale x 2 x i8> %a1649}1650 1651define <vscale x 2 x i8> @intrinsic_vadd_mask_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {1652; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv2i8_nxv2i8_i8:1653; CHECK:       # %bb.0: # %entry1654; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, mu1655; CHECK-NEXT:    vadd.vi v8, v9, -9, v0.t1656; CHECK-NEXT:    ret1657entry:1658  %a = call <vscale x 2 x i8> @llvm.riscv.vadd.mask.nxv2i8.i8(1659    <vscale x 2 x i8> %0,1660    <vscale x 2 x i8> %1,1661    i8 -9,1662    <vscale x 2 x i1> %2,1663    iXLen %3, iXLen 1)1664 1665  ret <vscale x 2 x i8> %a1666}1667 1668define <vscale x 4 x i8> @intrinsic_vadd_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, iXLen %1) nounwind {1669; CHECK-LABEL: intrinsic_vadd_vi_nxv4i8_nxv4i8_i8:1670; CHECK:       # %bb.0: # %entry1671; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma1672; CHECK-NEXT:    vadd.vi v8, v8, 91673; CHECK-NEXT:    ret1674entry:1675  %a = call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.i8(1676    <vscale x 4 x i8> poison,1677    <vscale x 4 x i8> %0,1678    i8 9,1679    iXLen %1)1680 1681  ret <vscale x 4 x i8> %a1682}1683 1684define <vscale x 4 x i8> @intrinsic_vadd_mask_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {1685; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv4i8_nxv4i8_i8:1686; CHECK:       # %bb.0: # %entry1687; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, mu1688; CHECK-NEXT:    vadd.vi v8, v9, -9, v0.t1689; CHECK-NEXT:    ret1690entry:1691  %a = call <vscale x 4 x i8> @llvm.riscv.vadd.mask.nxv4i8.i8(1692    <vscale x 4 x i8> %0,1693    <vscale x 4 x i8> %1,1694    i8 -9,1695    <vscale x 4 x i1> %2,1696    iXLen %3, iXLen 1)1697 1698  ret <vscale x 4 x i8> %a1699}1700 1701define <vscale x 8 x i8> @intrinsic_vadd_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, iXLen %1) nounwind {1702; CHECK-LABEL: intrinsic_vadd_vi_nxv8i8_nxv8i8_i8:1703; CHECK:       # %bb.0: # %entry1704; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma1705; CHECK-NEXT:    vadd.vi v8, v8, 91706; CHECK-NEXT:    ret1707entry:1708  %a = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.i8(1709    <vscale x 8 x i8> poison,1710    <vscale x 8 x i8> %0,1711    i8 9,1712    iXLen %1)1713 1714  ret <vscale x 8 x i8> %a1715}1716 1717define <vscale x 8 x i8> @intrinsic_vadd_mask_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {1718; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv8i8_nxv8i8_i8:1719; CHECK:       # %bb.0: # %entry1720; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, mu1721; CHECK-NEXT:    vadd.vi v8, v9, -9, v0.t1722; CHECK-NEXT:    ret1723entry:1724  %a = call <vscale x 8 x i8> @llvm.riscv.vadd.mask.nxv8i8.i8(1725    <vscale x 8 x i8> %0,1726    <vscale x 8 x i8> %1,1727    i8 -9,1728    <vscale x 8 x i1> %2,1729    iXLen %3, iXLen 1)1730 1731  ret <vscale x 8 x i8> %a1732}1733 1734define <vscale x 16 x i8> @intrinsic_vadd_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, iXLen %1) nounwind {1735; CHECK-LABEL: intrinsic_vadd_vi_nxv16i8_nxv16i8_i8:1736; CHECK:       # %bb.0: # %entry1737; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma1738; CHECK-NEXT:    vadd.vi v8, v8, 91739; CHECK-NEXT:    ret1740entry:1741  %a = call <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.i8(1742    <vscale x 16 x i8> poison,1743    <vscale x 16 x i8> %0,1744    i8 9,1745    iXLen %1)1746 1747  ret <vscale x 16 x i8> %a1748}1749 1750define <vscale x 16 x i8> @intrinsic_vadd_mask_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {1751; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv16i8_nxv16i8_i8:1752; CHECK:       # %bb.0: # %entry1753; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, mu1754; CHECK-NEXT:    vadd.vi v8, v10, -9, v0.t1755; CHECK-NEXT:    ret1756entry:1757  %a = call <vscale x 16 x i8> @llvm.riscv.vadd.mask.nxv16i8.i8(1758    <vscale x 16 x i8> %0,1759    <vscale x 16 x i8> %1,1760    i8 -9,1761    <vscale x 16 x i1> %2,1762    iXLen %3, iXLen 1)1763 1764  ret <vscale x 16 x i8> %a1765}1766 1767define <vscale x 32 x i8> @intrinsic_vadd_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, iXLen %1) nounwind {1768; CHECK-LABEL: intrinsic_vadd_vi_nxv32i8_nxv32i8_i8:1769; CHECK:       # %bb.0: # %entry1770; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma1771; CHECK-NEXT:    vadd.vi v8, v8, 91772; CHECK-NEXT:    ret1773entry:1774  %a = call <vscale x 32 x i8> @llvm.riscv.vadd.nxv32i8.i8(1775    <vscale x 32 x i8> poison,1776    <vscale x 32 x i8> %0,1777    i8 9,1778    iXLen %1)1779 1780  ret <vscale x 32 x i8> %a1781}1782 1783define <vscale x 32 x i8> @intrinsic_vadd_mask_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {1784; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv32i8_nxv32i8_i8:1785; CHECK:       # %bb.0: # %entry1786; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, mu1787; CHECK-NEXT:    vadd.vi v8, v12, -9, v0.t1788; CHECK-NEXT:    ret1789entry:1790  %a = call <vscale x 32 x i8> @llvm.riscv.vadd.mask.nxv32i8.i8(1791    <vscale x 32 x i8> %0,1792    <vscale x 32 x i8> %1,1793    i8 -9,1794    <vscale x 32 x i1> %2,1795    iXLen %3, iXLen 1)1796 1797  ret <vscale x 32 x i8> %a1798}1799 1800define <vscale x 64 x i8> @intrinsic_vadd_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, iXLen %1) nounwind {1801; CHECK-LABEL: intrinsic_vadd_vi_nxv64i8_nxv64i8_i8:1802; CHECK:       # %bb.0: # %entry1803; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma1804; CHECK-NEXT:    vadd.vi v8, v8, -91805; CHECK-NEXT:    ret1806entry:1807  %a = call <vscale x 64 x i8> @llvm.riscv.vadd.nxv64i8.i8(1808    <vscale x 64 x i8> poison,1809    <vscale x 64 x i8> %0,1810    i8 -9,1811    iXLen %1)1812 1813  ret <vscale x 64 x i8> %a1814}1815 1816define <vscale x 64 x i8> @intrinsic_vadd_mask_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i1> %2, iXLen %3) nounwind {1817; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv64i8_nxv64i8_i8:1818; CHECK:       # %bb.0: # %entry1819; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, mu1820; CHECK-NEXT:    vadd.vi v8, v16, -9, v0.t1821; CHECK-NEXT:    ret1822entry:1823  %a = call <vscale x 64 x i8> @llvm.riscv.vadd.mask.nxv64i8.i8(1824    <vscale x 64 x i8> %0,1825    <vscale x 64 x i8> %1,1826    i8 -9,1827    <vscale x 64 x i1> %2,1828    iXLen %3, iXLen 1)1829 1830  ret <vscale x 64 x i8> %a1831}1832 1833define <vscale x 1 x i16> @intrinsic_vadd_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, iXLen %1) nounwind {1834; CHECK-LABEL: intrinsic_vadd_vi_nxv1i16_nxv1i16_i16:1835; CHECK:       # %bb.0: # %entry1836; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma1837; CHECK-NEXT:    vadd.vi v8, v8, 91838; CHECK-NEXT:    ret1839entry:1840  %a = call <vscale x 1 x i16> @llvm.riscv.vadd.nxv1i16.i16(1841    <vscale x 1 x i16> poison,1842    <vscale x 1 x i16> %0,1843    i16 9,1844    iXLen %1)1845 1846  ret <vscale x 1 x i16> %a1847}1848 1849define <vscale x 1 x i16> @intrinsic_vadd_mask_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {1850; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv1i16_nxv1i16_i16:1851; CHECK:       # %bb.0: # %entry1852; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, mu1853; CHECK-NEXT:    vadd.vi v8, v9, -9, v0.t1854; CHECK-NEXT:    ret1855entry:1856  %a = call <vscale x 1 x i16> @llvm.riscv.vadd.mask.nxv1i16.i16(1857    <vscale x 1 x i16> %0,1858    <vscale x 1 x i16> %1,1859    i16 -9,1860    <vscale x 1 x i1> %2,1861    iXLen %3, iXLen 1)1862 1863  ret <vscale x 1 x i16> %a1864}1865 1866define <vscale x 2 x i16> @intrinsic_vadd_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, iXLen %1) nounwind {1867; CHECK-LABEL: intrinsic_vadd_vi_nxv2i16_nxv2i16_i16:1868; CHECK:       # %bb.0: # %entry1869; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma1870; CHECK-NEXT:    vadd.vi v8, v8, 91871; CHECK-NEXT:    ret1872entry:1873  %a = call <vscale x 2 x i16> @llvm.riscv.vadd.nxv2i16.i16(1874    <vscale x 2 x i16> poison,1875    <vscale x 2 x i16> %0,1876    i16 9,1877    iXLen %1)1878 1879  ret <vscale x 2 x i16> %a1880}1881 1882define <vscale x 2 x i16> @intrinsic_vadd_mask_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {1883; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv2i16_nxv2i16_i16:1884; CHECK:       # %bb.0: # %entry1885; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, mu1886; CHECK-NEXT:    vadd.vi v8, v9, -9, v0.t1887; CHECK-NEXT:    ret1888entry:1889  %a = call <vscale x 2 x i16> @llvm.riscv.vadd.mask.nxv2i16.i16(1890    <vscale x 2 x i16> %0,1891    <vscale x 2 x i16> %1,1892    i16 -9,1893    <vscale x 2 x i1> %2,1894    iXLen %3, iXLen 1)1895 1896  ret <vscale x 2 x i16> %a1897}1898 1899define <vscale x 4 x i16> @intrinsic_vadd_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, iXLen %1) nounwind {1900; CHECK-LABEL: intrinsic_vadd_vi_nxv4i16_nxv4i16_i16:1901; CHECK:       # %bb.0: # %entry1902; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma1903; CHECK-NEXT:    vadd.vi v8, v8, 91904; CHECK-NEXT:    ret1905entry:1906  %a = call <vscale x 4 x i16> @llvm.riscv.vadd.nxv4i16.i16(1907    <vscale x 4 x i16> poison,1908    <vscale x 4 x i16> %0,1909    i16 9,1910    iXLen %1)1911 1912  ret <vscale x 4 x i16> %a1913}1914 1915define <vscale x 4 x i16> @intrinsic_vadd_mask_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {1916; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv4i16_nxv4i16_i16:1917; CHECK:       # %bb.0: # %entry1918; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, mu1919; CHECK-NEXT:    vadd.vi v8, v9, -9, v0.t1920; CHECK-NEXT:    ret1921entry:1922  %a = call <vscale x 4 x i16> @llvm.riscv.vadd.mask.nxv4i16.i16(1923    <vscale x 4 x i16> %0,1924    <vscale x 4 x i16> %1,1925    i16 -9,1926    <vscale x 4 x i1> %2,1927    iXLen %3, iXLen 1)1928 1929  ret <vscale x 4 x i16> %a1930}1931 1932define <vscale x 8 x i16> @intrinsic_vadd_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, iXLen %1) nounwind {1933; CHECK-LABEL: intrinsic_vadd_vi_nxv8i16_nxv8i16_i16:1934; CHECK:       # %bb.0: # %entry1935; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma1936; CHECK-NEXT:    vadd.vi v8, v8, 91937; CHECK-NEXT:    ret1938entry:1939  %a = call <vscale x 8 x i16> @llvm.riscv.vadd.nxv8i16.i16(1940    <vscale x 8 x i16> poison,1941    <vscale x 8 x i16> %0,1942    i16 9,1943    iXLen %1)1944 1945  ret <vscale x 8 x i16> %a1946}1947 1948define <vscale x 8 x i16> @intrinsic_vadd_mask_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {1949; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv8i16_nxv8i16_i16:1950; CHECK:       # %bb.0: # %entry1951; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, mu1952; CHECK-NEXT:    vadd.vi v8, v10, -9, v0.t1953; CHECK-NEXT:    ret1954entry:1955  %a = call <vscale x 8 x i16> @llvm.riscv.vadd.mask.nxv8i16.i16(1956    <vscale x 8 x i16> %0,1957    <vscale x 8 x i16> %1,1958    i16 -9,1959    <vscale x 8 x i1> %2,1960    iXLen %3, iXLen 1)1961 1962  ret <vscale x 8 x i16> %a1963}1964 1965define <vscale x 16 x i16> @intrinsic_vadd_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, iXLen %1) nounwind {1966; CHECK-LABEL: intrinsic_vadd_vi_nxv16i16_nxv16i16_i16:1967; CHECK:       # %bb.0: # %entry1968; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma1969; CHECK-NEXT:    vadd.vi v8, v8, 91970; CHECK-NEXT:    ret1971entry:1972  %a = call <vscale x 16 x i16> @llvm.riscv.vadd.nxv16i16.i16(1973    <vscale x 16 x i16> poison,1974    <vscale x 16 x i16> %0,1975    i16 9,1976    iXLen %1)1977 1978  ret <vscale x 16 x i16> %a1979}1980 1981define <vscale x 16 x i16> @intrinsic_vadd_mask_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {1982; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv16i16_nxv16i16_i16:1983; CHECK:       # %bb.0: # %entry1984; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, mu1985; CHECK-NEXT:    vadd.vi v8, v12, -9, v0.t1986; CHECK-NEXT:    ret1987entry:1988  %a = call <vscale x 16 x i16> @llvm.riscv.vadd.mask.nxv16i16.i16(1989    <vscale x 16 x i16> %0,1990    <vscale x 16 x i16> %1,1991    i16 -9,1992    <vscale x 16 x i1> %2,1993    iXLen %3, iXLen 1)1994 1995  ret <vscale x 16 x i16> %a1996}1997 1998define <vscale x 32 x i16> @intrinsic_vadd_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, iXLen %1) nounwind {1999; CHECK-LABEL: intrinsic_vadd_vi_nxv32i16_nxv32i16_i16:2000; CHECK:       # %bb.0: # %entry2001; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, ma2002; CHECK-NEXT:    vadd.vi v8, v8, 92003; CHECK-NEXT:    ret2004entry:2005  %a = call <vscale x 32 x i16> @llvm.riscv.vadd.nxv32i16.i16(2006    <vscale x 32 x i16> poison,2007    <vscale x 32 x i16> %0,2008    i16 9,2009    iXLen %1)2010 2011  ret <vscale x 32 x i16> %a2012}2013 2014define <vscale x 32 x i16> @intrinsic_vadd_mask_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {2015; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv32i16_nxv32i16_i16:2016; CHECK:       # %bb.0: # %entry2017; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, mu2018; CHECK-NEXT:    vadd.vi v8, v16, -9, v0.t2019; CHECK-NEXT:    ret2020entry:2021  %a = call <vscale x 32 x i16> @llvm.riscv.vadd.mask.nxv32i16.i16(2022    <vscale x 32 x i16> %0,2023    <vscale x 32 x i16> %1,2024    i16 -9,2025    <vscale x 32 x i1> %2,2026    iXLen %3, iXLen 1)2027 2028  ret <vscale x 32 x i16> %a2029}2030 2031define <vscale x 1 x i32> @intrinsic_vadd_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, iXLen %1) nounwind {2032; CHECK-LABEL: intrinsic_vadd_vi_nxv1i32_nxv1i32_i32:2033; CHECK:       # %bb.0: # %entry2034; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma2035; CHECK-NEXT:    vadd.vi v8, v8, 92036; CHECK-NEXT:    ret2037entry:2038  %a = call <vscale x 1 x i32> @llvm.riscv.vadd.nxv1i32.i32(2039    <vscale x 1 x i32> poison,2040    <vscale x 1 x i32> %0,2041    i32 9,2042    iXLen %1)2043 2044  ret <vscale x 1 x i32> %a2045}2046 2047define <vscale x 1 x i32> @intrinsic_vadd_mask_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {2048; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv1i32_nxv1i32_i32:2049; CHECK:       # %bb.0: # %entry2050; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, mu2051; CHECK-NEXT:    vadd.vi v8, v9, -9, v0.t2052; CHECK-NEXT:    ret2053entry:2054  %a = call <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.i32(2055    <vscale x 1 x i32> %0,2056    <vscale x 1 x i32> %1,2057    i32 -9,2058    <vscale x 1 x i1> %2,2059    iXLen %3, iXLen 1)2060 2061  ret <vscale x 1 x i32> %a2062}2063 2064define <vscale x 2 x i32> @intrinsic_vadd_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, iXLen %1) nounwind {2065; CHECK-LABEL: intrinsic_vadd_vi_nxv2i32_nxv2i32_i32:2066; CHECK:       # %bb.0: # %entry2067; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma2068; CHECK-NEXT:    vadd.vi v8, v8, 92069; CHECK-NEXT:    ret2070entry:2071  %a = call <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32.i32(2072    <vscale x 2 x i32> poison,2073    <vscale x 2 x i32> %0,2074    i32 9,2075    iXLen %1)2076 2077  ret <vscale x 2 x i32> %a2078}2079 2080define <vscale x 2 x i32> @intrinsic_vadd_mask_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {2081; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv2i32_nxv2i32_i32:2082; CHECK:       # %bb.0: # %entry2083; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, mu2084; CHECK-NEXT:    vadd.vi v8, v9, -9, v0.t2085; CHECK-NEXT:    ret2086entry:2087  %a = call <vscale x 2 x i32> @llvm.riscv.vadd.mask.nxv2i32.i32(2088    <vscale x 2 x i32> %0,2089    <vscale x 2 x i32> %1,2090    i32 -9,2091    <vscale x 2 x i1> %2,2092    iXLen %3, iXLen 1)2093 2094  ret <vscale x 2 x i32> %a2095}2096 2097define <vscale x 4 x i32> @intrinsic_vadd_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, iXLen %1) nounwind {2098; CHECK-LABEL: intrinsic_vadd_vi_nxv4i32_nxv4i32_i32:2099; CHECK:       # %bb.0: # %entry2100; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma2101; CHECK-NEXT:    vadd.vi v8, v8, 92102; CHECK-NEXT:    ret2103entry:2104  %a = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.i32(2105    <vscale x 4 x i32> poison,2106    <vscale x 4 x i32> %0,2107    i32 9,2108    iXLen %1)2109 2110  ret <vscale x 4 x i32> %a2111}2112 2113define <vscale x 4 x i32> @intrinsic_vadd_mask_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {2114; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv4i32_nxv4i32_i32:2115; CHECK:       # %bb.0: # %entry2116; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, mu2117; CHECK-NEXT:    vadd.vi v8, v10, -9, v0.t2118; CHECK-NEXT:    ret2119entry:2120  %a = call <vscale x 4 x i32> @llvm.riscv.vadd.mask.nxv4i32.i32(2121    <vscale x 4 x i32> %0,2122    <vscale x 4 x i32> %1,2123    i32 -9,2124    <vscale x 4 x i1> %2,2125    iXLen %3, iXLen 1)2126 2127  ret <vscale x 4 x i32> %a2128}2129 2130define <vscale x 8 x i32> @intrinsic_vadd_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, iXLen %1) nounwind {2131; CHECK-LABEL: intrinsic_vadd_vi_nxv8i32_nxv8i32_i32:2132; CHECK:       # %bb.0: # %entry2133; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma2134; CHECK-NEXT:    vadd.vi v8, v8, 92135; CHECK-NEXT:    ret2136entry:2137  %a = call <vscale x 8 x i32> @llvm.riscv.vadd.nxv8i32.i32(2138    <vscale x 8 x i32> poison,2139    <vscale x 8 x i32> %0,2140    i32 9,2141    iXLen %1)2142 2143  ret <vscale x 8 x i32> %a2144}2145 2146define <vscale x 8 x i32> @intrinsic_vadd_mask_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {2147; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv8i32_nxv8i32_i32:2148; CHECK:       # %bb.0: # %entry2149; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, mu2150; CHECK-NEXT:    vadd.vi v8, v12, -9, v0.t2151; CHECK-NEXT:    ret2152entry:2153  %a = call <vscale x 8 x i32> @llvm.riscv.vadd.mask.nxv8i32.i32(2154    <vscale x 8 x i32> %0,2155    <vscale x 8 x i32> %1,2156    i32 -9,2157    <vscale x 8 x i1> %2,2158    iXLen %3, iXLen 1)2159 2160  ret <vscale x 8 x i32> %a2161}2162 2163define <vscale x 16 x i32> @intrinsic_vadd_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, iXLen %1) nounwind {2164; CHECK-LABEL: intrinsic_vadd_vi_nxv16i32_nxv16i32_i32:2165; CHECK:       # %bb.0: # %entry2166; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma2167; CHECK-NEXT:    vadd.vi v8, v8, 92168; CHECK-NEXT:    ret2169entry:2170  %a = call <vscale x 16 x i32> @llvm.riscv.vadd.nxv16i32.i32(2171    <vscale x 16 x i32> poison,2172    <vscale x 16 x i32> %0,2173    i32 9,2174    iXLen %1)2175 2176  ret <vscale x 16 x i32> %a2177}2178 2179define <vscale x 16 x i32> @intrinsic_vadd_mask_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {2180; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv16i32_nxv16i32_i32:2181; CHECK:       # %bb.0: # %entry2182; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, mu2183; CHECK-NEXT:    vadd.vi v8, v16, -9, v0.t2184; CHECK-NEXT:    ret2185entry:2186  %a = call <vscale x 16 x i32> @llvm.riscv.vadd.mask.nxv16i32.i32(2187    <vscale x 16 x i32> %0,2188    <vscale x 16 x i32> %1,2189    i32 -9,2190    <vscale x 16 x i1> %2,2191    iXLen %3, iXLen 1)2192 2193  ret <vscale x 16 x i32> %a2194}2195 2196define <vscale x 1 x i64> @intrinsic_vadd_vi_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, iXLen %1) nounwind {2197; CHECK-LABEL: intrinsic_vadd_vi_nxv1i64_nxv1i64_i64:2198; CHECK:       # %bb.0: # %entry2199; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma2200; CHECK-NEXT:    vadd.vi v8, v8, 92201; CHECK-NEXT:    ret2202entry:2203  %a = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.i64(2204    <vscale x 1 x i64> poison,2205    <vscale x 1 x i64> %0,2206    i64 9,2207    iXLen %1)2208 2209  ret <vscale x 1 x i64> %a2210}2211 2212define <vscale x 1 x i64> @intrinsic_vadd_mask_vi_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {2213; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv1i64_nxv1i64_i64:2214; CHECK:       # %bb.0: # %entry2215; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, mu2216; CHECK-NEXT:    vadd.vi v8, v9, 9, v0.t2217; CHECK-NEXT:    ret2218entry:2219  %a = call <vscale x 1 x i64> @llvm.riscv.vadd.mask.nxv1i64.i64(2220    <vscale x 1 x i64> %0,2221    <vscale x 1 x i64> %1,2222    i64 9,2223    <vscale x 1 x i1> %2,2224    iXLen %3, iXLen 1)2225 2226  ret <vscale x 1 x i64> %a2227}2228 2229define <vscale x 2 x i64> @intrinsic_vadd_vi_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, iXLen %1) nounwind {2230; CHECK-LABEL: intrinsic_vadd_vi_nxv2i64_nxv2i64_i64:2231; CHECK:       # %bb.0: # %entry2232; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma2233; CHECK-NEXT:    vadd.vi v8, v8, 92234; CHECK-NEXT:    ret2235entry:2236  %a = call <vscale x 2 x i64> @llvm.riscv.vadd.nxv2i64.i64(2237    <vscale x 2 x i64> poison,2238    <vscale x 2 x i64> %0,2239    i64 9,2240    iXLen %1)2241 2242  ret <vscale x 2 x i64> %a2243}2244 2245define <vscale x 2 x i64> @intrinsic_vadd_mask_vi_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {2246; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv2i64_nxv2i64_i64:2247; CHECK:       # %bb.0: # %entry2248; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, mu2249; CHECK-NEXT:    vadd.vi v8, v10, 9, v0.t2250; CHECK-NEXT:    ret2251entry:2252  %a = call <vscale x 2 x i64> @llvm.riscv.vadd.mask.nxv2i64.i64(2253    <vscale x 2 x i64> %0,2254    <vscale x 2 x i64> %1,2255    i64 9,2256    <vscale x 2 x i1> %2,2257    iXLen %3, iXLen 1)2258 2259  ret <vscale x 2 x i64> %a2260}2261 2262define <vscale x 4 x i64> @intrinsic_vadd_vi_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, iXLen %1) nounwind {2263; CHECK-LABEL: intrinsic_vadd_vi_nxv4i64_nxv4i64_i64:2264; CHECK:       # %bb.0: # %entry2265; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma2266; CHECK-NEXT:    vadd.vi v8, v8, 92267; CHECK-NEXT:    ret2268entry:2269  %a = call <vscale x 4 x i64> @llvm.riscv.vadd.nxv4i64.i64(2270    <vscale x 4 x i64> poison,2271    <vscale x 4 x i64> %0,2272    i64 9,2273    iXLen %1)2274 2275  ret <vscale x 4 x i64> %a2276}2277 2278define <vscale x 4 x i64> @intrinsic_vadd_mask_vi_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {2279; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv4i64_nxv4i64_i64:2280; CHECK:       # %bb.0: # %entry2281; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, mu2282; CHECK-NEXT:    vadd.vi v8, v12, 9, v0.t2283; CHECK-NEXT:    ret2284entry:2285  %a = call <vscale x 4 x i64> @llvm.riscv.vadd.mask.nxv4i64.i64(2286    <vscale x 4 x i64> %0,2287    <vscale x 4 x i64> %1,2288    i64 9,2289    <vscale x 4 x i1> %2,2290    iXLen %3, iXLen 1)2291 2292  ret <vscale x 4 x i64> %a2293}2294 2295define <vscale x 8 x i64> @intrinsic_vadd_vi_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, iXLen %1) nounwind {2296; CHECK-LABEL: intrinsic_vadd_vi_nxv8i64_nxv8i64_i64:2297; CHECK:       # %bb.0: # %entry2298; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma2299; CHECK-NEXT:    vadd.vi v8, v8, 92300; CHECK-NEXT:    ret2301entry:2302  %a = call <vscale x 8 x i64> @llvm.riscv.vadd.nxv8i64.i64(2303    <vscale x 8 x i64> poison,2304    <vscale x 8 x i64> %0,2305    i64 9,2306    iXLen %1)2307 2308  ret <vscale x 8 x i64> %a2309}2310 2311define <vscale x 8 x i64> @intrinsic_vadd_mask_vi_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {2312; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv8i64_nxv8i64_i64:2313; CHECK:       # %bb.0: # %entry2314; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, mu2315; CHECK-NEXT:    vadd.vi v8, v16, 9, v0.t2316; CHECK-NEXT:    ret2317entry:2318  %a = call <vscale x 8 x i64> @llvm.riscv.vadd.mask.nxv8i64.i64(2319    <vscale x 8 x i64> %0,2320    <vscale x 8 x i64> %1,2321    i64 9,2322    <vscale x 8 x i1> %2,2323    iXLen %3, iXLen 1)2324 2325  ret <vscale x 8 x i64> %a2326}2327