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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvkned \3; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvkned \5; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK6 7define <vscale x 4 x i32> @intrinsic_vaesef_vv_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, iXLen %2) nounwind {8; CHECK-LABEL: intrinsic_vaesef_vv_nxv4i32:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma11; CHECK-NEXT: vaesef.vv v8, v1012; CHECK-NEXT: ret13entry:14 %a = call <vscale x 4 x i32> @llvm.riscv.vaesef.vv.nxv4i32(15 <vscale x 4 x i32> %0,16 <vscale x 4 x i32> %1,17 iXLen %2, iXLen 2)18 19 ret <vscale x 4 x i32> %a20}21 22define <vscale x 8 x i32> @intrinsic_vaesef_vv_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, iXLen %2) nounwind {23; CHECK-LABEL: intrinsic_vaesef_vv_nxv8i32:24; CHECK: # %bb.0: # %entry25; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma26; CHECK-NEXT: vaesef.vv v8, v1227; CHECK-NEXT: ret28entry:29 %a = call <vscale x 8 x i32> @llvm.riscv.vaesef.vv.nxv8i32(30 <vscale x 8 x i32> %0,31 <vscale x 8 x i32> %1,32 iXLen %2, iXLen 2)33 34 ret <vscale x 8 x i32> %a35}36 37define <vscale x 16 x i32> @intrinsic_vaesef_vv_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, iXLen %2) nounwind {38; CHECK-LABEL: intrinsic_vaesef_vv_nxv16i32:39; CHECK: # %bb.0: # %entry40; CHECK-NEXT: vsetvli zero, a0, e32, m8, tu, ma41; CHECK-NEXT: vaesef.vv v8, v1642; CHECK-NEXT: ret43entry:44 %a = call <vscale x 16 x i32> @llvm.riscv.vaesef.vv.nxv16i32(45 <vscale x 16 x i32> %0,46 <vscale x 16 x i32> %1,47 iXLen %2, iXLen 2)48 49 ret <vscale x 16 x i32> %a50}51 52define <vscale x 4 x i32> @intrinsic_vaesef_vs_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, iXLen %2) nounwind {53; CHECK-LABEL: intrinsic_vaesef_vs_nxv4i32:54; CHECK: # %bb.0: # %entry55; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma56; CHECK-NEXT: vaesef.vs v8, v1057; CHECK-NEXT: ret58entry:59 %a = call <vscale x 4 x i32> @llvm.riscv.vaesef.vs.nxv4i32.nxv4i32(60 <vscale x 4 x i32> %0,61 <vscale x 4 x i32> %1,62 iXLen %2, iXLen 2)63 64 ret <vscale x 4 x i32> %a65}66 67define <vscale x 8 x i32> @intrinsic_vaesef_vs_nxv8i32(<vscale x 8 x i32> %0, <vscale x 4 x i32> %1, iXLen %2) nounwind {68; CHECK-LABEL: intrinsic_vaesef_vs_nxv8i32:69; CHECK: # %bb.0: # %entry70; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma71; CHECK-NEXT: vaesef.vs v8, v1272; CHECK-NEXT: ret73entry:74 %a = call <vscale x 8 x i32> @llvm.riscv.vaesef.vs.nxv8i32.nxv4i32(75 <vscale x 8 x i32> %0,76 <vscale x 4 x i32> %1,77 iXLen %2, iXLen 2)78 79 ret <vscale x 8 x i32> %a80}81 82define <vscale x 16 x i32> @intrinsic_vaesef_vs_nxv16i32(<vscale x 16 x i32> %0, <vscale x 4 x i32> %1, iXLen %2) nounwind {83; CHECK-LABEL: intrinsic_vaesef_vs_nxv16i32:84; CHECK: # %bb.0: # %entry85; CHECK-NEXT: vsetvli zero, a0, e32, m8, tu, ma86; CHECK-NEXT: vaesef.vs v8, v1687; CHECK-NEXT: ret88entry:89 %a = call <vscale x 16 x i32> @llvm.riscv.vaesef.vs.nxv16i32.nxv4i32(90 <vscale x 16 x i32> %0,91 <vscale x 4 x i32> %1,92 iXLen %2, iXLen 2)93 94 ret <vscale x 16 x i32> %a95}96