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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV323; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV644 5define <vscale x 1 x i8> @vand_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) {6; CHECK-LABEL: vand_vv_nxv1i8:7; CHECK: # %bb.0:8; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma9; CHECK-NEXT: vand.vv v8, v8, v910; CHECK-NEXT: ret11 %vc = and <vscale x 1 x i8> %va, %vb12 ret <vscale x 1 x i8> %vc13}14 15define <vscale x 1 x i8> @vand_vx_nxv1i8(<vscale x 1 x i8> %va, i8 signext %b) {16; CHECK-LABEL: vand_vx_nxv1i8:17; CHECK: # %bb.0:18; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma19; CHECK-NEXT: vand.vx v8, v8, a020; CHECK-NEXT: ret21 %head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 022 %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer23 %vc = and <vscale x 1 x i8> %va, %splat24 ret <vscale x 1 x i8> %vc25}26 27define <vscale x 1 x i8> @vand_vi_nxv1i8_0(<vscale x 1 x i8> %va) {28; CHECK-LABEL: vand_vi_nxv1i8_0:29; CHECK: # %bb.0:30; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma31; CHECK-NEXT: vand.vi v8, v8, -1032; CHECK-NEXT: ret33 %vc = and <vscale x 1 x i8> %va, splat (i8 -10)34 ret <vscale x 1 x i8> %vc35}36 37define <vscale x 1 x i8> @vand_vi_nxv1i8_1(<vscale x 1 x i8> %va) {38; CHECK-LABEL: vand_vi_nxv1i8_1:39; CHECK: # %bb.0:40; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma41; CHECK-NEXT: vand.vi v8, v8, 842; CHECK-NEXT: ret43 %vc = and <vscale x 1 x i8> %va, splat (i8 8)44 ret <vscale x 1 x i8> %vc45}46 47define <vscale x 1 x i8> @vand_vi_nxv1i8_2(<vscale x 1 x i8> %va) {48; CHECK-LABEL: vand_vi_nxv1i8_2:49; CHECK: # %bb.0:50; CHECK-NEXT: li a0, 1651; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma52; CHECK-NEXT: vand.vx v8, v8, a053; CHECK-NEXT: ret54 %vc = and <vscale x 1 x i8> %va, splat (i8 16)55 ret <vscale x 1 x i8> %vc56}57 58define <vscale x 2 x i8> @vand_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb) {59; CHECK-LABEL: vand_vv_nxv2i8:60; CHECK: # %bb.0:61; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma62; CHECK-NEXT: vand.vv v8, v8, v963; CHECK-NEXT: ret64 %vc = and <vscale x 2 x i8> %va, %vb65 ret <vscale x 2 x i8> %vc66}67 68define <vscale x 2 x i8> @vand_vx_nxv2i8(<vscale x 2 x i8> %va, i8 signext %b) {69; CHECK-LABEL: vand_vx_nxv2i8:70; CHECK: # %bb.0:71; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma72; CHECK-NEXT: vand.vx v8, v8, a073; CHECK-NEXT: ret74 %head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 075 %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer76 %vc = and <vscale x 2 x i8> %va, %splat77 ret <vscale x 2 x i8> %vc78}79 80define <vscale x 2 x i8> @vand_vi_nxv2i8_0(<vscale x 2 x i8> %va) {81; CHECK-LABEL: vand_vi_nxv2i8_0:82; CHECK: # %bb.0:83; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma84; CHECK-NEXT: vand.vi v8, v8, -1085; CHECK-NEXT: ret86 %vc = and <vscale x 2 x i8> %va, splat (i8 -10)87 ret <vscale x 2 x i8> %vc88}89 90define <vscale x 2 x i8> @vand_vi_nxv2i8_1(<vscale x 2 x i8> %va) {91; CHECK-LABEL: vand_vi_nxv2i8_1:92; CHECK: # %bb.0:93; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma94; CHECK-NEXT: vand.vi v8, v8, 895; CHECK-NEXT: ret96 %vc = and <vscale x 2 x i8> %va, splat (i8 8)97 ret <vscale x 2 x i8> %vc98}99 100define <vscale x 2 x i8> @vand_vi_nxv2i8_2(<vscale x 2 x i8> %va) {101; CHECK-LABEL: vand_vi_nxv2i8_2:102; CHECK: # %bb.0:103; CHECK-NEXT: li a0, 16104; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma105; CHECK-NEXT: vand.vx v8, v8, a0106; CHECK-NEXT: ret107 %vc = and <vscale x 2 x i8> %va, splat (i8 16)108 ret <vscale x 2 x i8> %vc109}110 111define <vscale x 4 x i8> @vand_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) {112; CHECK-LABEL: vand_vv_nxv4i8:113; CHECK: # %bb.0:114; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma115; CHECK-NEXT: vand.vv v8, v8, v9116; CHECK-NEXT: ret117 %vc = and <vscale x 4 x i8> %va, %vb118 ret <vscale x 4 x i8> %vc119}120 121define <vscale x 4 x i8> @vand_vx_nxv4i8(<vscale x 4 x i8> %va, i8 signext %b) {122; CHECK-LABEL: vand_vx_nxv4i8:123; CHECK: # %bb.0:124; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma125; CHECK-NEXT: vand.vx v8, v8, a0126; CHECK-NEXT: ret127 %head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0128 %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer129 %vc = and <vscale x 4 x i8> %va, %splat130 ret <vscale x 4 x i8> %vc131}132 133define <vscale x 4 x i8> @vand_vi_nxv4i8_0(<vscale x 4 x i8> %va) {134; CHECK-LABEL: vand_vi_nxv4i8_0:135; CHECK: # %bb.0:136; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma137; CHECK-NEXT: vand.vi v8, v8, -10138; CHECK-NEXT: ret139 %vc = and <vscale x 4 x i8> %va, splat (i8 -10)140 ret <vscale x 4 x i8> %vc141}142 143define <vscale x 4 x i8> @vand_vi_nxv4i8_1(<vscale x 4 x i8> %va) {144; CHECK-LABEL: vand_vi_nxv4i8_1:145; CHECK: # %bb.0:146; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma147; CHECK-NEXT: vand.vi v8, v8, 8148; CHECK-NEXT: ret149 %vc = and <vscale x 4 x i8> %va, splat (i8 8)150 ret <vscale x 4 x i8> %vc151}152 153define <vscale x 4 x i8> @vand_vi_nxv4i8_2(<vscale x 4 x i8> %va) {154; CHECK-LABEL: vand_vi_nxv4i8_2:155; CHECK: # %bb.0:156; CHECK-NEXT: li a0, 16157; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma158; CHECK-NEXT: vand.vx v8, v8, a0159; CHECK-NEXT: ret160 %vc = and <vscale x 4 x i8> %va, splat (i8 16)161 ret <vscale x 4 x i8> %vc162}163 164define <vscale x 8 x i8> @vand_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {165; CHECK-LABEL: vand_vv_nxv8i8:166; CHECK: # %bb.0:167; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma168; CHECK-NEXT: vand.vv v8, v8, v9169; CHECK-NEXT: ret170 %vc = and <vscale x 8 x i8> %va, %vb171 ret <vscale x 8 x i8> %vc172}173 174define <vscale x 8 x i8> @vand_vx_nxv8i8(<vscale x 8 x i8> %va, i8 signext %b) {175; CHECK-LABEL: vand_vx_nxv8i8:176; CHECK: # %bb.0:177; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma178; CHECK-NEXT: vand.vx v8, v8, a0179; CHECK-NEXT: ret180 %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0181 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer182 %vc = and <vscale x 8 x i8> %va, %splat183 ret <vscale x 8 x i8> %vc184}185 186define <vscale x 8 x i8> @vand_vi_nxv8i8_0(<vscale x 8 x i8> %va) {187; CHECK-LABEL: vand_vi_nxv8i8_0:188; CHECK: # %bb.0:189; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma190; CHECK-NEXT: vand.vi v8, v8, -10191; CHECK-NEXT: ret192 %vc = and <vscale x 8 x i8> %va, splat (i8 -10)193 ret <vscale x 8 x i8> %vc194}195 196define <vscale x 8 x i8> @vand_vi_nxv8i8_1(<vscale x 8 x i8> %va) {197; CHECK-LABEL: vand_vi_nxv8i8_1:198; CHECK: # %bb.0:199; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma200; CHECK-NEXT: vand.vi v8, v8, 8201; CHECK-NEXT: ret202 %vc = and <vscale x 8 x i8> %va, splat (i8 8)203 ret <vscale x 8 x i8> %vc204}205 206define <vscale x 8 x i8> @vand_vi_nxv8i8_2(<vscale x 8 x i8> %va) {207; CHECK-LABEL: vand_vi_nxv8i8_2:208; CHECK: # %bb.0:209; CHECK-NEXT: li a0, 16210; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma211; CHECK-NEXT: vand.vx v8, v8, a0212; CHECK-NEXT: ret213 %vc = and <vscale x 8 x i8> %va, splat (i8 16)214 ret <vscale x 8 x i8> %vc215}216 217define <vscale x 16 x i8> @vand_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb) {218; CHECK-LABEL: vand_vv_nxv16i8:219; CHECK: # %bb.0:220; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma221; CHECK-NEXT: vand.vv v8, v8, v10222; CHECK-NEXT: ret223 %vc = and <vscale x 16 x i8> %va, %vb224 ret <vscale x 16 x i8> %vc225}226 227define <vscale x 16 x i8> @vand_vx_nxv16i8(<vscale x 16 x i8> %va, i8 signext %b) {228; CHECK-LABEL: vand_vx_nxv16i8:229; CHECK: # %bb.0:230; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma231; CHECK-NEXT: vand.vx v8, v8, a0232; CHECK-NEXT: ret233 %head = insertelement <vscale x 16 x i8> poison, i8 %b, i32 0234 %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer235 %vc = and <vscale x 16 x i8> %va, %splat236 ret <vscale x 16 x i8> %vc237}238 239define <vscale x 16 x i8> @vand_vi_nxv16i8_0(<vscale x 16 x i8> %va) {240; CHECK-LABEL: vand_vi_nxv16i8_0:241; CHECK: # %bb.0:242; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma243; CHECK-NEXT: vand.vi v8, v8, -10244; CHECK-NEXT: ret245 %vc = and <vscale x 16 x i8> %va, splat (i8 -10)246 ret <vscale x 16 x i8> %vc247}248 249define <vscale x 16 x i8> @vand_vi_nxv16i8_1(<vscale x 16 x i8> %va) {250; CHECK-LABEL: vand_vi_nxv16i8_1:251; CHECK: # %bb.0:252; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma253; CHECK-NEXT: vand.vi v8, v8, 8254; CHECK-NEXT: ret255 %vc = and <vscale x 16 x i8> %va, splat (i8 8)256 ret <vscale x 16 x i8> %vc257}258 259define <vscale x 16 x i8> @vand_vi_nxv16i8_2(<vscale x 16 x i8> %va) {260; CHECK-LABEL: vand_vi_nxv16i8_2:261; CHECK: # %bb.0:262; CHECK-NEXT: li a0, 16263; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma264; CHECK-NEXT: vand.vx v8, v8, a0265; CHECK-NEXT: ret266 %vc = and <vscale x 16 x i8> %va, splat (i8 16)267 ret <vscale x 16 x i8> %vc268}269 270define <vscale x 32 x i8> @vand_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb) {271; CHECK-LABEL: vand_vv_nxv32i8:272; CHECK: # %bb.0:273; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma274; CHECK-NEXT: vand.vv v8, v8, v12275; CHECK-NEXT: ret276 %vc = and <vscale x 32 x i8> %va, %vb277 ret <vscale x 32 x i8> %vc278}279 280define <vscale x 32 x i8> @vand_vx_nxv32i8(<vscale x 32 x i8> %va, i8 signext %b) {281; CHECK-LABEL: vand_vx_nxv32i8:282; CHECK: # %bb.0:283; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma284; CHECK-NEXT: vand.vx v8, v8, a0285; CHECK-NEXT: ret286 %head = insertelement <vscale x 32 x i8> poison, i8 %b, i32 0287 %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer288 %vc = and <vscale x 32 x i8> %va, %splat289 ret <vscale x 32 x i8> %vc290}291 292define <vscale x 32 x i8> @vand_vi_nxv32i8_0(<vscale x 32 x i8> %va) {293; CHECK-LABEL: vand_vi_nxv32i8_0:294; CHECK: # %bb.0:295; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma296; CHECK-NEXT: vand.vi v8, v8, -10297; CHECK-NEXT: ret298 %vc = and <vscale x 32 x i8> %va, splat (i8 -10)299 ret <vscale x 32 x i8> %vc300}301 302define <vscale x 32 x i8> @vand_vi_nxv32i8_1(<vscale x 32 x i8> %va) {303; CHECK-LABEL: vand_vi_nxv32i8_1:304; CHECK: # %bb.0:305; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma306; CHECK-NEXT: vand.vi v8, v8, 8307; CHECK-NEXT: ret308 %vc = and <vscale x 32 x i8> %va, splat (i8 8)309 ret <vscale x 32 x i8> %vc310}311 312define <vscale x 32 x i8> @vand_vi_nxv32i8_2(<vscale x 32 x i8> %va) {313; CHECK-LABEL: vand_vi_nxv32i8_2:314; CHECK: # %bb.0:315; CHECK-NEXT: li a0, 16316; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma317; CHECK-NEXT: vand.vx v8, v8, a0318; CHECK-NEXT: ret319 %vc = and <vscale x 32 x i8> %va, splat (i8 16)320 ret <vscale x 32 x i8> %vc321}322 323define <vscale x 64 x i8> @vand_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb) {324; CHECK-LABEL: vand_vv_nxv64i8:325; CHECK: # %bb.0:326; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma327; CHECK-NEXT: vand.vv v8, v8, v16328; CHECK-NEXT: ret329 %vc = and <vscale x 64 x i8> %va, %vb330 ret <vscale x 64 x i8> %vc331}332 333define <vscale x 64 x i8> @vand_vx_nxv64i8(<vscale x 64 x i8> %va, i8 signext %b) {334; CHECK-LABEL: vand_vx_nxv64i8:335; CHECK: # %bb.0:336; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma337; CHECK-NEXT: vand.vx v8, v8, a0338; CHECK-NEXT: ret339 %head = insertelement <vscale x 64 x i8> poison, i8 %b, i32 0340 %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer341 %vc = and <vscale x 64 x i8> %va, %splat342 ret <vscale x 64 x i8> %vc343}344 345define <vscale x 64 x i8> @vand_vi_nxv64i8_0(<vscale x 64 x i8> %va) {346; CHECK-LABEL: vand_vi_nxv64i8_0:347; CHECK: # %bb.0:348; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma349; CHECK-NEXT: vand.vi v8, v8, -10350; CHECK-NEXT: ret351 %vc = and <vscale x 64 x i8> %va, splat (i8 -10)352 ret <vscale x 64 x i8> %vc353}354 355define <vscale x 64 x i8> @vand_vi_nxv64i8_1(<vscale x 64 x i8> %va) {356; CHECK-LABEL: vand_vi_nxv64i8_1:357; CHECK: # %bb.0:358; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma359; CHECK-NEXT: vand.vi v8, v8, 8360; CHECK-NEXT: ret361 %vc = and <vscale x 64 x i8> %va, splat (i8 8)362 ret <vscale x 64 x i8> %vc363}364 365define <vscale x 64 x i8> @vand_vi_nxv64i8_2(<vscale x 64 x i8> %va) {366; CHECK-LABEL: vand_vi_nxv64i8_2:367; CHECK: # %bb.0:368; CHECK-NEXT: li a0, 16369; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma370; CHECK-NEXT: vand.vx v8, v8, a0371; CHECK-NEXT: ret372 %vc = and <vscale x 64 x i8> %va, splat (i8 16)373 ret <vscale x 64 x i8> %vc374}375 376define <vscale x 1 x i16> @vand_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) {377; CHECK-LABEL: vand_vv_nxv1i16:378; CHECK: # %bb.0:379; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma380; CHECK-NEXT: vand.vv v8, v8, v9381; CHECK-NEXT: ret382 %vc = and <vscale x 1 x i16> %va, %vb383 ret <vscale x 1 x i16> %vc384}385 386define <vscale x 1 x i16> @vand_vx_nxv1i16(<vscale x 1 x i16> %va, i16 signext %b) {387; CHECK-LABEL: vand_vx_nxv1i16:388; CHECK: # %bb.0:389; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma390; CHECK-NEXT: vand.vx v8, v8, a0391; CHECK-NEXT: ret392 %head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0393 %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer394 %vc = and <vscale x 1 x i16> %va, %splat395 ret <vscale x 1 x i16> %vc396}397 398define <vscale x 1 x i16> @vand_vi_nxv1i16_0(<vscale x 1 x i16> %va) {399; CHECK-LABEL: vand_vi_nxv1i16_0:400; CHECK: # %bb.0:401; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma402; CHECK-NEXT: vand.vi v8, v8, -10403; CHECK-NEXT: ret404 %vc = and <vscale x 1 x i16> %va, splat (i16 -10)405 ret <vscale x 1 x i16> %vc406}407 408define <vscale x 1 x i16> @vand_vi_nxv1i16_1(<vscale x 1 x i16> %va) {409; CHECK-LABEL: vand_vi_nxv1i16_1:410; CHECK: # %bb.0:411; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma412; CHECK-NEXT: vand.vi v8, v8, 8413; CHECK-NEXT: ret414 %vc = and <vscale x 1 x i16> %va, splat (i16 8)415 ret <vscale x 1 x i16> %vc416}417 418define <vscale x 1 x i16> @vand_vi_nxv1i16_2(<vscale x 1 x i16> %va) {419; CHECK-LABEL: vand_vi_nxv1i16_2:420; CHECK: # %bb.0:421; CHECK-NEXT: li a0, 16422; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma423; CHECK-NEXT: vand.vx v8, v8, a0424; CHECK-NEXT: ret425 %vc = and <vscale x 1 x i16> %va, splat (i16 16)426 ret <vscale x 1 x i16> %vc427}428 429define <vscale x 2 x i16> @vand_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) {430; CHECK-LABEL: vand_vv_nxv2i16:431; CHECK: # %bb.0:432; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma433; CHECK-NEXT: vand.vv v8, v8, v9434; CHECK-NEXT: ret435 %vc = and <vscale x 2 x i16> %va, %vb436 ret <vscale x 2 x i16> %vc437}438 439define <vscale x 2 x i16> @vand_vx_nxv2i16(<vscale x 2 x i16> %va, i16 signext %b) {440; CHECK-LABEL: vand_vx_nxv2i16:441; CHECK: # %bb.0:442; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma443; CHECK-NEXT: vand.vx v8, v8, a0444; CHECK-NEXT: ret445 %head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0446 %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer447 %vc = and <vscale x 2 x i16> %va, %splat448 ret <vscale x 2 x i16> %vc449}450 451define <vscale x 2 x i16> @vand_vi_nxv2i16_0(<vscale x 2 x i16> %va) {452; CHECK-LABEL: vand_vi_nxv2i16_0:453; CHECK: # %bb.0:454; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma455; CHECK-NEXT: vand.vi v8, v8, -10456; CHECK-NEXT: ret457 %vc = and <vscale x 2 x i16> %va, splat (i16 -10)458 ret <vscale x 2 x i16> %vc459}460 461define <vscale x 2 x i16> @vand_vi_nxv2i16_1(<vscale x 2 x i16> %va) {462; CHECK-LABEL: vand_vi_nxv2i16_1:463; CHECK: # %bb.0:464; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma465; CHECK-NEXT: vand.vi v8, v8, 8466; CHECK-NEXT: ret467 %vc = and <vscale x 2 x i16> %va, splat (i16 8)468 ret <vscale x 2 x i16> %vc469}470 471define <vscale x 2 x i16> @vand_vi_nxv2i16_2(<vscale x 2 x i16> %va) {472; CHECK-LABEL: vand_vi_nxv2i16_2:473; CHECK: # %bb.0:474; CHECK-NEXT: li a0, 16475; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma476; CHECK-NEXT: vand.vx v8, v8, a0477; CHECK-NEXT: ret478 %vc = and <vscale x 2 x i16> %va, splat (i16 16)479 ret <vscale x 2 x i16> %vc480}481 482define <vscale x 4 x i16> @vand_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) {483; CHECK-LABEL: vand_vv_nxv4i16:484; CHECK: # %bb.0:485; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma486; CHECK-NEXT: vand.vv v8, v8, v9487; CHECK-NEXT: ret488 %vc = and <vscale x 4 x i16> %va, %vb489 ret <vscale x 4 x i16> %vc490}491 492define <vscale x 4 x i16> @vand_vx_nxv4i16(<vscale x 4 x i16> %va, i16 signext %b) {493; CHECK-LABEL: vand_vx_nxv4i16:494; CHECK: # %bb.0:495; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma496; CHECK-NEXT: vand.vx v8, v8, a0497; CHECK-NEXT: ret498 %head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0499 %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer500 %vc = and <vscale x 4 x i16> %va, %splat501 ret <vscale x 4 x i16> %vc502}503 504define <vscale x 4 x i16> @vand_vi_nxv4i16_0(<vscale x 4 x i16> %va) {505; CHECK-LABEL: vand_vi_nxv4i16_0:506; CHECK: # %bb.0:507; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma508; CHECK-NEXT: vand.vi v8, v8, -10509; CHECK-NEXT: ret510 %vc = and <vscale x 4 x i16> %va, splat (i16 -10)511 ret <vscale x 4 x i16> %vc512}513 514define <vscale x 4 x i16> @vand_vi_nxv4i16_1(<vscale x 4 x i16> %va) {515; CHECK-LABEL: vand_vi_nxv4i16_1:516; CHECK: # %bb.0:517; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma518; CHECK-NEXT: vand.vi v8, v8, 8519; CHECK-NEXT: ret520 %vc = and <vscale x 4 x i16> %va, splat (i16 8)521 ret <vscale x 4 x i16> %vc522}523 524define <vscale x 4 x i16> @vand_vi_nxv4i16_2(<vscale x 4 x i16> %va) {525; CHECK-LABEL: vand_vi_nxv4i16_2:526; CHECK: # %bb.0:527; CHECK-NEXT: li a0, 16528; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma529; CHECK-NEXT: vand.vx v8, v8, a0530; CHECK-NEXT: ret531 %vc = and <vscale x 4 x i16> %va, splat (i16 16)532 ret <vscale x 4 x i16> %vc533}534 535define <vscale x 8 x i16> @vand_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {536; CHECK-LABEL: vand_vv_nxv8i16:537; CHECK: # %bb.0:538; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma539; CHECK-NEXT: vand.vv v8, v8, v10540; CHECK-NEXT: ret541 %vc = and <vscale x 8 x i16> %va, %vb542 ret <vscale x 8 x i16> %vc543}544 545define <vscale x 8 x i16> @vand_vx_nxv8i16(<vscale x 8 x i16> %va, i16 signext %b) {546; CHECK-LABEL: vand_vx_nxv8i16:547; CHECK: # %bb.0:548; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma549; CHECK-NEXT: vand.vx v8, v8, a0550; CHECK-NEXT: ret551 %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0552 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer553 %vc = and <vscale x 8 x i16> %va, %splat554 ret <vscale x 8 x i16> %vc555}556 557define <vscale x 8 x i16> @vand_vi_nxv8i16_0(<vscale x 8 x i16> %va) {558; CHECK-LABEL: vand_vi_nxv8i16_0:559; CHECK: # %bb.0:560; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma561; CHECK-NEXT: vand.vi v8, v8, -10562; CHECK-NEXT: ret563 %vc = and <vscale x 8 x i16> %va, splat (i16 -10)564 ret <vscale x 8 x i16> %vc565}566 567define <vscale x 8 x i16> @vand_vi_nxv8i16_1(<vscale x 8 x i16> %va) {568; CHECK-LABEL: vand_vi_nxv8i16_1:569; CHECK: # %bb.0:570; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma571; CHECK-NEXT: vand.vi v8, v8, 8572; CHECK-NEXT: ret573 %vc = and <vscale x 8 x i16> %va, splat (i16 8)574 ret <vscale x 8 x i16> %vc575}576 577define <vscale x 8 x i16> @vand_vi_nxv8i16_2(<vscale x 8 x i16> %va) {578; CHECK-LABEL: vand_vi_nxv8i16_2:579; CHECK: # %bb.0:580; CHECK-NEXT: li a0, 16581; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma582; CHECK-NEXT: vand.vx v8, v8, a0583; CHECK-NEXT: ret584 %vc = and <vscale x 8 x i16> %va, splat (i16 16)585 ret <vscale x 8 x i16> %vc586}587 588define <vscale x 16 x i16> @vand_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb) {589; CHECK-LABEL: vand_vv_nxv16i16:590; CHECK: # %bb.0:591; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma592; CHECK-NEXT: vand.vv v8, v8, v12593; CHECK-NEXT: ret594 %vc = and <vscale x 16 x i16> %va, %vb595 ret <vscale x 16 x i16> %vc596}597 598define <vscale x 16 x i16> @vand_vx_nxv16i16(<vscale x 16 x i16> %va, i16 signext %b) {599; CHECK-LABEL: vand_vx_nxv16i16:600; CHECK: # %bb.0:601; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma602; CHECK-NEXT: vand.vx v8, v8, a0603; CHECK-NEXT: ret604 %head = insertelement <vscale x 16 x i16> poison, i16 %b, i32 0605 %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer606 %vc = and <vscale x 16 x i16> %va, %splat607 ret <vscale x 16 x i16> %vc608}609 610define <vscale x 16 x i16> @vand_vi_nxv16i16_0(<vscale x 16 x i16> %va) {611; CHECK-LABEL: vand_vi_nxv16i16_0:612; CHECK: # %bb.0:613; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma614; CHECK-NEXT: vand.vi v8, v8, -10615; CHECK-NEXT: ret616 %vc = and <vscale x 16 x i16> %va, splat (i16 -10)617 ret <vscale x 16 x i16> %vc618}619 620define <vscale x 16 x i16> @vand_vi_nxv16i16_1(<vscale x 16 x i16> %va) {621; CHECK-LABEL: vand_vi_nxv16i16_1:622; CHECK: # %bb.0:623; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma624; CHECK-NEXT: vand.vi v8, v8, 8625; CHECK-NEXT: ret626 %vc = and <vscale x 16 x i16> %va, splat (i16 8)627 ret <vscale x 16 x i16> %vc628}629 630define <vscale x 16 x i16> @vand_vi_nxv16i16_2(<vscale x 16 x i16> %va) {631; CHECK-LABEL: vand_vi_nxv16i16_2:632; CHECK: # %bb.0:633; CHECK-NEXT: li a0, 16634; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma635; CHECK-NEXT: vand.vx v8, v8, a0636; CHECK-NEXT: ret637 %vc = and <vscale x 16 x i16> %va, splat (i16 16)638 ret <vscale x 16 x i16> %vc639}640 641define <vscale x 32 x i16> @vand_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb) {642; CHECK-LABEL: vand_vv_nxv32i16:643; CHECK: # %bb.0:644; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma645; CHECK-NEXT: vand.vv v8, v8, v16646; CHECK-NEXT: ret647 %vc = and <vscale x 32 x i16> %va, %vb648 ret <vscale x 32 x i16> %vc649}650 651define <vscale x 32 x i16> @vand_vx_nxv32i16(<vscale x 32 x i16> %va, i16 signext %b) {652; CHECK-LABEL: vand_vx_nxv32i16:653; CHECK: # %bb.0:654; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma655; CHECK-NEXT: vand.vx v8, v8, a0656; CHECK-NEXT: ret657 %head = insertelement <vscale x 32 x i16> poison, i16 %b, i32 0658 %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer659 %vc = and <vscale x 32 x i16> %va, %splat660 ret <vscale x 32 x i16> %vc661}662 663define <vscale x 32 x i16> @vand_vi_nxv32i16_0(<vscale x 32 x i16> %va) {664; CHECK-LABEL: vand_vi_nxv32i16_0:665; CHECK: # %bb.0:666; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma667; CHECK-NEXT: vand.vi v8, v8, -10668; CHECK-NEXT: ret669 %vc = and <vscale x 32 x i16> %va, splat (i16 -10)670 ret <vscale x 32 x i16> %vc671}672 673define <vscale x 32 x i16> @vand_vi_nxv32i16_1(<vscale x 32 x i16> %va) {674; CHECK-LABEL: vand_vi_nxv32i16_1:675; CHECK: # %bb.0:676; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma677; CHECK-NEXT: vand.vi v8, v8, 8678; CHECK-NEXT: ret679 %vc = and <vscale x 32 x i16> %va, splat (i16 8)680 ret <vscale x 32 x i16> %vc681}682 683define <vscale x 32 x i16> @vand_vi_nxv32i16_2(<vscale x 32 x i16> %va) {684; CHECK-LABEL: vand_vi_nxv32i16_2:685; CHECK: # %bb.0:686; CHECK-NEXT: li a0, 16687; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma688; CHECK-NEXT: vand.vx v8, v8, a0689; CHECK-NEXT: ret690 %vc = and <vscale x 32 x i16> %va, splat (i16 16)691 ret <vscale x 32 x i16> %vc692}693 694define <vscale x 1 x i32> @vand_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {695; CHECK-LABEL: vand_vv_nxv1i32:696; CHECK: # %bb.0:697; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma698; CHECK-NEXT: vand.vv v8, v8, v9699; CHECK-NEXT: ret700 %vc = and <vscale x 1 x i32> %va, %vb701 ret <vscale x 1 x i32> %vc702}703 704define <vscale x 1 x i32> @vand_vx_nxv1i32(<vscale x 1 x i32> %va, i32 signext %b) {705; CHECK-LABEL: vand_vx_nxv1i32:706; CHECK: # %bb.0:707; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma708; CHECK-NEXT: vand.vx v8, v8, a0709; CHECK-NEXT: ret710 %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0711 %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer712 %vc = and <vscale x 1 x i32> %va, %splat713 ret <vscale x 1 x i32> %vc714}715 716define <vscale x 1 x i32> @vand_vi_nxv1i32_0(<vscale x 1 x i32> %va) {717; CHECK-LABEL: vand_vi_nxv1i32_0:718; CHECK: # %bb.0:719; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma720; CHECK-NEXT: vand.vi v8, v8, -10721; CHECK-NEXT: ret722 %vc = and <vscale x 1 x i32> %va, splat (i32 -10)723 ret <vscale x 1 x i32> %vc724}725 726define <vscale x 1 x i32> @vand_vi_nxv1i32_1(<vscale x 1 x i32> %va) {727; CHECK-LABEL: vand_vi_nxv1i32_1:728; CHECK: # %bb.0:729; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma730; CHECK-NEXT: vand.vi v8, v8, 8731; CHECK-NEXT: ret732 %vc = and <vscale x 1 x i32> %va, splat (i32 8)733 ret <vscale x 1 x i32> %vc734}735 736define <vscale x 1 x i32> @vand_vi_nxv1i32_2(<vscale x 1 x i32> %va) {737; CHECK-LABEL: vand_vi_nxv1i32_2:738; CHECK: # %bb.0:739; CHECK-NEXT: li a0, 16740; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma741; CHECK-NEXT: vand.vx v8, v8, a0742; CHECK-NEXT: ret743 %vc = and <vscale x 1 x i32> %va, splat (i32 16)744 ret <vscale x 1 x i32> %vc745}746 747define <vscale x 2 x i32> @vand_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {748; CHECK-LABEL: vand_vv_nxv2i32:749; CHECK: # %bb.0:750; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma751; CHECK-NEXT: vand.vv v8, v8, v9752; CHECK-NEXT: ret753 %vc = and <vscale x 2 x i32> %va, %vb754 ret <vscale x 2 x i32> %vc755}756 757define <vscale x 2 x i32> @vand_vx_nxv2i32(<vscale x 2 x i32> %va, i32 signext %b) {758; CHECK-LABEL: vand_vx_nxv2i32:759; CHECK: # %bb.0:760; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma761; CHECK-NEXT: vand.vx v8, v8, a0762; CHECK-NEXT: ret763 %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0764 %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer765 %vc = and <vscale x 2 x i32> %va, %splat766 ret <vscale x 2 x i32> %vc767}768 769define <vscale x 2 x i32> @vand_vi_nxv2i32_0(<vscale x 2 x i32> %va) {770; CHECK-LABEL: vand_vi_nxv2i32_0:771; CHECK: # %bb.0:772; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma773; CHECK-NEXT: vand.vi v8, v8, -10774; CHECK-NEXT: ret775 %vc = and <vscale x 2 x i32> %va, splat (i32 -10)776 ret <vscale x 2 x i32> %vc777}778 779define <vscale x 2 x i32> @vand_vi_nxv2i32_1(<vscale x 2 x i32> %va) {780; CHECK-LABEL: vand_vi_nxv2i32_1:781; CHECK: # %bb.0:782; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma783; CHECK-NEXT: vand.vi v8, v8, 8784; CHECK-NEXT: ret785 %vc = and <vscale x 2 x i32> %va, splat (i32 8)786 ret <vscale x 2 x i32> %vc787}788 789define <vscale x 2 x i32> @vand_vi_nxv2i32_2(<vscale x 2 x i32> %va) {790; CHECK-LABEL: vand_vi_nxv2i32_2:791; CHECK: # %bb.0:792; CHECK-NEXT: li a0, 16793; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma794; CHECK-NEXT: vand.vx v8, v8, a0795; CHECK-NEXT: ret796 %vc = and <vscale x 2 x i32> %va, splat (i32 16)797 ret <vscale x 2 x i32> %vc798}799 800define <vscale x 4 x i32> @vand_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {801; CHECK-LABEL: vand_vv_nxv4i32:802; CHECK: # %bb.0:803; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma804; CHECK-NEXT: vand.vv v8, v8, v10805; CHECK-NEXT: ret806 %vc = and <vscale x 4 x i32> %va, %vb807 ret <vscale x 4 x i32> %vc808}809 810define <vscale x 4 x i32> @vand_vx_nxv4i32(<vscale x 4 x i32> %va, i32 signext %b) {811; CHECK-LABEL: vand_vx_nxv4i32:812; CHECK: # %bb.0:813; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma814; CHECK-NEXT: vand.vx v8, v8, a0815; CHECK-NEXT: ret816 %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0817 %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer818 %vc = and <vscale x 4 x i32> %va, %splat819 ret <vscale x 4 x i32> %vc820}821 822define <vscale x 4 x i32> @vand_vi_nxv4i32_0(<vscale x 4 x i32> %va) {823; CHECK-LABEL: vand_vi_nxv4i32_0:824; CHECK: # %bb.0:825; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma826; CHECK-NEXT: vand.vi v8, v8, -10827; CHECK-NEXT: ret828 %vc = and <vscale x 4 x i32> %va, splat (i32 -10)829 ret <vscale x 4 x i32> %vc830}831 832define <vscale x 4 x i32> @vand_vi_nxv4i32_1(<vscale x 4 x i32> %va) {833; CHECK-LABEL: vand_vi_nxv4i32_1:834; CHECK: # %bb.0:835; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma836; CHECK-NEXT: vand.vi v8, v8, 8837; CHECK-NEXT: ret838 %vc = and <vscale x 4 x i32> %va, splat (i32 8)839 ret <vscale x 4 x i32> %vc840}841 842define <vscale x 4 x i32> @vand_vi_nxv4i32_2(<vscale x 4 x i32> %va) {843; CHECK-LABEL: vand_vi_nxv4i32_2:844; CHECK: # %bb.0:845; CHECK-NEXT: li a0, 16846; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma847; CHECK-NEXT: vand.vx v8, v8, a0848; CHECK-NEXT: ret849 %vc = and <vscale x 4 x i32> %va, splat (i32 16)850 ret <vscale x 4 x i32> %vc851}852 853define <vscale x 8 x i32> @vand_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {854; CHECK-LABEL: vand_vv_nxv8i32:855; CHECK: # %bb.0:856; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma857; CHECK-NEXT: vand.vv v8, v8, v12858; CHECK-NEXT: ret859 %vc = and <vscale x 8 x i32> %va, %vb860 ret <vscale x 8 x i32> %vc861}862 863define <vscale x 8 x i32> @vand_vx_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b) {864; CHECK-LABEL: vand_vx_nxv8i32:865; CHECK: # %bb.0:866; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma867; CHECK-NEXT: vand.vx v8, v8, a0868; CHECK-NEXT: ret869 %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0870 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer871 %vc = and <vscale x 8 x i32> %va, %splat872 ret <vscale x 8 x i32> %vc873}874 875define <vscale x 8 x i32> @vand_vi_nxv8i32_0(<vscale x 8 x i32> %va) {876; CHECK-LABEL: vand_vi_nxv8i32_0:877; CHECK: # %bb.0:878; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma879; CHECK-NEXT: vand.vi v8, v8, -10880; CHECK-NEXT: ret881 %vc = and <vscale x 8 x i32> %va, splat (i32 -10)882 ret <vscale x 8 x i32> %vc883}884 885define <vscale x 8 x i32> @vand_vi_nxv8i32_1(<vscale x 8 x i32> %va) {886; CHECK-LABEL: vand_vi_nxv8i32_1:887; CHECK: # %bb.0:888; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma889; CHECK-NEXT: vand.vi v8, v8, 8890; CHECK-NEXT: ret891 %vc = and <vscale x 8 x i32> %va, splat (i32 8)892 ret <vscale x 8 x i32> %vc893}894 895define <vscale x 8 x i32> @vand_vi_nxv8i32_2(<vscale x 8 x i32> %va) {896; CHECK-LABEL: vand_vi_nxv8i32_2:897; CHECK: # %bb.0:898; CHECK-NEXT: li a0, 16899; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma900; CHECK-NEXT: vand.vx v8, v8, a0901; CHECK-NEXT: ret902 %vc = and <vscale x 8 x i32> %va, splat (i32 16)903 ret <vscale x 8 x i32> %vc904}905 906define <vscale x 16 x i32> @vand_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb) {907; CHECK-LABEL: vand_vv_nxv16i32:908; CHECK: # %bb.0:909; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma910; CHECK-NEXT: vand.vv v8, v8, v16911; CHECK-NEXT: ret912 %vc = and <vscale x 16 x i32> %va, %vb913 ret <vscale x 16 x i32> %vc914}915 916define <vscale x 16 x i32> @vand_vx_nxv16i32(<vscale x 16 x i32> %va, i32 signext %b) {917; CHECK-LABEL: vand_vx_nxv16i32:918; CHECK: # %bb.0:919; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma920; CHECK-NEXT: vand.vx v8, v8, a0921; CHECK-NEXT: ret922 %head = insertelement <vscale x 16 x i32> poison, i32 %b, i32 0923 %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer924 %vc = and <vscale x 16 x i32> %va, %splat925 ret <vscale x 16 x i32> %vc926}927 928define <vscale x 16 x i32> @vand_vi_nxv16i32_0(<vscale x 16 x i32> %va) {929; CHECK-LABEL: vand_vi_nxv16i32_0:930; CHECK: # %bb.0:931; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma932; CHECK-NEXT: vand.vi v8, v8, -10933; CHECK-NEXT: ret934 %vc = and <vscale x 16 x i32> %va, splat (i32 -10)935 ret <vscale x 16 x i32> %vc936}937 938define <vscale x 16 x i32> @vand_vi_nxv16i32_1(<vscale x 16 x i32> %va) {939; CHECK-LABEL: vand_vi_nxv16i32_1:940; CHECK: # %bb.0:941; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma942; CHECK-NEXT: vand.vi v8, v8, 8943; CHECK-NEXT: ret944 %vc = and <vscale x 16 x i32> %va, splat (i32 8)945 ret <vscale x 16 x i32> %vc946}947 948define <vscale x 16 x i32> @vand_vi_nxv16i32_2(<vscale x 16 x i32> %va) {949; CHECK-LABEL: vand_vi_nxv16i32_2:950; CHECK: # %bb.0:951; CHECK-NEXT: li a0, 16952; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma953; CHECK-NEXT: vand.vx v8, v8, a0954; CHECK-NEXT: ret955 %vc = and <vscale x 16 x i32> %va, splat (i32 16)956 ret <vscale x 16 x i32> %vc957}958 959define <vscale x 1 x i64> @vand_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb) {960; CHECK-LABEL: vand_vv_nxv1i64:961; CHECK: # %bb.0:962; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma963; CHECK-NEXT: vand.vv v8, v8, v9964; CHECK-NEXT: ret965 %vc = and <vscale x 1 x i64> %va, %vb966 ret <vscale x 1 x i64> %vc967}968 969define <vscale x 1 x i64> @vand_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {970; RV32-LABEL: vand_vx_nxv1i64:971; RV32: # %bb.0:972; RV32-NEXT: addi sp, sp, -16973; RV32-NEXT: .cfi_def_cfa_offset 16974; RV32-NEXT: sw a0, 8(sp)975; RV32-NEXT: sw a1, 12(sp)976; RV32-NEXT: addi a0, sp, 8977; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma978; RV32-NEXT: vlse64.v v9, (a0), zero979; RV32-NEXT: vand.vv v8, v8, v9980; RV32-NEXT: addi sp, sp, 16981; RV32-NEXT: .cfi_def_cfa_offset 0982; RV32-NEXT: ret983;984; RV64-LABEL: vand_vx_nxv1i64:985; RV64: # %bb.0:986; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, ma987; RV64-NEXT: vand.vx v8, v8, a0988; RV64-NEXT: ret989 %head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0990 %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer991 %vc = and <vscale x 1 x i64> %va, %splat992 ret <vscale x 1 x i64> %vc993}994 995define <vscale x 1 x i64> @vand_vi_nxv1i64_0(<vscale x 1 x i64> %va) {996; CHECK-LABEL: vand_vi_nxv1i64_0:997; CHECK: # %bb.0:998; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma999; CHECK-NEXT: vand.vi v8, v8, -101000; CHECK-NEXT: ret1001 %vc = and <vscale x 1 x i64> %va, splat (i64 -10)1002 ret <vscale x 1 x i64> %vc1003}1004 1005define <vscale x 1 x i64> @vand_vi_nxv1i64_1(<vscale x 1 x i64> %va) {1006; CHECK-LABEL: vand_vi_nxv1i64_1:1007; CHECK: # %bb.0:1008; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma1009; CHECK-NEXT: vand.vi v8, v8, 81010; CHECK-NEXT: ret1011 %vc = and <vscale x 1 x i64> %va, splat (i64 8)1012 ret <vscale x 1 x i64> %vc1013}1014 1015define <vscale x 1 x i64> @vand_vi_nxv1i64_2(<vscale x 1 x i64> %va) {1016; CHECK-LABEL: vand_vi_nxv1i64_2:1017; CHECK: # %bb.0:1018; CHECK-NEXT: li a0, 161019; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma1020; CHECK-NEXT: vand.vx v8, v8, a01021; CHECK-NEXT: ret1022 %vc = and <vscale x 1 x i64> %va, splat (i64 16)1023 ret <vscale x 1 x i64> %vc1024}1025 1026define <vscale x 2 x i64> @vand_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) {1027; CHECK-LABEL: vand_vv_nxv2i64:1028; CHECK: # %bb.0:1029; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma1030; CHECK-NEXT: vand.vv v8, v8, v101031; CHECK-NEXT: ret1032 %vc = and <vscale x 2 x i64> %va, %vb1033 ret <vscale x 2 x i64> %vc1034}1035 1036define <vscale x 2 x i64> @vand_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {1037; RV32-LABEL: vand_vx_nxv2i64:1038; RV32: # %bb.0:1039; RV32-NEXT: addi sp, sp, -161040; RV32-NEXT: .cfi_def_cfa_offset 161041; RV32-NEXT: sw a0, 8(sp)1042; RV32-NEXT: sw a1, 12(sp)1043; RV32-NEXT: addi a0, sp, 81044; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma1045; RV32-NEXT: vlse64.v v10, (a0), zero1046; RV32-NEXT: vand.vv v8, v8, v101047; RV32-NEXT: addi sp, sp, 161048; RV32-NEXT: .cfi_def_cfa_offset 01049; RV32-NEXT: ret1050;1051; RV64-LABEL: vand_vx_nxv2i64:1052; RV64: # %bb.0:1053; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, ma1054; RV64-NEXT: vand.vx v8, v8, a01055; RV64-NEXT: ret1056 %head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 01057 %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer1058 %vc = and <vscale x 2 x i64> %va, %splat1059 ret <vscale x 2 x i64> %vc1060}1061 1062define <vscale x 2 x i64> @vand_vi_nxv2i64_0(<vscale x 2 x i64> %va) {1063; CHECK-LABEL: vand_vi_nxv2i64_0:1064; CHECK: # %bb.0:1065; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma1066; CHECK-NEXT: vand.vi v8, v8, -101067; CHECK-NEXT: ret1068 %vc = and <vscale x 2 x i64> %va, splat (i64 -10)1069 ret <vscale x 2 x i64> %vc1070}1071 1072define <vscale x 2 x i64> @vand_vi_nxv2i64_1(<vscale x 2 x i64> %va) {1073; CHECK-LABEL: vand_vi_nxv2i64_1:1074; CHECK: # %bb.0:1075; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma1076; CHECK-NEXT: vand.vi v8, v8, 81077; CHECK-NEXT: ret1078 %vc = and <vscale x 2 x i64> %va, splat (i64 8)1079 ret <vscale x 2 x i64> %vc1080}1081 1082define <vscale x 2 x i64> @vand_vi_nxv2i64_2(<vscale x 2 x i64> %va) {1083; CHECK-LABEL: vand_vi_nxv2i64_2:1084; CHECK: # %bb.0:1085; CHECK-NEXT: li a0, 161086; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma1087; CHECK-NEXT: vand.vx v8, v8, a01088; CHECK-NEXT: ret1089 %vc = and <vscale x 2 x i64> %va, splat (i64 16)1090 ret <vscale x 2 x i64> %vc1091}1092 1093define <vscale x 4 x i64> @vand_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) {1094; CHECK-LABEL: vand_vv_nxv4i64:1095; CHECK: # %bb.0:1096; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma1097; CHECK-NEXT: vand.vv v8, v8, v121098; CHECK-NEXT: ret1099 %vc = and <vscale x 4 x i64> %va, %vb1100 ret <vscale x 4 x i64> %vc1101}1102 1103define <vscale x 4 x i64> @vand_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {1104; RV32-LABEL: vand_vx_nxv4i64:1105; RV32: # %bb.0:1106; RV32-NEXT: addi sp, sp, -161107; RV32-NEXT: .cfi_def_cfa_offset 161108; RV32-NEXT: sw a0, 8(sp)1109; RV32-NEXT: sw a1, 12(sp)1110; RV32-NEXT: addi a0, sp, 81111; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma1112; RV32-NEXT: vlse64.v v12, (a0), zero1113; RV32-NEXT: vand.vv v8, v8, v121114; RV32-NEXT: addi sp, sp, 161115; RV32-NEXT: .cfi_def_cfa_offset 01116; RV32-NEXT: ret1117;1118; RV64-LABEL: vand_vx_nxv4i64:1119; RV64: # %bb.0:1120; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, ma1121; RV64-NEXT: vand.vx v8, v8, a01122; RV64-NEXT: ret1123 %head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 01124 %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer1125 %vc = and <vscale x 4 x i64> %va, %splat1126 ret <vscale x 4 x i64> %vc1127}1128 1129define <vscale x 4 x i64> @vand_vi_nxv4i64_0(<vscale x 4 x i64> %va) {1130; CHECK-LABEL: vand_vi_nxv4i64_0:1131; CHECK: # %bb.0:1132; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma1133; CHECK-NEXT: vand.vi v8, v8, -101134; CHECK-NEXT: ret1135 %vc = and <vscale x 4 x i64> %va, splat (i64 -10)1136 ret <vscale x 4 x i64> %vc1137}1138 1139define <vscale x 4 x i64> @vand_vi_nxv4i64_1(<vscale x 4 x i64> %va) {1140; CHECK-LABEL: vand_vi_nxv4i64_1:1141; CHECK: # %bb.0:1142; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma1143; CHECK-NEXT: vand.vi v8, v8, 81144; CHECK-NEXT: ret1145 %vc = and <vscale x 4 x i64> %va, splat (i64 8)1146 ret <vscale x 4 x i64> %vc1147}1148 1149define <vscale x 4 x i64> @vand_vi_nxv4i64_2(<vscale x 4 x i64> %va) {1150; CHECK-LABEL: vand_vi_nxv4i64_2:1151; CHECK: # %bb.0:1152; CHECK-NEXT: li a0, 161153; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, ma1154; CHECK-NEXT: vand.vx v8, v8, a01155; CHECK-NEXT: ret1156 %vc = and <vscale x 4 x i64> %va, splat (i64 16)1157 ret <vscale x 4 x i64> %vc1158}1159 1160define <vscale x 8 x i64> @vand_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {1161; CHECK-LABEL: vand_vv_nxv8i64:1162; CHECK: # %bb.0:1163; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma1164; CHECK-NEXT: vand.vv v8, v8, v161165; CHECK-NEXT: ret1166 %vc = and <vscale x 8 x i64> %va, %vb1167 ret <vscale x 8 x i64> %vc1168}1169 1170define <vscale x 8 x i64> @vand_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {1171; RV32-LABEL: vand_vx_nxv8i64:1172; RV32: # %bb.0:1173; RV32-NEXT: addi sp, sp, -161174; RV32-NEXT: .cfi_def_cfa_offset 161175; RV32-NEXT: sw a0, 8(sp)1176; RV32-NEXT: sw a1, 12(sp)1177; RV32-NEXT: addi a0, sp, 81178; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma1179; RV32-NEXT: vlse64.v v16, (a0), zero1180; RV32-NEXT: vand.vv v8, v8, v161181; RV32-NEXT: addi sp, sp, 161182; RV32-NEXT: .cfi_def_cfa_offset 01183; RV32-NEXT: ret1184;1185; RV64-LABEL: vand_vx_nxv8i64:1186; RV64: # %bb.0:1187; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma1188; RV64-NEXT: vand.vx v8, v8, a01189; RV64-NEXT: ret1190 %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 01191 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer1192 %vc = and <vscale x 8 x i64> %va, %splat1193 ret <vscale x 8 x i64> %vc1194}1195 1196define <vscale x 8 x i64> @vand_vi_nxv8i64_0(<vscale x 8 x i64> %va) {1197; CHECK-LABEL: vand_vi_nxv8i64_0:1198; CHECK: # %bb.0:1199; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma1200; CHECK-NEXT: vand.vi v8, v8, -101201; CHECK-NEXT: ret1202 %vc = and <vscale x 8 x i64> %va, splat (i64 -10)1203 ret <vscale x 8 x i64> %vc1204}1205 1206define <vscale x 8 x i64> @vand_vi_nxv8i64_1(<vscale x 8 x i64> %va) {1207; CHECK-LABEL: vand_vi_nxv8i64_1:1208; CHECK: # %bb.0:1209; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma1210; CHECK-NEXT: vand.vi v8, v8, 81211; CHECK-NEXT: ret1212 %vc = and <vscale x 8 x i64> %va, splat (i64 8)1213 ret <vscale x 8 x i64> %vc1214}1215 1216define <vscale x 8 x i64> @vand_vi_nxv8i64_2(<vscale x 8 x i64> %va) {1217; CHECK-LABEL: vand_vi_nxv8i64_2:1218; CHECK: # %bb.0:1219; CHECK-NEXT: li a0, 161220; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma1221; CHECK-NEXT: vand.vx v8, v8, a01222; CHECK-NEXT: ret1223 %vc = and <vscale x 8 x i64> %va, splat (i64 16)1224 ret <vscale x 8 x i64> %vc1225}1226 1227define <vscale x 8 x i64> @vand_xx_nxv8i64(i64 %a, i64 %b) nounwind {1228; RV32-LABEL: vand_xx_nxv8i64:1229; RV32: # %bb.0:1230; RV32-NEXT: addi sp, sp, -161231; RV32-NEXT: and a1, a1, a31232; RV32-NEXT: and a0, a0, a21233; RV32-NEXT: sw a0, 8(sp)1234; RV32-NEXT: sw a1, 12(sp)1235; RV32-NEXT: addi a0, sp, 81236; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma1237; RV32-NEXT: vlse64.v v8, (a0), zero1238; RV32-NEXT: addi sp, sp, 161239; RV32-NEXT: ret1240;1241; RV64-LABEL: vand_xx_nxv8i64:1242; RV64: # %bb.0:1243; RV64-NEXT: and a0, a0, a11244; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma1245; RV64-NEXT: vmv.v.x v8, a01246; RV64-NEXT: ret1247 %head1 = insertelement <vscale x 8 x i64> poison, i64 %a, i32 01248 %splat1 = shufflevector <vscale x 8 x i64> %head1, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer1249 %head2 = insertelement <vscale x 8 x i64> poison, i64 %b, i32 01250 %splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer1251 %v = and <vscale x 8 x i64> %splat1, %splat21252 ret <vscale x 8 x i64> %v1253}1254 1255define <vscale x 8 x i32> @vand_vv_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {1256; CHECK-LABEL: vand_vv_mask_nxv8i32:1257; CHECK: # %bb.0:1258; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu1259; CHECK-NEXT: vand.vv v8, v8, v12, v0.t1260; CHECK-NEXT: ret1261 %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> splat (i32 -1)1262 %vc = and <vscale x 8 x i32> %va, %vs1263 ret <vscale x 8 x i32> %vc1264}1265 1266define <vscale x 8 x i32> @vand_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {1267; CHECK-LABEL: vand_vx_mask_nxv8i32:1268; CHECK: # %bb.0:1269; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu1270; CHECK-NEXT: vand.vx v8, v8, a0, v0.t1271; CHECK-NEXT: ret1272 %head2 = insertelement <vscale x 8 x i32> poison, i32 %b, i32 01273 %splat = shufflevector <vscale x 8 x i32> %head2, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer1274 %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> splat (i32 -1)1275 %vc = and <vscale x 8 x i32> %va, %vs1276 ret <vscale x 8 x i32> %vc1277}1278 1279define <vscale x 8 x i32> @vand_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {1280; CHECK-LABEL: vand_vi_mask_nxv8i32:1281; CHECK: # %bb.0:1282; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu1283; CHECK-NEXT: vand.vi v8, v8, 7, v0.t1284; CHECK-NEXT: ret1285 %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> splat (i32 7), <vscale x 8 x i32> splat (i32 -1)1286 %vc = and <vscale x 8 x i32> %va, %vs1287 ret <vscale x 8 x i32> %vc1288}1289