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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 32; RUN: llc -mtriple=riscv32 -mattr=+v,+m -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV323; RUN: llc -mtriple=riscv64 -mattr=+v,+m -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV644; RUN: llc -mtriple=riscv32 -mattr=+v,+m,+zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB,CHECK-ZVKB-NOZBB,CHECK-ZVKB32,CHECK-ZVKB-NOZBB325; RUN: llc -mtriple=riscv64 -mattr=+v,+m,+zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB,CHECK-ZVKB-NOZBB,CHECK-ZVKB64,CHECK-ZVKB-NOZBB646; RUN: llc -mtriple=riscv32 -mattr=+v,+m,+zvkb,+zbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB,CHECK-ZVKB-ZBB,CHECK-ZVKB32,CHECK-ZVKB-ZBB327; RUN: llc -mtriple=riscv64 -mattr=+v,+m,+zvkb,+zbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB,CHECK-ZVKB-ZBB,CHECK-ZVKB64,CHECK-ZVKB-ZBB648 9define <vscale x 1 x i8> @vandn_vv_nxv1i8(<vscale x 1 x i8> %x, <vscale x 1 x i8> %y) {10; CHECK-LABEL: vandn_vv_nxv1i8:11; CHECK: # %bb.0:12; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma13; CHECK-NEXT: vnot.v v8, v814; CHECK-NEXT: vand.vv v8, v8, v915; CHECK-NEXT: ret16;17; CHECK-ZVKB-LABEL: vandn_vv_nxv1i8:18; CHECK-ZVKB: # %bb.0:19; CHECK-ZVKB-NEXT: vsetvli a0, zero, e8, mf8, ta, ma20; CHECK-ZVKB-NEXT: vandn.vv v8, v9, v821; CHECK-ZVKB-NEXT: ret22 %a = xor <vscale x 1 x i8> %x, splat (i8 -1)23 %b = and <vscale x 1 x i8> %a, %y24 ret <vscale x 1 x i8> %b25}26 27define <vscale x 1 x i8> @vandn_vv_swapped_nxv1i8(<vscale x 1 x i8> %x, <vscale x 1 x i8> %y) {28; CHECK-LABEL: vandn_vv_swapped_nxv1i8:29; CHECK: # %bb.0:30; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma31; CHECK-NEXT: vnot.v v8, v832; CHECK-NEXT: vand.vv v8, v9, v833; CHECK-NEXT: ret34;35; CHECK-ZVKB-LABEL: vandn_vv_swapped_nxv1i8:36; CHECK-ZVKB: # %bb.0:37; CHECK-ZVKB-NEXT: vsetvli a0, zero, e8, mf8, ta, ma38; CHECK-ZVKB-NEXT: vandn.vv v8, v9, v839; CHECK-ZVKB-NEXT: ret40 %a = xor <vscale x 1 x i8> %x, splat (i8 -1)41 %b = and <vscale x 1 x i8> %y, %a42 ret <vscale x 1 x i8> %b43}44 45define <vscale x 1 x i8> @vandn_vx_nxv1i8(i8 %x, <vscale x 1 x i8> %y) {46; CHECK-LABEL: vandn_vx_nxv1i8:47; CHECK: # %bb.0:48; CHECK-NEXT: not a0, a049; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma50; CHECK-NEXT: vand.vx v8, v8, a051; CHECK-NEXT: ret52;53; CHECK-ZVKB-LABEL: vandn_vx_nxv1i8:54; CHECK-ZVKB: # %bb.0:55; CHECK-ZVKB-NEXT: vsetvli a1, zero, e8, mf8, ta, ma56; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a057; CHECK-ZVKB-NEXT: ret58 %a = xor i8 %x, -159 %head = insertelement <vscale x 1 x i8> poison, i8 %a, i32 060 %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer61 %b = and <vscale x 1 x i8> %splat, %y62 ret <vscale x 1 x i8> %b63}64 65define <vscale x 1 x i8> @vandn_vx_swapped_nxv1i8(i8 %x, <vscale x 1 x i8> %y) {66; CHECK-LABEL: vandn_vx_swapped_nxv1i8:67; CHECK: # %bb.0:68; CHECK-NEXT: not a0, a069; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma70; CHECK-NEXT: vand.vx v8, v8, a071; CHECK-NEXT: ret72;73; CHECK-ZVKB-LABEL: vandn_vx_swapped_nxv1i8:74; CHECK-ZVKB: # %bb.0:75; CHECK-ZVKB-NEXT: vsetvli a1, zero, e8, mf8, ta, ma76; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a077; CHECK-ZVKB-NEXT: ret78 %a = xor i8 %x, -179 %head = insertelement <vscale x 1 x i8> poison, i8 %a, i32 080 %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer81 %b = and <vscale x 1 x i8> %splat, %y82 ret <vscale x 1 x i8> %b83}84 85define <vscale x 2 x i8> @vandn_vv_nxv2i8(<vscale x 2 x i8> %x, <vscale x 2 x i8> %y) {86; CHECK-LABEL: vandn_vv_nxv2i8:87; CHECK: # %bb.0:88; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma89; CHECK-NEXT: vnot.v v8, v890; CHECK-NEXT: vand.vv v8, v8, v991; CHECK-NEXT: ret92;93; CHECK-ZVKB-LABEL: vandn_vv_nxv2i8:94; CHECK-ZVKB: # %bb.0:95; CHECK-ZVKB-NEXT: vsetvli a0, zero, e8, mf4, ta, ma96; CHECK-ZVKB-NEXT: vandn.vv v8, v9, v897; CHECK-ZVKB-NEXT: ret98 %a = xor <vscale x 2 x i8> %x, splat (i8 -1)99 %b = and <vscale x 2 x i8> %a, %y100 ret <vscale x 2 x i8> %b101}102 103define <vscale x 2 x i8> @vandn_vv_swapped_nxv2i8(<vscale x 2 x i8> %x, <vscale x 2 x i8> %y) {104; CHECK-LABEL: vandn_vv_swapped_nxv2i8:105; CHECK: # %bb.0:106; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma107; CHECK-NEXT: vnot.v v8, v8108; CHECK-NEXT: vand.vv v8, v9, v8109; CHECK-NEXT: ret110;111; CHECK-ZVKB-LABEL: vandn_vv_swapped_nxv2i8:112; CHECK-ZVKB: # %bb.0:113; CHECK-ZVKB-NEXT: vsetvli a0, zero, e8, mf4, ta, ma114; CHECK-ZVKB-NEXT: vandn.vv v8, v9, v8115; CHECK-ZVKB-NEXT: ret116 %a = xor <vscale x 2 x i8> %x, splat (i8 -1)117 %b = and <vscale x 2 x i8> %y, %a118 ret <vscale x 2 x i8> %b119}120 121define <vscale x 2 x i8> @vandn_vx_nxv2i8(i8 %x, <vscale x 2 x i8> %y) {122; CHECK-LABEL: vandn_vx_nxv2i8:123; CHECK: # %bb.0:124; CHECK-NEXT: not a0, a0125; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma126; CHECK-NEXT: vand.vx v8, v8, a0127; CHECK-NEXT: ret128;129; CHECK-ZVKB-LABEL: vandn_vx_nxv2i8:130; CHECK-ZVKB: # %bb.0:131; CHECK-ZVKB-NEXT: vsetvli a1, zero, e8, mf4, ta, ma132; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a0133; CHECK-ZVKB-NEXT: ret134 %a = xor i8 %x, -1135 %head = insertelement <vscale x 2 x i8> poison, i8 %a, i32 0136 %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer137 %b = and <vscale x 2 x i8> %splat, %y138 ret <vscale x 2 x i8> %b139}140 141define <vscale x 2 x i8> @vandn_vx_swapped_nxv2i8(i8 %x, <vscale x 2 x i8> %y) {142; CHECK-LABEL: vandn_vx_swapped_nxv2i8:143; CHECK: # %bb.0:144; CHECK-NEXT: not a0, a0145; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma146; CHECK-NEXT: vand.vx v8, v8, a0147; CHECK-NEXT: ret148;149; CHECK-ZVKB-LABEL: vandn_vx_swapped_nxv2i8:150; CHECK-ZVKB: # %bb.0:151; CHECK-ZVKB-NEXT: vsetvli a1, zero, e8, mf4, ta, ma152; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a0153; CHECK-ZVKB-NEXT: ret154 %a = xor i8 %x, -1155 %head = insertelement <vscale x 2 x i8> poison, i8 %a, i32 0156 %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer157 %b = and <vscale x 2 x i8> %splat, %y158 ret <vscale x 2 x i8> %b159}160 161define <vscale x 4 x i8> @vandn_vv_nxv4i8(<vscale x 4 x i8> %x, <vscale x 4 x i8> %y) {162; CHECK-LABEL: vandn_vv_nxv4i8:163; CHECK: # %bb.0:164; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma165; CHECK-NEXT: vnot.v v8, v8166; CHECK-NEXT: vand.vv v8, v8, v9167; CHECK-NEXT: ret168;169; CHECK-ZVKB-LABEL: vandn_vv_nxv4i8:170; CHECK-ZVKB: # %bb.0:171; CHECK-ZVKB-NEXT: vsetvli a0, zero, e8, mf2, ta, ma172; CHECK-ZVKB-NEXT: vandn.vv v8, v9, v8173; CHECK-ZVKB-NEXT: ret174 %a = xor <vscale x 4 x i8> %x, splat (i8 -1)175 %b = and <vscale x 4 x i8> %a, %y176 ret <vscale x 4 x i8> %b177}178 179define <vscale x 4 x i8> @vandn_vv_swapped_nxv4i8(<vscale x 4 x i8> %x, <vscale x 4 x i8> %y) {180; CHECK-LABEL: vandn_vv_swapped_nxv4i8:181; CHECK: # %bb.0:182; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma183; CHECK-NEXT: vnot.v v8, v8184; CHECK-NEXT: vand.vv v8, v9, v8185; CHECK-NEXT: ret186;187; CHECK-ZVKB-LABEL: vandn_vv_swapped_nxv4i8:188; CHECK-ZVKB: # %bb.0:189; CHECK-ZVKB-NEXT: vsetvli a0, zero, e8, mf2, ta, ma190; CHECK-ZVKB-NEXT: vandn.vv v8, v9, v8191; CHECK-ZVKB-NEXT: ret192 %a = xor <vscale x 4 x i8> %x, splat (i8 -1)193 %b = and <vscale x 4 x i8> %y, %a194 ret <vscale x 4 x i8> %b195}196 197define <vscale x 4 x i8> @vandn_vx_nxv4i8(i8 %x, <vscale x 4 x i8> %y) {198; CHECK-LABEL: vandn_vx_nxv4i8:199; CHECK: # %bb.0:200; CHECK-NEXT: not a0, a0201; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma202; CHECK-NEXT: vand.vx v8, v8, a0203; CHECK-NEXT: ret204;205; CHECK-ZVKB-LABEL: vandn_vx_nxv4i8:206; CHECK-ZVKB: # %bb.0:207; CHECK-ZVKB-NEXT: vsetvli a1, zero, e8, mf2, ta, ma208; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a0209; CHECK-ZVKB-NEXT: ret210 %a = xor i8 %x, -1211 %head = insertelement <vscale x 4 x i8> poison, i8 %a, i32 0212 %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer213 %b = and <vscale x 4 x i8> %splat, %y214 ret <vscale x 4 x i8> %b215}216 217define <vscale x 4 x i8> @vandn_vx_swapped_nxv4i8(i8 %x, <vscale x 4 x i8> %y) {218; CHECK-LABEL: vandn_vx_swapped_nxv4i8:219; CHECK: # %bb.0:220; CHECK-NEXT: not a0, a0221; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma222; CHECK-NEXT: vand.vx v8, v8, a0223; CHECK-NEXT: ret224;225; CHECK-ZVKB-LABEL: vandn_vx_swapped_nxv4i8:226; CHECK-ZVKB: # %bb.0:227; CHECK-ZVKB-NEXT: vsetvli a1, zero, e8, mf2, ta, ma228; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a0229; CHECK-ZVKB-NEXT: ret230 %a = xor i8 %x, -1231 %head = insertelement <vscale x 4 x i8> poison, i8 %a, i32 0232 %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer233 %b = and <vscale x 4 x i8> %splat, %y234 ret <vscale x 4 x i8> %b235}236 237define <vscale x 8 x i8> @vandn_vv_nxv8i8(<vscale x 8 x i8> %x, <vscale x 8 x i8> %y) {238; CHECK-LABEL: vandn_vv_nxv8i8:239; CHECK: # %bb.0:240; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma241; CHECK-NEXT: vnot.v v8, v8242; CHECK-NEXT: vand.vv v8, v8, v9243; CHECK-NEXT: ret244;245; CHECK-ZVKB-LABEL: vandn_vv_nxv8i8:246; CHECK-ZVKB: # %bb.0:247; CHECK-ZVKB-NEXT: vsetvli a0, zero, e8, m1, ta, ma248; CHECK-ZVKB-NEXT: vandn.vv v8, v9, v8249; CHECK-ZVKB-NEXT: ret250 %a = xor <vscale x 8 x i8> %x, splat (i8 -1)251 %b = and <vscale x 8 x i8> %a, %y252 ret <vscale x 8 x i8> %b253}254 255define <vscale x 8 x i8> @vandn_vv_swapped_nxv8i8(<vscale x 8 x i8> %x, <vscale x 8 x i8> %y) {256; CHECK-LABEL: vandn_vv_swapped_nxv8i8:257; CHECK: # %bb.0:258; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma259; CHECK-NEXT: vnot.v v8, v8260; CHECK-NEXT: vand.vv v8, v9, v8261; CHECK-NEXT: ret262;263; CHECK-ZVKB-LABEL: vandn_vv_swapped_nxv8i8:264; CHECK-ZVKB: # %bb.0:265; CHECK-ZVKB-NEXT: vsetvli a0, zero, e8, m1, ta, ma266; CHECK-ZVKB-NEXT: vandn.vv v8, v9, v8267; CHECK-ZVKB-NEXT: ret268 %a = xor <vscale x 8 x i8> %x, splat (i8 -1)269 %b = and <vscale x 8 x i8> %y, %a270 ret <vscale x 8 x i8> %b271}272 273define <vscale x 8 x i8> @vandn_vx_nxv8i8(i8 %x, <vscale x 8 x i8> %y) {274; CHECK-LABEL: vandn_vx_nxv8i8:275; CHECK: # %bb.0:276; CHECK-NEXT: not a0, a0277; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma278; CHECK-NEXT: vand.vx v8, v8, a0279; CHECK-NEXT: ret280;281; CHECK-ZVKB-LABEL: vandn_vx_nxv8i8:282; CHECK-ZVKB: # %bb.0:283; CHECK-ZVKB-NEXT: vsetvli a1, zero, e8, m1, ta, ma284; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a0285; CHECK-ZVKB-NEXT: ret286 %a = xor i8 %x, -1287 %head = insertelement <vscale x 8 x i8> poison, i8 %a, i32 0288 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer289 %b = and <vscale x 8 x i8> %splat, %y290 ret <vscale x 8 x i8> %b291}292 293define <vscale x 8 x i8> @vandn_vx_swapped_nxv8i8(i8 %x, <vscale x 8 x i8> %y) {294; CHECK-LABEL: vandn_vx_swapped_nxv8i8:295; CHECK: # %bb.0:296; CHECK-NEXT: not a0, a0297; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma298; CHECK-NEXT: vand.vx v8, v8, a0299; CHECK-NEXT: ret300;301; CHECK-ZVKB-LABEL: vandn_vx_swapped_nxv8i8:302; CHECK-ZVKB: # %bb.0:303; CHECK-ZVKB-NEXT: vsetvli a1, zero, e8, m1, ta, ma304; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a0305; CHECK-ZVKB-NEXT: ret306 %a = xor i8 %x, -1307 %head = insertelement <vscale x 8 x i8> poison, i8 %a, i32 0308 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer309 %b = and <vscale x 8 x i8> %splat, %y310 ret <vscale x 8 x i8> %b311}312 313define <vscale x 16 x i8> @vandn_vv_nxv16i8(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y) {314; CHECK-LABEL: vandn_vv_nxv16i8:315; CHECK: # %bb.0:316; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma317; CHECK-NEXT: vnot.v v8, v8318; CHECK-NEXT: vand.vv v8, v8, v10319; CHECK-NEXT: ret320;321; CHECK-ZVKB-LABEL: vandn_vv_nxv16i8:322; CHECK-ZVKB: # %bb.0:323; CHECK-ZVKB-NEXT: vsetvli a0, zero, e8, m2, ta, ma324; CHECK-ZVKB-NEXT: vandn.vv v8, v10, v8325; CHECK-ZVKB-NEXT: ret326 %a = xor <vscale x 16 x i8> %x, splat (i8 -1)327 %b = and <vscale x 16 x i8> %a, %y328 ret <vscale x 16 x i8> %b329}330 331define <vscale x 16 x i8> @vandn_vv_swapped_nxv16i8(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y) {332; CHECK-LABEL: vandn_vv_swapped_nxv16i8:333; CHECK: # %bb.0:334; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma335; CHECK-NEXT: vnot.v v8, v8336; CHECK-NEXT: vand.vv v8, v10, v8337; CHECK-NEXT: ret338;339; CHECK-ZVKB-LABEL: vandn_vv_swapped_nxv16i8:340; CHECK-ZVKB: # %bb.0:341; CHECK-ZVKB-NEXT: vsetvli a0, zero, e8, m2, ta, ma342; CHECK-ZVKB-NEXT: vandn.vv v8, v10, v8343; CHECK-ZVKB-NEXT: ret344 %a = xor <vscale x 16 x i8> %x, splat (i8 -1)345 %b = and <vscale x 16 x i8> %y, %a346 ret <vscale x 16 x i8> %b347}348 349define <vscale x 16 x i8> @vandn_vx_nxv16i8(i8 %x, <vscale x 16 x i8> %y) {350; CHECK-LABEL: vandn_vx_nxv16i8:351; CHECK: # %bb.0:352; CHECK-NEXT: not a0, a0353; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma354; CHECK-NEXT: vand.vx v8, v8, a0355; CHECK-NEXT: ret356;357; CHECK-ZVKB-LABEL: vandn_vx_nxv16i8:358; CHECK-ZVKB: # %bb.0:359; CHECK-ZVKB-NEXT: vsetvli a1, zero, e8, m2, ta, ma360; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a0361; CHECK-ZVKB-NEXT: ret362 %a = xor i8 %x, -1363 %head = insertelement <vscale x 16 x i8> poison, i8 %a, i32 0364 %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer365 %b = and <vscale x 16 x i8> %splat, %y366 ret <vscale x 16 x i8> %b367}368 369define <vscale x 16 x i8> @vandn_vx_swapped_nxv16i8(i8 %x, <vscale x 16 x i8> %y) {370; CHECK-LABEL: vandn_vx_swapped_nxv16i8:371; CHECK: # %bb.0:372; CHECK-NEXT: not a0, a0373; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma374; CHECK-NEXT: vand.vx v8, v8, a0375; CHECK-NEXT: ret376;377; CHECK-ZVKB-LABEL: vandn_vx_swapped_nxv16i8:378; CHECK-ZVKB: # %bb.0:379; CHECK-ZVKB-NEXT: vsetvli a1, zero, e8, m2, ta, ma380; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a0381; CHECK-ZVKB-NEXT: ret382 %a = xor i8 %x, -1383 %head = insertelement <vscale x 16 x i8> poison, i8 %a, i32 0384 %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer385 %b = and <vscale x 16 x i8> %splat, %y386 ret <vscale x 16 x i8> %b387}388 389define <vscale x 32 x i8> @vandn_vv_nxv32i8(<vscale x 32 x i8> %x, <vscale x 32 x i8> %y) {390; CHECK-LABEL: vandn_vv_nxv32i8:391; CHECK: # %bb.0:392; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma393; CHECK-NEXT: vnot.v v8, v8394; CHECK-NEXT: vand.vv v8, v8, v12395; CHECK-NEXT: ret396;397; CHECK-ZVKB-LABEL: vandn_vv_nxv32i8:398; CHECK-ZVKB: # %bb.0:399; CHECK-ZVKB-NEXT: vsetvli a0, zero, e8, m4, ta, ma400; CHECK-ZVKB-NEXT: vandn.vv v8, v12, v8401; CHECK-ZVKB-NEXT: ret402 %a = xor <vscale x 32 x i8> %x, splat (i8 -1)403 %b = and <vscale x 32 x i8> %a, %y404 ret <vscale x 32 x i8> %b405}406 407define <vscale x 32 x i8> @vandn_vv_swapped_nxv32i8(<vscale x 32 x i8> %x, <vscale x 32 x i8> %y) {408; CHECK-LABEL: vandn_vv_swapped_nxv32i8:409; CHECK: # %bb.0:410; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma411; CHECK-NEXT: vnot.v v8, v8412; CHECK-NEXT: vand.vv v8, v12, v8413; CHECK-NEXT: ret414;415; CHECK-ZVKB-LABEL: vandn_vv_swapped_nxv32i8:416; CHECK-ZVKB: # %bb.0:417; CHECK-ZVKB-NEXT: vsetvli a0, zero, e8, m4, ta, ma418; CHECK-ZVKB-NEXT: vandn.vv v8, v12, v8419; CHECK-ZVKB-NEXT: ret420 %a = xor <vscale x 32 x i8> %x, splat (i8 -1)421 %b = and <vscale x 32 x i8> %y, %a422 ret <vscale x 32 x i8> %b423}424 425define <vscale x 32 x i8> @vandn_vx_nxv32i8(i8 %x, <vscale x 32 x i8> %y) {426; CHECK-LABEL: vandn_vx_nxv32i8:427; CHECK: # %bb.0:428; CHECK-NEXT: not a0, a0429; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma430; CHECK-NEXT: vand.vx v8, v8, a0431; CHECK-NEXT: ret432;433; CHECK-ZVKB-LABEL: vandn_vx_nxv32i8:434; CHECK-ZVKB: # %bb.0:435; CHECK-ZVKB-NEXT: vsetvli a1, zero, e8, m4, ta, ma436; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a0437; CHECK-ZVKB-NEXT: ret438 %a = xor i8 %x, -1439 %head = insertelement <vscale x 32 x i8> poison, i8 %a, i32 0440 %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer441 %b = and <vscale x 32 x i8> %splat, %y442 ret <vscale x 32 x i8> %b443}444 445define <vscale x 32 x i8> @vandn_vx_swapped_nxv32i8(i8 %x, <vscale x 32 x i8> %y) {446; CHECK-LABEL: vandn_vx_swapped_nxv32i8:447; CHECK: # %bb.0:448; CHECK-NEXT: not a0, a0449; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma450; CHECK-NEXT: vand.vx v8, v8, a0451; CHECK-NEXT: ret452;453; CHECK-ZVKB-LABEL: vandn_vx_swapped_nxv32i8:454; CHECK-ZVKB: # %bb.0:455; CHECK-ZVKB-NEXT: vsetvli a1, zero, e8, m4, ta, ma456; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a0457; CHECK-ZVKB-NEXT: ret458 %a = xor i8 %x, -1459 %head = insertelement <vscale x 32 x i8> poison, i8 %a, i32 0460 %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer461 %b = and <vscale x 32 x i8> %splat, %y462 ret <vscale x 32 x i8> %b463}464 465define <vscale x 64 x i8> @vandn_vv_nxv64i8(<vscale x 64 x i8> %x, <vscale x 64 x i8> %y) {466; CHECK-LABEL: vandn_vv_nxv64i8:467; CHECK: # %bb.0:468; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma469; CHECK-NEXT: vnot.v v8, v8470; CHECK-NEXT: vand.vv v8, v8, v16471; CHECK-NEXT: ret472;473; CHECK-ZVKB-LABEL: vandn_vv_nxv64i8:474; CHECK-ZVKB: # %bb.0:475; CHECK-ZVKB-NEXT: vsetvli a0, zero, e8, m8, ta, ma476; CHECK-ZVKB-NEXT: vandn.vv v8, v16, v8477; CHECK-ZVKB-NEXT: ret478 %a = xor <vscale x 64 x i8> %x, splat (i8 -1)479 %b = and <vscale x 64 x i8> %a, %y480 ret <vscale x 64 x i8> %b481}482 483define <vscale x 64 x i8> @vandn_vv_swapped_nxv64i8(<vscale x 64 x i8> %x, <vscale x 64 x i8> %y) {484; CHECK-LABEL: vandn_vv_swapped_nxv64i8:485; CHECK: # %bb.0:486; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma487; CHECK-NEXT: vnot.v v8, v8488; CHECK-NEXT: vand.vv v8, v16, v8489; CHECK-NEXT: ret490;491; CHECK-ZVKB-LABEL: vandn_vv_swapped_nxv64i8:492; CHECK-ZVKB: # %bb.0:493; CHECK-ZVKB-NEXT: vsetvli a0, zero, e8, m8, ta, ma494; CHECK-ZVKB-NEXT: vandn.vv v8, v16, v8495; CHECK-ZVKB-NEXT: ret496 %a = xor <vscale x 64 x i8> %x, splat (i8 -1)497 %b = and <vscale x 64 x i8> %y, %a498 ret <vscale x 64 x i8> %b499}500 501define <vscale x 64 x i8> @vandn_vx_nxv64i8(i8 %x, <vscale x 64 x i8> %y) {502; CHECK-LABEL: vandn_vx_nxv64i8:503; CHECK: # %bb.0:504; CHECK-NEXT: not a0, a0505; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma506; CHECK-NEXT: vand.vx v8, v8, a0507; CHECK-NEXT: ret508;509; CHECK-ZVKB-LABEL: vandn_vx_nxv64i8:510; CHECK-ZVKB: # %bb.0:511; CHECK-ZVKB-NEXT: vsetvli a1, zero, e8, m8, ta, ma512; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a0513; CHECK-ZVKB-NEXT: ret514 %a = xor i8 %x, -1515 %head = insertelement <vscale x 64 x i8> poison, i8 %a, i32 0516 %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer517 %b = and <vscale x 64 x i8> %splat, %y518 ret <vscale x 64 x i8> %b519}520 521define <vscale x 64 x i8> @vandn_vx_swapped_nxv64i8(i8 %x, <vscale x 64 x i8> %y) {522; CHECK-LABEL: vandn_vx_swapped_nxv64i8:523; CHECK: # %bb.0:524; CHECK-NEXT: not a0, a0525; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma526; CHECK-NEXT: vand.vx v8, v8, a0527; CHECK-NEXT: ret528;529; CHECK-ZVKB-LABEL: vandn_vx_swapped_nxv64i8:530; CHECK-ZVKB: # %bb.0:531; CHECK-ZVKB-NEXT: vsetvli a1, zero, e8, m8, ta, ma532; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a0533; CHECK-ZVKB-NEXT: ret534 %a = xor i8 %x, -1535 %head = insertelement <vscale x 64 x i8> poison, i8 %a, i32 0536 %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer537 %b = and <vscale x 64 x i8> %splat, %y538 ret <vscale x 64 x i8> %b539}540 541define <vscale x 1 x i16> @vandn_vv_nxv1i16(<vscale x 1 x i16> %x, <vscale x 1 x i16> %y) {542; CHECK-LABEL: vandn_vv_nxv1i16:543; CHECK: # %bb.0:544; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma545; CHECK-NEXT: vnot.v v8, v8546; CHECK-NEXT: vand.vv v8, v8, v9547; CHECK-NEXT: ret548;549; CHECK-ZVKB-LABEL: vandn_vv_nxv1i16:550; CHECK-ZVKB: # %bb.0:551; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, mf4, ta, ma552; CHECK-ZVKB-NEXT: vandn.vv v8, v9, v8553; CHECK-ZVKB-NEXT: ret554 %a = xor <vscale x 1 x i16> %x, splat (i16 -1)555 %b = and <vscale x 1 x i16> %a, %y556 ret <vscale x 1 x i16> %b557}558 559define <vscale x 1 x i16> @vandn_vv_swapped_nxv1i16(<vscale x 1 x i16> %x, <vscale x 1 x i16> %y) {560; CHECK-LABEL: vandn_vv_swapped_nxv1i16:561; CHECK: # %bb.0:562; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma563; CHECK-NEXT: vnot.v v8, v8564; CHECK-NEXT: vand.vv v8, v9, v8565; CHECK-NEXT: ret566;567; CHECK-ZVKB-LABEL: vandn_vv_swapped_nxv1i16:568; CHECK-ZVKB: # %bb.0:569; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, mf4, ta, ma570; CHECK-ZVKB-NEXT: vandn.vv v8, v9, v8571; CHECK-ZVKB-NEXT: ret572 %a = xor <vscale x 1 x i16> %x, splat (i16 -1)573 %b = and <vscale x 1 x i16> %y, %a574 ret <vscale x 1 x i16> %b575}576 577define <vscale x 1 x i16> @vandn_vx_nxv1i16(i16 %x, <vscale x 1 x i16> %y) {578; CHECK-LABEL: vandn_vx_nxv1i16:579; CHECK: # %bb.0:580; CHECK-NEXT: not a0, a0581; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma582; CHECK-NEXT: vand.vx v8, v8, a0583; CHECK-NEXT: ret584;585; CHECK-ZVKB-LABEL: vandn_vx_nxv1i16:586; CHECK-ZVKB: # %bb.0:587; CHECK-ZVKB-NEXT: vsetvli a1, zero, e16, mf4, ta, ma588; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a0589; CHECK-ZVKB-NEXT: ret590 %a = xor i16 %x, -1591 %head = insertelement <vscale x 1 x i16> poison, i16 %a, i32 0592 %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer593 %b = and <vscale x 1 x i16> %splat, %y594 ret <vscale x 1 x i16> %b595}596 597define <vscale x 1 x i16> @vandn_vx_swapped_nxv1i16(i16 %x, <vscale x 1 x i16> %y) {598; CHECK-LABEL: vandn_vx_swapped_nxv1i16:599; CHECK: # %bb.0:600; CHECK-NEXT: not a0, a0601; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma602; CHECK-NEXT: vand.vx v8, v8, a0603; CHECK-NEXT: ret604;605; CHECK-ZVKB-LABEL: vandn_vx_swapped_nxv1i16:606; CHECK-ZVKB: # %bb.0:607; CHECK-ZVKB-NEXT: vsetvli a1, zero, e16, mf4, ta, ma608; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a0609; CHECK-ZVKB-NEXT: ret610 %a = xor i16 %x, -1611 %head = insertelement <vscale x 1 x i16> poison, i16 %a, i32 0612 %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer613 %b = and <vscale x 1 x i16> %splat, %y614 ret <vscale x 1 x i16> %b615}616 617define <vscale x 2 x i16> @vandn_vv_nxv2i16(<vscale x 2 x i16> %x, <vscale x 2 x i16> %y) {618; CHECK-LABEL: vandn_vv_nxv2i16:619; CHECK: # %bb.0:620; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma621; CHECK-NEXT: vnot.v v8, v8622; CHECK-NEXT: vand.vv v8, v8, v9623; CHECK-NEXT: ret624;625; CHECK-ZVKB-LABEL: vandn_vv_nxv2i16:626; CHECK-ZVKB: # %bb.0:627; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, mf2, ta, ma628; CHECK-ZVKB-NEXT: vandn.vv v8, v9, v8629; CHECK-ZVKB-NEXT: ret630 %a = xor <vscale x 2 x i16> %x, splat (i16 -1)631 %b = and <vscale x 2 x i16> %a, %y632 ret <vscale x 2 x i16> %b633}634 635define <vscale x 2 x i16> @vandn_vv_swapped_nxv2i16(<vscale x 2 x i16> %x, <vscale x 2 x i16> %y) {636; CHECK-LABEL: vandn_vv_swapped_nxv2i16:637; CHECK: # %bb.0:638; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma639; CHECK-NEXT: vnot.v v8, v8640; CHECK-NEXT: vand.vv v8, v9, v8641; CHECK-NEXT: ret642;643; CHECK-ZVKB-LABEL: vandn_vv_swapped_nxv2i16:644; CHECK-ZVKB: # %bb.0:645; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, mf2, ta, ma646; CHECK-ZVKB-NEXT: vandn.vv v8, v9, v8647; CHECK-ZVKB-NEXT: ret648 %a = xor <vscale x 2 x i16> %x, splat (i16 -1)649 %b = and <vscale x 2 x i16> %y, %a650 ret <vscale x 2 x i16> %b651}652 653define <vscale x 2 x i16> @vandn_vx_nxv2i16(i16 %x, <vscale x 2 x i16> %y) {654; CHECK-LABEL: vandn_vx_nxv2i16:655; CHECK: # %bb.0:656; CHECK-NEXT: not a0, a0657; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma658; CHECK-NEXT: vand.vx v8, v8, a0659; CHECK-NEXT: ret660;661; CHECK-ZVKB-LABEL: vandn_vx_nxv2i16:662; CHECK-ZVKB: # %bb.0:663; CHECK-ZVKB-NEXT: vsetvli a1, zero, e16, mf2, ta, ma664; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a0665; CHECK-ZVKB-NEXT: ret666 %a = xor i16 %x, -1667 %head = insertelement <vscale x 2 x i16> poison, i16 %a, i32 0668 %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer669 %b = and <vscale x 2 x i16> %splat, %y670 ret <vscale x 2 x i16> %b671}672 673define <vscale x 2 x i16> @vandn_vx_swapped_nxv2i16(i16 %x, <vscale x 2 x i16> %y) {674; CHECK-LABEL: vandn_vx_swapped_nxv2i16:675; CHECK: # %bb.0:676; CHECK-NEXT: not a0, a0677; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma678; CHECK-NEXT: vand.vx v8, v8, a0679; CHECK-NEXT: ret680;681; CHECK-ZVKB-LABEL: vandn_vx_swapped_nxv2i16:682; CHECK-ZVKB: # %bb.0:683; CHECK-ZVKB-NEXT: vsetvli a1, zero, e16, mf2, ta, ma684; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a0685; CHECK-ZVKB-NEXT: ret686 %a = xor i16 %x, -1687 %head = insertelement <vscale x 2 x i16> poison, i16 %a, i32 0688 %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer689 %b = and <vscale x 2 x i16> %splat, %y690 ret <vscale x 2 x i16> %b691}692 693define <vscale x 4 x i16> @vandn_vv_nxv4i16(<vscale x 4 x i16> %x, <vscale x 4 x i16> %y) {694; CHECK-LABEL: vandn_vv_nxv4i16:695; CHECK: # %bb.0:696; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma697; CHECK-NEXT: vnot.v v8, v8698; CHECK-NEXT: vand.vv v8, v8, v9699; CHECK-NEXT: ret700;701; CHECK-ZVKB-LABEL: vandn_vv_nxv4i16:702; CHECK-ZVKB: # %bb.0:703; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, m1, ta, ma704; CHECK-ZVKB-NEXT: vandn.vv v8, v9, v8705; CHECK-ZVKB-NEXT: ret706 %a = xor <vscale x 4 x i16> %x, splat (i16 -1)707 %b = and <vscale x 4 x i16> %a, %y708 ret <vscale x 4 x i16> %b709}710 711define <vscale x 4 x i16> @vandn_vv_swapped_nxv4i16(<vscale x 4 x i16> %x, <vscale x 4 x i16> %y) {712; CHECK-LABEL: vandn_vv_swapped_nxv4i16:713; CHECK: # %bb.0:714; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma715; CHECK-NEXT: vnot.v v8, v8716; CHECK-NEXT: vand.vv v8, v9, v8717; CHECK-NEXT: ret718;719; CHECK-ZVKB-LABEL: vandn_vv_swapped_nxv4i16:720; CHECK-ZVKB: # %bb.0:721; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, m1, ta, ma722; CHECK-ZVKB-NEXT: vandn.vv v8, v9, v8723; CHECK-ZVKB-NEXT: ret724 %a = xor <vscale x 4 x i16> %x, splat (i16 -1)725 %b = and <vscale x 4 x i16> %y, %a726 ret <vscale x 4 x i16> %b727}728 729define <vscale x 4 x i16> @vandn_vx_nxv4i16(i16 %x, <vscale x 4 x i16> %y) {730; CHECK-LABEL: vandn_vx_nxv4i16:731; CHECK: # %bb.0:732; CHECK-NEXT: not a0, a0733; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma734; CHECK-NEXT: vand.vx v8, v8, a0735; CHECK-NEXT: ret736;737; CHECK-ZVKB-LABEL: vandn_vx_nxv4i16:738; CHECK-ZVKB: # %bb.0:739; CHECK-ZVKB-NEXT: vsetvli a1, zero, e16, m1, ta, ma740; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a0741; CHECK-ZVKB-NEXT: ret742 %a = xor i16 %x, -1743 %head = insertelement <vscale x 4 x i16> poison, i16 %a, i32 0744 %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer745 %b = and <vscale x 4 x i16> %splat, %y746 ret <vscale x 4 x i16> %b747}748 749define <vscale x 4 x i16> @vandn_vx_swapped_nxv4i16(i16 %x, <vscale x 4 x i16> %y) {750; CHECK-LABEL: vandn_vx_swapped_nxv4i16:751; CHECK: # %bb.0:752; CHECK-NEXT: not a0, a0753; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma754; CHECK-NEXT: vand.vx v8, v8, a0755; CHECK-NEXT: ret756;757; CHECK-ZVKB-LABEL: vandn_vx_swapped_nxv4i16:758; CHECK-ZVKB: # %bb.0:759; CHECK-ZVKB-NEXT: vsetvli a1, zero, e16, m1, ta, ma760; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a0761; CHECK-ZVKB-NEXT: ret762 %a = xor i16 %x, -1763 %head = insertelement <vscale x 4 x i16> poison, i16 %a, i32 0764 %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer765 %b = and <vscale x 4 x i16> %splat, %y766 ret <vscale x 4 x i16> %b767}768 769define <vscale x 8 x i16> @vandn_vv_nxv8i16(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y) {770; CHECK-LABEL: vandn_vv_nxv8i16:771; CHECK: # %bb.0:772; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma773; CHECK-NEXT: vnot.v v8, v8774; CHECK-NEXT: vand.vv v8, v8, v10775; CHECK-NEXT: ret776;777; CHECK-ZVKB-LABEL: vandn_vv_nxv8i16:778; CHECK-ZVKB: # %bb.0:779; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, m2, ta, ma780; CHECK-ZVKB-NEXT: vandn.vv v8, v10, v8781; CHECK-ZVKB-NEXT: ret782 %a = xor <vscale x 8 x i16> %x, splat (i16 -1)783 %b = and <vscale x 8 x i16> %a, %y784 ret <vscale x 8 x i16> %b785}786 787define <vscale x 8 x i16> @vandn_vv_swapped_nxv8i16(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y) {788; CHECK-LABEL: vandn_vv_swapped_nxv8i16:789; CHECK: # %bb.0:790; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma791; CHECK-NEXT: vnot.v v8, v8792; CHECK-NEXT: vand.vv v8, v10, v8793; CHECK-NEXT: ret794;795; CHECK-ZVKB-LABEL: vandn_vv_swapped_nxv8i16:796; CHECK-ZVKB: # %bb.0:797; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, m2, ta, ma798; CHECK-ZVKB-NEXT: vandn.vv v8, v10, v8799; CHECK-ZVKB-NEXT: ret800 %a = xor <vscale x 8 x i16> %x, splat (i16 -1)801 %b = and <vscale x 8 x i16> %y, %a802 ret <vscale x 8 x i16> %b803}804 805define <vscale x 8 x i16> @vandn_vx_nxv8i16(i16 %x, <vscale x 8 x i16> %y) {806; CHECK-LABEL: vandn_vx_nxv8i16:807; CHECK: # %bb.0:808; CHECK-NEXT: not a0, a0809; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma810; CHECK-NEXT: vand.vx v8, v8, a0811; CHECK-NEXT: ret812;813; CHECK-ZVKB-LABEL: vandn_vx_nxv8i16:814; CHECK-ZVKB: # %bb.0:815; CHECK-ZVKB-NEXT: vsetvli a1, zero, e16, m2, ta, ma816; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a0817; CHECK-ZVKB-NEXT: ret818 %a = xor i16 %x, -1819 %head = insertelement <vscale x 8 x i16> poison, i16 %a, i32 0820 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer821 %b = and <vscale x 8 x i16> %splat, %y822 ret <vscale x 8 x i16> %b823}824 825define <vscale x 8 x i16> @vandn_vx_swapped_nxv8i16(i16 %x, <vscale x 8 x i16> %y) {826; CHECK-LABEL: vandn_vx_swapped_nxv8i16:827; CHECK: # %bb.0:828; CHECK-NEXT: not a0, a0829; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma830; CHECK-NEXT: vand.vx v8, v8, a0831; CHECK-NEXT: ret832;833; CHECK-ZVKB-LABEL: vandn_vx_swapped_nxv8i16:834; CHECK-ZVKB: # %bb.0:835; CHECK-ZVKB-NEXT: vsetvli a1, zero, e16, m2, ta, ma836; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a0837; CHECK-ZVKB-NEXT: ret838 %a = xor i16 %x, -1839 %head = insertelement <vscale x 8 x i16> poison, i16 %a, i32 0840 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer841 %b = and <vscale x 8 x i16> %splat, %y842 ret <vscale x 8 x i16> %b843}844 845define <vscale x 16 x i16> @vandn_vv_nxv16i16(<vscale x 16 x i16> %x, <vscale x 16 x i16> %y) {846; CHECK-LABEL: vandn_vv_nxv16i16:847; CHECK: # %bb.0:848; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma849; CHECK-NEXT: vnot.v v8, v8850; CHECK-NEXT: vand.vv v8, v8, v12851; CHECK-NEXT: ret852;853; CHECK-ZVKB-LABEL: vandn_vv_nxv16i16:854; CHECK-ZVKB: # %bb.0:855; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, m4, ta, ma856; CHECK-ZVKB-NEXT: vandn.vv v8, v12, v8857; CHECK-ZVKB-NEXT: ret858 %a = xor <vscale x 16 x i16> %x, splat (i16 -1)859 %b = and <vscale x 16 x i16> %a, %y860 ret <vscale x 16 x i16> %b861}862 863define <vscale x 16 x i16> @vandn_vv_swapped_nxv16i16(<vscale x 16 x i16> %x, <vscale x 16 x i16> %y) {864; CHECK-LABEL: vandn_vv_swapped_nxv16i16:865; CHECK: # %bb.0:866; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma867; CHECK-NEXT: vnot.v v8, v8868; CHECK-NEXT: vand.vv v8, v12, v8869; CHECK-NEXT: ret870;871; CHECK-ZVKB-LABEL: vandn_vv_swapped_nxv16i16:872; CHECK-ZVKB: # %bb.0:873; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, m4, ta, ma874; CHECK-ZVKB-NEXT: vandn.vv v8, v12, v8875; CHECK-ZVKB-NEXT: ret876 %a = xor <vscale x 16 x i16> %x, splat (i16 -1)877 %b = and <vscale x 16 x i16> %y, %a878 ret <vscale x 16 x i16> %b879}880 881define <vscale x 16 x i16> @vandn_vx_nxv16i16(i16 %x, <vscale x 16 x i16> %y) {882; CHECK-LABEL: vandn_vx_nxv16i16:883; CHECK: # %bb.0:884; CHECK-NEXT: not a0, a0885; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma886; CHECK-NEXT: vand.vx v8, v8, a0887; CHECK-NEXT: ret888;889; CHECK-ZVKB-LABEL: vandn_vx_nxv16i16:890; CHECK-ZVKB: # %bb.0:891; CHECK-ZVKB-NEXT: vsetvli a1, zero, e16, m4, ta, ma892; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a0893; CHECK-ZVKB-NEXT: ret894 %a = xor i16 %x, -1895 %head = insertelement <vscale x 16 x i16> poison, i16 %a, i32 0896 %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer897 %b = and <vscale x 16 x i16> %splat, %y898 ret <vscale x 16 x i16> %b899}900 901define <vscale x 16 x i16> @vandn_vx_swapped_nxv16i16(i16 %x, <vscale x 16 x i16> %y) {902; CHECK-LABEL: vandn_vx_swapped_nxv16i16:903; CHECK: # %bb.0:904; CHECK-NEXT: not a0, a0905; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma906; CHECK-NEXT: vand.vx v8, v8, a0907; CHECK-NEXT: ret908;909; CHECK-ZVKB-LABEL: vandn_vx_swapped_nxv16i16:910; CHECK-ZVKB: # %bb.0:911; CHECK-ZVKB-NEXT: vsetvli a1, zero, e16, m4, ta, ma912; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a0913; CHECK-ZVKB-NEXT: ret914 %a = xor i16 %x, -1915 %head = insertelement <vscale x 16 x i16> poison, i16 %a, i32 0916 %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer917 %b = and <vscale x 16 x i16> %splat, %y918 ret <vscale x 16 x i16> %b919}920 921define <vscale x 32 x i16> @vandn_vv_nxv32i16(<vscale x 32 x i16> %x, <vscale x 32 x i16> %y) {922; CHECK-LABEL: vandn_vv_nxv32i16:923; CHECK: # %bb.0:924; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma925; CHECK-NEXT: vnot.v v8, v8926; CHECK-NEXT: vand.vv v8, v8, v16927; CHECK-NEXT: ret928;929; CHECK-ZVKB-LABEL: vandn_vv_nxv32i16:930; CHECK-ZVKB: # %bb.0:931; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, m8, ta, ma932; CHECK-ZVKB-NEXT: vandn.vv v8, v16, v8933; CHECK-ZVKB-NEXT: ret934 %a = xor <vscale x 32 x i16> %x, splat (i16 -1)935 %b = and <vscale x 32 x i16> %a, %y936 ret <vscale x 32 x i16> %b937}938 939define <vscale x 32 x i16> @vandn_vv_swapped_nxv32i16(<vscale x 32 x i16> %x, <vscale x 32 x i16> %y) {940; CHECK-LABEL: vandn_vv_swapped_nxv32i16:941; CHECK: # %bb.0:942; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma943; CHECK-NEXT: vnot.v v8, v8944; CHECK-NEXT: vand.vv v8, v16, v8945; CHECK-NEXT: ret946;947; CHECK-ZVKB-LABEL: vandn_vv_swapped_nxv32i16:948; CHECK-ZVKB: # %bb.0:949; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, m8, ta, ma950; CHECK-ZVKB-NEXT: vandn.vv v8, v16, v8951; CHECK-ZVKB-NEXT: ret952 %a = xor <vscale x 32 x i16> %x, splat (i16 -1)953 %b = and <vscale x 32 x i16> %y, %a954 ret <vscale x 32 x i16> %b955}956 957define <vscale x 32 x i16> @vandn_vx_nxv32i16(i16 %x, <vscale x 32 x i16> %y) {958; CHECK-LABEL: vandn_vx_nxv32i16:959; CHECK: # %bb.0:960; CHECK-NEXT: not a0, a0961; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma962; CHECK-NEXT: vand.vx v8, v8, a0963; CHECK-NEXT: ret964;965; CHECK-ZVKB-LABEL: vandn_vx_nxv32i16:966; CHECK-ZVKB: # %bb.0:967; CHECK-ZVKB-NEXT: vsetvli a1, zero, e16, m8, ta, ma968; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a0969; CHECK-ZVKB-NEXT: ret970 %a = xor i16 %x, -1971 %head = insertelement <vscale x 32 x i16> poison, i16 %a, i32 0972 %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer973 %b = and <vscale x 32 x i16> %splat, %y974 ret <vscale x 32 x i16> %b975}976 977define <vscale x 32 x i16> @vandn_vx_swapped_nxv32i16(i16 %x, <vscale x 32 x i16> %y) {978; CHECK-LABEL: vandn_vx_swapped_nxv32i16:979; CHECK: # %bb.0:980; CHECK-NEXT: not a0, a0981; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma982; CHECK-NEXT: vand.vx v8, v8, a0983; CHECK-NEXT: ret984;985; CHECK-ZVKB-LABEL: vandn_vx_swapped_nxv32i16:986; CHECK-ZVKB: # %bb.0:987; CHECK-ZVKB-NEXT: vsetvli a1, zero, e16, m8, ta, ma988; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a0989; CHECK-ZVKB-NEXT: ret990 %a = xor i16 %x, -1991 %head = insertelement <vscale x 32 x i16> poison, i16 %a, i32 0992 %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer993 %b = and <vscale x 32 x i16> %splat, %y994 ret <vscale x 32 x i16> %b995}996 997define <vscale x 1 x i32> @vandn_vv_nxv1i32(<vscale x 1 x i32> %x, <vscale x 1 x i32> %y) {998; CHECK-LABEL: vandn_vv_nxv1i32:999; CHECK: # %bb.0:1000; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma1001; CHECK-NEXT: vnot.v v8, v81002; CHECK-NEXT: vand.vv v8, v8, v91003; CHECK-NEXT: ret1004;1005; CHECK-ZVKB-LABEL: vandn_vv_nxv1i32:1006; CHECK-ZVKB: # %bb.0:1007; CHECK-ZVKB-NEXT: vsetvli a0, zero, e32, mf2, ta, ma1008; CHECK-ZVKB-NEXT: vandn.vv v8, v9, v81009; CHECK-ZVKB-NEXT: ret1010 %a = xor <vscale x 1 x i32> %x, splat (i32 -1)1011 %b = and <vscale x 1 x i32> %a, %y1012 ret <vscale x 1 x i32> %b1013}1014 1015define <vscale x 1 x i32> @vandn_vv_swapped_nxv1i32(<vscale x 1 x i32> %x, <vscale x 1 x i32> %y) {1016; CHECK-LABEL: vandn_vv_swapped_nxv1i32:1017; CHECK: # %bb.0:1018; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma1019; CHECK-NEXT: vnot.v v8, v81020; CHECK-NEXT: vand.vv v8, v9, v81021; CHECK-NEXT: ret1022;1023; CHECK-ZVKB-LABEL: vandn_vv_swapped_nxv1i32:1024; CHECK-ZVKB: # %bb.0:1025; CHECK-ZVKB-NEXT: vsetvli a0, zero, e32, mf2, ta, ma1026; CHECK-ZVKB-NEXT: vandn.vv v8, v9, v81027; CHECK-ZVKB-NEXT: ret1028 %a = xor <vscale x 1 x i32> %x, splat (i32 -1)1029 %b = and <vscale x 1 x i32> %y, %a1030 ret <vscale x 1 x i32> %b1031}1032 1033define <vscale x 1 x i32> @vandn_vx_nxv1i32(i32 %x, <vscale x 1 x i32> %y) {1034; CHECK-LABEL: vandn_vx_nxv1i32:1035; CHECK: # %bb.0:1036; CHECK-NEXT: not a0, a01037; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma1038; CHECK-NEXT: vand.vx v8, v8, a01039; CHECK-NEXT: ret1040;1041; CHECK-ZVKB-LABEL: vandn_vx_nxv1i32:1042; CHECK-ZVKB: # %bb.0:1043; CHECK-ZVKB-NEXT: vsetvli a1, zero, e32, mf2, ta, ma1044; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a01045; CHECK-ZVKB-NEXT: ret1046 %a = xor i32 %x, -11047 %head = insertelement <vscale x 1 x i32> poison, i32 %a, i32 01048 %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer1049 %b = and <vscale x 1 x i32> %splat, %y1050 ret <vscale x 1 x i32> %b1051}1052 1053define <vscale x 1 x i32> @vandn_vx_swapped_nxv1i32(i32 %x, <vscale x 1 x i32> %y) {1054; CHECK-LABEL: vandn_vx_swapped_nxv1i32:1055; CHECK: # %bb.0:1056; CHECK-NEXT: not a0, a01057; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma1058; CHECK-NEXT: vand.vx v8, v8, a01059; CHECK-NEXT: ret1060;1061; CHECK-ZVKB-LABEL: vandn_vx_swapped_nxv1i32:1062; CHECK-ZVKB: # %bb.0:1063; CHECK-ZVKB-NEXT: vsetvli a1, zero, e32, mf2, ta, ma1064; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a01065; CHECK-ZVKB-NEXT: ret1066 %a = xor i32 %x, -11067 %head = insertelement <vscale x 1 x i32> poison, i32 %a, i32 01068 %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer1069 %b = and <vscale x 1 x i32> %splat, %y1070 ret <vscale x 1 x i32> %b1071}1072 1073define <vscale x 2 x i32> @vandn_vv_nxv2i32(<vscale x 2 x i32> %x, <vscale x 2 x i32> %y) {1074; CHECK-LABEL: vandn_vv_nxv2i32:1075; CHECK: # %bb.0:1076; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma1077; CHECK-NEXT: vnot.v v8, v81078; CHECK-NEXT: vand.vv v8, v8, v91079; CHECK-NEXT: ret1080;1081; CHECK-ZVKB-LABEL: vandn_vv_nxv2i32:1082; CHECK-ZVKB: # %bb.0:1083; CHECK-ZVKB-NEXT: vsetvli a0, zero, e32, m1, ta, ma1084; CHECK-ZVKB-NEXT: vandn.vv v8, v9, v81085; CHECK-ZVKB-NEXT: ret1086 %a = xor <vscale x 2 x i32> %x, splat (i32 -1)1087 %b = and <vscale x 2 x i32> %a, %y1088 ret <vscale x 2 x i32> %b1089}1090 1091define <vscale x 2 x i32> @vandn_vv_swapped_nxv2i32(<vscale x 2 x i32> %x, <vscale x 2 x i32> %y) {1092; CHECK-LABEL: vandn_vv_swapped_nxv2i32:1093; CHECK: # %bb.0:1094; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma1095; CHECK-NEXT: vnot.v v8, v81096; CHECK-NEXT: vand.vv v8, v9, v81097; CHECK-NEXT: ret1098;1099; CHECK-ZVKB-LABEL: vandn_vv_swapped_nxv2i32:1100; CHECK-ZVKB: # %bb.0:1101; CHECK-ZVKB-NEXT: vsetvli a0, zero, e32, m1, ta, ma1102; CHECK-ZVKB-NEXT: vandn.vv v8, v9, v81103; CHECK-ZVKB-NEXT: ret1104 %a = xor <vscale x 2 x i32> %x, splat (i32 -1)1105 %b = and <vscale x 2 x i32> %y, %a1106 ret <vscale x 2 x i32> %b1107}1108 1109define <vscale x 2 x i32> @vandn_vx_nxv2i32(i32 %x, <vscale x 2 x i32> %y) {1110; CHECK-LABEL: vandn_vx_nxv2i32:1111; CHECK: # %bb.0:1112; CHECK-NEXT: not a0, a01113; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma1114; CHECK-NEXT: vand.vx v8, v8, a01115; CHECK-NEXT: ret1116;1117; CHECK-ZVKB-LABEL: vandn_vx_nxv2i32:1118; CHECK-ZVKB: # %bb.0:1119; CHECK-ZVKB-NEXT: vsetvli a1, zero, e32, m1, ta, ma1120; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a01121; CHECK-ZVKB-NEXT: ret1122 %a = xor i32 %x, -11123 %head = insertelement <vscale x 2 x i32> poison, i32 %a, i32 01124 %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer1125 %b = and <vscale x 2 x i32> %splat, %y1126 ret <vscale x 2 x i32> %b1127}1128 1129define <vscale x 2 x i32> @vandn_vx_swapped_nxv2i32(i32 %x, <vscale x 2 x i32> %y) {1130; CHECK-LABEL: vandn_vx_swapped_nxv2i32:1131; CHECK: # %bb.0:1132; CHECK-NEXT: not a0, a01133; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma1134; CHECK-NEXT: vand.vx v8, v8, a01135; CHECK-NEXT: ret1136;1137; CHECK-ZVKB-LABEL: vandn_vx_swapped_nxv2i32:1138; CHECK-ZVKB: # %bb.0:1139; CHECK-ZVKB-NEXT: vsetvli a1, zero, e32, m1, ta, ma1140; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a01141; CHECK-ZVKB-NEXT: ret1142 %a = xor i32 %x, -11143 %head = insertelement <vscale x 2 x i32> poison, i32 %a, i32 01144 %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer1145 %b = and <vscale x 2 x i32> %splat, %y1146 ret <vscale x 2 x i32> %b1147}1148 1149define <vscale x 4 x i32> @vandn_vv_nxv4i32(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y) {1150; CHECK-LABEL: vandn_vv_nxv4i32:1151; CHECK: # %bb.0:1152; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma1153; CHECK-NEXT: vnot.v v8, v81154; CHECK-NEXT: vand.vv v8, v8, v101155; CHECK-NEXT: ret1156;1157; CHECK-ZVKB-LABEL: vandn_vv_nxv4i32:1158; CHECK-ZVKB: # %bb.0:1159; CHECK-ZVKB-NEXT: vsetvli a0, zero, e32, m2, ta, ma1160; CHECK-ZVKB-NEXT: vandn.vv v8, v10, v81161; CHECK-ZVKB-NEXT: ret1162 %a = xor <vscale x 4 x i32> %x, splat (i32 -1)1163 %b = and <vscale x 4 x i32> %a, %y1164 ret <vscale x 4 x i32> %b1165}1166 1167define <vscale x 4 x i32> @vandn_vv_swapped_nxv4i32(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y) {1168; CHECK-LABEL: vandn_vv_swapped_nxv4i32:1169; CHECK: # %bb.0:1170; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma1171; CHECK-NEXT: vnot.v v8, v81172; CHECK-NEXT: vand.vv v8, v10, v81173; CHECK-NEXT: ret1174;1175; CHECK-ZVKB-LABEL: vandn_vv_swapped_nxv4i32:1176; CHECK-ZVKB: # %bb.0:1177; CHECK-ZVKB-NEXT: vsetvli a0, zero, e32, m2, ta, ma1178; CHECK-ZVKB-NEXT: vandn.vv v8, v10, v81179; CHECK-ZVKB-NEXT: ret1180 %a = xor <vscale x 4 x i32> %x, splat (i32 -1)1181 %b = and <vscale x 4 x i32> %y, %a1182 ret <vscale x 4 x i32> %b1183}1184 1185define <vscale x 4 x i32> @vandn_vx_nxv4i32(i32 %x, <vscale x 4 x i32> %y) {1186; CHECK-LABEL: vandn_vx_nxv4i32:1187; CHECK: # %bb.0:1188; CHECK-NEXT: not a0, a01189; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma1190; CHECK-NEXT: vand.vx v8, v8, a01191; CHECK-NEXT: ret1192;1193; CHECK-ZVKB-LABEL: vandn_vx_nxv4i32:1194; CHECK-ZVKB: # %bb.0:1195; CHECK-ZVKB-NEXT: vsetvli a1, zero, e32, m2, ta, ma1196; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a01197; CHECK-ZVKB-NEXT: ret1198 %a = xor i32 %x, -11199 %head = insertelement <vscale x 4 x i32> poison, i32 %a, i32 01200 %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer1201 %b = and <vscale x 4 x i32> %splat, %y1202 ret <vscale x 4 x i32> %b1203}1204 1205define <vscale x 4 x i32> @vandn_vx_swapped_nxv4i32(i32 %x, <vscale x 4 x i32> %y) {1206; CHECK-LABEL: vandn_vx_swapped_nxv4i32:1207; CHECK: # %bb.0:1208; CHECK-NEXT: not a0, a01209; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma1210; CHECK-NEXT: vand.vx v8, v8, a01211; CHECK-NEXT: ret1212;1213; CHECK-ZVKB-LABEL: vandn_vx_swapped_nxv4i32:1214; CHECK-ZVKB: # %bb.0:1215; CHECK-ZVKB-NEXT: vsetvli a1, zero, e32, m2, ta, ma1216; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a01217; CHECK-ZVKB-NEXT: ret1218 %a = xor i32 %x, -11219 %head = insertelement <vscale x 4 x i32> poison, i32 %a, i32 01220 %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer1221 %b = and <vscale x 4 x i32> %splat, %y1222 ret <vscale x 4 x i32> %b1223}1224 1225define <vscale x 8 x i32> @vandn_vv_nxv8i32(<vscale x 8 x i32> %x, <vscale x 8 x i32> %y) {1226; CHECK-LABEL: vandn_vv_nxv8i32:1227; CHECK: # %bb.0:1228; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma1229; CHECK-NEXT: vnot.v v8, v81230; CHECK-NEXT: vand.vv v8, v8, v121231; CHECK-NEXT: ret1232;1233; CHECK-ZVKB-LABEL: vandn_vv_nxv8i32:1234; CHECK-ZVKB: # %bb.0:1235; CHECK-ZVKB-NEXT: vsetvli a0, zero, e32, m4, ta, ma1236; CHECK-ZVKB-NEXT: vandn.vv v8, v12, v81237; CHECK-ZVKB-NEXT: ret1238 %a = xor <vscale x 8 x i32> %x, splat (i32 -1)1239 %b = and <vscale x 8 x i32> %a, %y1240 ret <vscale x 8 x i32> %b1241}1242 1243define <vscale x 8 x i32> @vandn_vv_swapped_nxv8i32(<vscale x 8 x i32> %x, <vscale x 8 x i32> %y) {1244; CHECK-LABEL: vandn_vv_swapped_nxv8i32:1245; CHECK: # %bb.0:1246; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma1247; CHECK-NEXT: vnot.v v8, v81248; CHECK-NEXT: vand.vv v8, v12, v81249; CHECK-NEXT: ret1250;1251; CHECK-ZVKB-LABEL: vandn_vv_swapped_nxv8i32:1252; CHECK-ZVKB: # %bb.0:1253; CHECK-ZVKB-NEXT: vsetvli a0, zero, e32, m4, ta, ma1254; CHECK-ZVKB-NEXT: vandn.vv v8, v12, v81255; CHECK-ZVKB-NEXT: ret1256 %a = xor <vscale x 8 x i32> %x, splat (i32 -1)1257 %b = and <vscale x 8 x i32> %y, %a1258 ret <vscale x 8 x i32> %b1259}1260 1261define <vscale x 8 x i32> @vandn_vx_nxv8i32(i32 %x, <vscale x 8 x i32> %y) {1262; CHECK-LABEL: vandn_vx_nxv8i32:1263; CHECK: # %bb.0:1264; CHECK-NEXT: not a0, a01265; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma1266; CHECK-NEXT: vand.vx v8, v8, a01267; CHECK-NEXT: ret1268;1269; CHECK-ZVKB-LABEL: vandn_vx_nxv8i32:1270; CHECK-ZVKB: # %bb.0:1271; CHECK-ZVKB-NEXT: vsetvli a1, zero, e32, m4, ta, ma1272; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a01273; CHECK-ZVKB-NEXT: ret1274 %a = xor i32 %x, -11275 %head = insertelement <vscale x 8 x i32> poison, i32 %a, i32 01276 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer1277 %b = and <vscale x 8 x i32> %splat, %y1278 ret <vscale x 8 x i32> %b1279}1280 1281define <vscale x 8 x i32> @vandn_vx_swapped_nxv8i32(i32 %x, <vscale x 8 x i32> %y) {1282; CHECK-LABEL: vandn_vx_swapped_nxv8i32:1283; CHECK: # %bb.0:1284; CHECK-NEXT: not a0, a01285; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma1286; CHECK-NEXT: vand.vx v8, v8, a01287; CHECK-NEXT: ret1288;1289; CHECK-ZVKB-LABEL: vandn_vx_swapped_nxv8i32:1290; CHECK-ZVKB: # %bb.0:1291; CHECK-ZVKB-NEXT: vsetvli a1, zero, e32, m4, ta, ma1292; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a01293; CHECK-ZVKB-NEXT: ret1294 %a = xor i32 %x, -11295 %head = insertelement <vscale x 8 x i32> poison, i32 %a, i32 01296 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer1297 %b = and <vscale x 8 x i32> %splat, %y1298 ret <vscale x 8 x i32> %b1299}1300 1301define <vscale x 16 x i32> @vandn_vv_nxv16i32(<vscale x 16 x i32> %x, <vscale x 16 x i32> %y) {1302; CHECK-LABEL: vandn_vv_nxv16i32:1303; CHECK: # %bb.0:1304; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma1305; CHECK-NEXT: vnot.v v8, v81306; CHECK-NEXT: vand.vv v8, v8, v161307; CHECK-NEXT: ret1308;1309; CHECK-ZVKB-LABEL: vandn_vv_nxv16i32:1310; CHECK-ZVKB: # %bb.0:1311; CHECK-ZVKB-NEXT: vsetvli a0, zero, e32, m8, ta, ma1312; CHECK-ZVKB-NEXT: vandn.vv v8, v16, v81313; CHECK-ZVKB-NEXT: ret1314 %a = xor <vscale x 16 x i32> %x, splat (i32 -1)1315 %b = and <vscale x 16 x i32> %a, %y1316 ret <vscale x 16 x i32> %b1317}1318 1319define <vscale x 16 x i32> @vandn_vv_swapped_nxv16i32(<vscale x 16 x i32> %x, <vscale x 16 x i32> %y) {1320; CHECK-LABEL: vandn_vv_swapped_nxv16i32:1321; CHECK: # %bb.0:1322; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma1323; CHECK-NEXT: vnot.v v8, v81324; CHECK-NEXT: vand.vv v8, v16, v81325; CHECK-NEXT: ret1326;1327; CHECK-ZVKB-LABEL: vandn_vv_swapped_nxv16i32:1328; CHECK-ZVKB: # %bb.0:1329; CHECK-ZVKB-NEXT: vsetvli a0, zero, e32, m8, ta, ma1330; CHECK-ZVKB-NEXT: vandn.vv v8, v16, v81331; CHECK-ZVKB-NEXT: ret1332 %a = xor <vscale x 16 x i32> %x, splat (i32 -1)1333 %b = and <vscale x 16 x i32> %y, %a1334 ret <vscale x 16 x i32> %b1335}1336 1337define <vscale x 16 x i32> @vandn_vx_nxv16i32(i32 %x, <vscale x 16 x i32> %y) {1338; CHECK-LABEL: vandn_vx_nxv16i32:1339; CHECK: # %bb.0:1340; CHECK-NEXT: not a0, a01341; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma1342; CHECK-NEXT: vand.vx v8, v8, a01343; CHECK-NEXT: ret1344;1345; CHECK-ZVKB-LABEL: vandn_vx_nxv16i32:1346; CHECK-ZVKB: # %bb.0:1347; CHECK-ZVKB-NEXT: vsetvli a1, zero, e32, m8, ta, ma1348; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a01349; CHECK-ZVKB-NEXT: ret1350 %a = xor i32 %x, -11351 %head = insertelement <vscale x 16 x i32> poison, i32 %a, i32 01352 %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer1353 %b = and <vscale x 16 x i32> %splat, %y1354 ret <vscale x 16 x i32> %b1355}1356 1357define <vscale x 16 x i32> @vandn_vx_swapped_nxv16i32(i32 %x, <vscale x 16 x i32> %y) {1358; CHECK-LABEL: vandn_vx_swapped_nxv16i32:1359; CHECK: # %bb.0:1360; CHECK-NEXT: not a0, a01361; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma1362; CHECK-NEXT: vand.vx v8, v8, a01363; CHECK-NEXT: ret1364;1365; CHECK-ZVKB-LABEL: vandn_vx_swapped_nxv16i32:1366; CHECK-ZVKB: # %bb.0:1367; CHECK-ZVKB-NEXT: vsetvli a1, zero, e32, m8, ta, ma1368; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a01369; CHECK-ZVKB-NEXT: ret1370 %a = xor i32 %x, -11371 %head = insertelement <vscale x 16 x i32> poison, i32 %a, i32 01372 %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer1373 %b = and <vscale x 16 x i32> %splat, %y1374 ret <vscale x 16 x i32> %b1375}1376 1377define <vscale x 1 x i64> @vandn_vv_nxv1i64(<vscale x 1 x i64> %x, <vscale x 1 x i64> %y) {1378; CHECK-LABEL: vandn_vv_nxv1i64:1379; CHECK: # %bb.0:1380; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma1381; CHECK-NEXT: vnot.v v8, v81382; CHECK-NEXT: vand.vv v8, v8, v91383; CHECK-NEXT: ret1384;1385; CHECK-ZVKB-LABEL: vandn_vv_nxv1i64:1386; CHECK-ZVKB: # %bb.0:1387; CHECK-ZVKB-NEXT: vsetvli a0, zero, e64, m1, ta, ma1388; CHECK-ZVKB-NEXT: vandn.vv v8, v9, v81389; CHECK-ZVKB-NEXT: ret1390 %a = xor <vscale x 1 x i64> %x, splat (i64 -1)1391 %b = and <vscale x 1 x i64> %a, %y1392 ret <vscale x 1 x i64> %b1393}1394 1395define <vscale x 1 x i64> @vandn_vv_swapped_nxv1i64(<vscale x 1 x i64> %x, <vscale x 1 x i64> %y) {1396; CHECK-LABEL: vandn_vv_swapped_nxv1i64:1397; CHECK: # %bb.0:1398; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma1399; CHECK-NEXT: vnot.v v8, v81400; CHECK-NEXT: vand.vv v8, v9, v81401; CHECK-NEXT: ret1402;1403; CHECK-ZVKB-LABEL: vandn_vv_swapped_nxv1i64:1404; CHECK-ZVKB: # %bb.0:1405; CHECK-ZVKB-NEXT: vsetvli a0, zero, e64, m1, ta, ma1406; CHECK-ZVKB-NEXT: vandn.vv v8, v9, v81407; CHECK-ZVKB-NEXT: ret1408 %a = xor <vscale x 1 x i64> %x, splat (i64 -1)1409 %b = and <vscale x 1 x i64> %y, %a1410 ret <vscale x 1 x i64> %b1411}1412 1413define <vscale x 1 x i64> @vandn_vx_nxv1i64(i64 %x, <vscale x 1 x i64> %y) {1414; CHECK-RV32-LABEL: vandn_vx_nxv1i64:1415; CHECK-RV32: # %bb.0:1416; CHECK-RV32-NEXT: addi sp, sp, -161417; CHECK-RV32-NEXT: .cfi_def_cfa_offset 161418; CHECK-RV32-NEXT: not a0, a01419; CHECK-RV32-NEXT: not a1, a11420; CHECK-RV32-NEXT: sw a0, 8(sp)1421; CHECK-RV32-NEXT: sw a1, 12(sp)1422; CHECK-RV32-NEXT: addi a0, sp, 81423; CHECK-RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma1424; CHECK-RV32-NEXT: vlse64.v v9, (a0), zero1425; CHECK-RV32-NEXT: vand.vv v8, v9, v81426; CHECK-RV32-NEXT: addi sp, sp, 161427; CHECK-RV32-NEXT: .cfi_def_cfa_offset 01428; CHECK-RV32-NEXT: ret1429;1430; CHECK-RV64-LABEL: vandn_vx_nxv1i64:1431; CHECK-RV64: # %bb.0:1432; CHECK-RV64-NEXT: not a0, a01433; CHECK-RV64-NEXT: vsetvli a1, zero, e64, m1, ta, ma1434; CHECK-RV64-NEXT: vand.vx v8, v8, a01435; CHECK-RV64-NEXT: ret1436;1437; CHECK-ZVKB32-LABEL: vandn_vx_nxv1i64:1438; CHECK-ZVKB32: # %bb.0:1439; CHECK-ZVKB32-NEXT: addi sp, sp, -161440; CHECK-ZVKB32-NEXT: .cfi_def_cfa_offset 161441; CHECK-ZVKB32-NEXT: not a0, a01442; CHECK-ZVKB32-NEXT: not a1, a11443; CHECK-ZVKB32-NEXT: sw a0, 8(sp)1444; CHECK-ZVKB32-NEXT: sw a1, 12(sp)1445; CHECK-ZVKB32-NEXT: addi a0, sp, 81446; CHECK-ZVKB32-NEXT: vsetvli a1, zero, e64, m1, ta, ma1447; CHECK-ZVKB32-NEXT: vlse64.v v9, (a0), zero1448; CHECK-ZVKB32-NEXT: vand.vv v8, v9, v81449; CHECK-ZVKB32-NEXT: addi sp, sp, 161450; CHECK-ZVKB32-NEXT: .cfi_def_cfa_offset 01451; CHECK-ZVKB32-NEXT: ret1452;1453; CHECK-ZVKB64-LABEL: vandn_vx_nxv1i64:1454; CHECK-ZVKB64: # %bb.0:1455; CHECK-ZVKB64-NEXT: vsetvli a1, zero, e64, m1, ta, ma1456; CHECK-ZVKB64-NEXT: vandn.vx v8, v8, a01457; CHECK-ZVKB64-NEXT: ret1458 %a = xor i64 %x, -11459 %head = insertelement <vscale x 1 x i64> poison, i64 %a, i32 01460 %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer1461 %b = and <vscale x 1 x i64> %splat, %y1462 ret <vscale x 1 x i64> %b1463}1464 1465define <vscale x 1 x i64> @vandn_vx_swapped_nxv1i64(i64 %x, <vscale x 1 x i64> %y) {1466; CHECK-RV32-LABEL: vandn_vx_swapped_nxv1i64:1467; CHECK-RV32: # %bb.0:1468; CHECK-RV32-NEXT: addi sp, sp, -161469; CHECK-RV32-NEXT: .cfi_def_cfa_offset 161470; CHECK-RV32-NEXT: not a0, a01471; CHECK-RV32-NEXT: not a1, a11472; CHECK-RV32-NEXT: sw a0, 8(sp)1473; CHECK-RV32-NEXT: sw a1, 12(sp)1474; CHECK-RV32-NEXT: addi a0, sp, 81475; CHECK-RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma1476; CHECK-RV32-NEXT: vlse64.v v9, (a0), zero1477; CHECK-RV32-NEXT: vand.vv v8, v9, v81478; CHECK-RV32-NEXT: addi sp, sp, 161479; CHECK-RV32-NEXT: .cfi_def_cfa_offset 01480; CHECK-RV32-NEXT: ret1481;1482; CHECK-RV64-LABEL: vandn_vx_swapped_nxv1i64:1483; CHECK-RV64: # %bb.0:1484; CHECK-RV64-NEXT: not a0, a01485; CHECK-RV64-NEXT: vsetvli a1, zero, e64, m1, ta, ma1486; CHECK-RV64-NEXT: vand.vx v8, v8, a01487; CHECK-RV64-NEXT: ret1488;1489; CHECK-ZVKB32-LABEL: vandn_vx_swapped_nxv1i64:1490; CHECK-ZVKB32: # %bb.0:1491; CHECK-ZVKB32-NEXT: addi sp, sp, -161492; CHECK-ZVKB32-NEXT: .cfi_def_cfa_offset 161493; CHECK-ZVKB32-NEXT: not a0, a01494; CHECK-ZVKB32-NEXT: not a1, a11495; CHECK-ZVKB32-NEXT: sw a0, 8(sp)1496; CHECK-ZVKB32-NEXT: sw a1, 12(sp)1497; CHECK-ZVKB32-NEXT: addi a0, sp, 81498; CHECK-ZVKB32-NEXT: vsetvli a1, zero, e64, m1, ta, ma1499; CHECK-ZVKB32-NEXT: vlse64.v v9, (a0), zero1500; CHECK-ZVKB32-NEXT: vand.vv v8, v9, v81501; CHECK-ZVKB32-NEXT: addi sp, sp, 161502; CHECK-ZVKB32-NEXT: .cfi_def_cfa_offset 01503; CHECK-ZVKB32-NEXT: ret1504;1505; CHECK-ZVKB64-LABEL: vandn_vx_swapped_nxv1i64:1506; CHECK-ZVKB64: # %bb.0:1507; CHECK-ZVKB64-NEXT: vsetvli a1, zero, e64, m1, ta, ma1508; CHECK-ZVKB64-NEXT: vandn.vx v8, v8, a01509; CHECK-ZVKB64-NEXT: ret1510 %a = xor i64 %x, -11511 %head = insertelement <vscale x 1 x i64> poison, i64 %a, i32 01512 %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer1513 %b = and <vscale x 1 x i64> %splat, %y1514 ret <vscale x 1 x i64> %b1515}1516 1517define <vscale x 2 x i64> @vandn_vv_nxv2i64(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y) {1518; CHECK-LABEL: vandn_vv_nxv2i64:1519; CHECK: # %bb.0:1520; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma1521; CHECK-NEXT: vnot.v v8, v81522; CHECK-NEXT: vand.vv v8, v8, v101523; CHECK-NEXT: ret1524;1525; CHECK-ZVKB-LABEL: vandn_vv_nxv2i64:1526; CHECK-ZVKB: # %bb.0:1527; CHECK-ZVKB-NEXT: vsetvli a0, zero, e64, m2, ta, ma1528; CHECK-ZVKB-NEXT: vandn.vv v8, v10, v81529; CHECK-ZVKB-NEXT: ret1530 %a = xor <vscale x 2 x i64> %x, splat (i64 -1)1531 %b = and <vscale x 2 x i64> %a, %y1532 ret <vscale x 2 x i64> %b1533}1534 1535define <vscale x 2 x i64> @vandn_vv_swapped_nxv2i64(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y) {1536; CHECK-LABEL: vandn_vv_swapped_nxv2i64:1537; CHECK: # %bb.0:1538; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma1539; CHECK-NEXT: vnot.v v8, v81540; CHECK-NEXT: vand.vv v8, v10, v81541; CHECK-NEXT: ret1542;1543; CHECK-ZVKB-LABEL: vandn_vv_swapped_nxv2i64:1544; CHECK-ZVKB: # %bb.0:1545; CHECK-ZVKB-NEXT: vsetvli a0, zero, e64, m2, ta, ma1546; CHECK-ZVKB-NEXT: vandn.vv v8, v10, v81547; CHECK-ZVKB-NEXT: ret1548 %a = xor <vscale x 2 x i64> %x, splat (i64 -1)1549 %b = and <vscale x 2 x i64> %y, %a1550 ret <vscale x 2 x i64> %b1551}1552 1553define <vscale x 2 x i64> @vandn_vx_nxv2i64(i64 %x, <vscale x 2 x i64> %y) {1554; CHECK-RV32-LABEL: vandn_vx_nxv2i64:1555; CHECK-RV32: # %bb.0:1556; CHECK-RV32-NEXT: addi sp, sp, -161557; CHECK-RV32-NEXT: .cfi_def_cfa_offset 161558; CHECK-RV32-NEXT: not a0, a01559; CHECK-RV32-NEXT: not a1, a11560; CHECK-RV32-NEXT: sw a0, 8(sp)1561; CHECK-RV32-NEXT: sw a1, 12(sp)1562; CHECK-RV32-NEXT: addi a0, sp, 81563; CHECK-RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma1564; CHECK-RV32-NEXT: vlse64.v v10, (a0), zero1565; CHECK-RV32-NEXT: vand.vv v8, v10, v81566; CHECK-RV32-NEXT: addi sp, sp, 161567; CHECK-RV32-NEXT: .cfi_def_cfa_offset 01568; CHECK-RV32-NEXT: ret1569;1570; CHECK-RV64-LABEL: vandn_vx_nxv2i64:1571; CHECK-RV64: # %bb.0:1572; CHECK-RV64-NEXT: not a0, a01573; CHECK-RV64-NEXT: vsetvli a1, zero, e64, m2, ta, ma1574; CHECK-RV64-NEXT: vand.vx v8, v8, a01575; CHECK-RV64-NEXT: ret1576;1577; CHECK-ZVKB32-LABEL: vandn_vx_nxv2i64:1578; CHECK-ZVKB32: # %bb.0:1579; CHECK-ZVKB32-NEXT: addi sp, sp, -161580; CHECK-ZVKB32-NEXT: .cfi_def_cfa_offset 161581; CHECK-ZVKB32-NEXT: not a0, a01582; CHECK-ZVKB32-NEXT: not a1, a11583; CHECK-ZVKB32-NEXT: sw a0, 8(sp)1584; CHECK-ZVKB32-NEXT: sw a1, 12(sp)1585; CHECK-ZVKB32-NEXT: addi a0, sp, 81586; CHECK-ZVKB32-NEXT: vsetvli a1, zero, e64, m2, ta, ma1587; CHECK-ZVKB32-NEXT: vlse64.v v10, (a0), zero1588; CHECK-ZVKB32-NEXT: vand.vv v8, v10, v81589; CHECK-ZVKB32-NEXT: addi sp, sp, 161590; CHECK-ZVKB32-NEXT: .cfi_def_cfa_offset 01591; CHECK-ZVKB32-NEXT: ret1592;1593; CHECK-ZVKB64-LABEL: vandn_vx_nxv2i64:1594; CHECK-ZVKB64: # %bb.0:1595; CHECK-ZVKB64-NEXT: vsetvli a1, zero, e64, m2, ta, ma1596; CHECK-ZVKB64-NEXT: vandn.vx v8, v8, a01597; CHECK-ZVKB64-NEXT: ret1598 %a = xor i64 %x, -11599 %head = insertelement <vscale x 2 x i64> poison, i64 %a, i32 01600 %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer1601 %b = and <vscale x 2 x i64> %splat, %y1602 ret <vscale x 2 x i64> %b1603}1604 1605define <vscale x 2 x i64> @vandn_vx_swapped_nxv2i64(i64 %x, <vscale x 2 x i64> %y) {1606; CHECK-RV32-LABEL: vandn_vx_swapped_nxv2i64:1607; CHECK-RV32: # %bb.0:1608; CHECK-RV32-NEXT: addi sp, sp, -161609; CHECK-RV32-NEXT: .cfi_def_cfa_offset 161610; CHECK-RV32-NEXT: not a0, a01611; CHECK-RV32-NEXT: not a1, a11612; CHECK-RV32-NEXT: sw a0, 8(sp)1613; CHECK-RV32-NEXT: sw a1, 12(sp)1614; CHECK-RV32-NEXT: addi a0, sp, 81615; CHECK-RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma1616; CHECK-RV32-NEXT: vlse64.v v10, (a0), zero1617; CHECK-RV32-NEXT: vand.vv v8, v10, v81618; CHECK-RV32-NEXT: addi sp, sp, 161619; CHECK-RV32-NEXT: .cfi_def_cfa_offset 01620; CHECK-RV32-NEXT: ret1621;1622; CHECK-RV64-LABEL: vandn_vx_swapped_nxv2i64:1623; CHECK-RV64: # %bb.0:1624; CHECK-RV64-NEXT: not a0, a01625; CHECK-RV64-NEXT: vsetvli a1, zero, e64, m2, ta, ma1626; CHECK-RV64-NEXT: vand.vx v8, v8, a01627; CHECK-RV64-NEXT: ret1628;1629; CHECK-ZVKB32-LABEL: vandn_vx_swapped_nxv2i64:1630; CHECK-ZVKB32: # %bb.0:1631; CHECK-ZVKB32-NEXT: addi sp, sp, -161632; CHECK-ZVKB32-NEXT: .cfi_def_cfa_offset 161633; CHECK-ZVKB32-NEXT: not a0, a01634; CHECK-ZVKB32-NEXT: not a1, a11635; CHECK-ZVKB32-NEXT: sw a0, 8(sp)1636; CHECK-ZVKB32-NEXT: sw a1, 12(sp)1637; CHECK-ZVKB32-NEXT: addi a0, sp, 81638; CHECK-ZVKB32-NEXT: vsetvli a1, zero, e64, m2, ta, ma1639; CHECK-ZVKB32-NEXT: vlse64.v v10, (a0), zero1640; CHECK-ZVKB32-NEXT: vand.vv v8, v10, v81641; CHECK-ZVKB32-NEXT: addi sp, sp, 161642; CHECK-ZVKB32-NEXT: .cfi_def_cfa_offset 01643; CHECK-ZVKB32-NEXT: ret1644;1645; CHECK-ZVKB64-LABEL: vandn_vx_swapped_nxv2i64:1646; CHECK-ZVKB64: # %bb.0:1647; CHECK-ZVKB64-NEXT: vsetvli a1, zero, e64, m2, ta, ma1648; CHECK-ZVKB64-NEXT: vandn.vx v8, v8, a01649; CHECK-ZVKB64-NEXT: ret1650 %a = xor i64 %x, -11651 %head = insertelement <vscale x 2 x i64> poison, i64 %a, i32 01652 %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer1653 %b = and <vscale x 2 x i64> %splat, %y1654 ret <vscale x 2 x i64> %b1655}1656 1657define <vscale x 4 x i64> @vandn_vv_nxv4i64(<vscale x 4 x i64> %x, <vscale x 4 x i64> %y) {1658; CHECK-LABEL: vandn_vv_nxv4i64:1659; CHECK: # %bb.0:1660; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma1661; CHECK-NEXT: vnot.v v8, v81662; CHECK-NEXT: vand.vv v8, v8, v121663; CHECK-NEXT: ret1664;1665; CHECK-ZVKB-LABEL: vandn_vv_nxv4i64:1666; CHECK-ZVKB: # %bb.0:1667; CHECK-ZVKB-NEXT: vsetvli a0, zero, e64, m4, ta, ma1668; CHECK-ZVKB-NEXT: vandn.vv v8, v12, v81669; CHECK-ZVKB-NEXT: ret1670 %a = xor <vscale x 4 x i64> %x, splat (i64 -1)1671 %b = and <vscale x 4 x i64> %a, %y1672 ret <vscale x 4 x i64> %b1673}1674 1675define <vscale x 4 x i64> @vandn_vv_swapped_nxv4i64(<vscale x 4 x i64> %x, <vscale x 4 x i64> %y) {1676; CHECK-LABEL: vandn_vv_swapped_nxv4i64:1677; CHECK: # %bb.0:1678; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma1679; CHECK-NEXT: vnot.v v8, v81680; CHECK-NEXT: vand.vv v8, v12, v81681; CHECK-NEXT: ret1682;1683; CHECK-ZVKB-LABEL: vandn_vv_swapped_nxv4i64:1684; CHECK-ZVKB: # %bb.0:1685; CHECK-ZVKB-NEXT: vsetvli a0, zero, e64, m4, ta, ma1686; CHECK-ZVKB-NEXT: vandn.vv v8, v12, v81687; CHECK-ZVKB-NEXT: ret1688 %a = xor <vscale x 4 x i64> %x, splat (i64 -1)1689 %b = and <vscale x 4 x i64> %y, %a1690 ret <vscale x 4 x i64> %b1691}1692 1693define <vscale x 4 x i64> @vandn_vx_nxv4i64(i64 %x, <vscale x 4 x i64> %y) {1694; CHECK-RV32-LABEL: vandn_vx_nxv4i64:1695; CHECK-RV32: # %bb.0:1696; CHECK-RV32-NEXT: addi sp, sp, -161697; CHECK-RV32-NEXT: .cfi_def_cfa_offset 161698; CHECK-RV32-NEXT: not a0, a01699; CHECK-RV32-NEXT: not a1, a11700; CHECK-RV32-NEXT: sw a0, 8(sp)1701; CHECK-RV32-NEXT: sw a1, 12(sp)1702; CHECK-RV32-NEXT: addi a0, sp, 81703; CHECK-RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma1704; CHECK-RV32-NEXT: vlse64.v v12, (a0), zero1705; CHECK-RV32-NEXT: vand.vv v8, v12, v81706; CHECK-RV32-NEXT: addi sp, sp, 161707; CHECK-RV32-NEXT: .cfi_def_cfa_offset 01708; CHECK-RV32-NEXT: ret1709;1710; CHECK-RV64-LABEL: vandn_vx_nxv4i64:1711; CHECK-RV64: # %bb.0:1712; CHECK-RV64-NEXT: not a0, a01713; CHECK-RV64-NEXT: vsetvli a1, zero, e64, m4, ta, ma1714; CHECK-RV64-NEXT: vand.vx v8, v8, a01715; CHECK-RV64-NEXT: ret1716;1717; CHECK-ZVKB32-LABEL: vandn_vx_nxv4i64:1718; CHECK-ZVKB32: # %bb.0:1719; CHECK-ZVKB32-NEXT: addi sp, sp, -161720; CHECK-ZVKB32-NEXT: .cfi_def_cfa_offset 161721; CHECK-ZVKB32-NEXT: not a0, a01722; CHECK-ZVKB32-NEXT: not a1, a11723; CHECK-ZVKB32-NEXT: sw a0, 8(sp)1724; CHECK-ZVKB32-NEXT: sw a1, 12(sp)1725; CHECK-ZVKB32-NEXT: addi a0, sp, 81726; CHECK-ZVKB32-NEXT: vsetvli a1, zero, e64, m4, ta, ma1727; CHECK-ZVKB32-NEXT: vlse64.v v12, (a0), zero1728; CHECK-ZVKB32-NEXT: vand.vv v8, v12, v81729; CHECK-ZVKB32-NEXT: addi sp, sp, 161730; CHECK-ZVKB32-NEXT: .cfi_def_cfa_offset 01731; CHECK-ZVKB32-NEXT: ret1732;1733; CHECK-ZVKB64-LABEL: vandn_vx_nxv4i64:1734; CHECK-ZVKB64: # %bb.0:1735; CHECK-ZVKB64-NEXT: vsetvli a1, zero, e64, m4, ta, ma1736; CHECK-ZVKB64-NEXT: vandn.vx v8, v8, a01737; CHECK-ZVKB64-NEXT: ret1738 %a = xor i64 %x, -11739 %head = insertelement <vscale x 4 x i64> poison, i64 %a, i32 01740 %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer1741 %b = and <vscale x 4 x i64> %splat, %y1742 ret <vscale x 4 x i64> %b1743}1744 1745define <vscale x 4 x i64> @vandn_vx_swapped_nxv4i64(i64 %x, <vscale x 4 x i64> %y) {1746; CHECK-RV32-LABEL: vandn_vx_swapped_nxv4i64:1747; CHECK-RV32: # %bb.0:1748; CHECK-RV32-NEXT: addi sp, sp, -161749; CHECK-RV32-NEXT: .cfi_def_cfa_offset 161750; CHECK-RV32-NEXT: not a0, a01751; CHECK-RV32-NEXT: not a1, a11752; CHECK-RV32-NEXT: sw a0, 8(sp)1753; CHECK-RV32-NEXT: sw a1, 12(sp)1754; CHECK-RV32-NEXT: addi a0, sp, 81755; CHECK-RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma1756; CHECK-RV32-NEXT: vlse64.v v12, (a0), zero1757; CHECK-RV32-NEXT: vand.vv v8, v12, v81758; CHECK-RV32-NEXT: addi sp, sp, 161759; CHECK-RV32-NEXT: .cfi_def_cfa_offset 01760; CHECK-RV32-NEXT: ret1761;1762; CHECK-RV64-LABEL: vandn_vx_swapped_nxv4i64:1763; CHECK-RV64: # %bb.0:1764; CHECK-RV64-NEXT: not a0, a01765; CHECK-RV64-NEXT: vsetvli a1, zero, e64, m4, ta, ma1766; CHECK-RV64-NEXT: vand.vx v8, v8, a01767; CHECK-RV64-NEXT: ret1768;1769; CHECK-ZVKB32-LABEL: vandn_vx_swapped_nxv4i64:1770; CHECK-ZVKB32: # %bb.0:1771; CHECK-ZVKB32-NEXT: addi sp, sp, -161772; CHECK-ZVKB32-NEXT: .cfi_def_cfa_offset 161773; CHECK-ZVKB32-NEXT: not a0, a01774; CHECK-ZVKB32-NEXT: not a1, a11775; CHECK-ZVKB32-NEXT: sw a0, 8(sp)1776; CHECK-ZVKB32-NEXT: sw a1, 12(sp)1777; CHECK-ZVKB32-NEXT: addi a0, sp, 81778; CHECK-ZVKB32-NEXT: vsetvli a1, zero, e64, m4, ta, ma1779; CHECK-ZVKB32-NEXT: vlse64.v v12, (a0), zero1780; CHECK-ZVKB32-NEXT: vand.vv v8, v12, v81781; CHECK-ZVKB32-NEXT: addi sp, sp, 161782; CHECK-ZVKB32-NEXT: .cfi_def_cfa_offset 01783; CHECK-ZVKB32-NEXT: ret1784;1785; CHECK-ZVKB64-LABEL: vandn_vx_swapped_nxv4i64:1786; CHECK-ZVKB64: # %bb.0:1787; CHECK-ZVKB64-NEXT: vsetvli a1, zero, e64, m4, ta, ma1788; CHECK-ZVKB64-NEXT: vandn.vx v8, v8, a01789; CHECK-ZVKB64-NEXT: ret1790 %a = xor i64 %x, -11791 %head = insertelement <vscale x 4 x i64> poison, i64 %a, i32 01792 %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer1793 %b = and <vscale x 4 x i64> %splat, %y1794 ret <vscale x 4 x i64> %b1795}1796 1797define <vscale x 8 x i64> @vandn_vv_nxv8i64(<vscale x 8 x i64> %x, <vscale x 8 x i64> %y) {1798; CHECK-LABEL: vandn_vv_nxv8i64:1799; CHECK: # %bb.0:1800; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma1801; CHECK-NEXT: vnot.v v8, v81802; CHECK-NEXT: vand.vv v8, v8, v161803; CHECK-NEXT: ret1804;1805; CHECK-ZVKB-LABEL: vandn_vv_nxv8i64:1806; CHECK-ZVKB: # %bb.0:1807; CHECK-ZVKB-NEXT: vsetvli a0, zero, e64, m8, ta, ma1808; CHECK-ZVKB-NEXT: vandn.vv v8, v16, v81809; CHECK-ZVKB-NEXT: ret1810 %a = xor <vscale x 8 x i64> %x, splat (i64 -1)1811 %b = and <vscale x 8 x i64> %a, %y1812 ret <vscale x 8 x i64> %b1813}1814 1815define <vscale x 8 x i64> @vandn_vv_swapped_nxv8i64(<vscale x 8 x i64> %x, <vscale x 8 x i64> %y) {1816; CHECK-LABEL: vandn_vv_swapped_nxv8i64:1817; CHECK: # %bb.0:1818; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma1819; CHECK-NEXT: vnot.v v8, v81820; CHECK-NEXT: vand.vv v8, v16, v81821; CHECK-NEXT: ret1822;1823; CHECK-ZVKB-LABEL: vandn_vv_swapped_nxv8i64:1824; CHECK-ZVKB: # %bb.0:1825; CHECK-ZVKB-NEXT: vsetvli a0, zero, e64, m8, ta, ma1826; CHECK-ZVKB-NEXT: vandn.vv v8, v16, v81827; CHECK-ZVKB-NEXT: ret1828 %a = xor <vscale x 8 x i64> %x, splat (i64 -1)1829 %b = and <vscale x 8 x i64> %y, %a1830 ret <vscale x 8 x i64> %b1831}1832 1833define <vscale x 8 x i64> @vandn_vx_nxv8i64(i64 %x, <vscale x 8 x i64> %y) {1834; CHECK-RV32-LABEL: vandn_vx_nxv8i64:1835; CHECK-RV32: # %bb.0:1836; CHECK-RV32-NEXT: addi sp, sp, -161837; CHECK-RV32-NEXT: .cfi_def_cfa_offset 161838; CHECK-RV32-NEXT: not a0, a01839; CHECK-RV32-NEXT: not a1, a11840; CHECK-RV32-NEXT: sw a0, 8(sp)1841; CHECK-RV32-NEXT: sw a1, 12(sp)1842; CHECK-RV32-NEXT: addi a0, sp, 81843; CHECK-RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma1844; CHECK-RV32-NEXT: vlse64.v v16, (a0), zero1845; CHECK-RV32-NEXT: vand.vv v8, v16, v81846; CHECK-RV32-NEXT: addi sp, sp, 161847; CHECK-RV32-NEXT: .cfi_def_cfa_offset 01848; CHECK-RV32-NEXT: ret1849;1850; CHECK-RV64-LABEL: vandn_vx_nxv8i64:1851; CHECK-RV64: # %bb.0:1852; CHECK-RV64-NEXT: not a0, a01853; CHECK-RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma1854; CHECK-RV64-NEXT: vand.vx v8, v8, a01855; CHECK-RV64-NEXT: ret1856;1857; CHECK-ZVKB32-LABEL: vandn_vx_nxv8i64:1858; CHECK-ZVKB32: # %bb.0:1859; CHECK-ZVKB32-NEXT: addi sp, sp, -161860; CHECK-ZVKB32-NEXT: .cfi_def_cfa_offset 161861; CHECK-ZVKB32-NEXT: not a0, a01862; CHECK-ZVKB32-NEXT: not a1, a11863; CHECK-ZVKB32-NEXT: sw a0, 8(sp)1864; CHECK-ZVKB32-NEXT: sw a1, 12(sp)1865; CHECK-ZVKB32-NEXT: addi a0, sp, 81866; CHECK-ZVKB32-NEXT: vsetvli a1, zero, e64, m8, ta, ma1867; CHECK-ZVKB32-NEXT: vlse64.v v16, (a0), zero1868; CHECK-ZVKB32-NEXT: vand.vv v8, v16, v81869; CHECK-ZVKB32-NEXT: addi sp, sp, 161870; CHECK-ZVKB32-NEXT: .cfi_def_cfa_offset 01871; CHECK-ZVKB32-NEXT: ret1872;1873; CHECK-ZVKB64-LABEL: vandn_vx_nxv8i64:1874; CHECK-ZVKB64: # %bb.0:1875; CHECK-ZVKB64-NEXT: vsetvli a1, zero, e64, m8, ta, ma1876; CHECK-ZVKB64-NEXT: vandn.vx v8, v8, a01877; CHECK-ZVKB64-NEXT: ret1878 %a = xor i64 %x, -11879 %head = insertelement <vscale x 8 x i64> poison, i64 %a, i32 01880 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer1881 %b = and <vscale x 8 x i64> %splat, %y1882 ret <vscale x 8 x i64> %b1883}1884 1885define <vscale x 8 x i64> @vandn_vx_swapped_nxv8i64(i64 %x, <vscale x 8 x i64> %y) {1886; CHECK-RV32-LABEL: vandn_vx_swapped_nxv8i64:1887; CHECK-RV32: # %bb.0:1888; CHECK-RV32-NEXT: addi sp, sp, -161889; CHECK-RV32-NEXT: .cfi_def_cfa_offset 161890; CHECK-RV32-NEXT: not a0, a01891; CHECK-RV32-NEXT: not a1, a11892; CHECK-RV32-NEXT: sw a0, 8(sp)1893; CHECK-RV32-NEXT: sw a1, 12(sp)1894; CHECK-RV32-NEXT: addi a0, sp, 81895; CHECK-RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma1896; CHECK-RV32-NEXT: vlse64.v v16, (a0), zero1897; CHECK-RV32-NEXT: vand.vv v8, v16, v81898; CHECK-RV32-NEXT: addi sp, sp, 161899; CHECK-RV32-NEXT: .cfi_def_cfa_offset 01900; CHECK-RV32-NEXT: ret1901;1902; CHECK-RV64-LABEL: vandn_vx_swapped_nxv8i64:1903; CHECK-RV64: # %bb.0:1904; CHECK-RV64-NEXT: not a0, a01905; CHECK-RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma1906; CHECK-RV64-NEXT: vand.vx v8, v8, a01907; CHECK-RV64-NEXT: ret1908;1909; CHECK-ZVKB32-LABEL: vandn_vx_swapped_nxv8i64:1910; CHECK-ZVKB32: # %bb.0:1911; CHECK-ZVKB32-NEXT: addi sp, sp, -161912; CHECK-ZVKB32-NEXT: .cfi_def_cfa_offset 161913; CHECK-ZVKB32-NEXT: not a0, a01914; CHECK-ZVKB32-NEXT: not a1, a11915; CHECK-ZVKB32-NEXT: sw a0, 8(sp)1916; CHECK-ZVKB32-NEXT: sw a1, 12(sp)1917; CHECK-ZVKB32-NEXT: addi a0, sp, 81918; CHECK-ZVKB32-NEXT: vsetvli a1, zero, e64, m8, ta, ma1919; CHECK-ZVKB32-NEXT: vlse64.v v16, (a0), zero1920; CHECK-ZVKB32-NEXT: vand.vv v8, v16, v81921; CHECK-ZVKB32-NEXT: addi sp, sp, 161922; CHECK-ZVKB32-NEXT: .cfi_def_cfa_offset 01923; CHECK-ZVKB32-NEXT: ret1924;1925; CHECK-ZVKB64-LABEL: vandn_vx_swapped_nxv8i64:1926; CHECK-ZVKB64: # %bb.0:1927; CHECK-ZVKB64-NEXT: vsetvli a1, zero, e64, m8, ta, ma1928; CHECK-ZVKB64-NEXT: vandn.vx v8, v8, a01929; CHECK-ZVKB64-NEXT: ret1930 %a = xor i64 %x, -11931 %head = insertelement <vscale x 8 x i64> poison, i64 %a, i32 01932 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer1933 %b = and <vscale x 8 x i64> %splat, %y1934 ret <vscale x 8 x i64> %b1935}1936 1937define <vscale x 1 x i16> @vandn_vx_imm16(<vscale x 1 x i16> %x) {1938; CHECK-LABEL: vandn_vx_imm16:1939; CHECK: # %bb.0:1940; CHECK-NEXT: lui a0, 81941; CHECK-NEXT: addi a0, a0, -11942; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma1943; CHECK-NEXT: vand.vx v8, v8, a01944; CHECK-NEXT: ret1945;1946; CHECK-ZVKB-LABEL: vandn_vx_imm16:1947; CHECK-ZVKB: # %bb.0:1948; CHECK-ZVKB-NEXT: lui a0, 10485681949; CHECK-ZVKB-NEXT: vsetvli a1, zero, e16, mf4, ta, ma1950; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a01951; CHECK-ZVKB-NEXT: ret1952 %a = and <vscale x 1 x i16> splat (i16 32767), %x1953 ret <vscale x 1 x i16> %a1954}1955 1956define <vscale x 1 x i16> @vandn_vx_swapped_imm16(<vscale x 1 x i16> %x) {1957; CHECK-LABEL: vandn_vx_swapped_imm16:1958; CHECK: # %bb.0:1959; CHECK-NEXT: lui a0, 81960; CHECK-NEXT: addi a0, a0, -11961; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma1962; CHECK-NEXT: vand.vx v8, v8, a01963; CHECK-NEXT: ret1964;1965; CHECK-ZVKB-LABEL: vandn_vx_swapped_imm16:1966; CHECK-ZVKB: # %bb.0:1967; CHECK-ZVKB-NEXT: lui a0, 10485681968; CHECK-ZVKB-NEXT: vsetvli a1, zero, e16, mf4, ta, ma1969; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a01970; CHECK-ZVKB-NEXT: ret1971 %a = and <vscale x 1 x i16> %x, splat (i16 32767)1972 ret <vscale x 1 x i16> %a1973}1974 1975define <vscale x 1 x i64> @vandn_vx_imm64(<vscale x 1 x i64> %x) {1976; CHECK-RV32-LABEL: vandn_vx_imm64:1977; CHECK-RV32: # %bb.0:1978; CHECK-RV32-NEXT: addi sp, sp, -161979; CHECK-RV32-NEXT: .cfi_def_cfa_offset 161980; CHECK-RV32-NEXT: lui a0, 10444801981; CHECK-RV32-NEXT: li a1, 2551982; CHECK-RV32-NEXT: sw a1, 8(sp)1983; CHECK-RV32-NEXT: sw a0, 12(sp)1984; CHECK-RV32-NEXT: addi a0, sp, 81985; CHECK-RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma1986; CHECK-RV32-NEXT: vlse64.v v9, (a0), zero1987; CHECK-RV32-NEXT: vand.vv v8, v8, v91988; CHECK-RV32-NEXT: addi sp, sp, 161989; CHECK-RV32-NEXT: .cfi_def_cfa_offset 01990; CHECK-RV32-NEXT: ret1991;1992; CHECK-RV64-LABEL: vandn_vx_imm64:1993; CHECK-RV64: # %bb.0:1994; CHECK-RV64-NEXT: li a0, -11995; CHECK-RV64-NEXT: slli a0, a0, 561996; CHECK-RV64-NEXT: addi a0, a0, 2551997; CHECK-RV64-NEXT: vsetvli a1, zero, e64, m1, ta, ma1998; CHECK-RV64-NEXT: vand.vx v8, v8, a01999; CHECK-RV64-NEXT: ret2000;2001; CHECK-ZVKB32-LABEL: vandn_vx_imm64:2002; CHECK-ZVKB32: # %bb.0:2003; CHECK-ZVKB32-NEXT: addi sp, sp, -162004; CHECK-ZVKB32-NEXT: .cfi_def_cfa_offset 162005; CHECK-ZVKB32-NEXT: lui a0, 10444802006; CHECK-ZVKB32-NEXT: li a1, 2552007; CHECK-ZVKB32-NEXT: sw a1, 8(sp)2008; CHECK-ZVKB32-NEXT: sw a0, 12(sp)2009; CHECK-ZVKB32-NEXT: addi a0, sp, 82010; CHECK-ZVKB32-NEXT: vsetvli a1, zero, e64, m1, ta, ma2011; CHECK-ZVKB32-NEXT: vlse64.v v9, (a0), zero2012; CHECK-ZVKB32-NEXT: vand.vv v8, v8, v92013; CHECK-ZVKB32-NEXT: addi sp, sp, 162014; CHECK-ZVKB32-NEXT: .cfi_def_cfa_offset 02015; CHECK-ZVKB32-NEXT: ret2016;2017; CHECK-ZVKB64-LABEL: vandn_vx_imm64:2018; CHECK-ZVKB64: # %bb.0:2019; CHECK-ZVKB64-NEXT: lui a0, 10485602020; CHECK-ZVKB64-NEXT: srli a0, a0, 82021; CHECK-ZVKB64-NEXT: vsetvli a1, zero, e64, m1, ta, ma2022; CHECK-ZVKB64-NEXT: vandn.vx v8, v8, a02023; CHECK-ZVKB64-NEXT: ret2024 %a = and <vscale x 1 x i64> %x, splat (i64 -72057594037927681)2025 ret <vscale x 1 x i64> %a2026}2027 2028define <vscale x 1 x i16> @vandn_vx_multi_imm16(<vscale x 1 x i16> %x, <vscale x 1 x i16> %y) {2029; CHECK-LABEL: vandn_vx_multi_imm16:2030; CHECK: # %bb.0:2031; CHECK-NEXT: lui a0, 42032; CHECK-NEXT: addi a0, a0, -12033; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma2034; CHECK-NEXT: vand.vx v8, v8, a02035; CHECK-NEXT: vand.vx v9, v9, a02036; CHECK-NEXT: vadd.vv v8, v8, v92037; CHECK-NEXT: ret2038;2039; CHECK-ZVKB-LABEL: vandn_vx_multi_imm16:2040; CHECK-ZVKB: # %bb.0:2041; CHECK-ZVKB-NEXT: lui a0, 10485722042; CHECK-ZVKB-NEXT: vsetvli a1, zero, e16, mf4, ta, ma2043; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a02044; CHECK-ZVKB-NEXT: vandn.vx v9, v9, a02045; CHECK-ZVKB-NEXT: vadd.vv v8, v8, v92046; CHECK-ZVKB-NEXT: ret2047 %a = and <vscale x 1 x i16> %x, splat (i16 16383)2048 %b = and <vscale x 1 x i16> %y, splat (i16 16383)2049 %c = add <vscale x 1 x i16> %a, %b2050 ret <vscale x 1 x i16> %c2051}2052 2053define <vscale x 1 x i16> @vandn_vx_multi_scalar_imm16(<vscale x 1 x i16> %x, i16 %y) {2054; CHECK-LABEL: vandn_vx_multi_scalar_imm16:2055; CHECK: # %bb.0:2056; CHECK-NEXT: lui a1, 82057; CHECK-NEXT: addi a1, a1, -12058; CHECK-NEXT: vsetvli a2, zero, e16, mf4, ta, ma2059; CHECK-NEXT: vand.vx v8, v8, a12060; CHECK-NEXT: or a0, a0, a12061; CHECK-NEXT: vadd.vx v8, v8, a02062; CHECK-NEXT: ret2063;2064; CHECK-ZVKB-NOZBB-LABEL: vandn_vx_multi_scalar_imm16:2065; CHECK-ZVKB-NOZBB: # %bb.0:2066; CHECK-ZVKB-NOZBB-NEXT: lui a1, 82067; CHECK-ZVKB-NOZBB-NEXT: addi a1, a1, -12068; CHECK-ZVKB-NOZBB-NEXT: vsetvli a2, zero, e16, mf4, ta, ma2069; CHECK-ZVKB-NOZBB-NEXT: vand.vx v8, v8, a12070; CHECK-ZVKB-NOZBB-NEXT: or a0, a0, a12071; CHECK-ZVKB-NOZBB-NEXT: vadd.vx v8, v8, a02072; CHECK-ZVKB-NOZBB-NEXT: ret2073;2074; CHECK-ZVKB-ZBB-LABEL: vandn_vx_multi_scalar_imm16:2075; CHECK-ZVKB-ZBB: # %bb.0:2076; CHECK-ZVKB-ZBB-NEXT: lui a1, 10485682077; CHECK-ZVKB-ZBB-NEXT: vsetvli a2, zero, e16, mf4, ta, ma2078; CHECK-ZVKB-ZBB-NEXT: vandn.vx v8, v8, a12079; CHECK-ZVKB-ZBB-NEXT: orn a0, a0, a12080; CHECK-ZVKB-ZBB-NEXT: vadd.vx v8, v8, a02081; CHECK-ZVKB-ZBB-NEXT: ret2082 %a = and <vscale x 1 x i16> %x, splat (i16 32767)2083 %b = or i16 %y, 327672084 %head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 02085 %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer2086 %c = add <vscale x 1 x i16> %a, %splat2087 ret <vscale x 1 x i16> %c2088}2089 2090define <vscale x 1 x i16> @vand_vadd_vx_imm16(<vscale x 1 x i16> %x) {2091; CHECK-LABEL: vand_vadd_vx_imm16:2092; CHECK: # %bb.0:2093; CHECK-NEXT: lui a0, 82094; CHECK-NEXT: addi a0, a0, -12095; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma2096; CHECK-NEXT: vand.vx v8, v8, a02097; CHECK-NEXT: vadd.vx v8, v8, a02098; CHECK-NEXT: ret2099;2100; CHECK-ZVKB-LABEL: vand_vadd_vx_imm16:2101; CHECK-ZVKB: # %bb.0:2102; CHECK-ZVKB-NEXT: lui a0, 82103; CHECK-ZVKB-NEXT: addi a0, a0, -12104; CHECK-ZVKB-NEXT: vsetvli a1, zero, e16, mf4, ta, ma2105; CHECK-ZVKB-NEXT: vand.vx v8, v8, a02106; CHECK-ZVKB-NEXT: vadd.vx v8, v8, a02107; CHECK-ZVKB-NEXT: ret2108 %a = and <vscale x 1 x i16> %x, splat (i16 32767)2109 %b = add <vscale x 1 x i16> %a, splat (i16 32767)2110 ret <vscale x 1 x i16> %b2111}2112 2113define <vscale x 1 x i8> @vand_vx_hoisted_not(<vscale x 1 x i8> %x, i8 %m, i1 zeroext %cond) {2114; CHECK-LABEL: vand_vx_hoisted_not:2115; CHECK: # %bb.0:2116; CHECK-NEXT: beqz a1, .LBB94_22117; CHECK-NEXT: # %bb.1: # %mask2118; CHECK-NEXT: not a0, a02119; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma2120; CHECK-NEXT: vand.vx v8, v8, a02121; CHECK-NEXT: .LBB94_2: # %identity2122; CHECK-NEXT: ret2123;2124; CHECK-ZVKB-LABEL: vand_vx_hoisted_not:2125; CHECK-ZVKB: # %bb.0:2126; CHECK-ZVKB-NEXT: beqz a1, .LBB94_22127; CHECK-ZVKB-NEXT: # %bb.1: # %mask2128; CHECK-ZVKB-NEXT: vsetvli a1, zero, e8, mf8, ta, ma2129; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a02130; CHECK-ZVKB-NEXT: .LBB94_2: # %identity2131; CHECK-ZVKB-NEXT: ret2132 %a = xor i8 %m, -12133 %head = insertelement <vscale x 1 x i8> poison, i8 %a, i32 02134 %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer2135 br i1 %cond, label %mask, label %identity2136 2137mask:2138 %masked = and <vscale x 1 x i8> %splat, %x2139 ret <vscale x 1 x i8> %masked2140 2141identity:2142 ret <vscale x 1 x i8> %x2143}2144 2145define <vscale x 1 x i8> @vand_vx_hoisted_not_swapped(<vscale x 1 x i8> %x, i8 %m, i1 zeroext %cond) {2146; CHECK-LABEL: vand_vx_hoisted_not_swapped:2147; CHECK: # %bb.0:2148; CHECK-NEXT: beqz a1, .LBB95_22149; CHECK-NEXT: # %bb.1: # %mask2150; CHECK-NEXT: not a0, a02151; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma2152; CHECK-NEXT: vand.vx v8, v8, a02153; CHECK-NEXT: .LBB95_2: # %identity2154; CHECK-NEXT: ret2155;2156; CHECK-ZVKB-LABEL: vand_vx_hoisted_not_swapped:2157; CHECK-ZVKB: # %bb.0:2158; CHECK-ZVKB-NEXT: beqz a1, .LBB95_22159; CHECK-ZVKB-NEXT: # %bb.1: # %mask2160; CHECK-ZVKB-NEXT: vsetvli a1, zero, e8, mf8, ta, ma2161; CHECK-ZVKB-NEXT: vandn.vx v8, v8, a02162; CHECK-ZVKB-NEXT: .LBB95_2: # %identity2163; CHECK-ZVKB-NEXT: ret2164 %a = xor i8 %m, -12165 %head = insertelement <vscale x 1 x i8> poison, i8 %a, i32 02166 %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer2167 br i1 %cond, label %mask, label %identity2168 2169mask:2170 %masked = and <vscale x 1 x i8> %x, %splat2171 ret <vscale x 1 x i8> %masked2172 2173identity:2174 ret <vscale x 1 x i8> %x2175}2176 2177define <vscale x 1 x i8> @vand_vv_hoisted_not(<vscale x 1 x i8> %x, <vscale x 1 x i8> %m, i1 zeroext %cond) {2178; CHECK-LABEL: vand_vv_hoisted_not:2179; CHECK: # %bb.0:2180; CHECK-NEXT: beqz a0, .LBB96_22181; CHECK-NEXT: # %bb.1: # %mask2182; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma2183; CHECK-NEXT: vnot.v v9, v92184; CHECK-NEXT: vand.vv v8, v9, v82185; CHECK-NEXT: .LBB96_2: # %identity2186; CHECK-NEXT: ret2187;2188; CHECK-ZVKB-LABEL: vand_vv_hoisted_not:2189; CHECK-ZVKB: # %bb.0:2190; CHECK-ZVKB-NEXT: beqz a0, .LBB96_22191; CHECK-ZVKB-NEXT: # %bb.1: # %mask2192; CHECK-ZVKB-NEXT: vsetvli a0, zero, e8, mf8, ta, ma2193; CHECK-ZVKB-NEXT: vandn.vv v8, v8, v92194; CHECK-ZVKB-NEXT: .LBB96_2: # %identity2195; CHECK-ZVKB-NEXT: ret2196 %a = xor <vscale x 1 x i8> %m, splat (i8 -1)2197 br i1 %cond, label %mask, label %identity2198 2199mask:2200 %masked = and <vscale x 1 x i8> %a, %x2201 ret <vscale x 1 x i8> %masked2202 2203identity:2204 ret <vscale x 1 x i8> %x2205}2206 2207define <vscale x 1 x i8> @vand_vv_hoisted_not_swapped(<vscale x 1 x i8> %x, <vscale x 1 x i8> %m, i1 zeroext %cond) {2208; CHECK-LABEL: vand_vv_hoisted_not_swapped:2209; CHECK: # %bb.0:2210; CHECK-NEXT: beqz a0, .LBB97_22211; CHECK-NEXT: # %bb.1: # %mask2212; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma2213; CHECK-NEXT: vnot.v v9, v92214; CHECK-NEXT: vand.vv v8, v8, v92215; CHECK-NEXT: .LBB97_2: # %identity2216; CHECK-NEXT: ret2217;2218; CHECK-ZVKB-LABEL: vand_vv_hoisted_not_swapped:2219; CHECK-ZVKB: # %bb.0:2220; CHECK-ZVKB-NEXT: beqz a0, .LBB97_22221; CHECK-ZVKB-NEXT: # %bb.1: # %mask2222; CHECK-ZVKB-NEXT: vsetvli a0, zero, e8, mf8, ta, ma2223; CHECK-ZVKB-NEXT: vandn.vv v8, v8, v92224; CHECK-ZVKB-NEXT: .LBB97_2: # %identity2225; CHECK-ZVKB-NEXT: ret2226 %a = xor <vscale x 1 x i8> %m, splat (i8 -1)2227 br i1 %cond, label %mask, label %identity2228 2229mask:2230 %masked = and <vscale x 1 x i8> %x, %a2231 ret <vscale x 1 x i8> %masked2232 2233identity:2234 ret <vscale x 1 x i8> %x2235}2236 2237define void @vand_vx_loop_hoisted_not(ptr %a, i32 noundef signext %mask) {2238; CHECK-RV32-LABEL: vand_vx_loop_hoisted_not:2239; CHECK-RV32: # %bb.0: # %entry2240; CHECK-RV32-NEXT: csrr a4, vlenb2241; CHECK-RV32-NEXT: srli a2, a4, 32242; CHECK-RV32-NEXT: li a3, 642243; CHECK-RV32-NEXT: not a1, a12244; CHECK-RV32-NEXT: bgeu a3, a2, .LBB98_22245; CHECK-RV32-NEXT: # %bb.1:2246; CHECK-RV32-NEXT: li a3, 02247; CHECK-RV32-NEXT: li a2, 02248; CHECK-RV32-NEXT: j .LBB98_52249; CHECK-RV32-NEXT: .LBB98_2: # %vector.ph2250; CHECK-RV32-NEXT: li a2, 02251; CHECK-RV32-NEXT: srli a4, a4, 12252; CHECK-RV32-NEXT: neg a3, a42253; CHECK-RV32-NEXT: andi a3, a3, 2562254; CHECK-RV32-NEXT: li a6, 02255; CHECK-RV32-NEXT: li a5, 02256; CHECK-RV32-NEXT: vsetvli a7, zero, e32, m2, ta, ma2257; CHECK-RV32-NEXT: .LBB98_3: # %vector.body2258; CHECK-RV32-NEXT: # =>This Inner Loop Header: Depth=12259; CHECK-RV32-NEXT: slli a7, a6, 22260; CHECK-RV32-NEXT: add t0, a6, a42261; CHECK-RV32-NEXT: add a7, a0, a72262; CHECK-RV32-NEXT: vl2re32.v v8, (a7)2263; CHECK-RV32-NEXT: sltu a6, t0, a62264; CHECK-RV32-NEXT: add a5, a5, a62265; CHECK-RV32-NEXT: xor a6, t0, a32266; CHECK-RV32-NEXT: vand.vx v8, v8, a12267; CHECK-RV32-NEXT: or t1, a6, a52268; CHECK-RV32-NEXT: vs2r.v v8, (a7)2269; CHECK-RV32-NEXT: mv a6, t02270; CHECK-RV32-NEXT: bnez t1, .LBB98_32271; CHECK-RV32-NEXT: # %bb.4: # %middle.block2272; CHECK-RV32-NEXT: bnez a3, .LBB98_62273; CHECK-RV32-NEXT: .LBB98_5: # %for.body2274; CHECK-RV32-NEXT: # =>This Inner Loop Header: Depth=12275; CHECK-RV32-NEXT: slli a4, a3, 22276; CHECK-RV32-NEXT: addi a3, a3, 12277; CHECK-RV32-NEXT: add a4, a0, a42278; CHECK-RV32-NEXT: lw a5, 0(a4)2279; CHECK-RV32-NEXT: seqz a6, a32280; CHECK-RV32-NEXT: add a2, a2, a62281; CHECK-RV32-NEXT: xori a6, a3, 2562282; CHECK-RV32-NEXT: and a5, a5, a12283; CHECK-RV32-NEXT: or a6, a6, a22284; CHECK-RV32-NEXT: sw a5, 0(a4)2285; CHECK-RV32-NEXT: bnez a6, .LBB98_52286; CHECK-RV32-NEXT: .LBB98_6: # %for.cond.cleanup2287; CHECK-RV32-NEXT: ret2288;2289; CHECK-RV64-LABEL: vand_vx_loop_hoisted_not:2290; CHECK-RV64: # %bb.0: # %entry2291; CHECK-RV64-NEXT: csrr a4, vlenb2292; CHECK-RV64-NEXT: srli a2, a4, 32293; CHECK-RV64-NEXT: li a3, 642294; CHECK-RV64-NEXT: not a1, a12295; CHECK-RV64-NEXT: bgeu a3, a2, .LBB98_22296; CHECK-RV64-NEXT: # %bb.1:2297; CHECK-RV64-NEXT: li a2, 02298; CHECK-RV64-NEXT: j .LBB98_52299; CHECK-RV64-NEXT: .LBB98_2: # %vector.ph2300; CHECK-RV64-NEXT: srli a3, a4, 12301; CHECK-RV64-NEXT: neg a2, a32302; CHECK-RV64-NEXT: andi a2, a2, 2562303; CHECK-RV64-NEXT: slli a4, a4, 12304; CHECK-RV64-NEXT: mv a5, a02305; CHECK-RV64-NEXT: mv a6, a22306; CHECK-RV64-NEXT: vsetvli a7, zero, e32, m2, ta, ma2307; CHECK-RV64-NEXT: .LBB98_3: # %vector.body2308; CHECK-RV64-NEXT: # =>This Inner Loop Header: Depth=12309; CHECK-RV64-NEXT: vl2re32.v v8, (a5)2310; CHECK-RV64-NEXT: sub a6, a6, a32311; CHECK-RV64-NEXT: vand.vx v8, v8, a12312; CHECK-RV64-NEXT: vs2r.v v8, (a5)2313; CHECK-RV64-NEXT: add a5, a5, a42314; CHECK-RV64-NEXT: bnez a6, .LBB98_32315; CHECK-RV64-NEXT: # %bb.4: # %middle.block2316; CHECK-RV64-NEXT: bnez a2, .LBB98_72317; CHECK-RV64-NEXT: .LBB98_5: # %for.body.preheader2318; CHECK-RV64-NEXT: slli a2, a2, 22319; CHECK-RV64-NEXT: add a2, a0, a22320; CHECK-RV64-NEXT: addi a0, a0, 10242321; CHECK-RV64-NEXT: .LBB98_6: # %for.body2322; CHECK-RV64-NEXT: # =>This Inner Loop Header: Depth=12323; CHECK-RV64-NEXT: lw a3, 0(a2)2324; CHECK-RV64-NEXT: and a3, a3, a12325; CHECK-RV64-NEXT: sw a3, 0(a2)2326; CHECK-RV64-NEXT: addi a2, a2, 42327; CHECK-RV64-NEXT: bne a2, a0, .LBB98_62328; CHECK-RV64-NEXT: .LBB98_7: # %for.cond.cleanup2329; CHECK-RV64-NEXT: ret2330;2331; CHECK-ZVKB-NOZBB32-LABEL: vand_vx_loop_hoisted_not:2332; CHECK-ZVKB-NOZBB32: # %bb.0: # %entry2333; CHECK-ZVKB-NOZBB32-NEXT: csrr a4, vlenb2334; CHECK-ZVKB-NOZBB32-NEXT: srli a2, a4, 32335; CHECK-ZVKB-NOZBB32-NEXT: li a3, 642336; CHECK-ZVKB-NOZBB32-NEXT: bgeu a3, a2, .LBB98_22337; CHECK-ZVKB-NOZBB32-NEXT: # %bb.1:2338; CHECK-ZVKB-NOZBB32-NEXT: li a3, 02339; CHECK-ZVKB-NOZBB32-NEXT: li a2, 02340; CHECK-ZVKB-NOZBB32-NEXT: j .LBB98_52341; CHECK-ZVKB-NOZBB32-NEXT: .LBB98_2: # %vector.ph2342; CHECK-ZVKB-NOZBB32-NEXT: li a2, 02343; CHECK-ZVKB-NOZBB32-NEXT: srli a4, a4, 12344; CHECK-ZVKB-NOZBB32-NEXT: neg a3, a42345; CHECK-ZVKB-NOZBB32-NEXT: andi a3, a3, 2562346; CHECK-ZVKB-NOZBB32-NEXT: li a6, 02347; CHECK-ZVKB-NOZBB32-NEXT: li a5, 02348; CHECK-ZVKB-NOZBB32-NEXT: vsetvli a7, zero, e32, m2, ta, ma2349; CHECK-ZVKB-NOZBB32-NEXT: .LBB98_3: # %vector.body2350; CHECK-ZVKB-NOZBB32-NEXT: # =>This Inner Loop Header: Depth=12351; CHECK-ZVKB-NOZBB32-NEXT: slli a7, a6, 22352; CHECK-ZVKB-NOZBB32-NEXT: add t0, a6, a42353; CHECK-ZVKB-NOZBB32-NEXT: add a7, a0, a72354; CHECK-ZVKB-NOZBB32-NEXT: vl2re32.v v8, (a7)2355; CHECK-ZVKB-NOZBB32-NEXT: sltu a6, t0, a62356; CHECK-ZVKB-NOZBB32-NEXT: add a5, a5, a62357; CHECK-ZVKB-NOZBB32-NEXT: xor a6, t0, a32358; CHECK-ZVKB-NOZBB32-NEXT: vandn.vx v8, v8, a12359; CHECK-ZVKB-NOZBB32-NEXT: or t1, a6, a52360; CHECK-ZVKB-NOZBB32-NEXT: vs2r.v v8, (a7)2361; CHECK-ZVKB-NOZBB32-NEXT: mv a6, t02362; CHECK-ZVKB-NOZBB32-NEXT: bnez t1, .LBB98_32363; CHECK-ZVKB-NOZBB32-NEXT: # %bb.4: # %middle.block2364; CHECK-ZVKB-NOZBB32-NEXT: bnez a3, .LBB98_72365; CHECK-ZVKB-NOZBB32-NEXT: .LBB98_5: # %for.body.preheader2366; CHECK-ZVKB-NOZBB32-NEXT: not a1, a12367; CHECK-ZVKB-NOZBB32-NEXT: .LBB98_6: # %for.body2368; CHECK-ZVKB-NOZBB32-NEXT: # =>This Inner Loop Header: Depth=12369; CHECK-ZVKB-NOZBB32-NEXT: slli a4, a3, 22370; CHECK-ZVKB-NOZBB32-NEXT: addi a3, a3, 12371; CHECK-ZVKB-NOZBB32-NEXT: add a4, a0, a42372; CHECK-ZVKB-NOZBB32-NEXT: lw a5, 0(a4)2373; CHECK-ZVKB-NOZBB32-NEXT: seqz a6, a32374; CHECK-ZVKB-NOZBB32-NEXT: add a2, a2, a62375; CHECK-ZVKB-NOZBB32-NEXT: xori a6, a3, 2562376; CHECK-ZVKB-NOZBB32-NEXT: and a5, a5, a12377; CHECK-ZVKB-NOZBB32-NEXT: or a6, a6, a22378; CHECK-ZVKB-NOZBB32-NEXT: sw a5, 0(a4)2379; CHECK-ZVKB-NOZBB32-NEXT: bnez a6, .LBB98_62380; CHECK-ZVKB-NOZBB32-NEXT: .LBB98_7: # %for.cond.cleanup2381; CHECK-ZVKB-NOZBB32-NEXT: ret2382;2383; CHECK-ZVKB-NOZBB64-LABEL: vand_vx_loop_hoisted_not:2384; CHECK-ZVKB-NOZBB64: # %bb.0: # %entry2385; CHECK-ZVKB-NOZBB64-NEXT: csrr a4, vlenb2386; CHECK-ZVKB-NOZBB64-NEXT: srli a2, a4, 32387; CHECK-ZVKB-NOZBB64-NEXT: li a3, 642388; CHECK-ZVKB-NOZBB64-NEXT: bgeu a3, a2, .LBB98_22389; CHECK-ZVKB-NOZBB64-NEXT: # %bb.1:2390; CHECK-ZVKB-NOZBB64-NEXT: li a2, 02391; CHECK-ZVKB-NOZBB64-NEXT: j .LBB98_52392; CHECK-ZVKB-NOZBB64-NEXT: .LBB98_2: # %vector.ph2393; CHECK-ZVKB-NOZBB64-NEXT: srli a3, a4, 12394; CHECK-ZVKB-NOZBB64-NEXT: neg a2, a32395; CHECK-ZVKB-NOZBB64-NEXT: andi a2, a2, 2562396; CHECK-ZVKB-NOZBB64-NEXT: slli a4, a4, 12397; CHECK-ZVKB-NOZBB64-NEXT: mv a5, a02398; CHECK-ZVKB-NOZBB64-NEXT: mv a6, a22399; CHECK-ZVKB-NOZBB64-NEXT: vsetvli a7, zero, e32, m2, ta, ma2400; CHECK-ZVKB-NOZBB64-NEXT: .LBB98_3: # %vector.body2401; CHECK-ZVKB-NOZBB64-NEXT: # =>This Inner Loop Header: Depth=12402; CHECK-ZVKB-NOZBB64-NEXT: vl2re32.v v8, (a5)2403; CHECK-ZVKB-NOZBB64-NEXT: sub a6, a6, a32404; CHECK-ZVKB-NOZBB64-NEXT: vandn.vx v8, v8, a12405; CHECK-ZVKB-NOZBB64-NEXT: vs2r.v v8, (a5)2406; CHECK-ZVKB-NOZBB64-NEXT: add a5, a5, a42407; CHECK-ZVKB-NOZBB64-NEXT: bnez a6, .LBB98_32408; CHECK-ZVKB-NOZBB64-NEXT: # %bb.4: # %middle.block2409; CHECK-ZVKB-NOZBB64-NEXT: bnez a2, .LBB98_72410; CHECK-ZVKB-NOZBB64-NEXT: .LBB98_5: # %for.body.preheader2411; CHECK-ZVKB-NOZBB64-NEXT: not a1, a12412; CHECK-ZVKB-NOZBB64-NEXT: slli a2, a2, 22413; CHECK-ZVKB-NOZBB64-NEXT: add a2, a0, a22414; CHECK-ZVKB-NOZBB64-NEXT: addi a0, a0, 10242415; CHECK-ZVKB-NOZBB64-NEXT: .LBB98_6: # %for.body2416; CHECK-ZVKB-NOZBB64-NEXT: # =>This Inner Loop Header: Depth=12417; CHECK-ZVKB-NOZBB64-NEXT: lw a3, 0(a2)2418; CHECK-ZVKB-NOZBB64-NEXT: and a3, a3, a12419; CHECK-ZVKB-NOZBB64-NEXT: sw a3, 0(a2)2420; CHECK-ZVKB-NOZBB64-NEXT: addi a2, a2, 42421; CHECK-ZVKB-NOZBB64-NEXT: bne a2, a0, .LBB98_62422; CHECK-ZVKB-NOZBB64-NEXT: .LBB98_7: # %for.cond.cleanup2423; CHECK-ZVKB-NOZBB64-NEXT: ret2424;2425; CHECK-ZVKB-ZBB32-LABEL: vand_vx_loop_hoisted_not:2426; CHECK-ZVKB-ZBB32: # %bb.0: # %entry2427; CHECK-ZVKB-ZBB32-NEXT: csrr a4, vlenb2428; CHECK-ZVKB-ZBB32-NEXT: srli a2, a4, 32429; CHECK-ZVKB-ZBB32-NEXT: li a3, 642430; CHECK-ZVKB-ZBB32-NEXT: bgeu a3, a2, .LBB98_22431; CHECK-ZVKB-ZBB32-NEXT: # %bb.1:2432; CHECK-ZVKB-ZBB32-NEXT: li a3, 02433; CHECK-ZVKB-ZBB32-NEXT: li a2, 02434; CHECK-ZVKB-ZBB32-NEXT: j .LBB98_52435; CHECK-ZVKB-ZBB32-NEXT: .LBB98_2: # %vector.ph2436; CHECK-ZVKB-ZBB32-NEXT: li a2, 02437; CHECK-ZVKB-ZBB32-NEXT: srli a4, a4, 12438; CHECK-ZVKB-ZBB32-NEXT: neg a3, a42439; CHECK-ZVKB-ZBB32-NEXT: andi a3, a3, 2562440; CHECK-ZVKB-ZBB32-NEXT: li a6, 02441; CHECK-ZVKB-ZBB32-NEXT: li a5, 02442; CHECK-ZVKB-ZBB32-NEXT: vsetvli a7, zero, e32, m2, ta, ma2443; CHECK-ZVKB-ZBB32-NEXT: .LBB98_3: # %vector.body2444; CHECK-ZVKB-ZBB32-NEXT: # =>This Inner Loop Header: Depth=12445; CHECK-ZVKB-ZBB32-NEXT: slli a7, a6, 22446; CHECK-ZVKB-ZBB32-NEXT: add t0, a6, a42447; CHECK-ZVKB-ZBB32-NEXT: add a7, a0, a72448; CHECK-ZVKB-ZBB32-NEXT: vl2re32.v v8, (a7)2449; CHECK-ZVKB-ZBB32-NEXT: sltu a6, t0, a62450; CHECK-ZVKB-ZBB32-NEXT: add a5, a5, a62451; CHECK-ZVKB-ZBB32-NEXT: xor a6, t0, a32452; CHECK-ZVKB-ZBB32-NEXT: vandn.vx v8, v8, a12453; CHECK-ZVKB-ZBB32-NEXT: or t1, a6, a52454; CHECK-ZVKB-ZBB32-NEXT: vs2r.v v8, (a7)2455; CHECK-ZVKB-ZBB32-NEXT: mv a6, t02456; CHECK-ZVKB-ZBB32-NEXT: bnez t1, .LBB98_32457; CHECK-ZVKB-ZBB32-NEXT: # %bb.4: # %middle.block2458; CHECK-ZVKB-ZBB32-NEXT: bnez a3, .LBB98_62459; CHECK-ZVKB-ZBB32-NEXT: .LBB98_5: # %for.body2460; CHECK-ZVKB-ZBB32-NEXT: # =>This Inner Loop Header: Depth=12461; CHECK-ZVKB-ZBB32-NEXT: slli a4, a3, 22462; CHECK-ZVKB-ZBB32-NEXT: addi a3, a3, 12463; CHECK-ZVKB-ZBB32-NEXT: add a4, a0, a42464; CHECK-ZVKB-ZBB32-NEXT: lw a5, 0(a4)2465; CHECK-ZVKB-ZBB32-NEXT: seqz a6, a32466; CHECK-ZVKB-ZBB32-NEXT: add a2, a2, a62467; CHECK-ZVKB-ZBB32-NEXT: xori a6, a3, 2562468; CHECK-ZVKB-ZBB32-NEXT: andn a5, a5, a12469; CHECK-ZVKB-ZBB32-NEXT: or a6, a6, a22470; CHECK-ZVKB-ZBB32-NEXT: sw a5, 0(a4)2471; CHECK-ZVKB-ZBB32-NEXT: bnez a6, .LBB98_52472; CHECK-ZVKB-ZBB32-NEXT: .LBB98_6: # %for.cond.cleanup2473; CHECK-ZVKB-ZBB32-NEXT: ret2474;2475; CHECK-ZVKB-ZBB64-LABEL: vand_vx_loop_hoisted_not:2476; CHECK-ZVKB-ZBB64: # %bb.0: # %entry2477; CHECK-ZVKB-ZBB64-NEXT: csrr a4, vlenb2478; CHECK-ZVKB-ZBB64-NEXT: srli a2, a4, 32479; CHECK-ZVKB-ZBB64-NEXT: li a3, 642480; CHECK-ZVKB-ZBB64-NEXT: bgeu a3, a2, .LBB98_22481; CHECK-ZVKB-ZBB64-NEXT: # %bb.1:2482; CHECK-ZVKB-ZBB64-NEXT: li a2, 02483; CHECK-ZVKB-ZBB64-NEXT: j .LBB98_52484; CHECK-ZVKB-ZBB64-NEXT: .LBB98_2: # %vector.ph2485; CHECK-ZVKB-ZBB64-NEXT: srli a3, a4, 12486; CHECK-ZVKB-ZBB64-NEXT: neg a2, a32487; CHECK-ZVKB-ZBB64-NEXT: andi a2, a2, 2562488; CHECK-ZVKB-ZBB64-NEXT: slli a4, a4, 12489; CHECK-ZVKB-ZBB64-NEXT: mv a5, a02490; CHECK-ZVKB-ZBB64-NEXT: mv a6, a22491; CHECK-ZVKB-ZBB64-NEXT: vsetvli a7, zero, e32, m2, ta, ma2492; CHECK-ZVKB-ZBB64-NEXT: .LBB98_3: # %vector.body2493; CHECK-ZVKB-ZBB64-NEXT: # =>This Inner Loop Header: Depth=12494; CHECK-ZVKB-ZBB64-NEXT: vl2re32.v v8, (a5)2495; CHECK-ZVKB-ZBB64-NEXT: sub a6, a6, a32496; CHECK-ZVKB-ZBB64-NEXT: vandn.vx v8, v8, a12497; CHECK-ZVKB-ZBB64-NEXT: vs2r.v v8, (a5)2498; CHECK-ZVKB-ZBB64-NEXT: add a5, a5, a42499; CHECK-ZVKB-ZBB64-NEXT: bnez a6, .LBB98_32500; CHECK-ZVKB-ZBB64-NEXT: # %bb.4: # %middle.block2501; CHECK-ZVKB-ZBB64-NEXT: bnez a2, .LBB98_72502; CHECK-ZVKB-ZBB64-NEXT: .LBB98_5: # %for.body.preheader2503; CHECK-ZVKB-ZBB64-NEXT: slli a2, a2, 22504; CHECK-ZVKB-ZBB64-NEXT: add a2, a0, a22505; CHECK-ZVKB-ZBB64-NEXT: addi a0, a0, 10242506; CHECK-ZVKB-ZBB64-NEXT: .LBB98_6: # %for.body2507; CHECK-ZVKB-ZBB64-NEXT: # =>This Inner Loop Header: Depth=12508; CHECK-ZVKB-ZBB64-NEXT: lw a3, 0(a2)2509; CHECK-ZVKB-ZBB64-NEXT: andn a3, a3, a12510; CHECK-ZVKB-ZBB64-NEXT: sw a3, 0(a2)2511; CHECK-ZVKB-ZBB64-NEXT: addi a2, a2, 42512; CHECK-ZVKB-ZBB64-NEXT: bne a2, a0, .LBB98_62513; CHECK-ZVKB-ZBB64-NEXT: .LBB98_7: # %for.cond.cleanup2514; CHECK-ZVKB-ZBB64-NEXT: ret2515entry:2516 %not = xor i32 %mask, -12517 %vscale = tail call i64 @llvm.vscale.i64()2518 %min.iters.check = icmp samesign ugt i64 %vscale, 642519 br i1 %min.iters.check, label %for.body.preheader, label %vector.ph2520 2521vector.ph:2522 %1 = tail call i64 @llvm.vscale.i64()2523 %.neg = mul nuw nsw i64 %1, 5082524 %n.vec = and i64 %.neg, 2562525 %2 = tail call i64 @llvm.vscale.i64()2526 %3 = shl nuw nsw i64 %2, 22527 %broadcast.splatinsert = insertelement <vscale x 4 x i32> poison, i32 %not, i64 02528 %broadcast.splat = shufflevector <vscale x 4 x i32> %broadcast.splatinsert, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer2529 br label %vector.body2530 2531vector.body:2532 %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]2533 %4 = getelementptr inbounds nuw i32, ptr %a, i64 %index2534 %wide.load = load <vscale x 4 x i32>, ptr %4, align 42535 %5 = and <vscale x 4 x i32> %wide.load, %broadcast.splat2536 store <vscale x 4 x i32> %5, ptr %4, align 42537 %index.next = add nuw i64 %index, %32538 %6 = icmp eq i64 %index.next, %n.vec2539 br i1 %6, label %middle.block, label %vector.body2540 2541middle.block:2542 %cmp.n.not = icmp eq i64 %n.vec, 02543 br i1 %cmp.n.not, label %for.body.preheader, label %for.cond.cleanup2544 2545for.body.preheader:2546 %indvars.iv.ph = phi i64 [ 0, %entry ], [ %n.vec, %middle.block ]2547 br label %for.body2548 2549for.cond.cleanup:2550 ret void2551 2552for.body:2553 %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ %indvars.iv.ph, %for.body.preheader ]2554 %arrayidx = getelementptr inbounds nuw i32, ptr %a, i64 %indvars.iv2555 %7 = load i32, ptr %arrayidx, align 42556 %and = and i32 %7, %not2557 store i32 %and, ptr %arrayidx, align 42558 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 12559 %exitcond.not = icmp eq i64 %indvars.iv.next, 2562560 br i1 %exitcond.not, label %for.cond.cleanup, label %for.body2561}2562 2563define <vscale x 1 x i8> @not_signbit_mask_nxv1i8(<vscale x 1 x i8> %a, <vscale x 1 x i8> %b) {2564; CHECK-LABEL: not_signbit_mask_nxv1i8:2565; CHECK: # %bb.0:2566; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma2567; CHECK-NEXT: vmsgt.vi v0, v8, -12568; CHECK-NEXT: vmv.v.i v8, 02569; CHECK-NEXT: vmerge.vvm v8, v8, v9, v02570; CHECK-NEXT: ret2571;2572; CHECK-ZVKB-LABEL: not_signbit_mask_nxv1i8:2573; CHECK-ZVKB: # %bb.0:2574; CHECK-ZVKB-NEXT: vsetvli a0, zero, e8, mf8, ta, ma2575; CHECK-ZVKB-NEXT: vsra.vi v8, v8, 72576; CHECK-ZVKB-NEXT: vandn.vv v8, v9, v82577; CHECK-ZVKB-NEXT: ret2578 %cond = icmp sgt <vscale x 1 x i8> %a, splat (i8 -1)2579 %r = select <vscale x 1 x i1> %cond, <vscale x 1 x i8> %b, <vscale x 1 x i8> zeroinitializer2580 ret <vscale x 1 x i8> %r2581}2582