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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \3; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV324; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \5; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV646 7define <vscale x 1 x i8> @intrinsic_vasubu_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {8; CHECK-LABEL: intrinsic_vasubu_vv_nxv1i8_nxv1i8_nxv1i8:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: csrwi vxrm, 011; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma12; CHECK-NEXT: vasubu.vv v8, v8, v913; CHECK-NEXT: ret14entry:15 %a = call <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.nxv1i8(16 <vscale x 1 x i8> poison,17 <vscale x 1 x i8> %0,18 <vscale x 1 x i8> %1,19 iXLen 0, iXLen %2)20 21 ret <vscale x 1 x i8> %a22}23 24define <vscale x 1 x i8> @intrinsic_vasubu_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {25; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv1i8_nxv1i8_nxv1i8:26; CHECK: # %bb.0: # %entry27; CHECK-NEXT: csrwi vxrm, 128; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu29; CHECK-NEXT: vasubu.vv v8, v9, v10, v0.t30; CHECK-NEXT: ret31entry:32 %a = call <vscale x 1 x i8> @llvm.riscv.vasubu.mask.nxv1i8.nxv1i8(33 <vscale x 1 x i8> %0,34 <vscale x 1 x i8> %1,35 <vscale x 1 x i8> %2,36 <vscale x 1 x i1> %3,37 iXLen 1, iXLen %4, iXLen 1)38 39 ret <vscale x 1 x i8> %a40}41 42define <vscale x 2 x i8> @intrinsic_vasubu_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, iXLen %2) nounwind {43; CHECK-LABEL: intrinsic_vasubu_vv_nxv2i8_nxv2i8_nxv2i8:44; CHECK: # %bb.0: # %entry45; CHECK-NEXT: csrwi vxrm, 046; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma47; CHECK-NEXT: vasubu.vv v8, v8, v948; CHECK-NEXT: ret49entry:50 %a = call <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.nxv2i8(51 <vscale x 2 x i8> poison,52 <vscale x 2 x i8> %0,53 <vscale x 2 x i8> %1,54 iXLen 0, iXLen %2)55 56 ret <vscale x 2 x i8> %a57}58 59define <vscale x 2 x i8> @intrinsic_vasubu_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {60; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv2i8_nxv2i8_nxv2i8:61; CHECK: # %bb.0: # %entry62; CHECK-NEXT: csrwi vxrm, 163; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu64; CHECK-NEXT: vasubu.vv v8, v9, v10, v0.t65; CHECK-NEXT: ret66entry:67 %a = call <vscale x 2 x i8> @llvm.riscv.vasubu.mask.nxv2i8.nxv2i8(68 <vscale x 2 x i8> %0,69 <vscale x 2 x i8> %1,70 <vscale x 2 x i8> %2,71 <vscale x 2 x i1> %3,72 iXLen 1, iXLen %4, iXLen 1)73 74 ret <vscale x 2 x i8> %a75}76 77define <vscale x 4 x i8> @intrinsic_vasubu_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, iXLen %2) nounwind {78; CHECK-LABEL: intrinsic_vasubu_vv_nxv4i8_nxv4i8_nxv4i8:79; CHECK: # %bb.0: # %entry80; CHECK-NEXT: csrwi vxrm, 081; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma82; CHECK-NEXT: vasubu.vv v8, v8, v983; CHECK-NEXT: ret84entry:85 %a = call <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.nxv4i8(86 <vscale x 4 x i8> poison,87 <vscale x 4 x i8> %0,88 <vscale x 4 x i8> %1,89 iXLen 0, iXLen %2)90 91 ret <vscale x 4 x i8> %a92}93 94define <vscale x 4 x i8> @intrinsic_vasubu_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {95; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv4i8_nxv4i8_nxv4i8:96; CHECK: # %bb.0: # %entry97; CHECK-NEXT: csrwi vxrm, 198; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu99; CHECK-NEXT: vasubu.vv v8, v9, v10, v0.t100; CHECK-NEXT: ret101entry:102 %a = call <vscale x 4 x i8> @llvm.riscv.vasubu.mask.nxv4i8.nxv4i8(103 <vscale x 4 x i8> %0,104 <vscale x 4 x i8> %1,105 <vscale x 4 x i8> %2,106 <vscale x 4 x i1> %3,107 iXLen 1, iXLen %4, iXLen 1)108 109 ret <vscale x 4 x i8> %a110}111 112define <vscale x 8 x i8> @intrinsic_vasubu_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, iXLen %2) nounwind {113; CHECK-LABEL: intrinsic_vasubu_vv_nxv8i8_nxv8i8_nxv8i8:114; CHECK: # %bb.0: # %entry115; CHECK-NEXT: csrwi vxrm, 0116; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma117; CHECK-NEXT: vasubu.vv v8, v8, v9118; CHECK-NEXT: ret119entry:120 %a = call <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.nxv8i8(121 <vscale x 8 x i8> poison,122 <vscale x 8 x i8> %0,123 <vscale x 8 x i8> %1,124 iXLen 0, iXLen %2)125 126 ret <vscale x 8 x i8> %a127}128 129define <vscale x 8 x i8> @intrinsic_vasubu_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {130; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv8i8_nxv8i8_nxv8i8:131; CHECK: # %bb.0: # %entry132; CHECK-NEXT: csrwi vxrm, 1133; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu134; CHECK-NEXT: vasubu.vv v8, v9, v10, v0.t135; CHECK-NEXT: ret136entry:137 %a = call <vscale x 8 x i8> @llvm.riscv.vasubu.mask.nxv8i8.nxv8i8(138 <vscale x 8 x i8> %0,139 <vscale x 8 x i8> %1,140 <vscale x 8 x i8> %2,141 <vscale x 8 x i1> %3,142 iXLen 1, iXLen %4, iXLen 1)143 144 ret <vscale x 8 x i8> %a145}146 147define <vscale x 16 x i8> @intrinsic_vasubu_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, iXLen %2) nounwind {148; CHECK-LABEL: intrinsic_vasubu_vv_nxv16i8_nxv16i8_nxv16i8:149; CHECK: # %bb.0: # %entry150; CHECK-NEXT: csrwi vxrm, 0151; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma152; CHECK-NEXT: vasubu.vv v8, v8, v10153; CHECK-NEXT: ret154entry:155 %a = call <vscale x 16 x i8> @llvm.riscv.vasubu.nxv16i8.nxv16i8(156 <vscale x 16 x i8> poison,157 <vscale x 16 x i8> %0,158 <vscale x 16 x i8> %1,159 iXLen 0, iXLen %2)160 161 ret <vscale x 16 x i8> %a162}163 164define <vscale x 16 x i8> @intrinsic_vasubu_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {165; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv16i8_nxv16i8_nxv16i8:166; CHECK: # %bb.0: # %entry167; CHECK-NEXT: csrwi vxrm, 1168; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu169; CHECK-NEXT: vasubu.vv v8, v10, v12, v0.t170; CHECK-NEXT: ret171entry:172 %a = call <vscale x 16 x i8> @llvm.riscv.vasubu.mask.nxv16i8.nxv16i8(173 <vscale x 16 x i8> %0,174 <vscale x 16 x i8> %1,175 <vscale x 16 x i8> %2,176 <vscale x 16 x i1> %3,177 iXLen 1, iXLen %4, iXLen 1)178 179 ret <vscale x 16 x i8> %a180}181 182define <vscale x 32 x i8> @intrinsic_vasubu_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, iXLen %2) nounwind {183; CHECK-LABEL: intrinsic_vasubu_vv_nxv32i8_nxv32i8_nxv32i8:184; CHECK: # %bb.0: # %entry185; CHECK-NEXT: csrwi vxrm, 0186; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma187; CHECK-NEXT: vasubu.vv v8, v8, v12188; CHECK-NEXT: ret189entry:190 %a = call <vscale x 32 x i8> @llvm.riscv.vasubu.nxv32i8.nxv32i8(191 <vscale x 32 x i8> poison,192 <vscale x 32 x i8> %0,193 <vscale x 32 x i8> %1,194 iXLen 0, iXLen %2)195 196 ret <vscale x 32 x i8> %a197}198 199define <vscale x 32 x i8> @intrinsic_vasubu_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {200; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv32i8_nxv32i8_nxv32i8:201; CHECK: # %bb.0: # %entry202; CHECK-NEXT: csrwi vxrm, 1203; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu204; CHECK-NEXT: vasubu.vv v8, v12, v16, v0.t205; CHECK-NEXT: ret206entry:207 %a = call <vscale x 32 x i8> @llvm.riscv.vasubu.mask.nxv32i8.nxv32i8(208 <vscale x 32 x i8> %0,209 <vscale x 32 x i8> %1,210 <vscale x 32 x i8> %2,211 <vscale x 32 x i1> %3,212 iXLen 1, iXLen %4, iXLen 1)213 214 ret <vscale x 32 x i8> %a215}216 217define <vscale x 64 x i8> @intrinsic_vasubu_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, iXLen %2) nounwind {218; CHECK-LABEL: intrinsic_vasubu_vv_nxv64i8_nxv64i8_nxv64i8:219; CHECK: # %bb.0: # %entry220; CHECK-NEXT: csrwi vxrm, 0221; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma222; CHECK-NEXT: vasubu.vv v8, v8, v16223; CHECK-NEXT: ret224entry:225 %a = call <vscale x 64 x i8> @llvm.riscv.vasubu.nxv64i8.nxv64i8(226 <vscale x 64 x i8> poison,227 <vscale x 64 x i8> %0,228 <vscale x 64 x i8> %1,229 iXLen 0, iXLen %2)230 231 ret <vscale x 64 x i8> %a232}233 234define <vscale x 64 x i8> @intrinsic_vasubu_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, iXLen %4) nounwind {235; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv64i8_nxv64i8_nxv64i8:236; CHECK: # %bb.0: # %entry237; CHECK-NEXT: vl8r.v v24, (a0)238; CHECK-NEXT: csrwi vxrm, 1239; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu240; CHECK-NEXT: vasubu.vv v8, v16, v24, v0.t241; CHECK-NEXT: ret242entry:243 %a = call <vscale x 64 x i8> @llvm.riscv.vasubu.mask.nxv64i8.nxv64i8(244 <vscale x 64 x i8> %0,245 <vscale x 64 x i8> %1,246 <vscale x 64 x i8> %2,247 <vscale x 64 x i1> %3,248 iXLen 1, iXLen %4, iXLen 1)249 250 ret <vscale x 64 x i8> %a251}252 253define <vscale x 1 x i16> @intrinsic_vasubu_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, iXLen %2) nounwind {254; CHECK-LABEL: intrinsic_vasubu_vv_nxv1i16_nxv1i16_nxv1i16:255; CHECK: # %bb.0: # %entry256; CHECK-NEXT: csrwi vxrm, 0257; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma258; CHECK-NEXT: vasubu.vv v8, v8, v9259; CHECK-NEXT: ret260entry:261 %a = call <vscale x 1 x i16> @llvm.riscv.vasubu.nxv1i16.nxv1i16(262 <vscale x 1 x i16> poison,263 <vscale x 1 x i16> %0,264 <vscale x 1 x i16> %1,265 iXLen 0, iXLen %2)266 267 ret <vscale x 1 x i16> %a268}269 270define <vscale x 1 x i16> @intrinsic_vasubu_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {271; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv1i16_nxv1i16_nxv1i16:272; CHECK: # %bb.0: # %entry273; CHECK-NEXT: csrwi vxrm, 1274; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu275; CHECK-NEXT: vasubu.vv v8, v9, v10, v0.t276; CHECK-NEXT: ret277entry:278 %a = call <vscale x 1 x i16> @llvm.riscv.vasubu.mask.nxv1i16.nxv1i16(279 <vscale x 1 x i16> %0,280 <vscale x 1 x i16> %1,281 <vscale x 1 x i16> %2,282 <vscale x 1 x i1> %3,283 iXLen 1, iXLen %4, iXLen 1)284 285 ret <vscale x 1 x i16> %a286}287 288define <vscale x 2 x i16> @intrinsic_vasubu_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, iXLen %2) nounwind {289; CHECK-LABEL: intrinsic_vasubu_vv_nxv2i16_nxv2i16_nxv2i16:290; CHECK: # %bb.0: # %entry291; CHECK-NEXT: csrwi vxrm, 0292; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma293; CHECK-NEXT: vasubu.vv v8, v8, v9294; CHECK-NEXT: ret295entry:296 %a = call <vscale x 2 x i16> @llvm.riscv.vasubu.nxv2i16.nxv2i16(297 <vscale x 2 x i16> poison,298 <vscale x 2 x i16> %0,299 <vscale x 2 x i16> %1,300 iXLen 0, iXLen %2)301 302 ret <vscale x 2 x i16> %a303}304 305define <vscale x 2 x i16> @intrinsic_vasubu_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {306; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv2i16_nxv2i16_nxv2i16:307; CHECK: # %bb.0: # %entry308; CHECK-NEXT: csrwi vxrm, 1309; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu310; CHECK-NEXT: vasubu.vv v8, v9, v10, v0.t311; CHECK-NEXT: ret312entry:313 %a = call <vscale x 2 x i16> @llvm.riscv.vasubu.mask.nxv2i16.nxv2i16(314 <vscale x 2 x i16> %0,315 <vscale x 2 x i16> %1,316 <vscale x 2 x i16> %2,317 <vscale x 2 x i1> %3,318 iXLen 1, iXLen %4, iXLen 1)319 320 ret <vscale x 2 x i16> %a321}322 323define <vscale x 4 x i16> @intrinsic_vasubu_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, iXLen %2) nounwind {324; CHECK-LABEL: intrinsic_vasubu_vv_nxv4i16_nxv4i16_nxv4i16:325; CHECK: # %bb.0: # %entry326; CHECK-NEXT: csrwi vxrm, 0327; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma328; CHECK-NEXT: vasubu.vv v8, v8, v9329; CHECK-NEXT: ret330entry:331 %a = call <vscale x 4 x i16> @llvm.riscv.vasubu.nxv4i16.nxv4i16(332 <vscale x 4 x i16> poison,333 <vscale x 4 x i16> %0,334 <vscale x 4 x i16> %1,335 iXLen 0, iXLen %2)336 337 ret <vscale x 4 x i16> %a338}339 340define <vscale x 4 x i16> @intrinsic_vasubu_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {341; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv4i16_nxv4i16_nxv4i16:342; CHECK: # %bb.0: # %entry343; CHECK-NEXT: csrwi vxrm, 1344; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu345; CHECK-NEXT: vasubu.vv v8, v9, v10, v0.t346; CHECK-NEXT: ret347entry:348 %a = call <vscale x 4 x i16> @llvm.riscv.vasubu.mask.nxv4i16.nxv4i16(349 <vscale x 4 x i16> %0,350 <vscale x 4 x i16> %1,351 <vscale x 4 x i16> %2,352 <vscale x 4 x i1> %3,353 iXLen 1, iXLen %4, iXLen 1)354 355 ret <vscale x 4 x i16> %a356}357 358define <vscale x 8 x i16> @intrinsic_vasubu_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, iXLen %2) nounwind {359; CHECK-LABEL: intrinsic_vasubu_vv_nxv8i16_nxv8i16_nxv8i16:360; CHECK: # %bb.0: # %entry361; CHECK-NEXT: csrwi vxrm, 0362; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma363; CHECK-NEXT: vasubu.vv v8, v8, v10364; CHECK-NEXT: ret365entry:366 %a = call <vscale x 8 x i16> @llvm.riscv.vasubu.nxv8i16.nxv8i16(367 <vscale x 8 x i16> poison,368 <vscale x 8 x i16> %0,369 <vscale x 8 x i16> %1,370 iXLen 0, iXLen %2)371 372 ret <vscale x 8 x i16> %a373}374 375define <vscale x 8 x i16> @intrinsic_vasubu_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {376; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv8i16_nxv8i16_nxv8i16:377; CHECK: # %bb.0: # %entry378; CHECK-NEXT: csrwi vxrm, 1379; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu380; CHECK-NEXT: vasubu.vv v8, v10, v12, v0.t381; CHECK-NEXT: ret382entry:383 %a = call <vscale x 8 x i16> @llvm.riscv.vasubu.mask.nxv8i16.nxv8i16(384 <vscale x 8 x i16> %0,385 <vscale x 8 x i16> %1,386 <vscale x 8 x i16> %2,387 <vscale x 8 x i1> %3,388 iXLen 1, iXLen %4, iXLen 1)389 390 ret <vscale x 8 x i16> %a391}392 393define <vscale x 16 x i16> @intrinsic_vasubu_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, iXLen %2) nounwind {394; CHECK-LABEL: intrinsic_vasubu_vv_nxv16i16_nxv16i16_nxv16i16:395; CHECK: # %bb.0: # %entry396; CHECK-NEXT: csrwi vxrm, 0397; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma398; CHECK-NEXT: vasubu.vv v8, v8, v12399; CHECK-NEXT: ret400entry:401 %a = call <vscale x 16 x i16> @llvm.riscv.vasubu.nxv16i16.nxv16i16(402 <vscale x 16 x i16> poison,403 <vscale x 16 x i16> %0,404 <vscale x 16 x i16> %1,405 iXLen 0, iXLen %2)406 407 ret <vscale x 16 x i16> %a408}409 410define <vscale x 16 x i16> @intrinsic_vasubu_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {411; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv16i16_nxv16i16_nxv16i16:412; CHECK: # %bb.0: # %entry413; CHECK-NEXT: csrwi vxrm, 1414; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu415; CHECK-NEXT: vasubu.vv v8, v12, v16, v0.t416; CHECK-NEXT: ret417entry:418 %a = call <vscale x 16 x i16> @llvm.riscv.vasubu.mask.nxv16i16.nxv16i16(419 <vscale x 16 x i16> %0,420 <vscale x 16 x i16> %1,421 <vscale x 16 x i16> %2,422 <vscale x 16 x i1> %3,423 iXLen 1, iXLen %4, iXLen 1)424 425 ret <vscale x 16 x i16> %a426}427 428define <vscale x 32 x i16> @intrinsic_vasubu_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, iXLen %2) nounwind {429; CHECK-LABEL: intrinsic_vasubu_vv_nxv32i16_nxv32i16_nxv32i16:430; CHECK: # %bb.0: # %entry431; CHECK-NEXT: csrwi vxrm, 0432; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma433; CHECK-NEXT: vasubu.vv v8, v8, v16434; CHECK-NEXT: ret435entry:436 %a = call <vscale x 32 x i16> @llvm.riscv.vasubu.nxv32i16.nxv32i16(437 <vscale x 32 x i16> poison,438 <vscale x 32 x i16> %0,439 <vscale x 32 x i16> %1,440 iXLen 0, iXLen %2)441 442 ret <vscale x 32 x i16> %a443}444 445define <vscale x 32 x i16> @intrinsic_vasubu_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {446; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv32i16_nxv32i16_nxv32i16:447; CHECK: # %bb.0: # %entry448; CHECK-NEXT: vl8re16.v v24, (a0)449; CHECK-NEXT: csrwi vxrm, 1450; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu451; CHECK-NEXT: vasubu.vv v8, v16, v24, v0.t452; CHECK-NEXT: ret453entry:454 %a = call <vscale x 32 x i16> @llvm.riscv.vasubu.mask.nxv32i16.nxv32i16(455 <vscale x 32 x i16> %0,456 <vscale x 32 x i16> %1,457 <vscale x 32 x i16> %2,458 <vscale x 32 x i1> %3,459 iXLen 1, iXLen %4, iXLen 1)460 461 ret <vscale x 32 x i16> %a462}463 464define <vscale x 1 x i32> @intrinsic_vasubu_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, iXLen %2) nounwind {465; CHECK-LABEL: intrinsic_vasubu_vv_nxv1i32_nxv1i32_nxv1i32:466; CHECK: # %bb.0: # %entry467; CHECK-NEXT: csrwi vxrm, 0468; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma469; CHECK-NEXT: vasubu.vv v8, v8, v9470; CHECK-NEXT: ret471entry:472 %a = call <vscale x 1 x i32> @llvm.riscv.vasubu.nxv1i32.nxv1i32(473 <vscale x 1 x i32> poison,474 <vscale x 1 x i32> %0,475 <vscale x 1 x i32> %1,476 iXLen 0, iXLen %2)477 478 ret <vscale x 1 x i32> %a479}480 481define <vscale x 1 x i32> @intrinsic_vasubu_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {482; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv1i32_nxv1i32_nxv1i32:483; CHECK: # %bb.0: # %entry484; CHECK-NEXT: csrwi vxrm, 1485; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu486; CHECK-NEXT: vasubu.vv v8, v9, v10, v0.t487; CHECK-NEXT: ret488entry:489 %a = call <vscale x 1 x i32> @llvm.riscv.vasubu.mask.nxv1i32.nxv1i32(490 <vscale x 1 x i32> %0,491 <vscale x 1 x i32> %1,492 <vscale x 1 x i32> %2,493 <vscale x 1 x i1> %3,494 iXLen 1, iXLen %4, iXLen 1)495 496 ret <vscale x 1 x i32> %a497}498 499define <vscale x 2 x i32> @intrinsic_vasubu_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, iXLen %2) nounwind {500; CHECK-LABEL: intrinsic_vasubu_vv_nxv2i32_nxv2i32_nxv2i32:501; CHECK: # %bb.0: # %entry502; CHECK-NEXT: csrwi vxrm, 0503; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma504; CHECK-NEXT: vasubu.vv v8, v8, v9505; CHECK-NEXT: ret506entry:507 %a = call <vscale x 2 x i32> @llvm.riscv.vasubu.nxv2i32.nxv2i32(508 <vscale x 2 x i32> poison,509 <vscale x 2 x i32> %0,510 <vscale x 2 x i32> %1,511 iXLen 0, iXLen %2)512 513 ret <vscale x 2 x i32> %a514}515 516define <vscale x 2 x i32> @intrinsic_vasubu_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {517; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv2i32_nxv2i32_nxv2i32:518; CHECK: # %bb.0: # %entry519; CHECK-NEXT: csrwi vxrm, 1520; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu521; CHECK-NEXT: vasubu.vv v8, v9, v10, v0.t522; CHECK-NEXT: ret523entry:524 %a = call <vscale x 2 x i32> @llvm.riscv.vasubu.mask.nxv2i32.nxv2i32(525 <vscale x 2 x i32> %0,526 <vscale x 2 x i32> %1,527 <vscale x 2 x i32> %2,528 <vscale x 2 x i1> %3,529 iXLen 1, iXLen %4, iXLen 1)530 531 ret <vscale x 2 x i32> %a532}533 534define <vscale x 4 x i32> @intrinsic_vasubu_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, iXLen %2) nounwind {535; CHECK-LABEL: intrinsic_vasubu_vv_nxv4i32_nxv4i32_nxv4i32:536; CHECK: # %bb.0: # %entry537; CHECK-NEXT: csrwi vxrm, 0538; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma539; CHECK-NEXT: vasubu.vv v8, v8, v10540; CHECK-NEXT: ret541entry:542 %a = call <vscale x 4 x i32> @llvm.riscv.vasubu.nxv4i32.nxv4i32(543 <vscale x 4 x i32> poison,544 <vscale x 4 x i32> %0,545 <vscale x 4 x i32> %1,546 iXLen 0, iXLen %2)547 548 ret <vscale x 4 x i32> %a549}550 551define <vscale x 4 x i32> @intrinsic_vasubu_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {552; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv4i32_nxv4i32_nxv4i32:553; CHECK: # %bb.0: # %entry554; CHECK-NEXT: csrwi vxrm, 1555; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu556; CHECK-NEXT: vasubu.vv v8, v10, v12, v0.t557; CHECK-NEXT: ret558entry:559 %a = call <vscale x 4 x i32> @llvm.riscv.vasubu.mask.nxv4i32.nxv4i32(560 <vscale x 4 x i32> %0,561 <vscale x 4 x i32> %1,562 <vscale x 4 x i32> %2,563 <vscale x 4 x i1> %3,564 iXLen 1, iXLen %4, iXLen 1)565 566 ret <vscale x 4 x i32> %a567}568 569define <vscale x 8 x i32> @intrinsic_vasubu_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, iXLen %2) nounwind {570; CHECK-LABEL: intrinsic_vasubu_vv_nxv8i32_nxv8i32_nxv8i32:571; CHECK: # %bb.0: # %entry572; CHECK-NEXT: csrwi vxrm, 0573; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma574; CHECK-NEXT: vasubu.vv v8, v8, v12575; CHECK-NEXT: ret576entry:577 %a = call <vscale x 8 x i32> @llvm.riscv.vasubu.nxv8i32.nxv8i32(578 <vscale x 8 x i32> poison,579 <vscale x 8 x i32> %0,580 <vscale x 8 x i32> %1,581 iXLen 0, iXLen %2)582 583 ret <vscale x 8 x i32> %a584}585 586define <vscale x 8 x i32> @intrinsic_vasubu_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {587; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv8i32_nxv8i32_nxv8i32:588; CHECK: # %bb.0: # %entry589; CHECK-NEXT: csrwi vxrm, 1590; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu591; CHECK-NEXT: vasubu.vv v8, v12, v16, v0.t592; CHECK-NEXT: ret593entry:594 %a = call <vscale x 8 x i32> @llvm.riscv.vasubu.mask.nxv8i32.nxv8i32(595 <vscale x 8 x i32> %0,596 <vscale x 8 x i32> %1,597 <vscale x 8 x i32> %2,598 <vscale x 8 x i1> %3,599 iXLen 1, iXLen %4, iXLen 1)600 601 ret <vscale x 8 x i32> %a602}603 604define <vscale x 16 x i32> @intrinsic_vasubu_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, iXLen %2) nounwind {605; CHECK-LABEL: intrinsic_vasubu_vv_nxv16i32_nxv16i32_nxv16i32:606; CHECK: # %bb.0: # %entry607; CHECK-NEXT: csrwi vxrm, 0608; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma609; CHECK-NEXT: vasubu.vv v8, v8, v16610; CHECK-NEXT: ret611entry:612 %a = call <vscale x 16 x i32> @llvm.riscv.vasubu.nxv16i32.nxv16i32(613 <vscale x 16 x i32> poison,614 <vscale x 16 x i32> %0,615 <vscale x 16 x i32> %1,616 iXLen 0, iXLen %2)617 618 ret <vscale x 16 x i32> %a619}620 621define <vscale x 16 x i32> @intrinsic_vasubu_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {622; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv16i32_nxv16i32_nxv16i32:623; CHECK: # %bb.0: # %entry624; CHECK-NEXT: vl8re32.v v24, (a0)625; CHECK-NEXT: csrwi vxrm, 1626; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu627; CHECK-NEXT: vasubu.vv v8, v16, v24, v0.t628; CHECK-NEXT: ret629entry:630 %a = call <vscale x 16 x i32> @llvm.riscv.vasubu.mask.nxv16i32.nxv16i32(631 <vscale x 16 x i32> %0,632 <vscale x 16 x i32> %1,633 <vscale x 16 x i32> %2,634 <vscale x 16 x i1> %3,635 iXLen 1, iXLen %4, iXLen 1)636 637 ret <vscale x 16 x i32> %a638}639 640define <vscale x 1 x i64> @intrinsic_vasubu_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, iXLen %2) nounwind {641; CHECK-LABEL: intrinsic_vasubu_vv_nxv1i64_nxv1i64_nxv1i64:642; CHECK: # %bb.0: # %entry643; CHECK-NEXT: csrwi vxrm, 0644; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma645; CHECK-NEXT: vasubu.vv v8, v8, v9646; CHECK-NEXT: ret647entry:648 %a = call <vscale x 1 x i64> @llvm.riscv.vasubu.nxv1i64.nxv1i64(649 <vscale x 1 x i64> poison,650 <vscale x 1 x i64> %0,651 <vscale x 1 x i64> %1,652 iXLen 0, iXLen %2)653 654 ret <vscale x 1 x i64> %a655}656 657define <vscale x 1 x i64> @intrinsic_vasubu_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {658; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv1i64_nxv1i64_nxv1i64:659; CHECK: # %bb.0: # %entry660; CHECK-NEXT: csrwi vxrm, 1661; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu662; CHECK-NEXT: vasubu.vv v8, v9, v10, v0.t663; CHECK-NEXT: ret664entry:665 %a = call <vscale x 1 x i64> @llvm.riscv.vasubu.mask.nxv1i64.nxv1i64(666 <vscale x 1 x i64> %0,667 <vscale x 1 x i64> %1,668 <vscale x 1 x i64> %2,669 <vscale x 1 x i1> %3,670 iXLen 1, iXLen %4, iXLen 1)671 672 ret <vscale x 1 x i64> %a673}674 675define <vscale x 2 x i64> @intrinsic_vasubu_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, iXLen %2) nounwind {676; CHECK-LABEL: intrinsic_vasubu_vv_nxv2i64_nxv2i64_nxv2i64:677; CHECK: # %bb.0: # %entry678; CHECK-NEXT: csrwi vxrm, 0679; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma680; CHECK-NEXT: vasubu.vv v8, v8, v10681; CHECK-NEXT: ret682entry:683 %a = call <vscale x 2 x i64> @llvm.riscv.vasubu.nxv2i64.nxv2i64(684 <vscale x 2 x i64> poison,685 <vscale x 2 x i64> %0,686 <vscale x 2 x i64> %1,687 iXLen 0, iXLen %2)688 689 ret <vscale x 2 x i64> %a690}691 692define <vscale x 2 x i64> @intrinsic_vasubu_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {693; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv2i64_nxv2i64_nxv2i64:694; CHECK: # %bb.0: # %entry695; CHECK-NEXT: csrwi vxrm, 1696; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu697; CHECK-NEXT: vasubu.vv v8, v10, v12, v0.t698; CHECK-NEXT: ret699entry:700 %a = call <vscale x 2 x i64> @llvm.riscv.vasubu.mask.nxv2i64.nxv2i64(701 <vscale x 2 x i64> %0,702 <vscale x 2 x i64> %1,703 <vscale x 2 x i64> %2,704 <vscale x 2 x i1> %3,705 iXLen 1, iXLen %4, iXLen 1)706 707 ret <vscale x 2 x i64> %a708}709 710define <vscale x 4 x i64> @intrinsic_vasubu_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, iXLen %2) nounwind {711; CHECK-LABEL: intrinsic_vasubu_vv_nxv4i64_nxv4i64_nxv4i64:712; CHECK: # %bb.0: # %entry713; CHECK-NEXT: csrwi vxrm, 0714; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma715; CHECK-NEXT: vasubu.vv v8, v8, v12716; CHECK-NEXT: ret717entry:718 %a = call <vscale x 4 x i64> @llvm.riscv.vasubu.nxv4i64.nxv4i64(719 <vscale x 4 x i64> poison,720 <vscale x 4 x i64> %0,721 <vscale x 4 x i64> %1,722 iXLen 0, iXLen %2)723 724 ret <vscale x 4 x i64> %a725}726 727define <vscale x 4 x i64> @intrinsic_vasubu_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {728; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv4i64_nxv4i64_nxv4i64:729; CHECK: # %bb.0: # %entry730; CHECK-NEXT: csrwi vxrm, 1731; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu732; CHECK-NEXT: vasubu.vv v8, v12, v16, v0.t733; CHECK-NEXT: ret734entry:735 %a = call <vscale x 4 x i64> @llvm.riscv.vasubu.mask.nxv4i64.nxv4i64(736 <vscale x 4 x i64> %0,737 <vscale x 4 x i64> %1,738 <vscale x 4 x i64> %2,739 <vscale x 4 x i1> %3,740 iXLen 1, iXLen %4, iXLen 1)741 742 ret <vscale x 4 x i64> %a743}744 745define <vscale x 8 x i64> @intrinsic_vasubu_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, iXLen %2) nounwind {746; CHECK-LABEL: intrinsic_vasubu_vv_nxv8i64_nxv8i64_nxv8i64:747; CHECK: # %bb.0: # %entry748; CHECK-NEXT: csrwi vxrm, 0749; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma750; CHECK-NEXT: vasubu.vv v8, v8, v16751; CHECK-NEXT: ret752entry:753 %a = call <vscale x 8 x i64> @llvm.riscv.vasubu.nxv8i64.nxv8i64(754 <vscale x 8 x i64> poison,755 <vscale x 8 x i64> %0,756 <vscale x 8 x i64> %1,757 iXLen 0, iXLen %2)758 759 ret <vscale x 8 x i64> %a760}761 762define <vscale x 8 x i64> @intrinsic_vasubu_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {763; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv8i64_nxv8i64_nxv8i64:764; CHECK: # %bb.0: # %entry765; CHECK-NEXT: vl8re64.v v24, (a0)766; CHECK-NEXT: csrwi vxrm, 1767; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu768; CHECK-NEXT: vasubu.vv v8, v16, v24, v0.t769; CHECK-NEXT: ret770entry:771 %a = call <vscale x 8 x i64> @llvm.riscv.vasubu.mask.nxv8i64.nxv8i64(772 <vscale x 8 x i64> %0,773 <vscale x 8 x i64> %1,774 <vscale x 8 x i64> %2,775 <vscale x 8 x i1> %3,776 iXLen 1, iXLen %4, iXLen 1)777 778 ret <vscale x 8 x i64> %a779}780 781define <vscale x 1 x i8> @intrinsic_vasubu_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, iXLen %2) nounwind {782; CHECK-LABEL: intrinsic_vasubu_vx_nxv1i8_nxv1i8_i8:783; CHECK: # %bb.0: # %entry784; CHECK-NEXT: csrwi vxrm, 0785; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma786; CHECK-NEXT: vasubu.vx v8, v8, a0787; CHECK-NEXT: ret788entry:789 %a = call <vscale x 1 x i8> @llvm.riscv.vasubu.nxv1i8.i8(790 <vscale x 1 x i8> poison,791 <vscale x 1 x i8> %0,792 i8 %1,793 iXLen 0, iXLen %2)794 795 ret <vscale x 1 x i8> %a796}797 798define <vscale x 1 x i8> @intrinsic_vasubu_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {799; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv1i8_nxv1i8_i8:800; CHECK: # %bb.0: # %entry801; CHECK-NEXT: csrwi vxrm, 1802; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu803; CHECK-NEXT: vasubu.vx v8, v9, a0, v0.t804; CHECK-NEXT: ret805entry:806 %a = call <vscale x 1 x i8> @llvm.riscv.vasubu.mask.nxv1i8.i8(807 <vscale x 1 x i8> %0,808 <vscale x 1 x i8> %1,809 i8 %2,810 <vscale x 1 x i1> %3,811 iXLen 1, iXLen %4, iXLen 1)812 813 ret <vscale x 1 x i8> %a814}815 816define <vscale x 2 x i8> @intrinsic_vasubu_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, iXLen %2) nounwind {817; CHECK-LABEL: intrinsic_vasubu_vx_nxv2i8_nxv2i8_i8:818; CHECK: # %bb.0: # %entry819; CHECK-NEXT: csrwi vxrm, 0820; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma821; CHECK-NEXT: vasubu.vx v8, v8, a0822; CHECK-NEXT: ret823entry:824 %a = call <vscale x 2 x i8> @llvm.riscv.vasubu.nxv2i8.i8(825 <vscale x 2 x i8> poison,826 <vscale x 2 x i8> %0,827 i8 %1,828 iXLen 0, iXLen %2)829 830 ret <vscale x 2 x i8> %a831}832 833define <vscale x 2 x i8> @intrinsic_vasubu_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {834; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv2i8_nxv2i8_i8:835; CHECK: # %bb.0: # %entry836; CHECK-NEXT: csrwi vxrm, 1837; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu838; CHECK-NEXT: vasubu.vx v8, v9, a0, v0.t839; CHECK-NEXT: ret840entry:841 %a = call <vscale x 2 x i8> @llvm.riscv.vasubu.mask.nxv2i8.i8(842 <vscale x 2 x i8> %0,843 <vscale x 2 x i8> %1,844 i8 %2,845 <vscale x 2 x i1> %3,846 iXLen 1, iXLen %4, iXLen 1)847 848 ret <vscale x 2 x i8> %a849}850 851define <vscale x 4 x i8> @intrinsic_vasubu_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, iXLen %2) nounwind {852; CHECK-LABEL: intrinsic_vasubu_vx_nxv4i8_nxv4i8_i8:853; CHECK: # %bb.0: # %entry854; CHECK-NEXT: csrwi vxrm, 0855; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma856; CHECK-NEXT: vasubu.vx v8, v8, a0857; CHECK-NEXT: ret858entry:859 %a = call <vscale x 4 x i8> @llvm.riscv.vasubu.nxv4i8.i8(860 <vscale x 4 x i8> poison,861 <vscale x 4 x i8> %0,862 i8 %1,863 iXLen 0, iXLen %2)864 865 ret <vscale x 4 x i8> %a866}867 868define <vscale x 4 x i8> @intrinsic_vasubu_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {869; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv4i8_nxv4i8_i8:870; CHECK: # %bb.0: # %entry871; CHECK-NEXT: csrwi vxrm, 1872; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu873; CHECK-NEXT: vasubu.vx v8, v9, a0, v0.t874; CHECK-NEXT: ret875entry:876 %a = call <vscale x 4 x i8> @llvm.riscv.vasubu.mask.nxv4i8.i8(877 <vscale x 4 x i8> %0,878 <vscale x 4 x i8> %1,879 i8 %2,880 <vscale x 4 x i1> %3,881 iXLen 1, iXLen %4, iXLen 1)882 883 ret <vscale x 4 x i8> %a884}885 886define <vscale x 8 x i8> @intrinsic_vasubu_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, iXLen %2) nounwind {887; CHECK-LABEL: intrinsic_vasubu_vx_nxv8i8_nxv8i8_i8:888; CHECK: # %bb.0: # %entry889; CHECK-NEXT: csrwi vxrm, 0890; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma891; CHECK-NEXT: vasubu.vx v8, v8, a0892; CHECK-NEXT: ret893entry:894 %a = call <vscale x 8 x i8> @llvm.riscv.vasubu.nxv8i8.i8(895 <vscale x 8 x i8> poison,896 <vscale x 8 x i8> %0,897 i8 %1,898 iXLen 0, iXLen %2)899 900 ret <vscale x 8 x i8> %a901}902 903define <vscale x 8 x i8> @intrinsic_vasubu_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {904; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv8i8_nxv8i8_i8:905; CHECK: # %bb.0: # %entry906; CHECK-NEXT: csrwi vxrm, 1907; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu908; CHECK-NEXT: vasubu.vx v8, v9, a0, v0.t909; CHECK-NEXT: ret910entry:911 %a = call <vscale x 8 x i8> @llvm.riscv.vasubu.mask.nxv8i8.i8(912 <vscale x 8 x i8> %0,913 <vscale x 8 x i8> %1,914 i8 %2,915 <vscale x 8 x i1> %3,916 iXLen 1, iXLen %4, iXLen 1)917 918 ret <vscale x 8 x i8> %a919}920 921define <vscale x 16 x i8> @intrinsic_vasubu_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, iXLen %2) nounwind {922; CHECK-LABEL: intrinsic_vasubu_vx_nxv16i8_nxv16i8_i8:923; CHECK: # %bb.0: # %entry924; CHECK-NEXT: csrwi vxrm, 0925; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma926; CHECK-NEXT: vasubu.vx v8, v8, a0927; CHECK-NEXT: ret928entry:929 %a = call <vscale x 16 x i8> @llvm.riscv.vasubu.nxv16i8.i8(930 <vscale x 16 x i8> poison,931 <vscale x 16 x i8> %0,932 i8 %1,933 iXLen 0, iXLen %2)934 935 ret <vscale x 16 x i8> %a936}937 938define <vscale x 16 x i8> @intrinsic_vasubu_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {939; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv16i8_nxv16i8_i8:940; CHECK: # %bb.0: # %entry941; CHECK-NEXT: csrwi vxrm, 1942; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu943; CHECK-NEXT: vasubu.vx v8, v10, a0, v0.t944; CHECK-NEXT: ret945entry:946 %a = call <vscale x 16 x i8> @llvm.riscv.vasubu.mask.nxv16i8.i8(947 <vscale x 16 x i8> %0,948 <vscale x 16 x i8> %1,949 i8 %2,950 <vscale x 16 x i1> %3,951 iXLen 1, iXLen %4, iXLen 1)952 953 ret <vscale x 16 x i8> %a954}955 956define <vscale x 32 x i8> @intrinsic_vasubu_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, iXLen %2) nounwind {957; CHECK-LABEL: intrinsic_vasubu_vx_nxv32i8_nxv32i8_i8:958; CHECK: # %bb.0: # %entry959; CHECK-NEXT: csrwi vxrm, 0960; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma961; CHECK-NEXT: vasubu.vx v8, v8, a0962; CHECK-NEXT: ret963entry:964 %a = call <vscale x 32 x i8> @llvm.riscv.vasubu.nxv32i8.i8(965 <vscale x 32 x i8> poison,966 <vscale x 32 x i8> %0,967 i8 %1,968 iXLen 0, iXLen %2)969 970 ret <vscale x 32 x i8> %a971}972 973define <vscale x 32 x i8> @intrinsic_vasubu_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {974; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv32i8_nxv32i8_i8:975; CHECK: # %bb.0: # %entry976; CHECK-NEXT: csrwi vxrm, 1977; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu978; CHECK-NEXT: vasubu.vx v8, v12, a0, v0.t979; CHECK-NEXT: ret980entry:981 %a = call <vscale x 32 x i8> @llvm.riscv.vasubu.mask.nxv32i8.i8(982 <vscale x 32 x i8> %0,983 <vscale x 32 x i8> %1,984 i8 %2,985 <vscale x 32 x i1> %3,986 iXLen 1, iXLen %4, iXLen 1)987 988 ret <vscale x 32 x i8> %a989}990 991define <vscale x 64 x i8> @intrinsic_vasubu_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, iXLen %2) nounwind {992; CHECK-LABEL: intrinsic_vasubu_vx_nxv64i8_nxv64i8_i8:993; CHECK: # %bb.0: # %entry994; CHECK-NEXT: csrwi vxrm, 0995; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma996; CHECK-NEXT: vasubu.vx v8, v8, a0997; CHECK-NEXT: ret998entry:999 %a = call <vscale x 64 x i8> @llvm.riscv.vasubu.nxv64i8.i8(1000 <vscale x 64 x i8> poison,1001 <vscale x 64 x i8> %0,1002 i8 %1,1003 iXLen 0, iXLen %2)1004 1005 ret <vscale x 64 x i8> %a1006}1007 1008define <vscale x 64 x i8> @intrinsic_vasubu_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, iXLen %4) nounwind {1009; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv64i8_nxv64i8_i8:1010; CHECK: # %bb.0: # %entry1011; CHECK-NEXT: csrwi vxrm, 11012; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu1013; CHECK-NEXT: vasubu.vx v8, v16, a0, v0.t1014; CHECK-NEXT: ret1015entry:1016 %a = call <vscale x 64 x i8> @llvm.riscv.vasubu.mask.nxv64i8.i8(1017 <vscale x 64 x i8> %0,1018 <vscale x 64 x i8> %1,1019 i8 %2,1020 <vscale x 64 x i1> %3,1021 iXLen 1, iXLen %4, iXLen 1)1022 1023 ret <vscale x 64 x i8> %a1024}1025 1026define <vscale x 1 x i16> @intrinsic_vasubu_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, iXLen %2) nounwind {1027; CHECK-LABEL: intrinsic_vasubu_vx_nxv1i16_nxv1i16_i16:1028; CHECK: # %bb.0: # %entry1029; CHECK-NEXT: csrwi vxrm, 01030; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma1031; CHECK-NEXT: vasubu.vx v8, v8, a01032; CHECK-NEXT: ret1033entry:1034 %a = call <vscale x 1 x i16> @llvm.riscv.vasubu.nxv1i16.i16(1035 <vscale x 1 x i16> poison,1036 <vscale x 1 x i16> %0,1037 i16 %1,1038 iXLen 0, iXLen %2)1039 1040 ret <vscale x 1 x i16> %a1041}1042 1043define <vscale x 1 x i16> @intrinsic_vasubu_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {1044; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv1i16_nxv1i16_i16:1045; CHECK: # %bb.0: # %entry1046; CHECK-NEXT: csrwi vxrm, 11047; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu1048; CHECK-NEXT: vasubu.vx v8, v9, a0, v0.t1049; CHECK-NEXT: ret1050entry:1051 %a = call <vscale x 1 x i16> @llvm.riscv.vasubu.mask.nxv1i16.i16(1052 <vscale x 1 x i16> %0,1053 <vscale x 1 x i16> %1,1054 i16 %2,1055 <vscale x 1 x i1> %3,1056 iXLen 1, iXLen %4, iXLen 1)1057 1058 ret <vscale x 1 x i16> %a1059}1060 1061define <vscale x 2 x i16> @intrinsic_vasubu_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, iXLen %2) nounwind {1062; CHECK-LABEL: intrinsic_vasubu_vx_nxv2i16_nxv2i16_i16:1063; CHECK: # %bb.0: # %entry1064; CHECK-NEXT: csrwi vxrm, 01065; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma1066; CHECK-NEXT: vasubu.vx v8, v8, a01067; CHECK-NEXT: ret1068entry:1069 %a = call <vscale x 2 x i16> @llvm.riscv.vasubu.nxv2i16.i16(1070 <vscale x 2 x i16> poison,1071 <vscale x 2 x i16> %0,1072 i16 %1,1073 iXLen 0, iXLen %2)1074 1075 ret <vscale x 2 x i16> %a1076}1077 1078define <vscale x 2 x i16> @intrinsic_vasubu_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {1079; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv2i16_nxv2i16_i16:1080; CHECK: # %bb.0: # %entry1081; CHECK-NEXT: csrwi vxrm, 11082; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu1083; CHECK-NEXT: vasubu.vx v8, v9, a0, v0.t1084; CHECK-NEXT: ret1085entry:1086 %a = call <vscale x 2 x i16> @llvm.riscv.vasubu.mask.nxv2i16.i16(1087 <vscale x 2 x i16> %0,1088 <vscale x 2 x i16> %1,1089 i16 %2,1090 <vscale x 2 x i1> %3,1091 iXLen 1, iXLen %4, iXLen 1)1092 1093 ret <vscale x 2 x i16> %a1094}1095 1096define <vscale x 4 x i16> @intrinsic_vasubu_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, iXLen %2) nounwind {1097; CHECK-LABEL: intrinsic_vasubu_vx_nxv4i16_nxv4i16_i16:1098; CHECK: # %bb.0: # %entry1099; CHECK-NEXT: csrwi vxrm, 01100; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma1101; CHECK-NEXT: vasubu.vx v8, v8, a01102; CHECK-NEXT: ret1103entry:1104 %a = call <vscale x 4 x i16> @llvm.riscv.vasubu.nxv4i16.i16(1105 <vscale x 4 x i16> poison,1106 <vscale x 4 x i16> %0,1107 i16 %1,1108 iXLen 0, iXLen %2)1109 1110 ret <vscale x 4 x i16> %a1111}1112 1113define <vscale x 4 x i16> @intrinsic_vasubu_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1114; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv4i16_nxv4i16_i16:1115; CHECK: # %bb.0: # %entry1116; CHECK-NEXT: csrwi vxrm, 11117; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu1118; CHECK-NEXT: vasubu.vx v8, v9, a0, v0.t1119; CHECK-NEXT: ret1120entry:1121 %a = call <vscale x 4 x i16> @llvm.riscv.vasubu.mask.nxv4i16.i16(1122 <vscale x 4 x i16> %0,1123 <vscale x 4 x i16> %1,1124 i16 %2,1125 <vscale x 4 x i1> %3,1126 iXLen 1, iXLen %4, iXLen 1)1127 1128 ret <vscale x 4 x i16> %a1129}1130 1131define <vscale x 8 x i16> @intrinsic_vasubu_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, iXLen %2) nounwind {1132; CHECK-LABEL: intrinsic_vasubu_vx_nxv8i16_nxv8i16_i16:1133; CHECK: # %bb.0: # %entry1134; CHECK-NEXT: csrwi vxrm, 01135; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma1136; CHECK-NEXT: vasubu.vx v8, v8, a01137; CHECK-NEXT: ret1138entry:1139 %a = call <vscale x 8 x i16> @llvm.riscv.vasubu.nxv8i16.i16(1140 <vscale x 8 x i16> poison,1141 <vscale x 8 x i16> %0,1142 i16 %1,1143 iXLen 0, iXLen %2)1144 1145 ret <vscale x 8 x i16> %a1146}1147 1148define <vscale x 8 x i16> @intrinsic_vasubu_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {1149; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv8i16_nxv8i16_i16:1150; CHECK: # %bb.0: # %entry1151; CHECK-NEXT: csrwi vxrm, 11152; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu1153; CHECK-NEXT: vasubu.vx v8, v10, a0, v0.t1154; CHECK-NEXT: ret1155entry:1156 %a = call <vscale x 8 x i16> @llvm.riscv.vasubu.mask.nxv8i16.i16(1157 <vscale x 8 x i16> %0,1158 <vscale x 8 x i16> %1,1159 i16 %2,1160 <vscale x 8 x i1> %3,1161 iXLen 1, iXLen %4, iXLen 1)1162 1163 ret <vscale x 8 x i16> %a1164}1165 1166define <vscale x 16 x i16> @intrinsic_vasubu_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, iXLen %2) nounwind {1167; CHECK-LABEL: intrinsic_vasubu_vx_nxv16i16_nxv16i16_i16:1168; CHECK: # %bb.0: # %entry1169; CHECK-NEXT: csrwi vxrm, 01170; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma1171; CHECK-NEXT: vasubu.vx v8, v8, a01172; CHECK-NEXT: ret1173entry:1174 %a = call <vscale x 16 x i16> @llvm.riscv.vasubu.nxv16i16.i16(1175 <vscale x 16 x i16> poison,1176 <vscale x 16 x i16> %0,1177 i16 %1,1178 iXLen 0, iXLen %2)1179 1180 ret <vscale x 16 x i16> %a1181}1182 1183define <vscale x 16 x i16> @intrinsic_vasubu_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {1184; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv16i16_nxv16i16_i16:1185; CHECK: # %bb.0: # %entry1186; CHECK-NEXT: csrwi vxrm, 11187; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu1188; CHECK-NEXT: vasubu.vx v8, v12, a0, v0.t1189; CHECK-NEXT: ret1190entry:1191 %a = call <vscale x 16 x i16> @llvm.riscv.vasubu.mask.nxv16i16.i16(1192 <vscale x 16 x i16> %0,1193 <vscale x 16 x i16> %1,1194 i16 %2,1195 <vscale x 16 x i1> %3,1196 iXLen 1, iXLen %4, iXLen 1)1197 1198 ret <vscale x 16 x i16> %a1199}1200 1201define <vscale x 32 x i16> @intrinsic_vasubu_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, iXLen %2) nounwind {1202; CHECK-LABEL: intrinsic_vasubu_vx_nxv32i16_nxv32i16_i16:1203; CHECK: # %bb.0: # %entry1204; CHECK-NEXT: csrwi vxrm, 01205; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma1206; CHECK-NEXT: vasubu.vx v8, v8, a01207; CHECK-NEXT: ret1208entry:1209 %a = call <vscale x 32 x i16> @llvm.riscv.vasubu.nxv32i16.i16(1210 <vscale x 32 x i16> poison,1211 <vscale x 32 x i16> %0,1212 i16 %1,1213 iXLen 0, iXLen %2)1214 1215 ret <vscale x 32 x i16> %a1216}1217 1218define <vscale x 32 x i16> @intrinsic_vasubu_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {1219; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv32i16_nxv32i16_i16:1220; CHECK: # %bb.0: # %entry1221; CHECK-NEXT: csrwi vxrm, 11222; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu1223; CHECK-NEXT: vasubu.vx v8, v16, a0, v0.t1224; CHECK-NEXT: ret1225entry:1226 %a = call <vscale x 32 x i16> @llvm.riscv.vasubu.mask.nxv32i16.i16(1227 <vscale x 32 x i16> %0,1228 <vscale x 32 x i16> %1,1229 i16 %2,1230 <vscale x 32 x i1> %3,1231 iXLen 1, iXLen %4, iXLen 1)1232 1233 ret <vscale x 32 x i16> %a1234}1235 1236define <vscale x 1 x i32> @intrinsic_vasubu_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, iXLen %2) nounwind {1237; CHECK-LABEL: intrinsic_vasubu_vx_nxv1i32_nxv1i32_i32:1238; CHECK: # %bb.0: # %entry1239; CHECK-NEXT: csrwi vxrm, 01240; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma1241; CHECK-NEXT: vasubu.vx v8, v8, a01242; CHECK-NEXT: ret1243entry:1244 %a = call <vscale x 1 x i32> @llvm.riscv.vasubu.nxv1i32.i32(1245 <vscale x 1 x i32> poison,1246 <vscale x 1 x i32> %0,1247 i32 %1,1248 iXLen 0, iXLen %2)1249 1250 ret <vscale x 1 x i32> %a1251}1252 1253define <vscale x 1 x i32> @intrinsic_vasubu_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {1254; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv1i32_nxv1i32_i32:1255; CHECK: # %bb.0: # %entry1256; CHECK-NEXT: csrwi vxrm, 11257; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu1258; CHECK-NEXT: vasubu.vx v8, v9, a0, v0.t1259; CHECK-NEXT: ret1260entry:1261 %a = call <vscale x 1 x i32> @llvm.riscv.vasubu.mask.nxv1i32.i32(1262 <vscale x 1 x i32> %0,1263 <vscale x 1 x i32> %1,1264 i32 %2,1265 <vscale x 1 x i1> %3,1266 iXLen 1, iXLen %4, iXLen 1)1267 1268 ret <vscale x 1 x i32> %a1269}1270 1271define <vscale x 2 x i32> @intrinsic_vasubu_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, iXLen %2) nounwind {1272; CHECK-LABEL: intrinsic_vasubu_vx_nxv2i32_nxv2i32_i32:1273; CHECK: # %bb.0: # %entry1274; CHECK-NEXT: csrwi vxrm, 01275; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma1276; CHECK-NEXT: vasubu.vx v8, v8, a01277; CHECK-NEXT: ret1278entry:1279 %a = call <vscale x 2 x i32> @llvm.riscv.vasubu.nxv2i32.i32(1280 <vscale x 2 x i32> poison,1281 <vscale x 2 x i32> %0,1282 i32 %1,1283 iXLen 0, iXLen %2)1284 1285 ret <vscale x 2 x i32> %a1286}1287 1288define <vscale x 2 x i32> @intrinsic_vasubu_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {1289; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv2i32_nxv2i32_i32:1290; CHECK: # %bb.0: # %entry1291; CHECK-NEXT: csrwi vxrm, 11292; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu1293; CHECK-NEXT: vasubu.vx v8, v9, a0, v0.t1294; CHECK-NEXT: ret1295entry:1296 %a = call <vscale x 2 x i32> @llvm.riscv.vasubu.mask.nxv2i32.i32(1297 <vscale x 2 x i32> %0,1298 <vscale x 2 x i32> %1,1299 i32 %2,1300 <vscale x 2 x i1> %3,1301 iXLen 1, iXLen %4, iXLen 1)1302 1303 ret <vscale x 2 x i32> %a1304}1305 1306define <vscale x 4 x i32> @intrinsic_vasubu_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, iXLen %2) nounwind {1307; CHECK-LABEL: intrinsic_vasubu_vx_nxv4i32_nxv4i32_i32:1308; CHECK: # %bb.0: # %entry1309; CHECK-NEXT: csrwi vxrm, 01310; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma1311; CHECK-NEXT: vasubu.vx v8, v8, a01312; CHECK-NEXT: ret1313entry:1314 %a = call <vscale x 4 x i32> @llvm.riscv.vasubu.nxv4i32.i32(1315 <vscale x 4 x i32> poison,1316 <vscale x 4 x i32> %0,1317 i32 %1,1318 iXLen 0, iXLen %2)1319 1320 ret <vscale x 4 x i32> %a1321}1322 1323define <vscale x 4 x i32> @intrinsic_vasubu_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1324; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv4i32_nxv4i32_i32:1325; CHECK: # %bb.0: # %entry1326; CHECK-NEXT: csrwi vxrm, 11327; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu1328; CHECK-NEXT: vasubu.vx v8, v10, a0, v0.t1329; CHECK-NEXT: ret1330entry:1331 %a = call <vscale x 4 x i32> @llvm.riscv.vasubu.mask.nxv4i32.i32(1332 <vscale x 4 x i32> %0,1333 <vscale x 4 x i32> %1,1334 i32 %2,1335 <vscale x 4 x i1> %3,1336 iXLen 1, iXLen %4, iXLen 1)1337 1338 ret <vscale x 4 x i32> %a1339}1340 1341define <vscale x 8 x i32> @intrinsic_vasubu_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, iXLen %2) nounwind {1342; CHECK-LABEL: intrinsic_vasubu_vx_nxv8i32_nxv8i32_i32:1343; CHECK: # %bb.0: # %entry1344; CHECK-NEXT: csrwi vxrm, 01345; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma1346; CHECK-NEXT: vasubu.vx v8, v8, a01347; CHECK-NEXT: ret1348entry:1349 %a = call <vscale x 8 x i32> @llvm.riscv.vasubu.nxv8i32.i32(1350 <vscale x 8 x i32> poison,1351 <vscale x 8 x i32> %0,1352 i32 %1,1353 iXLen 0, iXLen %2)1354 1355 ret <vscale x 8 x i32> %a1356}1357 1358define <vscale x 8 x i32> @intrinsic_vasubu_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {1359; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv8i32_nxv8i32_i32:1360; CHECK: # %bb.0: # %entry1361; CHECK-NEXT: csrwi vxrm, 11362; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu1363; CHECK-NEXT: vasubu.vx v8, v12, a0, v0.t1364; CHECK-NEXT: ret1365entry:1366 %a = call <vscale x 8 x i32> @llvm.riscv.vasubu.mask.nxv8i32.i32(1367 <vscale x 8 x i32> %0,1368 <vscale x 8 x i32> %1,1369 i32 %2,1370 <vscale x 8 x i1> %3,1371 iXLen 1, iXLen %4, iXLen 1)1372 1373 ret <vscale x 8 x i32> %a1374}1375 1376define <vscale x 16 x i32> @intrinsic_vasubu_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, iXLen %2) nounwind {1377; CHECK-LABEL: intrinsic_vasubu_vx_nxv16i32_nxv16i32_i32:1378; CHECK: # %bb.0: # %entry1379; CHECK-NEXT: csrwi vxrm, 01380; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma1381; CHECK-NEXT: vasubu.vx v8, v8, a01382; CHECK-NEXT: ret1383entry:1384 %a = call <vscale x 16 x i32> @llvm.riscv.vasubu.nxv16i32.i32(1385 <vscale x 16 x i32> poison,1386 <vscale x 16 x i32> %0,1387 i32 %1,1388 iXLen 0, iXLen %2)1389 1390 ret <vscale x 16 x i32> %a1391}1392 1393define <vscale x 16 x i32> @intrinsic_vasubu_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {1394; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv16i32_nxv16i32_i32:1395; CHECK: # %bb.0: # %entry1396; CHECK-NEXT: csrwi vxrm, 11397; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu1398; CHECK-NEXT: vasubu.vx v8, v16, a0, v0.t1399; CHECK-NEXT: ret1400entry:1401 %a = call <vscale x 16 x i32> @llvm.riscv.vasubu.mask.nxv16i32.i32(1402 <vscale x 16 x i32> %0,1403 <vscale x 16 x i32> %1,1404 i32 %2,1405 <vscale x 16 x i1> %3,1406 iXLen 1, iXLen %4, iXLen 1)1407 1408 ret <vscale x 16 x i32> %a1409}1410 1411define <vscale x 1 x i64> @intrinsic_vasubu_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, iXLen %2) nounwind {1412; RV32-LABEL: intrinsic_vasubu_vx_nxv1i64_nxv1i64_i64:1413; RV32: # %bb.0: # %entry1414; RV32-NEXT: addi sp, sp, -161415; RV32-NEXT: sw a0, 8(sp)1416; RV32-NEXT: sw a1, 12(sp)1417; RV32-NEXT: addi a0, sp, 81418; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma1419; RV32-NEXT: vlse64.v v9, (a0), zero1420; RV32-NEXT: csrwi vxrm, 01421; RV32-NEXT: vasubu.vv v8, v8, v91422; RV32-NEXT: addi sp, sp, 161423; RV32-NEXT: ret1424;1425; RV64-LABEL: intrinsic_vasubu_vx_nxv1i64_nxv1i64_i64:1426; RV64: # %bb.0: # %entry1427; RV64-NEXT: csrwi vxrm, 01428; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma1429; RV64-NEXT: vasubu.vx v8, v8, a01430; RV64-NEXT: ret1431entry:1432 %a = call <vscale x 1 x i64> @llvm.riscv.vasubu.nxv1i64.i64(1433 <vscale x 1 x i64> poison,1434 <vscale x 1 x i64> %0,1435 i64 %1,1436 iXLen 0, iXLen %2)1437 1438 ret <vscale x 1 x i64> %a1439}1440 1441define <vscale x 1 x i64> @intrinsic_vasubu_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {1442; RV32-LABEL: intrinsic_vasubu_mask_vx_nxv1i64_nxv1i64_i64:1443; RV32: # %bb.0: # %entry1444; RV32-NEXT: addi sp, sp, -161445; RV32-NEXT: sw a0, 8(sp)1446; RV32-NEXT: sw a1, 12(sp)1447; RV32-NEXT: addi a0, sp, 81448; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu1449; RV32-NEXT: vlse64.v v10, (a0), zero1450; RV32-NEXT: csrwi vxrm, 11451; RV32-NEXT: vasubu.vv v8, v9, v10, v0.t1452; RV32-NEXT: addi sp, sp, 161453; RV32-NEXT: ret1454;1455; RV64-LABEL: intrinsic_vasubu_mask_vx_nxv1i64_nxv1i64_i64:1456; RV64: # %bb.0: # %entry1457; RV64-NEXT: csrwi vxrm, 11458; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu1459; RV64-NEXT: vasubu.vx v8, v9, a0, v0.t1460; RV64-NEXT: ret1461entry:1462 %a = call <vscale x 1 x i64> @llvm.riscv.vasubu.mask.nxv1i64.i64(1463 <vscale x 1 x i64> %0,1464 <vscale x 1 x i64> %1,1465 i64 %2,1466 <vscale x 1 x i1> %3,1467 iXLen 1, iXLen %4, iXLen 1)1468 1469 ret <vscale x 1 x i64> %a1470}1471 1472define <vscale x 2 x i64> @intrinsic_vasubu_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, iXLen %2) nounwind {1473; RV32-LABEL: intrinsic_vasubu_vx_nxv2i64_nxv2i64_i64:1474; RV32: # %bb.0: # %entry1475; RV32-NEXT: addi sp, sp, -161476; RV32-NEXT: sw a0, 8(sp)1477; RV32-NEXT: sw a1, 12(sp)1478; RV32-NEXT: addi a0, sp, 81479; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma1480; RV32-NEXT: vlse64.v v10, (a0), zero1481; RV32-NEXT: csrwi vxrm, 01482; RV32-NEXT: vasubu.vv v8, v8, v101483; RV32-NEXT: addi sp, sp, 161484; RV32-NEXT: ret1485;1486; RV64-LABEL: intrinsic_vasubu_vx_nxv2i64_nxv2i64_i64:1487; RV64: # %bb.0: # %entry1488; RV64-NEXT: csrwi vxrm, 01489; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma1490; RV64-NEXT: vasubu.vx v8, v8, a01491; RV64-NEXT: ret1492entry:1493 %a = call <vscale x 2 x i64> @llvm.riscv.vasubu.nxv2i64.i64(1494 <vscale x 2 x i64> poison,1495 <vscale x 2 x i64> %0,1496 i64 %1,1497 iXLen 0, iXLen %2)1498 1499 ret <vscale x 2 x i64> %a1500}1501 1502define <vscale x 2 x i64> @intrinsic_vasubu_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {1503; RV32-LABEL: intrinsic_vasubu_mask_vx_nxv2i64_nxv2i64_i64:1504; RV32: # %bb.0: # %entry1505; RV32-NEXT: addi sp, sp, -161506; RV32-NEXT: sw a0, 8(sp)1507; RV32-NEXT: sw a1, 12(sp)1508; RV32-NEXT: addi a0, sp, 81509; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu1510; RV32-NEXT: vlse64.v v12, (a0), zero1511; RV32-NEXT: csrwi vxrm, 11512; RV32-NEXT: vasubu.vv v8, v10, v12, v0.t1513; RV32-NEXT: addi sp, sp, 161514; RV32-NEXT: ret1515;1516; RV64-LABEL: intrinsic_vasubu_mask_vx_nxv2i64_nxv2i64_i64:1517; RV64: # %bb.0: # %entry1518; RV64-NEXT: csrwi vxrm, 11519; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu1520; RV64-NEXT: vasubu.vx v8, v10, a0, v0.t1521; RV64-NEXT: ret1522entry:1523 %a = call <vscale x 2 x i64> @llvm.riscv.vasubu.mask.nxv2i64.i64(1524 <vscale x 2 x i64> %0,1525 <vscale x 2 x i64> %1,1526 i64 %2,1527 <vscale x 2 x i1> %3,1528 iXLen 1, iXLen %4, iXLen 1)1529 1530 ret <vscale x 2 x i64> %a1531}1532 1533define <vscale x 4 x i64> @intrinsic_vasubu_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, iXLen %2) nounwind {1534; RV32-LABEL: intrinsic_vasubu_vx_nxv4i64_nxv4i64_i64:1535; RV32: # %bb.0: # %entry1536; RV32-NEXT: addi sp, sp, -161537; RV32-NEXT: sw a0, 8(sp)1538; RV32-NEXT: sw a1, 12(sp)1539; RV32-NEXT: addi a0, sp, 81540; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma1541; RV32-NEXT: vlse64.v v12, (a0), zero1542; RV32-NEXT: csrwi vxrm, 01543; RV32-NEXT: vasubu.vv v8, v8, v121544; RV32-NEXT: addi sp, sp, 161545; RV32-NEXT: ret1546;1547; RV64-LABEL: intrinsic_vasubu_vx_nxv4i64_nxv4i64_i64:1548; RV64: # %bb.0: # %entry1549; RV64-NEXT: csrwi vxrm, 01550; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma1551; RV64-NEXT: vasubu.vx v8, v8, a01552; RV64-NEXT: ret1553entry:1554 %a = call <vscale x 4 x i64> @llvm.riscv.vasubu.nxv4i64.i64(1555 <vscale x 4 x i64> poison,1556 <vscale x 4 x i64> %0,1557 i64 %1,1558 iXLen 0, iXLen %2)1559 1560 ret <vscale x 4 x i64> %a1561}1562 1563define <vscale x 4 x i64> @intrinsic_vasubu_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1564; RV32-LABEL: intrinsic_vasubu_mask_vx_nxv4i64_nxv4i64_i64:1565; RV32: # %bb.0: # %entry1566; RV32-NEXT: addi sp, sp, -161567; RV32-NEXT: sw a0, 8(sp)1568; RV32-NEXT: sw a1, 12(sp)1569; RV32-NEXT: addi a0, sp, 81570; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu1571; RV32-NEXT: vlse64.v v16, (a0), zero1572; RV32-NEXT: csrwi vxrm, 11573; RV32-NEXT: vasubu.vv v8, v12, v16, v0.t1574; RV32-NEXT: addi sp, sp, 161575; RV32-NEXT: ret1576;1577; RV64-LABEL: intrinsic_vasubu_mask_vx_nxv4i64_nxv4i64_i64:1578; RV64: # %bb.0: # %entry1579; RV64-NEXT: csrwi vxrm, 11580; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu1581; RV64-NEXT: vasubu.vx v8, v12, a0, v0.t1582; RV64-NEXT: ret1583entry:1584 %a = call <vscale x 4 x i64> @llvm.riscv.vasubu.mask.nxv4i64.i64(1585 <vscale x 4 x i64> %0,1586 <vscale x 4 x i64> %1,1587 i64 %2,1588 <vscale x 4 x i1> %3,1589 iXLen 1, iXLen %4, iXLen 1)1590 1591 ret <vscale x 4 x i64> %a1592}1593 1594define <vscale x 8 x i64> @intrinsic_vasubu_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, iXLen %2) nounwind {1595; RV32-LABEL: intrinsic_vasubu_vx_nxv8i64_nxv8i64_i64:1596; RV32: # %bb.0: # %entry1597; RV32-NEXT: addi sp, sp, -161598; RV32-NEXT: sw a0, 8(sp)1599; RV32-NEXT: sw a1, 12(sp)1600; RV32-NEXT: addi a0, sp, 81601; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma1602; RV32-NEXT: vlse64.v v16, (a0), zero1603; RV32-NEXT: csrwi vxrm, 01604; RV32-NEXT: vasubu.vv v8, v8, v161605; RV32-NEXT: addi sp, sp, 161606; RV32-NEXT: ret1607;1608; RV64-LABEL: intrinsic_vasubu_vx_nxv8i64_nxv8i64_i64:1609; RV64: # %bb.0: # %entry1610; RV64-NEXT: csrwi vxrm, 01611; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma1612; RV64-NEXT: vasubu.vx v8, v8, a01613; RV64-NEXT: ret1614entry:1615 %a = call <vscale x 8 x i64> @llvm.riscv.vasubu.nxv8i64.i64(1616 <vscale x 8 x i64> poison,1617 <vscale x 8 x i64> %0,1618 i64 %1,1619 iXLen 0, iXLen %2)1620 1621 ret <vscale x 8 x i64> %a1622}1623 1624define <vscale x 8 x i64> @intrinsic_vasubu_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {1625; RV32-LABEL: intrinsic_vasubu_mask_vx_nxv8i64_nxv8i64_i64:1626; RV32: # %bb.0: # %entry1627; RV32-NEXT: addi sp, sp, -161628; RV32-NEXT: sw a0, 8(sp)1629; RV32-NEXT: sw a1, 12(sp)1630; RV32-NEXT: addi a0, sp, 81631; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu1632; RV32-NEXT: vlse64.v v24, (a0), zero1633; RV32-NEXT: csrwi vxrm, 11634; RV32-NEXT: vasubu.vv v8, v16, v24, v0.t1635; RV32-NEXT: addi sp, sp, 161636; RV32-NEXT: ret1637;1638; RV64-LABEL: intrinsic_vasubu_mask_vx_nxv8i64_nxv8i64_i64:1639; RV64: # %bb.0: # %entry1640; RV64-NEXT: csrwi vxrm, 11641; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu1642; RV64-NEXT: vasubu.vx v8, v16, a0, v0.t1643; RV64-NEXT: ret1644entry:1645 %a = call <vscale x 8 x i64> @llvm.riscv.vasubu.mask.nxv8i64.i64(1646 <vscale x 8 x i64> %0,1647 <vscale x 8 x i64> %1,1648 i64 %2,1649 <vscale x 8 x i1> %3,1650 iXLen 1, iXLen %4, iXLen 1)1651 1652 ret <vscale x 8 x i64> %a1653}1654