367 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvbc \3; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV324; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvbc \5; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV646 7define <vscale x 1 x i64> @intrinsic_vclmulh_vv_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, iXLen %2) nounwind {8; CHECK-LABEL: intrinsic_vclmulh_vv_nxv1i64_nxv1i64:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma11; CHECK-NEXT: vclmulh.vv v8, v8, v912; CHECK-NEXT: ret13entry:14 %a = call <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.nxv1i64(15 <vscale x 1 x i64> poison,16 <vscale x 1 x i64> %0,17 <vscale x 1 x i64> %1,18 iXLen %2)19 20 ret <vscale x 1 x i64> %a21}22 23define <vscale x 1 x i64> @intrinsic_vclmulh_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {24; CHECK-LABEL: intrinsic_vclmulh_mask_vv_nxv1i64_nxv1i64:25; CHECK: # %bb.0: # %entry26; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu27; CHECK-NEXT: vclmulh.vv v8, v9, v10, v0.t28; CHECK-NEXT: ret29entry:30 %a = call <vscale x 1 x i64> @llvm.riscv.vclmulh.mask.nxv1i64.nxv1i64(31 <vscale x 1 x i64> %0,32 <vscale x 1 x i64> %1,33 <vscale x 1 x i64> %2,34 <vscale x 1 x i1> %3,35 iXLen %4, iXLen 1)36 37 ret <vscale x 1 x i64> %a38}39 40define <vscale x 2 x i64> @intrinsic_vclmulh_vv_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, iXLen %2) nounwind {41; CHECK-LABEL: intrinsic_vclmulh_vv_nxv2i64_nxv2i64:42; CHECK: # %bb.0: # %entry43; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma44; CHECK-NEXT: vclmulh.vv v8, v8, v1045; CHECK-NEXT: ret46entry:47 %a = call <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.nxv2i64(48 <vscale x 2 x i64> poison,49 <vscale x 2 x i64> %0,50 <vscale x 2 x i64> %1,51 iXLen %2)52 53 ret <vscale x 2 x i64> %a54}55 56define <vscale x 2 x i64> @intrinsic_vclmulh_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {57; CHECK-LABEL: intrinsic_vclmulh_mask_vv_nxv2i64_nxv2i64:58; CHECK: # %bb.0: # %entry59; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu60; CHECK-NEXT: vclmulh.vv v8, v10, v12, v0.t61; CHECK-NEXT: ret62entry:63 %a = call <vscale x 2 x i64> @llvm.riscv.vclmulh.mask.nxv2i64.nxv2i64(64 <vscale x 2 x i64> %0,65 <vscale x 2 x i64> %1,66 <vscale x 2 x i64> %2,67 <vscale x 2 x i1> %3,68 iXLen %4, iXLen 1)69 70 ret <vscale x 2 x i64> %a71}72 73define <vscale x 4 x i64> @intrinsic_vclmulh_vv_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, iXLen %2) nounwind {74; CHECK-LABEL: intrinsic_vclmulh_vv_nxv4i64_nxv4i64:75; CHECK: # %bb.0: # %entry76; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma77; CHECK-NEXT: vclmulh.vv v8, v8, v1278; CHECK-NEXT: ret79entry:80 %a = call <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.nxv4i64(81 <vscale x 4 x i64> poison,82 <vscale x 4 x i64> %0,83 <vscale x 4 x i64> %1,84 iXLen %2)85 86 ret <vscale x 4 x i64> %a87}88 89define <vscale x 4 x i64> @intrinsic_vclmulh_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {90; CHECK-LABEL: intrinsic_vclmulh_mask_vv_nxv4i64_nxv4i64:91; CHECK: # %bb.0: # %entry92; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu93; CHECK-NEXT: vclmulh.vv v8, v12, v16, v0.t94; CHECK-NEXT: ret95entry:96 %a = call <vscale x 4 x i64> @llvm.riscv.vclmulh.mask.nxv4i64.nxv4i64(97 <vscale x 4 x i64> %0,98 <vscale x 4 x i64> %1,99 <vscale x 4 x i64> %2,100 <vscale x 4 x i1> %3,101 iXLen %4, iXLen 1)102 103 ret <vscale x 4 x i64> %a104}105 106define <vscale x 8 x i64> @intrinsic_vclmulh_vv_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, iXLen %2) nounwind {107; CHECK-LABEL: intrinsic_vclmulh_vv_nxv8i64_nxv8i64:108; CHECK: # %bb.0: # %entry109; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma110; CHECK-NEXT: vclmulh.vv v8, v8, v16111; CHECK-NEXT: ret112entry:113 %a = call <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.nxv8i64(114 <vscale x 8 x i64> poison,115 <vscale x 8 x i64> %0,116 <vscale x 8 x i64> %1,117 iXLen %2)118 119 ret <vscale x 8 x i64> %a120}121 122define <vscale x 8 x i64> @intrinsic_vclmulh_mask_vv_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {123; CHECK-LABEL: intrinsic_vclmulh_mask_vv_nxv8i64_nxv8i64:124; CHECK: # %bb.0: # %entry125; CHECK-NEXT: vl8re64.v v24, (a0)126; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu127; CHECK-NEXT: vclmulh.vv v8, v16, v24, v0.t128; CHECK-NEXT: ret129entry:130 %a = call <vscale x 8 x i64> @llvm.riscv.vclmulh.mask.nxv8i64.nxv8i64(131 <vscale x 8 x i64> %0,132 <vscale x 8 x i64> %1,133 <vscale x 8 x i64> %2,134 <vscale x 8 x i1> %3,135 iXLen %4, iXLen 1)136 137 ret <vscale x 8 x i64> %a138}139 140define <vscale x 1 x i64> @intrinsic_vclmulh_vx_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, iXLen %2) nounwind {141; RV32-LABEL: intrinsic_vclmulh_vx_nxv1i64_i64:142; RV32: # %bb.0: # %entry143; RV32-NEXT: addi sp, sp, -16144; RV32-NEXT: sw a0, 8(sp)145; RV32-NEXT: sw a1, 12(sp)146; RV32-NEXT: addi a0, sp, 8147; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma148; RV32-NEXT: vlse64.v v9, (a0), zero149; RV32-NEXT: vclmulh.vv v8, v8, v9150; RV32-NEXT: addi sp, sp, 16151; RV32-NEXT: ret152;153; RV64-LABEL: intrinsic_vclmulh_vx_nxv1i64_i64:154; RV64: # %bb.0: # %entry155; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma156; RV64-NEXT: vclmulh.vx v8, v8, a0157; RV64-NEXT: ret158entry:159 %a = call <vscale x 1 x i64> @llvm.riscv.vclmulh.nxv1i64.i64(160 <vscale x 1 x i64> poison,161 <vscale x 1 x i64> %0,162 i64 %1,163 iXLen %2)164 165 ret <vscale x 1 x i64> %a166}167 168define <vscale x 1 x i64> @intrinsic_vclmulh_mask_vx_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {169; RV32-LABEL: intrinsic_vclmulh_mask_vx_nxv1i64_i64:170; RV32: # %bb.0: # %entry171; RV32-NEXT: addi sp, sp, -16172; RV32-NEXT: sw a0, 8(sp)173; RV32-NEXT: sw a1, 12(sp)174; RV32-NEXT: addi a0, sp, 8175; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu176; RV32-NEXT: vlse64.v v10, (a0), zero177; RV32-NEXT: vclmulh.vv v8, v9, v10, v0.t178; RV32-NEXT: addi sp, sp, 16179; RV32-NEXT: ret180;181; RV64-LABEL: intrinsic_vclmulh_mask_vx_nxv1i64_i64:182; RV64: # %bb.0: # %entry183; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu184; RV64-NEXT: vclmulh.vx v8, v9, a0, v0.t185; RV64-NEXT: ret186entry:187 %a = call <vscale x 1 x i64> @llvm.riscv.vclmulh.mask.nxv1i64.i64(188 <vscale x 1 x i64> %0,189 <vscale x 1 x i64> %1,190 i64 %2,191 <vscale x 1 x i1> %3,192 iXLen %4, iXLen 1)193 194 ret <vscale x 1 x i64> %a195}196 197define <vscale x 2 x i64> @intrinsic_vclmulh_vx_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, iXLen %2) nounwind {198; RV32-LABEL: intrinsic_vclmulh_vx_nxv2i64_i64:199; RV32: # %bb.0: # %entry200; RV32-NEXT: addi sp, sp, -16201; RV32-NEXT: sw a0, 8(sp)202; RV32-NEXT: sw a1, 12(sp)203; RV32-NEXT: addi a0, sp, 8204; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma205; RV32-NEXT: vlse64.v v10, (a0), zero206; RV32-NEXT: vclmulh.vv v8, v8, v10207; RV32-NEXT: addi sp, sp, 16208; RV32-NEXT: ret209;210; RV64-LABEL: intrinsic_vclmulh_vx_nxv2i64_i64:211; RV64: # %bb.0: # %entry212; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma213; RV64-NEXT: vclmulh.vx v8, v8, a0214; RV64-NEXT: ret215entry:216 %a = call <vscale x 2 x i64> @llvm.riscv.vclmulh.nxv2i64.i64(217 <vscale x 2 x i64> poison,218 <vscale x 2 x i64> %0,219 i64 %1,220 iXLen %2)221 222 ret <vscale x 2 x i64> %a223}224 225define <vscale x 2 x i64> @intrinsic_vclmulh_mask_vx_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {226; RV32-LABEL: intrinsic_vclmulh_mask_vx_nxv2i64_i64:227; RV32: # %bb.0: # %entry228; RV32-NEXT: addi sp, sp, -16229; RV32-NEXT: sw a0, 8(sp)230; RV32-NEXT: sw a1, 12(sp)231; RV32-NEXT: addi a0, sp, 8232; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu233; RV32-NEXT: vlse64.v v12, (a0), zero234; RV32-NEXT: vclmulh.vv v8, v10, v12, v0.t235; RV32-NEXT: addi sp, sp, 16236; RV32-NEXT: ret237;238; RV64-LABEL: intrinsic_vclmulh_mask_vx_nxv2i64_i64:239; RV64: # %bb.0: # %entry240; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu241; RV64-NEXT: vclmulh.vx v8, v10, a0, v0.t242; RV64-NEXT: ret243entry:244 %a = call <vscale x 2 x i64> @llvm.riscv.vclmulh.mask.nxv2i64.i64(245 <vscale x 2 x i64> %0,246 <vscale x 2 x i64> %1,247 i64 %2,248 <vscale x 2 x i1> %3,249 iXLen %4, iXLen 1)250 251 ret <vscale x 2 x i64> %a252}253 254define <vscale x 4 x i64> @intrinsic_vclmulh_vx_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, iXLen %2) nounwind {255; RV32-LABEL: intrinsic_vclmulh_vx_nxv4i64_i64:256; RV32: # %bb.0: # %entry257; RV32-NEXT: addi sp, sp, -16258; RV32-NEXT: sw a0, 8(sp)259; RV32-NEXT: sw a1, 12(sp)260; RV32-NEXT: addi a0, sp, 8261; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma262; RV32-NEXT: vlse64.v v12, (a0), zero263; RV32-NEXT: vclmulh.vv v8, v8, v12264; RV32-NEXT: addi sp, sp, 16265; RV32-NEXT: ret266;267; RV64-LABEL: intrinsic_vclmulh_vx_nxv4i64_i64:268; RV64: # %bb.0: # %entry269; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma270; RV64-NEXT: vclmulh.vx v8, v8, a0271; RV64-NEXT: ret272entry:273 %a = call <vscale x 4 x i64> @llvm.riscv.vclmulh.nxv4i64.i64(274 <vscale x 4 x i64> poison,275 <vscale x 4 x i64> %0,276 i64 %1,277 iXLen %2)278 279 ret <vscale x 4 x i64> %a280}281 282define <vscale x 4 x i64> @intrinsic_vclmulh_mask_vx_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {283; RV32-LABEL: intrinsic_vclmulh_mask_vx_nxv4i64_i64:284; RV32: # %bb.0: # %entry285; RV32-NEXT: addi sp, sp, -16286; RV32-NEXT: sw a0, 8(sp)287; RV32-NEXT: sw a1, 12(sp)288; RV32-NEXT: addi a0, sp, 8289; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu290; RV32-NEXT: vlse64.v v16, (a0), zero291; RV32-NEXT: vclmulh.vv v8, v12, v16, v0.t292; RV32-NEXT: addi sp, sp, 16293; RV32-NEXT: ret294;295; RV64-LABEL: intrinsic_vclmulh_mask_vx_nxv4i64_i64:296; RV64: # %bb.0: # %entry297; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu298; RV64-NEXT: vclmulh.vx v8, v12, a0, v0.t299; RV64-NEXT: ret300entry:301 %a = call <vscale x 4 x i64> @llvm.riscv.vclmulh.mask.nxv4i64.i64(302 <vscale x 4 x i64> %0,303 <vscale x 4 x i64> %1,304 i64 %2,305 <vscale x 4 x i1> %3,306 iXLen %4, iXLen 1)307 308 ret <vscale x 4 x i64> %a309}310 311define <vscale x 8 x i64> @intrinsic_vclmulh_vx_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, iXLen %2) nounwind {312; RV32-LABEL: intrinsic_vclmulh_vx_nxv8i64_i64:313; RV32: # %bb.0: # %entry314; RV32-NEXT: addi sp, sp, -16315; RV32-NEXT: sw a0, 8(sp)316; RV32-NEXT: sw a1, 12(sp)317; RV32-NEXT: addi a0, sp, 8318; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma319; RV32-NEXT: vlse64.v v16, (a0), zero320; RV32-NEXT: vclmulh.vv v8, v8, v16321; RV32-NEXT: addi sp, sp, 16322; RV32-NEXT: ret323;324; RV64-LABEL: intrinsic_vclmulh_vx_nxv8i64_i64:325; RV64: # %bb.0: # %entry326; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma327; RV64-NEXT: vclmulh.vx v8, v8, a0328; RV64-NEXT: ret329entry:330 %a = call <vscale x 8 x i64> @llvm.riscv.vclmulh.nxv8i64.i64(331 <vscale x 8 x i64> poison,332 <vscale x 8 x i64> %0,333 i64 %1,334 iXLen %2)335 336 ret <vscale x 8 x i64> %a337}338 339define <vscale x 8 x i64> @intrinsic_vclmulh_mask_vx_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {340; RV32-LABEL: intrinsic_vclmulh_mask_vx_nxv8i64_i64:341; RV32: # %bb.0: # %entry342; RV32-NEXT: addi sp, sp, -16343; RV32-NEXT: sw a0, 8(sp)344; RV32-NEXT: sw a1, 12(sp)345; RV32-NEXT: addi a0, sp, 8346; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu347; RV32-NEXT: vlse64.v v24, (a0), zero348; RV32-NEXT: vclmulh.vv v8, v16, v24, v0.t349; RV32-NEXT: addi sp, sp, 16350; RV32-NEXT: ret351;352; RV64-LABEL: intrinsic_vclmulh_mask_vx_nxv8i64_i64:353; RV64: # %bb.0: # %entry354; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu355; RV64-NEXT: vclmulh.vx v8, v16, a0, v0.t356; RV64-NEXT: ret357entry:358 %a = call <vscale x 8 x i64> @llvm.riscv.vclmulh.mask.nxv8i64.i64(359 <vscale x 8 x i64> %0,360 <vscale x 8 x i64> %1,361 i64 %2,362 <vscale x 8 x i1> %3,363 iXLen %4, iXLen 1)364 365 ret <vscale x 8 x i64> %a366}367