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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfhmin,+zvfbfmin \3; RUN: -verify-machineinstrs | FileCheck %s4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfhmin,+zvfbfmin \5; RUN: -verify-machineinstrs | FileCheck %s6 7define <vscale x 1 x i8> @intrinsic_vcompress_vm_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {8; CHECK-LABEL: intrinsic_vcompress_vm_nxv1i8_nxv1i8:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma11; CHECK-NEXT: vcompress.vm v8, v9, v012; CHECK-NEXT: ret13entry:14 %a = call <vscale x 1 x i8> @llvm.riscv.vcompress.nxv1i8(15 <vscale x 1 x i8> %0,16 <vscale x 1 x i8> %1,17 <vscale x 1 x i1> %2,18 iXLen %3)19 20 ret <vscale x 1 x i8> %a21}22 23define <vscale x 2 x i8> @intrinsic_vcompress_vm_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {24; CHECK-LABEL: intrinsic_vcompress_vm_nxv2i8_nxv2i8:25; CHECK: # %bb.0: # %entry26; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, ma27; CHECK-NEXT: vcompress.vm v8, v9, v028; CHECK-NEXT: ret29entry:30 %a = call <vscale x 2 x i8> @llvm.riscv.vcompress.nxv2i8(31 <vscale x 2 x i8> %0,32 <vscale x 2 x i8> %1,33 <vscale x 2 x i1> %2,34 iXLen %3)35 36 ret <vscale x 2 x i8> %a37}38 39define <vscale x 4 x i8> @intrinsic_vcompress_vm_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {40; CHECK-LABEL: intrinsic_vcompress_vm_nxv4i8_nxv4i8:41; CHECK: # %bb.0: # %entry42; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, ma43; CHECK-NEXT: vcompress.vm v8, v9, v044; CHECK-NEXT: ret45entry:46 %a = call <vscale x 4 x i8> @llvm.riscv.vcompress.nxv4i8(47 <vscale x 4 x i8> %0,48 <vscale x 4 x i8> %1,49 <vscale x 4 x i1> %2,50 iXLen %3)51 52 ret <vscale x 4 x i8> %a53}54 55define <vscale x 8 x i8> @intrinsic_vcompress_vm_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {56; CHECK-LABEL: intrinsic_vcompress_vm_nxv8i8_nxv8i8:57; CHECK: # %bb.0: # %entry58; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma59; CHECK-NEXT: vcompress.vm v8, v9, v060; CHECK-NEXT: ret61entry:62 %a = call <vscale x 8 x i8> @llvm.riscv.vcompress.nxv8i8(63 <vscale x 8 x i8> %0,64 <vscale x 8 x i8> %1,65 <vscale x 8 x i1> %2,66 iXLen %3)67 68 ret <vscale x 8 x i8> %a69}70 71define <vscale x 16 x i8> @intrinsic_vcompress_vm_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {72; CHECK-LABEL: intrinsic_vcompress_vm_nxv16i8_nxv16i8:73; CHECK: # %bb.0: # %entry74; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, ma75; CHECK-NEXT: vcompress.vm v8, v10, v076; CHECK-NEXT: ret77entry:78 %a = call <vscale x 16 x i8> @llvm.riscv.vcompress.nxv16i8(79 <vscale x 16 x i8> %0,80 <vscale x 16 x i8> %1,81 <vscale x 16 x i1> %2,82 iXLen %3)83 84 ret <vscale x 16 x i8> %a85}86 87define <vscale x 32 x i8> @intrinsic_vcompress_vm_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {88; CHECK-LABEL: intrinsic_vcompress_vm_nxv32i8_nxv32i8:89; CHECK: # %bb.0: # %entry90; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, ma91; CHECK-NEXT: vcompress.vm v8, v12, v092; CHECK-NEXT: ret93entry:94 %a = call <vscale x 32 x i8> @llvm.riscv.vcompress.nxv32i8(95 <vscale x 32 x i8> %0,96 <vscale x 32 x i8> %1,97 <vscale x 32 x i1> %2,98 iXLen %3)99 100 ret <vscale x 32 x i8> %a101}102 103define <vscale x 64 x i8> @intrinsic_vcompress_vm_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i1> %2, iXLen %3) nounwind {104; CHECK-LABEL: intrinsic_vcompress_vm_nxv64i8_nxv64i8:105; CHECK: # %bb.0: # %entry106; CHECK-NEXT: vsetvli zero, a0, e8, m8, tu, ma107; CHECK-NEXT: vcompress.vm v8, v16, v0108; CHECK-NEXT: ret109entry:110 %a = call <vscale x 64 x i8> @llvm.riscv.vcompress.nxv64i8(111 <vscale x 64 x i8> %0,112 <vscale x 64 x i8> %1,113 <vscale x 64 x i1> %2,114 iXLen %3)115 116 ret <vscale x 64 x i8> %a117}118 119define <vscale x 1 x i16> @intrinsic_vcompress_vm_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {120; CHECK-LABEL: intrinsic_vcompress_vm_nxv1i16_nxv1i16:121; CHECK: # %bb.0: # %entry122; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma123; CHECK-NEXT: vcompress.vm v8, v9, v0124; CHECK-NEXT: ret125entry:126 %a = call <vscale x 1 x i16> @llvm.riscv.vcompress.nxv1i16(127 <vscale x 1 x i16> %0,128 <vscale x 1 x i16> %1,129 <vscale x 1 x i1> %2,130 iXLen %3)131 132 ret <vscale x 1 x i16> %a133}134 135define <vscale x 2 x i16> @intrinsic_vcompress_vm_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {136; CHECK-LABEL: intrinsic_vcompress_vm_nxv2i16_nxv2i16:137; CHECK: # %bb.0: # %entry138; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma139; CHECK-NEXT: vcompress.vm v8, v9, v0140; CHECK-NEXT: ret141entry:142 %a = call <vscale x 2 x i16> @llvm.riscv.vcompress.nxv2i16(143 <vscale x 2 x i16> %0,144 <vscale x 2 x i16> %1,145 <vscale x 2 x i1> %2,146 iXLen %3)147 148 ret <vscale x 2 x i16> %a149}150 151define <vscale x 4 x i16> @intrinsic_vcompress_vm_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {152; CHECK-LABEL: intrinsic_vcompress_vm_nxv4i16_nxv4i16:153; CHECK: # %bb.0: # %entry154; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma155; CHECK-NEXT: vcompress.vm v8, v9, v0156; CHECK-NEXT: ret157entry:158 %a = call <vscale x 4 x i16> @llvm.riscv.vcompress.nxv4i16(159 <vscale x 4 x i16> %0,160 <vscale x 4 x i16> %1,161 <vscale x 4 x i1> %2,162 iXLen %3)163 164 ret <vscale x 4 x i16> %a165}166 167define <vscale x 8 x i16> @intrinsic_vcompress_vm_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {168; CHECK-LABEL: intrinsic_vcompress_vm_nxv8i16_nxv8i16:169; CHECK: # %bb.0: # %entry170; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma171; CHECK-NEXT: vcompress.vm v8, v10, v0172; CHECK-NEXT: ret173entry:174 %a = call <vscale x 8 x i16> @llvm.riscv.vcompress.nxv8i16(175 <vscale x 8 x i16> %0,176 <vscale x 8 x i16> %1,177 <vscale x 8 x i1> %2,178 iXLen %3)179 180 ret <vscale x 8 x i16> %a181}182 183define <vscale x 16 x i16> @intrinsic_vcompress_vm_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {184; CHECK-LABEL: intrinsic_vcompress_vm_nxv16i16_nxv16i16:185; CHECK: # %bb.0: # %entry186; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma187; CHECK-NEXT: vcompress.vm v8, v12, v0188; CHECK-NEXT: ret189entry:190 %a = call <vscale x 16 x i16> @llvm.riscv.vcompress.nxv16i16(191 <vscale x 16 x i16> %0,192 <vscale x 16 x i16> %1,193 <vscale x 16 x i1> %2,194 iXLen %3)195 196 ret <vscale x 16 x i16> %a197}198 199define <vscale x 32 x i16> @intrinsic_vcompress_vm_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {200; CHECK-LABEL: intrinsic_vcompress_vm_nxv32i16_nxv32i16:201; CHECK: # %bb.0: # %entry202; CHECK-NEXT: vsetvli zero, a0, e16, m8, tu, ma203; CHECK-NEXT: vcompress.vm v8, v16, v0204; CHECK-NEXT: ret205entry:206 %a = call <vscale x 32 x i16> @llvm.riscv.vcompress.nxv32i16(207 <vscale x 32 x i16> %0,208 <vscale x 32 x i16> %1,209 <vscale x 32 x i1> %2,210 iXLen %3)211 212 ret <vscale x 32 x i16> %a213}214 215define <vscale x 1 x i32> @intrinsic_vcompress_vm_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {216; CHECK-LABEL: intrinsic_vcompress_vm_nxv1i32_nxv1i32:217; CHECK: # %bb.0: # %entry218; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma219; CHECK-NEXT: vcompress.vm v8, v9, v0220; CHECK-NEXT: ret221entry:222 %a = call <vscale x 1 x i32> @llvm.riscv.vcompress.nxv1i32(223 <vscale x 1 x i32> %0,224 <vscale x 1 x i32> %1,225 <vscale x 1 x i1> %2,226 iXLen %3)227 228 ret <vscale x 1 x i32> %a229}230 231define <vscale x 2 x i32> @intrinsic_vcompress_vm_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {232; CHECK-LABEL: intrinsic_vcompress_vm_nxv2i32_nxv2i32:233; CHECK: # %bb.0: # %entry234; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma235; CHECK-NEXT: vcompress.vm v8, v9, v0236; CHECK-NEXT: ret237entry:238 %a = call <vscale x 2 x i32> @llvm.riscv.vcompress.nxv2i32(239 <vscale x 2 x i32> %0,240 <vscale x 2 x i32> %1,241 <vscale x 2 x i1> %2,242 iXLen %3)243 244 ret <vscale x 2 x i32> %a245}246 247define <vscale x 4 x i32> @intrinsic_vcompress_vm_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {248; CHECK-LABEL: intrinsic_vcompress_vm_nxv4i32_nxv4i32:249; CHECK: # %bb.0: # %entry250; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma251; CHECK-NEXT: vcompress.vm v8, v10, v0252; CHECK-NEXT: ret253entry:254 %a = call <vscale x 4 x i32> @llvm.riscv.vcompress.nxv4i32(255 <vscale x 4 x i32> %0,256 <vscale x 4 x i32> %1,257 <vscale x 4 x i1> %2,258 iXLen %3)259 260 ret <vscale x 4 x i32> %a261}262 263define <vscale x 8 x i32> @intrinsic_vcompress_vm_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {264; CHECK-LABEL: intrinsic_vcompress_vm_nxv8i32_nxv8i32:265; CHECK: # %bb.0: # %entry266; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma267; CHECK-NEXT: vcompress.vm v8, v12, v0268; CHECK-NEXT: ret269entry:270 %a = call <vscale x 8 x i32> @llvm.riscv.vcompress.nxv8i32(271 <vscale x 8 x i32> %0,272 <vscale x 8 x i32> %1,273 <vscale x 8 x i1> %2,274 iXLen %3)275 276 ret <vscale x 8 x i32> %a277}278 279define <vscale x 16 x i32> @intrinsic_vcompress_vm_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {280; CHECK-LABEL: intrinsic_vcompress_vm_nxv16i32_nxv16i32:281; CHECK: # %bb.0: # %entry282; CHECK-NEXT: vsetvli zero, a0, e32, m8, tu, ma283; CHECK-NEXT: vcompress.vm v8, v16, v0284; CHECK-NEXT: ret285entry:286 %a = call <vscale x 16 x i32> @llvm.riscv.vcompress.nxv16i32(287 <vscale x 16 x i32> %0,288 <vscale x 16 x i32> %1,289 <vscale x 16 x i1> %2,290 iXLen %3)291 292 ret <vscale x 16 x i32> %a293}294 295define <vscale x 1 x i64> @intrinsic_vcompress_vm_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {296; CHECK-LABEL: intrinsic_vcompress_vm_nxv1i64_nxv1i64:297; CHECK: # %bb.0: # %entry298; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma299; CHECK-NEXT: vcompress.vm v8, v9, v0300; CHECK-NEXT: ret301entry:302 %a = call <vscale x 1 x i64> @llvm.riscv.vcompress.nxv1i64(303 <vscale x 1 x i64> %0,304 <vscale x 1 x i64> %1,305 <vscale x 1 x i1> %2,306 iXLen %3)307 308 ret <vscale x 1 x i64> %a309}310 311define <vscale x 2 x i64> @intrinsic_vcompress_vm_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {312; CHECK-LABEL: intrinsic_vcompress_vm_nxv2i64_nxv2i64:313; CHECK: # %bb.0: # %entry314; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma315; CHECK-NEXT: vcompress.vm v8, v10, v0316; CHECK-NEXT: ret317entry:318 %a = call <vscale x 2 x i64> @llvm.riscv.vcompress.nxv2i64(319 <vscale x 2 x i64> %0,320 <vscale x 2 x i64> %1,321 <vscale x 2 x i1> %2,322 iXLen %3)323 324 ret <vscale x 2 x i64> %a325}326 327define <vscale x 4 x i64> @intrinsic_vcompress_vm_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {328; CHECK-LABEL: intrinsic_vcompress_vm_nxv4i64_nxv4i64:329; CHECK: # %bb.0: # %entry330; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma331; CHECK-NEXT: vcompress.vm v8, v12, v0332; CHECK-NEXT: ret333entry:334 %a = call <vscale x 4 x i64> @llvm.riscv.vcompress.nxv4i64(335 <vscale x 4 x i64> %0,336 <vscale x 4 x i64> %1,337 <vscale x 4 x i1> %2,338 iXLen %3)339 340 ret <vscale x 4 x i64> %a341}342 343define <vscale x 8 x i64> @intrinsic_vcompress_vm_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {344; CHECK-LABEL: intrinsic_vcompress_vm_nxv8i64_nxv8i64:345; CHECK: # %bb.0: # %entry346; CHECK-NEXT: vsetvli zero, a0, e64, m8, tu, ma347; CHECK-NEXT: vcompress.vm v8, v16, v0348; CHECK-NEXT: ret349entry:350 %a = call <vscale x 8 x i64> @llvm.riscv.vcompress.nxv8i64(351 <vscale x 8 x i64> %0,352 <vscale x 8 x i64> %1,353 <vscale x 8 x i1> %2,354 iXLen %3)355 356 ret <vscale x 8 x i64> %a357}358 359define <vscale x 1 x half> @intrinsic_vcompress_vm_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {360; CHECK-LABEL: intrinsic_vcompress_vm_nxv1f16_nxv1f16:361; CHECK: # %bb.0: # %entry362; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma363; CHECK-NEXT: vcompress.vm v8, v9, v0364; CHECK-NEXT: ret365entry:366 %a = call <vscale x 1 x half> @llvm.riscv.vcompress.nxv1f16(367 <vscale x 1 x half> %0,368 <vscale x 1 x half> %1,369 <vscale x 1 x i1> %2,370 iXLen %3)371 372 ret <vscale x 1 x half> %a373}374 375define <vscale x 2 x half> @intrinsic_vcompress_vm_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {376; CHECK-LABEL: intrinsic_vcompress_vm_nxv2f16_nxv2f16:377; CHECK: # %bb.0: # %entry378; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma379; CHECK-NEXT: vcompress.vm v8, v9, v0380; CHECK-NEXT: ret381entry:382 %a = call <vscale x 2 x half> @llvm.riscv.vcompress.nxv2f16(383 <vscale x 2 x half> %0,384 <vscale x 2 x half> %1,385 <vscale x 2 x i1> %2,386 iXLen %3)387 388 ret <vscale x 2 x half> %a389}390 391define <vscale x 4 x half> @intrinsic_vcompress_vm_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {392; CHECK-LABEL: intrinsic_vcompress_vm_nxv4f16_nxv4f16:393; CHECK: # %bb.0: # %entry394; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma395; CHECK-NEXT: vcompress.vm v8, v9, v0396; CHECK-NEXT: ret397entry:398 %a = call <vscale x 4 x half> @llvm.riscv.vcompress.nxv4f16(399 <vscale x 4 x half> %0,400 <vscale x 4 x half> %1,401 <vscale x 4 x i1> %2,402 iXLen %3)403 404 ret <vscale x 4 x half> %a405}406 407define <vscale x 8 x half> @intrinsic_vcompress_vm_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {408; CHECK-LABEL: intrinsic_vcompress_vm_nxv8f16_nxv8f16:409; CHECK: # %bb.0: # %entry410; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma411; CHECK-NEXT: vcompress.vm v8, v10, v0412; CHECK-NEXT: ret413entry:414 %a = call <vscale x 8 x half> @llvm.riscv.vcompress.nxv8f16(415 <vscale x 8 x half> %0,416 <vscale x 8 x half> %1,417 <vscale x 8 x i1> %2,418 iXLen %3)419 420 ret <vscale x 8 x half> %a421}422 423define <vscale x 16 x half> @intrinsic_vcompress_vm_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {424; CHECK-LABEL: intrinsic_vcompress_vm_nxv16f16_nxv16f16:425; CHECK: # %bb.0: # %entry426; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma427; CHECK-NEXT: vcompress.vm v8, v12, v0428; CHECK-NEXT: ret429entry:430 %a = call <vscale x 16 x half> @llvm.riscv.vcompress.nxv16f16(431 <vscale x 16 x half> %0,432 <vscale x 16 x half> %1,433 <vscale x 16 x i1> %2,434 iXLen %3)435 436 ret <vscale x 16 x half> %a437}438 439define <vscale x 32 x half> @intrinsic_vcompress_vm_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {440; CHECK-LABEL: intrinsic_vcompress_vm_nxv32f16_nxv32f16:441; CHECK: # %bb.0: # %entry442; CHECK-NEXT: vsetvli zero, a0, e16, m8, tu, ma443; CHECK-NEXT: vcompress.vm v8, v16, v0444; CHECK-NEXT: ret445entry:446 %a = call <vscale x 32 x half> @llvm.riscv.vcompress.nxv32f16(447 <vscale x 32 x half> %0,448 <vscale x 32 x half> %1,449 <vscale x 32 x i1> %2,450 iXLen %3)451 452 ret <vscale x 32 x half> %a453}454 455define <vscale x 1 x float> @intrinsic_vcompress_vm_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {456; CHECK-LABEL: intrinsic_vcompress_vm_nxv1f32_nxv1f32:457; CHECK: # %bb.0: # %entry458; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma459; CHECK-NEXT: vcompress.vm v8, v9, v0460; CHECK-NEXT: ret461entry:462 %a = call <vscale x 1 x float> @llvm.riscv.vcompress.nxv1f32(463 <vscale x 1 x float> %0,464 <vscale x 1 x float> %1,465 <vscale x 1 x i1> %2,466 iXLen %3)467 468 ret <vscale x 1 x float> %a469}470 471define <vscale x 2 x float> @intrinsic_vcompress_vm_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {472; CHECK-LABEL: intrinsic_vcompress_vm_nxv2f32_nxv2f32:473; CHECK: # %bb.0: # %entry474; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma475; CHECK-NEXT: vcompress.vm v8, v9, v0476; CHECK-NEXT: ret477entry:478 %a = call <vscale x 2 x float> @llvm.riscv.vcompress.nxv2f32(479 <vscale x 2 x float> %0,480 <vscale x 2 x float> %1,481 <vscale x 2 x i1> %2,482 iXLen %3)483 484 ret <vscale x 2 x float> %a485}486 487define <vscale x 4 x float> @intrinsic_vcompress_vm_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {488; CHECK-LABEL: intrinsic_vcompress_vm_nxv4f32_nxv4f32:489; CHECK: # %bb.0: # %entry490; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma491; CHECK-NEXT: vcompress.vm v8, v10, v0492; CHECK-NEXT: ret493entry:494 %a = call <vscale x 4 x float> @llvm.riscv.vcompress.nxv4f32(495 <vscale x 4 x float> %0,496 <vscale x 4 x float> %1,497 <vscale x 4 x i1> %2,498 iXLen %3)499 500 ret <vscale x 4 x float> %a501}502 503define <vscale x 8 x float> @intrinsic_vcompress_vm_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {504; CHECK-LABEL: intrinsic_vcompress_vm_nxv8f32_nxv8f32:505; CHECK: # %bb.0: # %entry506; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma507; CHECK-NEXT: vcompress.vm v8, v12, v0508; CHECK-NEXT: ret509entry:510 %a = call <vscale x 8 x float> @llvm.riscv.vcompress.nxv8f32(511 <vscale x 8 x float> %0,512 <vscale x 8 x float> %1,513 <vscale x 8 x i1> %2,514 iXLen %3)515 516 ret <vscale x 8 x float> %a517}518 519define <vscale x 16 x float> @intrinsic_vcompress_vm_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {520; CHECK-LABEL: intrinsic_vcompress_vm_nxv16f32_nxv16f32:521; CHECK: # %bb.0: # %entry522; CHECK-NEXT: vsetvli zero, a0, e32, m8, tu, ma523; CHECK-NEXT: vcompress.vm v8, v16, v0524; CHECK-NEXT: ret525entry:526 %a = call <vscale x 16 x float> @llvm.riscv.vcompress.nxv16f32(527 <vscale x 16 x float> %0,528 <vscale x 16 x float> %1,529 <vscale x 16 x i1> %2,530 iXLen %3)531 532 ret <vscale x 16 x float> %a533}534 535define <vscale x 1 x double> @intrinsic_vcompress_vm_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {536; CHECK-LABEL: intrinsic_vcompress_vm_nxv1f64_nxv1f64:537; CHECK: # %bb.0: # %entry538; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma539; CHECK-NEXT: vcompress.vm v8, v9, v0540; CHECK-NEXT: ret541entry:542 %a = call <vscale x 1 x double> @llvm.riscv.vcompress.nxv1f64(543 <vscale x 1 x double> %0,544 <vscale x 1 x double> %1,545 <vscale x 1 x i1> %2,546 iXLen %3)547 548 ret <vscale x 1 x double> %a549}550 551define <vscale x 2 x double> @intrinsic_vcompress_vm_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {552; CHECK-LABEL: intrinsic_vcompress_vm_nxv2f64_nxv2f64:553; CHECK: # %bb.0: # %entry554; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma555; CHECK-NEXT: vcompress.vm v8, v10, v0556; CHECK-NEXT: ret557entry:558 %a = call <vscale x 2 x double> @llvm.riscv.vcompress.nxv2f64(559 <vscale x 2 x double> %0,560 <vscale x 2 x double> %1,561 <vscale x 2 x i1> %2,562 iXLen %3)563 564 ret <vscale x 2 x double> %a565}566 567define <vscale x 4 x double> @intrinsic_vcompress_vm_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {568; CHECK-LABEL: intrinsic_vcompress_vm_nxv4f64_nxv4f64:569; CHECK: # %bb.0: # %entry570; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma571; CHECK-NEXT: vcompress.vm v8, v12, v0572; CHECK-NEXT: ret573entry:574 %a = call <vscale x 4 x double> @llvm.riscv.vcompress.nxv4f64(575 <vscale x 4 x double> %0,576 <vscale x 4 x double> %1,577 <vscale x 4 x i1> %2,578 iXLen %3)579 580 ret <vscale x 4 x double> %a581}582 583define <vscale x 8 x double> @intrinsic_vcompress_vm_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {584; CHECK-LABEL: intrinsic_vcompress_vm_nxv8f64_nxv8f64:585; CHECK: # %bb.0: # %entry586; CHECK-NEXT: vsetvli zero, a0, e64, m8, tu, ma587; CHECK-NEXT: vcompress.vm v8, v16, v0588; CHECK-NEXT: ret589entry:590 %a = call <vscale x 8 x double> @llvm.riscv.vcompress.nxv8f64(591 <vscale x 8 x double> %0,592 <vscale x 8 x double> %1,593 <vscale x 8 x i1> %2,594 iXLen %3)595 596 ret <vscale x 8 x double> %a597}598 599define <vscale x 1 x bfloat> @intrinsic_vcompress_vm_nxv1bf16(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {600; CHECK-LABEL: intrinsic_vcompress_vm_nxv1bf16:601; CHECK: # %bb.0: # %entry602; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma603; CHECK-NEXT: vcompress.vm v8, v9, v0604; CHECK-NEXT: ret605entry:606 %a = call <vscale x 1 x bfloat> @llvm.riscv.vcompress.nxv1bf16(607 <vscale x 1 x bfloat> %0,608 <vscale x 1 x bfloat> %1,609 <vscale x 1 x i1> %2,610 iXLen %3)611 612 ret <vscale x 1 x bfloat> %a613}614 615define <vscale x 2 x bfloat> @intrinsic_vcompress_vm_nxv2bf16(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {616; CHECK-LABEL: intrinsic_vcompress_vm_nxv2bf16:617; CHECK: # %bb.0: # %entry618; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma619; CHECK-NEXT: vcompress.vm v8, v9, v0620; CHECK-NEXT: ret621entry:622 %a = call <vscale x 2 x bfloat> @llvm.riscv.vcompress.nxv2bf16(623 <vscale x 2 x bfloat> %0,624 <vscale x 2 x bfloat> %1,625 <vscale x 2 x i1> %2,626 iXLen %3)627 628 ret <vscale x 2 x bfloat> %a629}630 631define <vscale x 4 x bfloat> @intrinsic_vcompress_vm_nxv4bf16(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {632; CHECK-LABEL: intrinsic_vcompress_vm_nxv4bf16:633; CHECK: # %bb.0: # %entry634; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma635; CHECK-NEXT: vcompress.vm v8, v9, v0636; CHECK-NEXT: ret637entry:638 %a = call <vscale x 4 x bfloat> @llvm.riscv.vcompress.nxv4bf16(639 <vscale x 4 x bfloat> %0,640 <vscale x 4 x bfloat> %1,641 <vscale x 4 x i1> %2,642 iXLen %3)643 644 ret <vscale x 4 x bfloat> %a645}646 647define <vscale x 8 x bfloat> @intrinsic_vcompress_vm_nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {648; CHECK-LABEL: intrinsic_vcompress_vm_nxv8bf16:649; CHECK: # %bb.0: # %entry650; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma651; CHECK-NEXT: vcompress.vm v8, v10, v0652; CHECK-NEXT: ret653entry:654 %a = call <vscale x 8 x bfloat> @llvm.riscv.vcompress.nxv8bf16(655 <vscale x 8 x bfloat> %0,656 <vscale x 8 x bfloat> %1,657 <vscale x 8 x i1> %2,658 iXLen %3)659 660 ret <vscale x 8 x bfloat> %a661}662 663define <vscale x 16 x bfloat> @intrinsic_vcompress_vm_nxv16bf16(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {664; CHECK-LABEL: intrinsic_vcompress_vm_nxv16bf16:665; CHECK: # %bb.0: # %entry666; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma667; CHECK-NEXT: vcompress.vm v8, v12, v0668; CHECK-NEXT: ret669entry:670 %a = call <vscale x 16 x bfloat> @llvm.riscv.vcompress.nxv16bf16(671 <vscale x 16 x bfloat> %0,672 <vscale x 16 x bfloat> %1,673 <vscale x 16 x i1> %2,674 iXLen %3)675 676 ret <vscale x 16 x bfloat> %a677}678 679define <vscale x 32 x bfloat> @intrinsic_vcompress_vm_nxv32bf16(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {680; CHECK-LABEL: intrinsic_vcompress_vm_nxv32bf16:681; CHECK: # %bb.0: # %entry682; CHECK-NEXT: vsetvli zero, a0, e16, m8, tu, ma683; CHECK-NEXT: vcompress.vm v8, v16, v0684; CHECK-NEXT: ret685entry:686 %a = call <vscale x 32 x bfloat> @llvm.riscv.vcompress.nxv32bf16(687 <vscale x 32 x bfloat> %0,688 <vscale x 32 x bfloat> %1,689 <vscale x 32 x i1> %2,690 iXLen %3)691 692 ret <vscale x 32 x bfloat> %a693}694 695