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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zvfbfmin,+v -target-abi=ilp32d \3; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH4; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zvfbfmin,+v -target-abi=lp64d \5; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH6; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+zvfbfmin,+v -target-abi=ilp32d \7; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN8; RUN: llc -mtriple=riscv64 -mattr=+d,+zfhmin,+zvfhmin,+zvfbfmin,+v -target-abi=lp64d \9; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN10; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+experimental-zvfbfa,+v -target-abi=ilp32d \11; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFBFA12; RUN: llc -mtriple=riscv64 -mattr=+d,+zfhmin,+zvfhmin,+experimental-zvfbfa,+v -target-abi=lp64d \13; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFBFA14 15define <vscale x 1 x bfloat> @vfsgnj_vv_nxv1bf16(<vscale x 1 x bfloat> %va, <vscale x 1 x bfloat> %vb, <vscale x 1 x i1> %m, i32 zeroext %evl) {16; ZVFH-LABEL: vfsgnj_vv_nxv1bf16:17; ZVFH: # %bb.0:18; ZVFH-NEXT: lui a1, 819; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma20; ZVFH-NEXT: vand.vx v9, v9, a1, v0.t21; ZVFH-NEXT: addi a1, a1, -122; ZVFH-NEXT: vand.vx v8, v8, a1, v0.t23; ZVFH-NEXT: vor.vv v8, v8, v9, v0.t24; ZVFH-NEXT: ret25;26; ZVFHMIN-LABEL: vfsgnj_vv_nxv1bf16:27; ZVFHMIN: # %bb.0:28; ZVFHMIN-NEXT: lui a1, 829; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma30; ZVFHMIN-NEXT: vand.vx v9, v9, a1, v0.t31; ZVFHMIN-NEXT: addi a1, a1, -132; ZVFHMIN-NEXT: vand.vx v8, v8, a1, v0.t33; ZVFHMIN-NEXT: vor.vv v8, v8, v9, v0.t34; ZVFHMIN-NEXT: ret35;36; ZVFBFA-LABEL: vfsgnj_vv_nxv1bf16:37; ZVFBFA: # %bb.0:38; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, mf4, ta, ma39; ZVFBFA-NEXT: vfsgnj.vv v8, v8, v9, v0.t40; ZVFBFA-NEXT: ret41 %v = call <vscale x 1 x bfloat> @llvm.vp.copysign.nxv1bf16(<vscale x 1 x bfloat> %va, <vscale x 1 x bfloat> %vb, <vscale x 1 x i1> %m, i32 %evl)42 ret <vscale x 1 x bfloat> %v43}44 45define <vscale x 1 x bfloat> @vfsgnj_vv_nxv1bf16_unmasked(<vscale x 1 x bfloat> %va, <vscale x 1 x bfloat> %vb, i32 zeroext %evl) {46; ZVFH-LABEL: vfsgnj_vv_nxv1bf16_unmasked:47; ZVFH: # %bb.0:48; ZVFH-NEXT: lui a1, 849; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma50; ZVFH-NEXT: vand.vx v9, v9, a151; ZVFH-NEXT: addi a1, a1, -152; ZVFH-NEXT: vand.vx v8, v8, a153; ZVFH-NEXT: vor.vv v8, v8, v954; ZVFH-NEXT: ret55;56; ZVFHMIN-LABEL: vfsgnj_vv_nxv1bf16_unmasked:57; ZVFHMIN: # %bb.0:58; ZVFHMIN-NEXT: lui a1, 859; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma60; ZVFHMIN-NEXT: vand.vx v9, v9, a161; ZVFHMIN-NEXT: addi a1, a1, -162; ZVFHMIN-NEXT: vand.vx v8, v8, a163; ZVFHMIN-NEXT: vor.vv v8, v8, v964; ZVFHMIN-NEXT: ret65;66; ZVFBFA-LABEL: vfsgnj_vv_nxv1bf16_unmasked:67; ZVFBFA: # %bb.0:68; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, mf4, ta, ma69; ZVFBFA-NEXT: vfsgnj.vv v8, v8, v970; ZVFBFA-NEXT: ret71 %v = call <vscale x 1 x bfloat> @llvm.vp.copysign.nxv1bf16(<vscale x 1 x bfloat> %va, <vscale x 1 x bfloat> %vb, <vscale x 1 x i1> splat (i1 true), i32 %evl)72 ret <vscale x 1 x bfloat> %v73}74 75define <vscale x 2 x bfloat> @vfsgnj_vv_nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x bfloat> %vb, <vscale x 2 x i1> %m, i32 zeroext %evl) {76; ZVFH-LABEL: vfsgnj_vv_nxv2bf16:77; ZVFH: # %bb.0:78; ZVFH-NEXT: lui a1, 879; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma80; ZVFH-NEXT: vand.vx v9, v9, a1, v0.t81; ZVFH-NEXT: addi a1, a1, -182; ZVFH-NEXT: vand.vx v8, v8, a1, v0.t83; ZVFH-NEXT: vor.vv v8, v8, v9, v0.t84; ZVFH-NEXT: ret85;86; ZVFHMIN-LABEL: vfsgnj_vv_nxv2bf16:87; ZVFHMIN: # %bb.0:88; ZVFHMIN-NEXT: lui a1, 889; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma90; ZVFHMIN-NEXT: vand.vx v9, v9, a1, v0.t91; ZVFHMIN-NEXT: addi a1, a1, -192; ZVFHMIN-NEXT: vand.vx v8, v8, a1, v0.t93; ZVFHMIN-NEXT: vor.vv v8, v8, v9, v0.t94; ZVFHMIN-NEXT: ret95;96; ZVFBFA-LABEL: vfsgnj_vv_nxv2bf16:97; ZVFBFA: # %bb.0:98; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, mf2, ta, ma99; ZVFBFA-NEXT: vfsgnj.vv v8, v8, v9, v0.t100; ZVFBFA-NEXT: ret101 %v = call <vscale x 2 x bfloat> @llvm.vp.copysign.nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x bfloat> %vb, <vscale x 2 x i1> %m, i32 %evl)102 ret <vscale x 2 x bfloat> %v103}104 105define <vscale x 2 x bfloat> @vfsgnj_vv_nxv2bf16_unmasked(<vscale x 2 x bfloat> %va, <vscale x 2 x bfloat> %vb, i32 zeroext %evl) {106; ZVFH-LABEL: vfsgnj_vv_nxv2bf16_unmasked:107; ZVFH: # %bb.0:108; ZVFH-NEXT: lui a1, 8109; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma110; ZVFH-NEXT: vand.vx v9, v9, a1111; ZVFH-NEXT: addi a1, a1, -1112; ZVFH-NEXT: vand.vx v8, v8, a1113; ZVFH-NEXT: vor.vv v8, v8, v9114; ZVFH-NEXT: ret115;116; ZVFHMIN-LABEL: vfsgnj_vv_nxv2bf16_unmasked:117; ZVFHMIN: # %bb.0:118; ZVFHMIN-NEXT: lui a1, 8119; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma120; ZVFHMIN-NEXT: vand.vx v9, v9, a1121; ZVFHMIN-NEXT: addi a1, a1, -1122; ZVFHMIN-NEXT: vand.vx v8, v8, a1123; ZVFHMIN-NEXT: vor.vv v8, v8, v9124; ZVFHMIN-NEXT: ret125;126; ZVFBFA-LABEL: vfsgnj_vv_nxv2bf16_unmasked:127; ZVFBFA: # %bb.0:128; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, mf2, ta, ma129; ZVFBFA-NEXT: vfsgnj.vv v8, v8, v9130; ZVFBFA-NEXT: ret131 %v = call <vscale x 2 x bfloat> @llvm.vp.copysign.nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x bfloat> %vb, <vscale x 2 x i1> splat (i1 true), i32 %evl)132 ret <vscale x 2 x bfloat> %v133}134 135define <vscale x 4 x bfloat> @vfsgnj_vv_nxv4bf16(<vscale x 4 x bfloat> %va, <vscale x 4 x bfloat> %vb, <vscale x 4 x i1> %m, i32 zeroext %evl) {136; ZVFH-LABEL: vfsgnj_vv_nxv4bf16:137; ZVFH: # %bb.0:138; ZVFH-NEXT: lui a1, 8139; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma140; ZVFH-NEXT: vand.vx v9, v9, a1, v0.t141; ZVFH-NEXT: addi a1, a1, -1142; ZVFH-NEXT: vand.vx v8, v8, a1, v0.t143; ZVFH-NEXT: vor.vv v8, v8, v9, v0.t144; ZVFH-NEXT: ret145;146; ZVFHMIN-LABEL: vfsgnj_vv_nxv4bf16:147; ZVFHMIN: # %bb.0:148; ZVFHMIN-NEXT: lui a1, 8149; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma150; ZVFHMIN-NEXT: vand.vx v9, v9, a1, v0.t151; ZVFHMIN-NEXT: addi a1, a1, -1152; ZVFHMIN-NEXT: vand.vx v8, v8, a1, v0.t153; ZVFHMIN-NEXT: vor.vv v8, v8, v9, v0.t154; ZVFHMIN-NEXT: ret155;156; ZVFBFA-LABEL: vfsgnj_vv_nxv4bf16:157; ZVFBFA: # %bb.0:158; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, m1, ta, ma159; ZVFBFA-NEXT: vfsgnj.vv v8, v8, v9, v0.t160; ZVFBFA-NEXT: ret161 %v = call <vscale x 4 x bfloat> @llvm.vp.copysign.nxv4bf16(<vscale x 4 x bfloat> %va, <vscale x 4 x bfloat> %vb, <vscale x 4 x i1> %m, i32 %evl)162 ret <vscale x 4 x bfloat> %v163}164 165define <vscale x 4 x bfloat> @vfsgnj_vv_nxv4bf16_unmasked(<vscale x 4 x bfloat> %va, <vscale x 4 x bfloat> %vb, i32 zeroext %evl) {166; ZVFH-LABEL: vfsgnj_vv_nxv4bf16_unmasked:167; ZVFH: # %bb.0:168; ZVFH-NEXT: lui a1, 8169; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma170; ZVFH-NEXT: vand.vx v9, v9, a1171; ZVFH-NEXT: addi a1, a1, -1172; ZVFH-NEXT: vand.vx v8, v8, a1173; ZVFH-NEXT: vor.vv v8, v8, v9174; ZVFH-NEXT: ret175;176; ZVFHMIN-LABEL: vfsgnj_vv_nxv4bf16_unmasked:177; ZVFHMIN: # %bb.0:178; ZVFHMIN-NEXT: lui a1, 8179; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma180; ZVFHMIN-NEXT: vand.vx v9, v9, a1181; ZVFHMIN-NEXT: addi a1, a1, -1182; ZVFHMIN-NEXT: vand.vx v8, v8, a1183; ZVFHMIN-NEXT: vor.vv v8, v8, v9184; ZVFHMIN-NEXT: ret185;186; ZVFBFA-LABEL: vfsgnj_vv_nxv4bf16_unmasked:187; ZVFBFA: # %bb.0:188; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, m1, ta, ma189; ZVFBFA-NEXT: vfsgnj.vv v8, v8, v9190; ZVFBFA-NEXT: ret191 %v = call <vscale x 4 x bfloat> @llvm.vp.copysign.nxv4bf16(<vscale x 4 x bfloat> %va, <vscale x 4 x bfloat> %vb, <vscale x 4 x i1> splat (i1 true), i32 %evl)192 ret <vscale x 4 x bfloat> %v193}194 195define <vscale x 8 x bfloat> @vfsgnj_vv_nxv8bf16(<vscale x 8 x bfloat> %va, <vscale x 8 x bfloat> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) {196; ZVFH-LABEL: vfsgnj_vv_nxv8bf16:197; ZVFH: # %bb.0:198; ZVFH-NEXT: lui a1, 8199; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma200; ZVFH-NEXT: vand.vx v10, v10, a1, v0.t201; ZVFH-NEXT: addi a1, a1, -1202; ZVFH-NEXT: vand.vx v8, v8, a1, v0.t203; ZVFH-NEXT: vor.vv v8, v8, v10, v0.t204; ZVFH-NEXT: ret205;206; ZVFHMIN-LABEL: vfsgnj_vv_nxv8bf16:207; ZVFHMIN: # %bb.0:208; ZVFHMIN-NEXT: lui a1, 8209; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma210; ZVFHMIN-NEXT: vand.vx v10, v10, a1, v0.t211; ZVFHMIN-NEXT: addi a1, a1, -1212; ZVFHMIN-NEXT: vand.vx v8, v8, a1, v0.t213; ZVFHMIN-NEXT: vor.vv v8, v8, v10, v0.t214; ZVFHMIN-NEXT: ret215;216; ZVFBFA-LABEL: vfsgnj_vv_nxv8bf16:217; ZVFBFA: # %bb.0:218; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, m2, ta, ma219; ZVFBFA-NEXT: vfsgnj.vv v8, v8, v10, v0.t220; ZVFBFA-NEXT: ret221 %v = call <vscale x 8 x bfloat> @llvm.vp.copysign.nxv8bf16(<vscale x 8 x bfloat> %va, <vscale x 8 x bfloat> %vb, <vscale x 8 x i1> %m, i32 %evl)222 ret <vscale x 8 x bfloat> %v223}224 225define <vscale x 8 x bfloat> @vfsgnj_vv_nxv8bf16_unmasked(<vscale x 8 x bfloat> %va, <vscale x 8 x bfloat> %vb, i32 zeroext %evl) {226; ZVFH-LABEL: vfsgnj_vv_nxv8bf16_unmasked:227; ZVFH: # %bb.0:228; ZVFH-NEXT: lui a1, 8229; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma230; ZVFH-NEXT: vand.vx v10, v10, a1231; ZVFH-NEXT: addi a1, a1, -1232; ZVFH-NEXT: vand.vx v8, v8, a1233; ZVFH-NEXT: vor.vv v8, v8, v10234; ZVFH-NEXT: ret235;236; ZVFHMIN-LABEL: vfsgnj_vv_nxv8bf16_unmasked:237; ZVFHMIN: # %bb.0:238; ZVFHMIN-NEXT: lui a1, 8239; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma240; ZVFHMIN-NEXT: vand.vx v10, v10, a1241; ZVFHMIN-NEXT: addi a1, a1, -1242; ZVFHMIN-NEXT: vand.vx v8, v8, a1243; ZVFHMIN-NEXT: vor.vv v8, v8, v10244; ZVFHMIN-NEXT: ret245;246; ZVFBFA-LABEL: vfsgnj_vv_nxv8bf16_unmasked:247; ZVFBFA: # %bb.0:248; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, m2, ta, ma249; ZVFBFA-NEXT: vfsgnj.vv v8, v8, v10250; ZVFBFA-NEXT: ret251 %v = call <vscale x 8 x bfloat> @llvm.vp.copysign.nxv8bf16(<vscale x 8 x bfloat> %va, <vscale x 8 x bfloat> %vb, <vscale x 8 x i1> splat (i1 true), i32 %evl)252 ret <vscale x 8 x bfloat> %v253}254 255define <vscale x 16 x bfloat> @vfsgnj_vv_nxv16bf16(<vscale x 16 x bfloat> %va, <vscale x 16 x bfloat> %vb, <vscale x 16 x i1> %m, i32 zeroext %evl) {256; ZVFH-LABEL: vfsgnj_vv_nxv16bf16:257; ZVFH: # %bb.0:258; ZVFH-NEXT: lui a1, 8259; ZVFH-NEXT: vsetvli zero, a0, e16, m4, ta, ma260; ZVFH-NEXT: vand.vx v12, v12, a1, v0.t261; ZVFH-NEXT: addi a1, a1, -1262; ZVFH-NEXT: vand.vx v8, v8, a1, v0.t263; ZVFH-NEXT: vor.vv v8, v8, v12, v0.t264; ZVFH-NEXT: ret265;266; ZVFHMIN-LABEL: vfsgnj_vv_nxv16bf16:267; ZVFHMIN: # %bb.0:268; ZVFHMIN-NEXT: lui a1, 8269; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma270; ZVFHMIN-NEXT: vand.vx v12, v12, a1, v0.t271; ZVFHMIN-NEXT: addi a1, a1, -1272; ZVFHMIN-NEXT: vand.vx v8, v8, a1, v0.t273; ZVFHMIN-NEXT: vor.vv v8, v8, v12, v0.t274; ZVFHMIN-NEXT: ret275;276; ZVFBFA-LABEL: vfsgnj_vv_nxv16bf16:277; ZVFBFA: # %bb.0:278; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, m4, ta, ma279; ZVFBFA-NEXT: vfsgnj.vv v8, v8, v12, v0.t280; ZVFBFA-NEXT: ret281 %v = call <vscale x 16 x bfloat> @llvm.vp.copysign.nxv16bf16(<vscale x 16 x bfloat> %va, <vscale x 16 x bfloat> %vb, <vscale x 16 x i1> %m, i32 %evl)282 ret <vscale x 16 x bfloat> %v283}284 285define <vscale x 16 x bfloat> @vfsgnj_vv_nxv16bf16_unmasked(<vscale x 16 x bfloat> %va, <vscale x 16 x bfloat> %vb, i32 zeroext %evl) {286; ZVFH-LABEL: vfsgnj_vv_nxv16bf16_unmasked:287; ZVFH: # %bb.0:288; ZVFH-NEXT: lui a1, 8289; ZVFH-NEXT: vsetvli zero, a0, e16, m4, ta, ma290; ZVFH-NEXT: vand.vx v12, v12, a1291; ZVFH-NEXT: addi a1, a1, -1292; ZVFH-NEXT: vand.vx v8, v8, a1293; ZVFH-NEXT: vor.vv v8, v8, v12294; ZVFH-NEXT: ret295;296; ZVFHMIN-LABEL: vfsgnj_vv_nxv16bf16_unmasked:297; ZVFHMIN: # %bb.0:298; ZVFHMIN-NEXT: lui a1, 8299; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma300; ZVFHMIN-NEXT: vand.vx v12, v12, a1301; ZVFHMIN-NEXT: addi a1, a1, -1302; ZVFHMIN-NEXT: vand.vx v8, v8, a1303; ZVFHMIN-NEXT: vor.vv v8, v8, v12304; ZVFHMIN-NEXT: ret305;306; ZVFBFA-LABEL: vfsgnj_vv_nxv16bf16_unmasked:307; ZVFBFA: # %bb.0:308; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, m4, ta, ma309; ZVFBFA-NEXT: vfsgnj.vv v8, v8, v12310; ZVFBFA-NEXT: ret311 %v = call <vscale x 16 x bfloat> @llvm.vp.copysign.nxv16bf16(<vscale x 16 x bfloat> %va, <vscale x 16 x bfloat> %vb, <vscale x 16 x i1> splat (i1 true), i32 %evl)312 ret <vscale x 16 x bfloat> %v313}314 315define <vscale x 32 x bfloat> @vfsgnj_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <vscale x 32 x bfloat> %vb, <vscale x 32 x i1> %m, i32 zeroext %evl) {316; ZVFH-LABEL: vfsgnj_vv_nxv32bf16:317; ZVFH: # %bb.0:318; ZVFH-NEXT: lui a1, 8319; ZVFH-NEXT: vsetvli zero, a0, e16, m8, ta, ma320; ZVFH-NEXT: vand.vx v16, v16, a1, v0.t321; ZVFH-NEXT: addi a1, a1, -1322; ZVFH-NEXT: vand.vx v8, v8, a1, v0.t323; ZVFH-NEXT: vor.vv v8, v8, v16, v0.t324; ZVFH-NEXT: ret325;326; ZVFHMIN-LABEL: vfsgnj_vv_nxv32bf16:327; ZVFHMIN: # %bb.0:328; ZVFHMIN-NEXT: lui a1, 8329; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma330; ZVFHMIN-NEXT: vand.vx v16, v16, a1, v0.t331; ZVFHMIN-NEXT: addi a1, a1, -1332; ZVFHMIN-NEXT: vand.vx v8, v8, a1, v0.t333; ZVFHMIN-NEXT: vor.vv v8, v8, v16, v0.t334; ZVFHMIN-NEXT: ret335;336; ZVFBFA-LABEL: vfsgnj_vv_nxv32bf16:337; ZVFBFA: # %bb.0:338; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, m8, ta, ma339; ZVFBFA-NEXT: vfsgnj.vv v8, v8, v16, v0.t340; ZVFBFA-NEXT: ret341 %v = call <vscale x 32 x bfloat> @llvm.vp.copysign.nxv32bf16(<vscale x 32 x bfloat> %va, <vscale x 32 x bfloat> %vb, <vscale x 32 x i1> %m, i32 %evl)342 ret <vscale x 32 x bfloat> %v343}344 345define <vscale x 32 x bfloat> @vfsgnj_vv_nxv32bf16_unmasked(<vscale x 32 x bfloat> %va, <vscale x 32 x bfloat> %vb, i32 zeroext %evl) {346; ZVFH-LABEL: vfsgnj_vv_nxv32bf16_unmasked:347; ZVFH: # %bb.0:348; ZVFH-NEXT: lui a1, 8349; ZVFH-NEXT: vsetvli zero, a0, e16, m8, ta, ma350; ZVFH-NEXT: vand.vx v16, v16, a1351; ZVFH-NEXT: addi a1, a1, -1352; ZVFH-NEXT: vand.vx v8, v8, a1353; ZVFH-NEXT: vor.vv v8, v8, v16354; ZVFH-NEXT: ret355;356; ZVFHMIN-LABEL: vfsgnj_vv_nxv32bf16_unmasked:357; ZVFHMIN: # %bb.0:358; ZVFHMIN-NEXT: lui a1, 8359; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma360; ZVFHMIN-NEXT: vand.vx v16, v16, a1361; ZVFHMIN-NEXT: addi a1, a1, -1362; ZVFHMIN-NEXT: vand.vx v8, v8, a1363; ZVFHMIN-NEXT: vor.vv v8, v8, v16364; ZVFHMIN-NEXT: ret365;366; ZVFBFA-LABEL: vfsgnj_vv_nxv32bf16_unmasked:367; ZVFBFA: # %bb.0:368; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, m8, ta, ma369; ZVFBFA-NEXT: vfsgnj.vv v8, v8, v16370; ZVFBFA-NEXT: ret371 %v = call <vscale x 32 x bfloat> @llvm.vp.copysign.nxv32bf16(<vscale x 32 x bfloat> %va, <vscale x 32 x bfloat> %vb, <vscale x 32 x i1> splat (i1 true), i32 %evl)372 ret <vscale x 32 x bfloat> %v373}374 375define <vscale x 1 x half> @vfsgnj_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, <vscale x 1 x i1> %m, i32 zeroext %evl) {376; ZVFH-LABEL: vfsgnj_vv_nxv1f16:377; ZVFH: # %bb.0:378; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma379; ZVFH-NEXT: vfsgnj.vv v8, v8, v9, v0.t380; ZVFH-NEXT: ret381;382; ZVFHMIN-LABEL: vfsgnj_vv_nxv1f16:383; ZVFHMIN: # %bb.0:384; ZVFHMIN-NEXT: lui a1, 8385; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma386; ZVFHMIN-NEXT: vand.vx v9, v9, a1, v0.t387; ZVFHMIN-NEXT: addi a1, a1, -1388; ZVFHMIN-NEXT: vand.vx v8, v8, a1, v0.t389; ZVFHMIN-NEXT: vor.vv v8, v8, v9, v0.t390; ZVFHMIN-NEXT: ret391;392; ZVFBFA-LABEL: vfsgnj_vv_nxv1f16:393; ZVFBFA: # %bb.0:394; ZVFBFA-NEXT: lui a1, 8395; ZVFBFA-NEXT: vsetvli zero, a0, e16, mf4, ta, ma396; ZVFBFA-NEXT: vand.vx v9, v9, a1, v0.t397; ZVFBFA-NEXT: addi a1, a1, -1398; ZVFBFA-NEXT: vand.vx v8, v8, a1, v0.t399; ZVFBFA-NEXT: vor.vv v8, v8, v9, v0.t400; ZVFBFA-NEXT: ret401 %v = call <vscale x 1 x half> @llvm.vp.copysign.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, <vscale x 1 x i1> %m, i32 %evl)402 ret <vscale x 1 x half> %v403}404 405define <vscale x 1 x half> @vfsgnj_vv_nxv1f16_unmasked(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, i32 zeroext %evl) {406; ZVFH-LABEL: vfsgnj_vv_nxv1f16_unmasked:407; ZVFH: # %bb.0:408; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma409; ZVFH-NEXT: vfsgnj.vv v8, v8, v9410; ZVFH-NEXT: ret411;412; ZVFHMIN-LABEL: vfsgnj_vv_nxv1f16_unmasked:413; ZVFHMIN: # %bb.0:414; ZVFHMIN-NEXT: lui a1, 8415; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma416; ZVFHMIN-NEXT: vand.vx v9, v9, a1417; ZVFHMIN-NEXT: addi a1, a1, -1418; ZVFHMIN-NEXT: vand.vx v8, v8, a1419; ZVFHMIN-NEXT: vor.vv v8, v8, v9420; ZVFHMIN-NEXT: ret421;422; ZVFBFA-LABEL: vfsgnj_vv_nxv1f16_unmasked:423; ZVFBFA: # %bb.0:424; ZVFBFA-NEXT: lui a1, 8425; ZVFBFA-NEXT: vsetvli zero, a0, e16, mf4, ta, ma426; ZVFBFA-NEXT: vand.vx v9, v9, a1427; ZVFBFA-NEXT: addi a1, a1, -1428; ZVFBFA-NEXT: vand.vx v8, v8, a1429; ZVFBFA-NEXT: vor.vv v8, v8, v9430; ZVFBFA-NEXT: ret431 %v = call <vscale x 1 x half> @llvm.vp.copysign.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, <vscale x 1 x i1> splat (i1 true), i32 %evl)432 ret <vscale x 1 x half> %v433}434 435define <vscale x 2 x half> @vfsgnj_vv_nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x half> %vb, <vscale x 2 x i1> %m, i32 zeroext %evl) {436; ZVFH-LABEL: vfsgnj_vv_nxv2f16:437; ZVFH: # %bb.0:438; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma439; ZVFH-NEXT: vfsgnj.vv v8, v8, v9, v0.t440; ZVFH-NEXT: ret441;442; ZVFHMIN-LABEL: vfsgnj_vv_nxv2f16:443; ZVFHMIN: # %bb.0:444; ZVFHMIN-NEXT: lui a1, 8445; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma446; ZVFHMIN-NEXT: vand.vx v9, v9, a1, v0.t447; ZVFHMIN-NEXT: addi a1, a1, -1448; ZVFHMIN-NEXT: vand.vx v8, v8, a1, v0.t449; ZVFHMIN-NEXT: vor.vv v8, v8, v9, v0.t450; ZVFHMIN-NEXT: ret451;452; ZVFBFA-LABEL: vfsgnj_vv_nxv2f16:453; ZVFBFA: # %bb.0:454; ZVFBFA-NEXT: lui a1, 8455; ZVFBFA-NEXT: vsetvli zero, a0, e16, mf2, ta, ma456; ZVFBFA-NEXT: vand.vx v9, v9, a1, v0.t457; ZVFBFA-NEXT: addi a1, a1, -1458; ZVFBFA-NEXT: vand.vx v8, v8, a1, v0.t459; ZVFBFA-NEXT: vor.vv v8, v8, v9, v0.t460; ZVFBFA-NEXT: ret461 %v = call <vscale x 2 x half> @llvm.vp.copysign.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x half> %vb, <vscale x 2 x i1> %m, i32 %evl)462 ret <vscale x 2 x half> %v463}464 465define <vscale x 2 x half> @vfsgnj_vv_nxv2f16_unmasked(<vscale x 2 x half> %va, <vscale x 2 x half> %vb, i32 zeroext %evl) {466; ZVFH-LABEL: vfsgnj_vv_nxv2f16_unmasked:467; ZVFH: # %bb.0:468; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma469; ZVFH-NEXT: vfsgnj.vv v8, v8, v9470; ZVFH-NEXT: ret471;472; ZVFHMIN-LABEL: vfsgnj_vv_nxv2f16_unmasked:473; ZVFHMIN: # %bb.0:474; ZVFHMIN-NEXT: lui a1, 8475; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma476; ZVFHMIN-NEXT: vand.vx v9, v9, a1477; ZVFHMIN-NEXT: addi a1, a1, -1478; ZVFHMIN-NEXT: vand.vx v8, v8, a1479; ZVFHMIN-NEXT: vor.vv v8, v8, v9480; ZVFHMIN-NEXT: ret481;482; ZVFBFA-LABEL: vfsgnj_vv_nxv2f16_unmasked:483; ZVFBFA: # %bb.0:484; ZVFBFA-NEXT: lui a1, 8485; ZVFBFA-NEXT: vsetvli zero, a0, e16, mf2, ta, ma486; ZVFBFA-NEXT: vand.vx v9, v9, a1487; ZVFBFA-NEXT: addi a1, a1, -1488; ZVFBFA-NEXT: vand.vx v8, v8, a1489; ZVFBFA-NEXT: vor.vv v8, v8, v9490; ZVFBFA-NEXT: ret491 %v = call <vscale x 2 x half> @llvm.vp.copysign.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x half> %vb, <vscale x 2 x i1> splat (i1 true), i32 %evl)492 ret <vscale x 2 x half> %v493}494 495define <vscale x 4 x half> @vfsgnj_vv_nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x half> %vb, <vscale x 4 x i1> %m, i32 zeroext %evl) {496; ZVFH-LABEL: vfsgnj_vv_nxv4f16:497; ZVFH: # %bb.0:498; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma499; ZVFH-NEXT: vfsgnj.vv v8, v8, v9, v0.t500; ZVFH-NEXT: ret501;502; ZVFHMIN-LABEL: vfsgnj_vv_nxv4f16:503; ZVFHMIN: # %bb.0:504; ZVFHMIN-NEXT: lui a1, 8505; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma506; ZVFHMIN-NEXT: vand.vx v9, v9, a1, v0.t507; ZVFHMIN-NEXT: addi a1, a1, -1508; ZVFHMIN-NEXT: vand.vx v8, v8, a1, v0.t509; ZVFHMIN-NEXT: vor.vv v8, v8, v9, v0.t510; ZVFHMIN-NEXT: ret511;512; ZVFBFA-LABEL: vfsgnj_vv_nxv4f16:513; ZVFBFA: # %bb.0:514; ZVFBFA-NEXT: lui a1, 8515; ZVFBFA-NEXT: vsetvli zero, a0, e16, m1, ta, ma516; ZVFBFA-NEXT: vand.vx v9, v9, a1, v0.t517; ZVFBFA-NEXT: addi a1, a1, -1518; ZVFBFA-NEXT: vand.vx v8, v8, a1, v0.t519; ZVFBFA-NEXT: vor.vv v8, v8, v9, v0.t520; ZVFBFA-NEXT: ret521 %v = call <vscale x 4 x half> @llvm.vp.copysign.nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x half> %vb, <vscale x 4 x i1> %m, i32 %evl)522 ret <vscale x 4 x half> %v523}524 525define <vscale x 4 x half> @vfsgnj_vv_nxv4f16_unmasked(<vscale x 4 x half> %va, <vscale x 4 x half> %vb, i32 zeroext %evl) {526; ZVFH-LABEL: vfsgnj_vv_nxv4f16_unmasked:527; ZVFH: # %bb.0:528; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma529; ZVFH-NEXT: vfsgnj.vv v8, v8, v9530; ZVFH-NEXT: ret531;532; ZVFHMIN-LABEL: vfsgnj_vv_nxv4f16_unmasked:533; ZVFHMIN: # %bb.0:534; ZVFHMIN-NEXT: lui a1, 8535; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma536; ZVFHMIN-NEXT: vand.vx v9, v9, a1537; ZVFHMIN-NEXT: addi a1, a1, -1538; ZVFHMIN-NEXT: vand.vx v8, v8, a1539; ZVFHMIN-NEXT: vor.vv v8, v8, v9540; ZVFHMIN-NEXT: ret541;542; ZVFBFA-LABEL: vfsgnj_vv_nxv4f16_unmasked:543; ZVFBFA: # %bb.0:544; ZVFBFA-NEXT: lui a1, 8545; ZVFBFA-NEXT: vsetvli zero, a0, e16, m1, ta, ma546; ZVFBFA-NEXT: vand.vx v9, v9, a1547; ZVFBFA-NEXT: addi a1, a1, -1548; ZVFBFA-NEXT: vand.vx v8, v8, a1549; ZVFBFA-NEXT: vor.vv v8, v8, v9550; ZVFBFA-NEXT: ret551 %v = call <vscale x 4 x half> @llvm.vp.copysign.nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x half> %vb, <vscale x 4 x i1> splat (i1 true), i32 %evl)552 ret <vscale x 4 x half> %v553}554 555define <vscale x 8 x half> @vfsgnj_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) {556; ZVFH-LABEL: vfsgnj_vv_nxv8f16:557; ZVFH: # %bb.0:558; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma559; ZVFH-NEXT: vfsgnj.vv v8, v8, v10, v0.t560; ZVFH-NEXT: ret561;562; ZVFHMIN-LABEL: vfsgnj_vv_nxv8f16:563; ZVFHMIN: # %bb.0:564; ZVFHMIN-NEXT: lui a1, 8565; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma566; ZVFHMIN-NEXT: vand.vx v10, v10, a1, v0.t567; ZVFHMIN-NEXT: addi a1, a1, -1568; ZVFHMIN-NEXT: vand.vx v8, v8, a1, v0.t569; ZVFHMIN-NEXT: vor.vv v8, v8, v10, v0.t570; ZVFHMIN-NEXT: ret571;572; ZVFBFA-LABEL: vfsgnj_vv_nxv8f16:573; ZVFBFA: # %bb.0:574; ZVFBFA-NEXT: lui a1, 8575; ZVFBFA-NEXT: vsetvli zero, a0, e16, m2, ta, ma576; ZVFBFA-NEXT: vand.vx v10, v10, a1, v0.t577; ZVFBFA-NEXT: addi a1, a1, -1578; ZVFBFA-NEXT: vand.vx v8, v8, a1, v0.t579; ZVFBFA-NEXT: vor.vv v8, v8, v10, v0.t580; ZVFBFA-NEXT: ret581 %v = call <vscale x 8 x half> @llvm.vp.copysign.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, <vscale x 8 x i1> %m, i32 %evl)582 ret <vscale x 8 x half> %v583}584 585define <vscale x 8 x half> @vfsgnj_vv_nxv8f16_unmasked(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, i32 zeroext %evl) {586; ZVFH-LABEL: vfsgnj_vv_nxv8f16_unmasked:587; ZVFH: # %bb.0:588; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma589; ZVFH-NEXT: vfsgnj.vv v8, v8, v10590; ZVFH-NEXT: ret591;592; ZVFHMIN-LABEL: vfsgnj_vv_nxv8f16_unmasked:593; ZVFHMIN: # %bb.0:594; ZVFHMIN-NEXT: lui a1, 8595; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma596; ZVFHMIN-NEXT: vand.vx v10, v10, a1597; ZVFHMIN-NEXT: addi a1, a1, -1598; ZVFHMIN-NEXT: vand.vx v8, v8, a1599; ZVFHMIN-NEXT: vor.vv v8, v8, v10600; ZVFHMIN-NEXT: ret601;602; ZVFBFA-LABEL: vfsgnj_vv_nxv8f16_unmasked:603; ZVFBFA: # %bb.0:604; ZVFBFA-NEXT: lui a1, 8605; ZVFBFA-NEXT: vsetvli zero, a0, e16, m2, ta, ma606; ZVFBFA-NEXT: vand.vx v10, v10, a1607; ZVFBFA-NEXT: addi a1, a1, -1608; ZVFBFA-NEXT: vand.vx v8, v8, a1609; ZVFBFA-NEXT: vor.vv v8, v8, v10610; ZVFBFA-NEXT: ret611 %v = call <vscale x 8 x half> @llvm.vp.copysign.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, <vscale x 8 x i1> splat (i1 true), i32 %evl)612 ret <vscale x 8 x half> %v613}614 615define <vscale x 16 x half> @vfsgnj_vv_nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x half> %vb, <vscale x 16 x i1> %m, i32 zeroext %evl) {616; ZVFH-LABEL: vfsgnj_vv_nxv16f16:617; ZVFH: # %bb.0:618; ZVFH-NEXT: vsetvli zero, a0, e16, m4, ta, ma619; ZVFH-NEXT: vfsgnj.vv v8, v8, v12, v0.t620; ZVFH-NEXT: ret621;622; ZVFHMIN-LABEL: vfsgnj_vv_nxv16f16:623; ZVFHMIN: # %bb.0:624; ZVFHMIN-NEXT: lui a1, 8625; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma626; ZVFHMIN-NEXT: vand.vx v12, v12, a1, v0.t627; ZVFHMIN-NEXT: addi a1, a1, -1628; ZVFHMIN-NEXT: vand.vx v8, v8, a1, v0.t629; ZVFHMIN-NEXT: vor.vv v8, v8, v12, v0.t630; ZVFHMIN-NEXT: ret631;632; ZVFBFA-LABEL: vfsgnj_vv_nxv16f16:633; ZVFBFA: # %bb.0:634; ZVFBFA-NEXT: lui a1, 8635; ZVFBFA-NEXT: vsetvli zero, a0, e16, m4, ta, ma636; ZVFBFA-NEXT: vand.vx v12, v12, a1, v0.t637; ZVFBFA-NEXT: addi a1, a1, -1638; ZVFBFA-NEXT: vand.vx v8, v8, a1, v0.t639; ZVFBFA-NEXT: vor.vv v8, v8, v12, v0.t640; ZVFBFA-NEXT: ret641 %v = call <vscale x 16 x half> @llvm.vp.copysign.nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x half> %vb, <vscale x 16 x i1> %m, i32 %evl)642 ret <vscale x 16 x half> %v643}644 645define <vscale x 16 x half> @vfsgnj_vv_nxv16f16_unmasked(<vscale x 16 x half> %va, <vscale x 16 x half> %vb, i32 zeroext %evl) {646; ZVFH-LABEL: vfsgnj_vv_nxv16f16_unmasked:647; ZVFH: # %bb.0:648; ZVFH-NEXT: vsetvli zero, a0, e16, m4, ta, ma649; ZVFH-NEXT: vfsgnj.vv v8, v8, v12650; ZVFH-NEXT: ret651;652; ZVFHMIN-LABEL: vfsgnj_vv_nxv16f16_unmasked:653; ZVFHMIN: # %bb.0:654; ZVFHMIN-NEXT: lui a1, 8655; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma656; ZVFHMIN-NEXT: vand.vx v12, v12, a1657; ZVFHMIN-NEXT: addi a1, a1, -1658; ZVFHMIN-NEXT: vand.vx v8, v8, a1659; ZVFHMIN-NEXT: vor.vv v8, v8, v12660; ZVFHMIN-NEXT: ret661;662; ZVFBFA-LABEL: vfsgnj_vv_nxv16f16_unmasked:663; ZVFBFA: # %bb.0:664; ZVFBFA-NEXT: lui a1, 8665; ZVFBFA-NEXT: vsetvli zero, a0, e16, m4, ta, ma666; ZVFBFA-NEXT: vand.vx v12, v12, a1667; ZVFBFA-NEXT: addi a1, a1, -1668; ZVFBFA-NEXT: vand.vx v8, v8, a1669; ZVFBFA-NEXT: vor.vv v8, v8, v12670; ZVFBFA-NEXT: ret671 %v = call <vscale x 16 x half> @llvm.vp.copysign.nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x half> %vb, <vscale x 16 x i1> splat (i1 true), i32 %evl)672 ret <vscale x 16 x half> %v673}674 675define <vscale x 32 x half> @vfsgnj_vv_nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x half> %vb, <vscale x 32 x i1> %m, i32 zeroext %evl) {676; ZVFH-LABEL: vfsgnj_vv_nxv32f16:677; ZVFH: # %bb.0:678; ZVFH-NEXT: vsetvli zero, a0, e16, m8, ta, ma679; ZVFH-NEXT: vfsgnj.vv v8, v8, v16, v0.t680; ZVFH-NEXT: ret681;682; ZVFHMIN-LABEL: vfsgnj_vv_nxv32f16:683; ZVFHMIN: # %bb.0:684; ZVFHMIN-NEXT: lui a1, 8685; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma686; ZVFHMIN-NEXT: vand.vx v16, v16, a1, v0.t687; ZVFHMIN-NEXT: addi a1, a1, -1688; ZVFHMIN-NEXT: vand.vx v8, v8, a1, v0.t689; ZVFHMIN-NEXT: vor.vv v8, v8, v16, v0.t690; ZVFHMIN-NEXT: ret691;692; ZVFBFA-LABEL: vfsgnj_vv_nxv32f16:693; ZVFBFA: # %bb.0:694; ZVFBFA-NEXT: lui a1, 8695; ZVFBFA-NEXT: vsetvli zero, a0, e16, m8, ta, ma696; ZVFBFA-NEXT: vand.vx v16, v16, a1, v0.t697; ZVFBFA-NEXT: addi a1, a1, -1698; ZVFBFA-NEXT: vand.vx v8, v8, a1, v0.t699; ZVFBFA-NEXT: vor.vv v8, v8, v16, v0.t700; ZVFBFA-NEXT: ret701 %v = call <vscale x 32 x half> @llvm.vp.copysign.nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x half> %vb, <vscale x 32 x i1> %m, i32 %evl)702 ret <vscale x 32 x half> %v703}704 705define <vscale x 32 x half> @vfsgnj_vv_nxv32f16_unmasked(<vscale x 32 x half> %va, <vscale x 32 x half> %vb, i32 zeroext %evl) {706; ZVFH-LABEL: vfsgnj_vv_nxv32f16_unmasked:707; ZVFH: # %bb.0:708; ZVFH-NEXT: vsetvli zero, a0, e16, m8, ta, ma709; ZVFH-NEXT: vfsgnj.vv v8, v8, v16710; ZVFH-NEXT: ret711;712; ZVFHMIN-LABEL: vfsgnj_vv_nxv32f16_unmasked:713; ZVFHMIN: # %bb.0:714; ZVFHMIN-NEXT: lui a1, 8715; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma716; ZVFHMIN-NEXT: vand.vx v16, v16, a1717; ZVFHMIN-NEXT: addi a1, a1, -1718; ZVFHMIN-NEXT: vand.vx v8, v8, a1719; ZVFHMIN-NEXT: vor.vv v8, v8, v16720; ZVFHMIN-NEXT: ret721;722; ZVFBFA-LABEL: vfsgnj_vv_nxv32f16_unmasked:723; ZVFBFA: # %bb.0:724; ZVFBFA-NEXT: lui a1, 8725; ZVFBFA-NEXT: vsetvli zero, a0, e16, m8, ta, ma726; ZVFBFA-NEXT: vand.vx v16, v16, a1727; ZVFBFA-NEXT: addi a1, a1, -1728; ZVFBFA-NEXT: vand.vx v8, v8, a1729; ZVFBFA-NEXT: vor.vv v8, v8, v16730; ZVFBFA-NEXT: ret731 %v = call <vscale x 32 x half> @llvm.vp.copysign.nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x half> %vb, <vscale x 32 x i1> splat (i1 true), i32 %evl)732 ret <vscale x 32 x half> %v733}734 735define <vscale x 1 x float> @vfsgnj_vv_nxv1f32(<vscale x 1 x float> %va, <vscale x 1 x float> %vb, <vscale x 1 x i1> %m, i32 zeroext %evl) {736; CHECK-LABEL: vfsgnj_vv_nxv1f32:737; CHECK: # %bb.0:738; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma739; CHECK-NEXT: vfsgnj.vv v8, v8, v9, v0.t740; CHECK-NEXT: ret741 %v = call <vscale x 1 x float> @llvm.vp.copysign.nxv1f32(<vscale x 1 x float> %va, <vscale x 1 x float> %vb, <vscale x 1 x i1> %m, i32 %evl)742 ret <vscale x 1 x float> %v743}744 745define <vscale x 1 x float> @vfsgnj_vv_nxv1f32_unmasked(<vscale x 1 x float> %va, <vscale x 1 x float> %vb, i32 zeroext %evl) {746; CHECK-LABEL: vfsgnj_vv_nxv1f32_unmasked:747; CHECK: # %bb.0:748; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma749; CHECK-NEXT: vfsgnj.vv v8, v8, v9750; CHECK-NEXT: ret751 %v = call <vscale x 1 x float> @llvm.vp.copysign.nxv1f32(<vscale x 1 x float> %va, <vscale x 1 x float> %vb, <vscale x 1 x i1> splat (i1 true), i32 %evl)752 ret <vscale x 1 x float> %v753}754 755define <vscale x 2 x float> @vfsgnj_vv_nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x float> %vb, <vscale x 2 x i1> %m, i32 zeroext %evl) {756; CHECK-LABEL: vfsgnj_vv_nxv2f32:757; CHECK: # %bb.0:758; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma759; CHECK-NEXT: vfsgnj.vv v8, v8, v9, v0.t760; CHECK-NEXT: ret761 %v = call <vscale x 2 x float> @llvm.vp.copysign.nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x float> %vb, <vscale x 2 x i1> %m, i32 %evl)762 ret <vscale x 2 x float> %v763}764 765define <vscale x 2 x float> @vfsgnj_vv_nxv2f32_unmasked(<vscale x 2 x float> %va, <vscale x 2 x float> %vb, i32 zeroext %evl) {766; CHECK-LABEL: vfsgnj_vv_nxv2f32_unmasked:767; CHECK: # %bb.0:768; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma769; CHECK-NEXT: vfsgnj.vv v8, v8, v9770; CHECK-NEXT: ret771 %v = call <vscale x 2 x float> @llvm.vp.copysign.nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x float> %vb, <vscale x 2 x i1> splat (i1 true), i32 %evl)772 ret <vscale x 2 x float> %v773}774 775define <vscale x 4 x float> @vfsgnj_vv_nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x float> %vb, <vscale x 4 x i1> %m, i32 zeroext %evl) {776; CHECK-LABEL: vfsgnj_vv_nxv4f32:777; CHECK: # %bb.0:778; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma779; CHECK-NEXT: vfsgnj.vv v8, v8, v10, v0.t780; CHECK-NEXT: ret781 %v = call <vscale x 4 x float> @llvm.vp.copysign.nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x float> %vb, <vscale x 4 x i1> %m, i32 %evl)782 ret <vscale x 4 x float> %v783}784 785define <vscale x 4 x float> @vfsgnj_vv_nxv4f32_unmasked(<vscale x 4 x float> %va, <vscale x 4 x float> %vb, i32 zeroext %evl) {786; CHECK-LABEL: vfsgnj_vv_nxv4f32_unmasked:787; CHECK: # %bb.0:788; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma789; CHECK-NEXT: vfsgnj.vv v8, v8, v10790; CHECK-NEXT: ret791 %v = call <vscale x 4 x float> @llvm.vp.copysign.nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x float> %vb, <vscale x 4 x i1> splat (i1 true), i32 %evl)792 ret <vscale x 4 x float> %v793}794 795define <vscale x 8 x float> @vfsgnj_vv_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) {796; CHECK-LABEL: vfsgnj_vv_nxv8f32:797; CHECK: # %bb.0:798; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma799; CHECK-NEXT: vfsgnj.vv v8, v8, v12, v0.t800; CHECK-NEXT: ret801 %v = call <vscale x 8 x float> @llvm.vp.copysign.nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %vb, <vscale x 8 x i1> %m, i32 %evl)802 ret <vscale x 8 x float> %v803}804 805define <vscale x 8 x float> @vfsgnj_vv_nxv8f32_unmasked(<vscale x 8 x float> %va, <vscale x 8 x float> %vb, i32 zeroext %evl) {806; CHECK-LABEL: vfsgnj_vv_nxv8f32_unmasked:807; CHECK: # %bb.0:808; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma809; CHECK-NEXT: vfsgnj.vv v8, v8, v12810; CHECK-NEXT: ret811 %v = call <vscale x 8 x float> @llvm.vp.copysign.nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %vb, <vscale x 8 x i1> splat (i1 true), i32 %evl)812 ret <vscale x 8 x float> %v813}814 815define <vscale x 16 x float> @vfsgnj_vv_nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x float> %vb, <vscale x 16 x i1> %m, i32 zeroext %evl) {816; CHECK-LABEL: vfsgnj_vv_nxv16f32:817; CHECK: # %bb.0:818; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma819; CHECK-NEXT: vfsgnj.vv v8, v8, v16, v0.t820; CHECK-NEXT: ret821 %v = call <vscale x 16 x float> @llvm.vp.copysign.nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x float> %vb, <vscale x 16 x i1> %m, i32 %evl)822 ret <vscale x 16 x float> %v823}824 825define <vscale x 16 x float> @vfsgnj_vv_nxv16f32_unmasked(<vscale x 16 x float> %va, <vscale x 16 x float> %vb, i32 zeroext %evl) {826; CHECK-LABEL: vfsgnj_vv_nxv16f32_unmasked:827; CHECK: # %bb.0:828; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma829; CHECK-NEXT: vfsgnj.vv v8, v8, v16830; CHECK-NEXT: ret831 %v = call <vscale x 16 x float> @llvm.vp.copysign.nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x float> %vb, <vscale x 16 x i1> splat (i1 true), i32 %evl)832 ret <vscale x 16 x float> %v833}834 835define <vscale x 1 x double> @vfsgnj_vv_nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, <vscale x 1 x i1> %m, i32 zeroext %evl) {836; CHECK-LABEL: vfsgnj_vv_nxv1f64:837; CHECK: # %bb.0:838; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma839; CHECK-NEXT: vfsgnj.vv v8, v8, v9, v0.t840; CHECK-NEXT: ret841 %v = call <vscale x 1 x double> @llvm.vp.copysign.nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, <vscale x 1 x i1> %m, i32 %evl)842 ret <vscale x 1 x double> %v843}844 845define <vscale x 1 x double> @vfsgnj_vv_nxv1f64_unmasked(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, i32 zeroext %evl) {846; CHECK-LABEL: vfsgnj_vv_nxv1f64_unmasked:847; CHECK: # %bb.0:848; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma849; CHECK-NEXT: vfsgnj.vv v8, v8, v9850; CHECK-NEXT: ret851 %v = call <vscale x 1 x double> @llvm.vp.copysign.nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, <vscale x 1 x i1> splat (i1 true), i32 %evl)852 ret <vscale x 1 x double> %v853}854 855define <vscale x 2 x double> @vfsgnj_vv_nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x double> %vb, <vscale x 2 x i1> %m, i32 zeroext %evl) {856; CHECK-LABEL: vfsgnj_vv_nxv2f64:857; CHECK: # %bb.0:858; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma859; CHECK-NEXT: vfsgnj.vv v8, v8, v10, v0.t860; CHECK-NEXT: ret861 %v = call <vscale x 2 x double> @llvm.vp.copysign.nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x double> %vb, <vscale x 2 x i1> %m, i32 %evl)862 ret <vscale x 2 x double> %v863}864 865define <vscale x 2 x double> @vfsgnj_vv_nxv2f64_unmasked(<vscale x 2 x double> %va, <vscale x 2 x double> %vb, i32 zeroext %evl) {866; CHECK-LABEL: vfsgnj_vv_nxv2f64_unmasked:867; CHECK: # %bb.0:868; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma869; CHECK-NEXT: vfsgnj.vv v8, v8, v10870; CHECK-NEXT: ret871 %v = call <vscale x 2 x double> @llvm.vp.copysign.nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x double> %vb, <vscale x 2 x i1> splat (i1 true), i32 %evl)872 ret <vscale x 2 x double> %v873}874 875define <vscale x 4 x double> @vfsgnj_vv_nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x double> %vb, <vscale x 4 x i1> %m, i32 zeroext %evl) {876; CHECK-LABEL: vfsgnj_vv_nxv4f64:877; CHECK: # %bb.0:878; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma879; CHECK-NEXT: vfsgnj.vv v8, v8, v12, v0.t880; CHECK-NEXT: ret881 %v = call <vscale x 4 x double> @llvm.vp.copysign.nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x double> %vb, <vscale x 4 x i1> %m, i32 %evl)882 ret <vscale x 4 x double> %v883}884 885define <vscale x 4 x double> @vfsgnj_vv_nxv4f64_unmasked(<vscale x 4 x double> %va, <vscale x 4 x double> %vb, i32 zeroext %evl) {886; CHECK-LABEL: vfsgnj_vv_nxv4f64_unmasked:887; CHECK: # %bb.0:888; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma889; CHECK-NEXT: vfsgnj.vv v8, v8, v12890; CHECK-NEXT: ret891 %v = call <vscale x 4 x double> @llvm.vp.copysign.nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x double> %vb, <vscale x 4 x i1> splat (i1 true), i32 %evl)892 ret <vscale x 4 x double> %v893}894 895define <vscale x 8 x double> @vfsgnj_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) {896; CHECK-LABEL: vfsgnj_vv_nxv8f64:897; CHECK: # %bb.0:898; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma899; CHECK-NEXT: vfsgnj.vv v8, v8, v16, v0.t900; CHECK-NEXT: ret901 %v = call <vscale x 8 x double> @llvm.vp.copysign.nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, <vscale x 8 x i1> %m, i32 %evl)902 ret <vscale x 8 x double> %v903}904 905define <vscale x 8 x double> @vfsgnj_vv_nxv8f64_unmasked(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, i32 zeroext %evl) {906; CHECK-LABEL: vfsgnj_vv_nxv8f64_unmasked:907; CHECK: # %bb.0:908; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma909; CHECK-NEXT: vfsgnj.vv v8, v8, v16910; CHECK-NEXT: ret911 %v = call <vscale x 8 x double> @llvm.vp.copysign.nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, <vscale x 8 x i1> splat (i1 true), i32 %evl)912 ret <vscale x 8 x double> %v913}914