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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32-V3; RUN: llc -mtriple=riscv32 -mattr=+zve64x -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,ZVE64X4; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64-V5; RUN: llc -mtriple=riscv64 -mattr=+zve64x -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,ZVE64X6 7define <vscale x 1 x i8> @vdiv_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) {8; CHECK-LABEL: vdiv_vv_nxv1i8:9; CHECK: # %bb.0:10; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma11; CHECK-NEXT: vdiv.vv v8, v8, v912; CHECK-NEXT: ret13 %vc = sdiv <vscale x 1 x i8> %va, %vb14 ret <vscale x 1 x i8> %vc15}16 17define <vscale x 1 x i8> @vdiv_vx_nxv1i8(<vscale x 1 x i8> %va, i8 signext %b) {18; CHECK-LABEL: vdiv_vx_nxv1i8:19; CHECK: # %bb.0:20; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma21; CHECK-NEXT: vdiv.vx v8, v8, a022; CHECK-NEXT: ret23 %head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 024 %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer25 %vc = sdiv <vscale x 1 x i8> %va, %splat26 ret <vscale x 1 x i8> %vc27}28 29define <vscale x 1 x i8> @vdiv_vi_nxv1i8_0(<vscale x 1 x i8> %va) {30; CHECK-LABEL: vdiv_vi_nxv1i8_0:31; CHECK: # %bb.0:32; CHECK-NEXT: li a0, 10933; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma34; CHECK-NEXT: vmulh.vx v9, v8, a035; CHECK-NEXT: vsub.vv v8, v9, v836; CHECK-NEXT: vsra.vi v8, v8, 237; CHECK-NEXT: vsrl.vi v9, v8, 738; CHECK-NEXT: vadd.vv v8, v8, v939; CHECK-NEXT: ret40 %vc = sdiv <vscale x 1 x i8> %va, splat (i8 -7)41 ret <vscale x 1 x i8> %vc42}43 44; Test V/1 to see if we can optimize it away for scalable vectors.45define <vscale x 1 x i8> @vdiv_vi_nxv1i8_1(<vscale x 1 x i8> %va) {46; CHECK-LABEL: vdiv_vi_nxv1i8_1:47; CHECK: # %bb.0:48; CHECK-NEXT: ret49 %vc = sdiv <vscale x 1 x i8> %va, splat (i8 1)50 ret <vscale x 1 x i8> %vc51}52 53; Test 0/V to see if we can optimize it away for scalable vectors.54define <vscale x 1 x i8> @vdiv_iv_nxv1i8_0(<vscale x 1 x i8> %va) {55; CHECK-LABEL: vdiv_iv_nxv1i8_0:56; CHECK: # %bb.0:57; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma58; CHECK-NEXT: vmv.v.i v8, 059; CHECK-NEXT: ret60 %vc = sdiv <vscale x 1 x i8> splat (i8 0), %va61 ret <vscale x 1 x i8> %vc62}63 64define <vscale x 2 x i8> @vdiv_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb) {65; CHECK-LABEL: vdiv_vv_nxv2i8:66; CHECK: # %bb.0:67; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma68; CHECK-NEXT: vdiv.vv v8, v8, v969; CHECK-NEXT: ret70 %vc = sdiv <vscale x 2 x i8> %va, %vb71 ret <vscale x 2 x i8> %vc72}73 74define <vscale x 2 x i8> @vdiv_vx_nxv2i8(<vscale x 2 x i8> %va, i8 signext %b) {75; CHECK-LABEL: vdiv_vx_nxv2i8:76; CHECK: # %bb.0:77; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma78; CHECK-NEXT: vdiv.vx v8, v8, a079; CHECK-NEXT: ret80 %head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 081 %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer82 %vc = sdiv <vscale x 2 x i8> %va, %splat83 ret <vscale x 2 x i8> %vc84}85 86define <vscale x 2 x i8> @vdiv_vi_nxv2i8_0(<vscale x 2 x i8> %va) {87; CHECK-LABEL: vdiv_vi_nxv2i8_0:88; CHECK: # %bb.0:89; CHECK-NEXT: li a0, 10990; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma91; CHECK-NEXT: vmulh.vx v9, v8, a092; CHECK-NEXT: vsub.vv v8, v9, v893; CHECK-NEXT: vsra.vi v8, v8, 294; CHECK-NEXT: vsrl.vi v9, v8, 795; CHECK-NEXT: vadd.vv v8, v8, v996; CHECK-NEXT: ret97 %vc = sdiv <vscale x 2 x i8> %va, splat (i8 -7)98 ret <vscale x 2 x i8> %vc99}100 101define <vscale x 4 x i8> @vdiv_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) {102; CHECK-LABEL: vdiv_vv_nxv4i8:103; CHECK: # %bb.0:104; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma105; CHECK-NEXT: vdiv.vv v8, v8, v9106; CHECK-NEXT: ret107 %vc = sdiv <vscale x 4 x i8> %va, %vb108 ret <vscale x 4 x i8> %vc109}110 111define <vscale x 4 x i8> @vdiv_vx_nxv4i8(<vscale x 4 x i8> %va, i8 signext %b) {112; CHECK-LABEL: vdiv_vx_nxv4i8:113; CHECK: # %bb.0:114; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma115; CHECK-NEXT: vdiv.vx v8, v8, a0116; CHECK-NEXT: ret117 %head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0118 %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer119 %vc = sdiv <vscale x 4 x i8> %va, %splat120 ret <vscale x 4 x i8> %vc121}122 123define <vscale x 4 x i8> @vdiv_vi_nxv4i8_0(<vscale x 4 x i8> %va) {124; CHECK-LABEL: vdiv_vi_nxv4i8_0:125; CHECK: # %bb.0:126; CHECK-NEXT: li a0, 109127; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma128; CHECK-NEXT: vmulh.vx v9, v8, a0129; CHECK-NEXT: vsub.vv v8, v9, v8130; CHECK-NEXT: vsra.vi v8, v8, 2131; CHECK-NEXT: vsrl.vi v9, v8, 7132; CHECK-NEXT: vadd.vv v8, v8, v9133; CHECK-NEXT: ret134 %vc = sdiv <vscale x 4 x i8> %va, splat (i8 -7)135 ret <vscale x 4 x i8> %vc136}137 138define <vscale x 8 x i8> @vdiv_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {139; CHECK-LABEL: vdiv_vv_nxv8i8:140; CHECK: # %bb.0:141; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma142; CHECK-NEXT: vdiv.vv v8, v8, v9143; CHECK-NEXT: ret144 %vc = sdiv <vscale x 8 x i8> %va, %vb145 ret <vscale x 8 x i8> %vc146}147 148define <vscale x 8 x i8> @vdiv_vx_nxv8i8(<vscale x 8 x i8> %va, i8 signext %b) {149; CHECK-LABEL: vdiv_vx_nxv8i8:150; CHECK: # %bb.0:151; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma152; CHECK-NEXT: vdiv.vx v8, v8, a0153; CHECK-NEXT: ret154 %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0155 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer156 %vc = sdiv <vscale x 8 x i8> %va, %splat157 ret <vscale x 8 x i8> %vc158}159 160define <vscale x 8 x i8> @vdiv_vi_nxv8i8_0(<vscale x 8 x i8> %va) {161; CHECK-LABEL: vdiv_vi_nxv8i8_0:162; CHECK: # %bb.0:163; CHECK-NEXT: li a0, 109164; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma165; CHECK-NEXT: vmulh.vx v9, v8, a0166; CHECK-NEXT: vsub.vv v8, v9, v8167; CHECK-NEXT: vsra.vi v8, v8, 2168; CHECK-NEXT: vsrl.vi v9, v8, 7169; CHECK-NEXT: vadd.vv v8, v8, v9170; CHECK-NEXT: ret171 %vc = sdiv <vscale x 8 x i8> %va, splat (i8 -7)172 ret <vscale x 8 x i8> %vc173}174 175define <vscale x 16 x i8> @vdiv_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb) {176; CHECK-LABEL: vdiv_vv_nxv16i8:177; CHECK: # %bb.0:178; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma179; CHECK-NEXT: vdiv.vv v8, v8, v10180; CHECK-NEXT: ret181 %vc = sdiv <vscale x 16 x i8> %va, %vb182 ret <vscale x 16 x i8> %vc183}184 185define <vscale x 16 x i8> @vdiv_vx_nxv16i8(<vscale x 16 x i8> %va, i8 signext %b) {186; CHECK-LABEL: vdiv_vx_nxv16i8:187; CHECK: # %bb.0:188; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma189; CHECK-NEXT: vdiv.vx v8, v8, a0190; CHECK-NEXT: ret191 %head = insertelement <vscale x 16 x i8> poison, i8 %b, i32 0192 %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer193 %vc = sdiv <vscale x 16 x i8> %va, %splat194 ret <vscale x 16 x i8> %vc195}196 197define <vscale x 16 x i8> @vdiv_vi_nxv16i8_0(<vscale x 16 x i8> %va) {198; CHECK-LABEL: vdiv_vi_nxv16i8_0:199; CHECK: # %bb.0:200; CHECK-NEXT: li a0, 109201; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma202; CHECK-NEXT: vmulh.vx v10, v8, a0203; CHECK-NEXT: vsub.vv v8, v10, v8204; CHECK-NEXT: vsra.vi v8, v8, 2205; CHECK-NEXT: vsrl.vi v10, v8, 7206; CHECK-NEXT: vadd.vv v8, v8, v10207; CHECK-NEXT: ret208 %vc = sdiv <vscale x 16 x i8> %va, splat (i8 -7)209 ret <vscale x 16 x i8> %vc210}211 212define <vscale x 32 x i8> @vdiv_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb) {213; CHECK-LABEL: vdiv_vv_nxv32i8:214; CHECK: # %bb.0:215; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma216; CHECK-NEXT: vdiv.vv v8, v8, v12217; CHECK-NEXT: ret218 %vc = sdiv <vscale x 32 x i8> %va, %vb219 ret <vscale x 32 x i8> %vc220}221 222define <vscale x 32 x i8> @vdiv_vx_nxv32i8(<vscale x 32 x i8> %va, i8 signext %b) {223; CHECK-LABEL: vdiv_vx_nxv32i8:224; CHECK: # %bb.0:225; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma226; CHECK-NEXT: vdiv.vx v8, v8, a0227; CHECK-NEXT: ret228 %head = insertelement <vscale x 32 x i8> poison, i8 %b, i32 0229 %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer230 %vc = sdiv <vscale x 32 x i8> %va, %splat231 ret <vscale x 32 x i8> %vc232}233 234define <vscale x 32 x i8> @vdiv_vi_nxv32i8_0(<vscale x 32 x i8> %va) {235; CHECK-LABEL: vdiv_vi_nxv32i8_0:236; CHECK: # %bb.0:237; CHECK-NEXT: li a0, 109238; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma239; CHECK-NEXT: vmulh.vx v12, v8, a0240; CHECK-NEXT: vsub.vv v8, v12, v8241; CHECK-NEXT: vsra.vi v8, v8, 2242; CHECK-NEXT: vsrl.vi v12, v8, 7243; CHECK-NEXT: vadd.vv v8, v8, v12244; CHECK-NEXT: ret245 %vc = sdiv <vscale x 32 x i8> %va, splat (i8 -7)246 ret <vscale x 32 x i8> %vc247}248 249define <vscale x 64 x i8> @vdiv_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb) {250; CHECK-LABEL: vdiv_vv_nxv64i8:251; CHECK: # %bb.0:252; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma253; CHECK-NEXT: vdiv.vv v8, v8, v16254; CHECK-NEXT: ret255 %vc = sdiv <vscale x 64 x i8> %va, %vb256 ret <vscale x 64 x i8> %vc257}258 259define <vscale x 64 x i8> @vdiv_vx_nxv64i8(<vscale x 64 x i8> %va, i8 signext %b) {260; CHECK-LABEL: vdiv_vx_nxv64i8:261; CHECK: # %bb.0:262; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma263; CHECK-NEXT: vdiv.vx v8, v8, a0264; CHECK-NEXT: ret265 %head = insertelement <vscale x 64 x i8> poison, i8 %b, i32 0266 %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer267 %vc = sdiv <vscale x 64 x i8> %va, %splat268 ret <vscale x 64 x i8> %vc269}270 271define <vscale x 64 x i8> @vdiv_vi_nxv64i8_0(<vscale x 64 x i8> %va) {272; CHECK-LABEL: vdiv_vi_nxv64i8_0:273; CHECK: # %bb.0:274; CHECK-NEXT: li a0, 109275; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma276; CHECK-NEXT: vmulh.vx v16, v8, a0277; CHECK-NEXT: vsub.vv v8, v16, v8278; CHECK-NEXT: vsra.vi v8, v8, 2279; CHECK-NEXT: vsrl.vi v16, v8, 7280; CHECK-NEXT: vadd.vv v8, v8, v16281; CHECK-NEXT: ret282 %vc = sdiv <vscale x 64 x i8> %va, splat (i8 -7)283 ret <vscale x 64 x i8> %vc284}285 286define <vscale x 1 x i16> @vdiv_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) {287; CHECK-LABEL: vdiv_vv_nxv1i16:288; CHECK: # %bb.0:289; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma290; CHECK-NEXT: vdiv.vv v8, v8, v9291; CHECK-NEXT: ret292 %vc = sdiv <vscale x 1 x i16> %va, %vb293 ret <vscale x 1 x i16> %vc294}295 296define <vscale x 1 x i16> @vdiv_vx_nxv1i16(<vscale x 1 x i16> %va, i16 signext %b) {297; CHECK-LABEL: vdiv_vx_nxv1i16:298; CHECK: # %bb.0:299; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma300; CHECK-NEXT: vdiv.vx v8, v8, a0301; CHECK-NEXT: ret302 %head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0303 %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer304 %vc = sdiv <vscale x 1 x i16> %va, %splat305 ret <vscale x 1 x i16> %vc306}307 308define <vscale x 1 x i16> @vdiv_vi_nxv1i16_0(<vscale x 1 x i16> %va) {309; CHECK-LABEL: vdiv_vi_nxv1i16_0:310; CHECK: # %bb.0:311; CHECK-NEXT: lui a0, 1048571312; CHECK-NEXT: addi a0, a0, 1755313; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma314; CHECK-NEXT: vmulh.vx v8, v8, a0315; CHECK-NEXT: vsra.vi v8, v8, 1316; CHECK-NEXT: vsrl.vi v9, v8, 15317; CHECK-NEXT: vadd.vv v8, v8, v9318; CHECK-NEXT: ret319 %vc = sdiv <vscale x 1 x i16> %va, splat (i16 -7)320 ret <vscale x 1 x i16> %vc321}322 323define <vscale x 2 x i16> @vdiv_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) {324; CHECK-LABEL: vdiv_vv_nxv2i16:325; CHECK: # %bb.0:326; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma327; CHECK-NEXT: vdiv.vv v8, v8, v9328; CHECK-NEXT: ret329 %vc = sdiv <vscale x 2 x i16> %va, %vb330 ret <vscale x 2 x i16> %vc331}332 333define <vscale x 2 x i16> @vdiv_vx_nxv2i16(<vscale x 2 x i16> %va, i16 signext %b) {334; CHECK-LABEL: vdiv_vx_nxv2i16:335; CHECK: # %bb.0:336; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma337; CHECK-NEXT: vdiv.vx v8, v8, a0338; CHECK-NEXT: ret339 %head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0340 %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer341 %vc = sdiv <vscale x 2 x i16> %va, %splat342 ret <vscale x 2 x i16> %vc343}344 345define <vscale x 2 x i16> @vdiv_vi_nxv2i16_0(<vscale x 2 x i16> %va) {346; CHECK-LABEL: vdiv_vi_nxv2i16_0:347; CHECK: # %bb.0:348; CHECK-NEXT: lui a0, 1048571349; CHECK-NEXT: addi a0, a0, 1755350; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma351; CHECK-NEXT: vmulh.vx v8, v8, a0352; CHECK-NEXT: vsra.vi v8, v8, 1353; CHECK-NEXT: vsrl.vi v9, v8, 15354; CHECK-NEXT: vadd.vv v8, v8, v9355; CHECK-NEXT: ret356 %vc = sdiv <vscale x 2 x i16> %va, splat (i16 -7)357 ret <vscale x 2 x i16> %vc358}359 360define <vscale x 4 x i16> @vdiv_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) {361; CHECK-LABEL: vdiv_vv_nxv4i16:362; CHECK: # %bb.0:363; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma364; CHECK-NEXT: vdiv.vv v8, v8, v9365; CHECK-NEXT: ret366 %vc = sdiv <vscale x 4 x i16> %va, %vb367 ret <vscale x 4 x i16> %vc368}369 370define <vscale x 4 x i16> @vdiv_vx_nxv4i16(<vscale x 4 x i16> %va, i16 signext %b) {371; CHECK-LABEL: vdiv_vx_nxv4i16:372; CHECK: # %bb.0:373; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma374; CHECK-NEXT: vdiv.vx v8, v8, a0375; CHECK-NEXT: ret376 %head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0377 %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer378 %vc = sdiv <vscale x 4 x i16> %va, %splat379 ret <vscale x 4 x i16> %vc380}381 382define <vscale x 4 x i16> @vdiv_vi_nxv4i16_0(<vscale x 4 x i16> %va) {383; CHECK-LABEL: vdiv_vi_nxv4i16_0:384; CHECK: # %bb.0:385; CHECK-NEXT: lui a0, 1048571386; CHECK-NEXT: addi a0, a0, 1755387; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma388; CHECK-NEXT: vmulh.vx v8, v8, a0389; CHECK-NEXT: vsra.vi v8, v8, 1390; CHECK-NEXT: vsrl.vi v9, v8, 15391; CHECK-NEXT: vadd.vv v8, v8, v9392; CHECK-NEXT: ret393 %vc = sdiv <vscale x 4 x i16> %va, splat (i16 -7)394 ret <vscale x 4 x i16> %vc395}396 397define <vscale x 8 x i16> @vdiv_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {398; CHECK-LABEL: vdiv_vv_nxv8i16:399; CHECK: # %bb.0:400; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma401; CHECK-NEXT: vdiv.vv v8, v8, v10402; CHECK-NEXT: ret403 %vc = sdiv <vscale x 8 x i16> %va, %vb404 ret <vscale x 8 x i16> %vc405}406 407define <vscale x 8 x i16> @vdiv_vx_nxv8i16(<vscale x 8 x i16> %va, i16 signext %b) {408; CHECK-LABEL: vdiv_vx_nxv8i16:409; CHECK: # %bb.0:410; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma411; CHECK-NEXT: vdiv.vx v8, v8, a0412; CHECK-NEXT: ret413 %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0414 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer415 %vc = sdiv <vscale x 8 x i16> %va, %splat416 ret <vscale x 8 x i16> %vc417}418 419define <vscale x 8 x i16> @vdiv_vi_nxv8i16_0(<vscale x 8 x i16> %va) {420; CHECK-LABEL: vdiv_vi_nxv8i16_0:421; CHECK: # %bb.0:422; CHECK-NEXT: lui a0, 1048571423; CHECK-NEXT: addi a0, a0, 1755424; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma425; CHECK-NEXT: vmulh.vx v8, v8, a0426; CHECK-NEXT: vsra.vi v8, v8, 1427; CHECK-NEXT: vsrl.vi v10, v8, 15428; CHECK-NEXT: vadd.vv v8, v8, v10429; CHECK-NEXT: ret430 %vc = sdiv <vscale x 8 x i16> %va, splat (i16 -7)431 ret <vscale x 8 x i16> %vc432}433 434define <vscale x 16 x i16> @vdiv_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb) {435; CHECK-LABEL: vdiv_vv_nxv16i16:436; CHECK: # %bb.0:437; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma438; CHECK-NEXT: vdiv.vv v8, v8, v12439; CHECK-NEXT: ret440 %vc = sdiv <vscale x 16 x i16> %va, %vb441 ret <vscale x 16 x i16> %vc442}443 444define <vscale x 16 x i16> @vdiv_vx_nxv16i16(<vscale x 16 x i16> %va, i16 signext %b) {445; CHECK-LABEL: vdiv_vx_nxv16i16:446; CHECK: # %bb.0:447; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma448; CHECK-NEXT: vdiv.vx v8, v8, a0449; CHECK-NEXT: ret450 %head = insertelement <vscale x 16 x i16> poison, i16 %b, i32 0451 %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer452 %vc = sdiv <vscale x 16 x i16> %va, %splat453 ret <vscale x 16 x i16> %vc454}455 456define <vscale x 16 x i16> @vdiv_vi_nxv16i16_0(<vscale x 16 x i16> %va) {457; CHECK-LABEL: vdiv_vi_nxv16i16_0:458; CHECK: # %bb.0:459; CHECK-NEXT: lui a0, 1048571460; CHECK-NEXT: addi a0, a0, 1755461; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma462; CHECK-NEXT: vmulh.vx v8, v8, a0463; CHECK-NEXT: vsra.vi v8, v8, 1464; CHECK-NEXT: vsrl.vi v12, v8, 15465; CHECK-NEXT: vadd.vv v8, v8, v12466; CHECK-NEXT: ret467 %vc = sdiv <vscale x 16 x i16> %va, splat (i16 -7)468 ret <vscale x 16 x i16> %vc469}470 471define <vscale x 32 x i16> @vdiv_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb) {472; CHECK-LABEL: vdiv_vv_nxv32i16:473; CHECK: # %bb.0:474; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma475; CHECK-NEXT: vdiv.vv v8, v8, v16476; CHECK-NEXT: ret477 %vc = sdiv <vscale x 32 x i16> %va, %vb478 ret <vscale x 32 x i16> %vc479}480 481define <vscale x 32 x i16> @vdiv_vx_nxv32i16(<vscale x 32 x i16> %va, i16 signext %b) {482; CHECK-LABEL: vdiv_vx_nxv32i16:483; CHECK: # %bb.0:484; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma485; CHECK-NEXT: vdiv.vx v8, v8, a0486; CHECK-NEXT: ret487 %head = insertelement <vscale x 32 x i16> poison, i16 %b, i32 0488 %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer489 %vc = sdiv <vscale x 32 x i16> %va, %splat490 ret <vscale x 32 x i16> %vc491}492 493define <vscale x 32 x i16> @vdiv_vi_nxv32i16_0(<vscale x 32 x i16> %va) {494; CHECK-LABEL: vdiv_vi_nxv32i16_0:495; CHECK: # %bb.0:496; CHECK-NEXT: lui a0, 1048571497; CHECK-NEXT: addi a0, a0, 1755498; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma499; CHECK-NEXT: vmulh.vx v8, v8, a0500; CHECK-NEXT: vsra.vi v8, v8, 1501; CHECK-NEXT: vsrl.vi v16, v8, 15502; CHECK-NEXT: vadd.vv v8, v8, v16503; CHECK-NEXT: ret504 %vc = sdiv <vscale x 32 x i16> %va, splat (i16 -7)505 ret <vscale x 32 x i16> %vc506}507 508define <vscale x 1 x i32> @vdiv_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {509; CHECK-LABEL: vdiv_vv_nxv1i32:510; CHECK: # %bb.0:511; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma512; CHECK-NEXT: vdiv.vv v8, v8, v9513; CHECK-NEXT: ret514 %vc = sdiv <vscale x 1 x i32> %va, %vb515 ret <vscale x 1 x i32> %vc516}517 518define <vscale x 1 x i32> @vdiv_vx_nxv1i32(<vscale x 1 x i32> %va, i32 signext %b) {519; CHECK-LABEL: vdiv_vx_nxv1i32:520; CHECK: # %bb.0:521; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma522; CHECK-NEXT: vdiv.vx v8, v8, a0523; CHECK-NEXT: ret524 %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0525 %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer526 %vc = sdiv <vscale x 1 x i32> %va, %splat527 ret <vscale x 1 x i32> %vc528}529 530define <vscale x 1 x i32> @vdiv_vi_nxv1i32_0(<vscale x 1 x i32> %va) {531; RV32-LABEL: vdiv_vi_nxv1i32_0:532; RV32: # %bb.0:533; RV32-NEXT: lui a0, 449390534; RV32-NEXT: addi a0, a0, -1171535; RV32-NEXT: vsetvli a1, zero, e32, mf2, ta, ma536; RV32-NEXT: vmulh.vx v9, v8, a0537; RV32-NEXT: vsub.vv v8, v9, v8538; RV32-NEXT: vsrl.vi v9, v8, 31539; RV32-NEXT: vsra.vi v8, v8, 2540; RV32-NEXT: vadd.vv v8, v8, v9541; RV32-NEXT: ret542;543; RV64-LABEL: vdiv_vi_nxv1i32_0:544; RV64: # %bb.0:545; RV64-NEXT: lui a0, 449390546; RV64-NEXT: addi a0, a0, -1171547; RV64-NEXT: vsetvli a1, zero, e32, mf2, ta, ma548; RV64-NEXT: vmulh.vx v9, v8, a0549; RV64-NEXT: vsub.vv v8, v9, v8550; RV64-NEXT: vsra.vi v8, v8, 2551; RV64-NEXT: vsrl.vi v9, v8, 31552; RV64-NEXT: vadd.vv v8, v8, v9553; RV64-NEXT: ret554 %vc = sdiv <vscale x 1 x i32> %va, splat (i32 -7)555 ret <vscale x 1 x i32> %vc556}557 558define <vscale x 2 x i32> @vdiv_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {559; CHECK-LABEL: vdiv_vv_nxv2i32:560; CHECK: # %bb.0:561; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma562; CHECK-NEXT: vdiv.vv v8, v8, v9563; CHECK-NEXT: ret564 %vc = sdiv <vscale x 2 x i32> %va, %vb565 ret <vscale x 2 x i32> %vc566}567 568define <vscale x 2 x i32> @vdiv_vx_nxv2i32(<vscale x 2 x i32> %va, i32 signext %b) {569; CHECK-LABEL: vdiv_vx_nxv2i32:570; CHECK: # %bb.0:571; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma572; CHECK-NEXT: vdiv.vx v8, v8, a0573; CHECK-NEXT: ret574 %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0575 %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer576 %vc = sdiv <vscale x 2 x i32> %va, %splat577 ret <vscale x 2 x i32> %vc578}579 580define <vscale x 2 x i32> @vdiv_vi_nxv2i32_0(<vscale x 2 x i32> %va) {581; RV32-LABEL: vdiv_vi_nxv2i32_0:582; RV32: # %bb.0:583; RV32-NEXT: lui a0, 449390584; RV32-NEXT: addi a0, a0, -1171585; RV32-NEXT: vsetvli a1, zero, e32, m1, ta, ma586; RV32-NEXT: vmulh.vx v9, v8, a0587; RV32-NEXT: vsub.vv v8, v9, v8588; RV32-NEXT: vsrl.vi v9, v8, 31589; RV32-NEXT: vsra.vi v8, v8, 2590; RV32-NEXT: vadd.vv v8, v8, v9591; RV32-NEXT: ret592;593; RV64-LABEL: vdiv_vi_nxv2i32_0:594; RV64: # %bb.0:595; RV64-NEXT: lui a0, 449390596; RV64-NEXT: addi a0, a0, -1171597; RV64-NEXT: vsetvli a1, zero, e32, m1, ta, ma598; RV64-NEXT: vmulh.vx v9, v8, a0599; RV64-NEXT: vsub.vv v8, v9, v8600; RV64-NEXT: vsra.vi v8, v8, 2601; RV64-NEXT: vsrl.vi v9, v8, 31602; RV64-NEXT: vadd.vv v8, v8, v9603; RV64-NEXT: ret604 %vc = sdiv <vscale x 2 x i32> %va, splat (i32 -7)605 ret <vscale x 2 x i32> %vc606}607 608define <vscale x 4 x i32> @vdiv_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {609; CHECK-LABEL: vdiv_vv_nxv4i32:610; CHECK: # %bb.0:611; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma612; CHECK-NEXT: vdiv.vv v8, v8, v10613; CHECK-NEXT: ret614 %vc = sdiv <vscale x 4 x i32> %va, %vb615 ret <vscale x 4 x i32> %vc616}617 618define <vscale x 4 x i32> @vdiv_vx_nxv4i32(<vscale x 4 x i32> %va, i32 signext %b) {619; CHECK-LABEL: vdiv_vx_nxv4i32:620; CHECK: # %bb.0:621; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma622; CHECK-NEXT: vdiv.vx v8, v8, a0623; CHECK-NEXT: ret624 %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0625 %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer626 %vc = sdiv <vscale x 4 x i32> %va, %splat627 ret <vscale x 4 x i32> %vc628}629 630define <vscale x 4 x i32> @vdiv_vi_nxv4i32_0(<vscale x 4 x i32> %va) {631; RV32-LABEL: vdiv_vi_nxv4i32_0:632; RV32: # %bb.0:633; RV32-NEXT: lui a0, 449390634; RV32-NEXT: addi a0, a0, -1171635; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, ma636; RV32-NEXT: vmulh.vx v10, v8, a0637; RV32-NEXT: vsub.vv v8, v10, v8638; RV32-NEXT: vsrl.vi v10, v8, 31639; RV32-NEXT: vsra.vi v8, v8, 2640; RV32-NEXT: vadd.vv v8, v8, v10641; RV32-NEXT: ret642;643; RV64-LABEL: vdiv_vi_nxv4i32_0:644; RV64: # %bb.0:645; RV64-NEXT: lui a0, 449390646; RV64-NEXT: addi a0, a0, -1171647; RV64-NEXT: vsetvli a1, zero, e32, m2, ta, ma648; RV64-NEXT: vmulh.vx v10, v8, a0649; RV64-NEXT: vsub.vv v8, v10, v8650; RV64-NEXT: vsra.vi v8, v8, 2651; RV64-NEXT: vsrl.vi v10, v8, 31652; RV64-NEXT: vadd.vv v8, v8, v10653; RV64-NEXT: ret654 %vc = sdiv <vscale x 4 x i32> %va, splat (i32 -7)655 ret <vscale x 4 x i32> %vc656}657 658define <vscale x 8 x i32> @vdiv_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {659; CHECK-LABEL: vdiv_vv_nxv8i32:660; CHECK: # %bb.0:661; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma662; CHECK-NEXT: vdiv.vv v8, v8, v12663; CHECK-NEXT: ret664 %vc = sdiv <vscale x 8 x i32> %va, %vb665 ret <vscale x 8 x i32> %vc666}667 668define <vscale x 8 x i32> @vdiv_vx_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b) {669; CHECK-LABEL: vdiv_vx_nxv8i32:670; CHECK: # %bb.0:671; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma672; CHECK-NEXT: vdiv.vx v8, v8, a0673; CHECK-NEXT: ret674 %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0675 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer676 %vc = sdiv <vscale x 8 x i32> %va, %splat677 ret <vscale x 8 x i32> %vc678}679 680define <vscale x 8 x i32> @vdiv_vi_nxv8i32_0(<vscale x 8 x i32> %va) {681; RV32-LABEL: vdiv_vi_nxv8i32_0:682; RV32: # %bb.0:683; RV32-NEXT: lui a0, 449390684; RV32-NEXT: addi a0, a0, -1171685; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, ma686; RV32-NEXT: vmulh.vx v12, v8, a0687; RV32-NEXT: vsub.vv v8, v12, v8688; RV32-NEXT: vsrl.vi v12, v8, 31689; RV32-NEXT: vsra.vi v8, v8, 2690; RV32-NEXT: vadd.vv v8, v8, v12691; RV32-NEXT: ret692;693; RV64-LABEL: vdiv_vi_nxv8i32_0:694; RV64: # %bb.0:695; RV64-NEXT: lui a0, 449390696; RV64-NEXT: addi a0, a0, -1171697; RV64-NEXT: vsetvli a1, zero, e32, m4, ta, ma698; RV64-NEXT: vmulh.vx v12, v8, a0699; RV64-NEXT: vsub.vv v8, v12, v8700; RV64-NEXT: vsra.vi v8, v8, 2701; RV64-NEXT: vsrl.vi v12, v8, 31702; RV64-NEXT: vadd.vv v8, v8, v12703; RV64-NEXT: ret704 %vc = sdiv <vscale x 8 x i32> %va, splat (i32 -7)705 ret <vscale x 8 x i32> %vc706}707 708define <vscale x 16 x i32> @vdiv_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb) {709; CHECK-LABEL: vdiv_vv_nxv16i32:710; CHECK: # %bb.0:711; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma712; CHECK-NEXT: vdiv.vv v8, v8, v16713; CHECK-NEXT: ret714 %vc = sdiv <vscale x 16 x i32> %va, %vb715 ret <vscale x 16 x i32> %vc716}717 718define <vscale x 16 x i32> @vdiv_vx_nxv16i32(<vscale x 16 x i32> %va, i32 signext %b) {719; CHECK-LABEL: vdiv_vx_nxv16i32:720; CHECK: # %bb.0:721; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma722; CHECK-NEXT: vdiv.vx v8, v8, a0723; CHECK-NEXT: ret724 %head = insertelement <vscale x 16 x i32> poison, i32 %b, i32 0725 %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer726 %vc = sdiv <vscale x 16 x i32> %va, %splat727 ret <vscale x 16 x i32> %vc728}729 730define <vscale x 16 x i32> @vdiv_vi_nxv16i32_0(<vscale x 16 x i32> %va) {731; RV32-LABEL: vdiv_vi_nxv16i32_0:732; RV32: # %bb.0:733; RV32-NEXT: lui a0, 449390734; RV32-NEXT: addi a0, a0, -1171735; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma736; RV32-NEXT: vmulh.vx v16, v8, a0737; RV32-NEXT: vsub.vv v8, v16, v8738; RV32-NEXT: vsrl.vi v16, v8, 31739; RV32-NEXT: vsra.vi v8, v8, 2740; RV32-NEXT: vadd.vv v8, v8, v16741; RV32-NEXT: ret742;743; RV64-LABEL: vdiv_vi_nxv16i32_0:744; RV64: # %bb.0:745; RV64-NEXT: lui a0, 449390746; RV64-NEXT: addi a0, a0, -1171747; RV64-NEXT: vsetvli a1, zero, e32, m8, ta, ma748; RV64-NEXT: vmulh.vx v16, v8, a0749; RV64-NEXT: vsub.vv v8, v16, v8750; RV64-NEXT: vsra.vi v8, v8, 2751; RV64-NEXT: vsrl.vi v16, v8, 31752; RV64-NEXT: vadd.vv v8, v8, v16753; RV64-NEXT: ret754 %vc = sdiv <vscale x 16 x i32> %va, splat (i32 -7)755 ret <vscale x 16 x i32> %vc756}757 758define <vscale x 1 x i64> @vdiv_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb) {759; CHECK-LABEL: vdiv_vv_nxv1i64:760; CHECK: # %bb.0:761; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma762; CHECK-NEXT: vdiv.vv v8, v8, v9763; CHECK-NEXT: ret764 %vc = sdiv <vscale x 1 x i64> %va, %vb765 ret <vscale x 1 x i64> %vc766}767 768define <vscale x 1 x i64> @vdiv_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {769; RV32-LABEL: vdiv_vx_nxv1i64:770; RV32: # %bb.0:771; RV32-NEXT: addi sp, sp, -16772; RV32-NEXT: .cfi_def_cfa_offset 16773; RV32-NEXT: sw a0, 8(sp)774; RV32-NEXT: sw a1, 12(sp)775; RV32-NEXT: addi a0, sp, 8776; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma777; RV32-NEXT: vlse64.v v9, (a0), zero778; RV32-NEXT: vdiv.vv v8, v8, v9779; RV32-NEXT: addi sp, sp, 16780; RV32-NEXT: .cfi_def_cfa_offset 0781; RV32-NEXT: ret782;783; RV64-LABEL: vdiv_vx_nxv1i64:784; RV64: # %bb.0:785; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, ma786; RV64-NEXT: vdiv.vx v8, v8, a0787; RV64-NEXT: ret788 %head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0789 %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer790 %vc = sdiv <vscale x 1 x i64> %va, %splat791 ret <vscale x 1 x i64> %vc792}793 794define <vscale x 1 x i64> @vdiv_vi_nxv1i64_0(<vscale x 1 x i64> %va) {795; RV32-V-LABEL: vdiv_vi_nxv1i64_0:796; RV32-V: # %bb.0:797; RV32-V-NEXT: addi sp, sp, -16798; RV32-V-NEXT: .cfi_def_cfa_offset 16799; RV32-V-NEXT: lui a0, 748983800; RV32-V-NEXT: lui a1, 898779801; RV32-V-NEXT: addi a0, a0, -586802; RV32-V-NEXT: addi a1, a1, 1755803; RV32-V-NEXT: sw a1, 8(sp)804; RV32-V-NEXT: sw a0, 12(sp)805; RV32-V-NEXT: addi a0, sp, 8806; RV32-V-NEXT: vsetvli a1, zero, e64, m1, ta, ma807; RV32-V-NEXT: vlse64.v v9, (a0), zero808; RV32-V-NEXT: li a0, 63809; RV32-V-NEXT: vmulh.vv v8, v8, v9810; RV32-V-NEXT: vsrl.vx v9, v8, a0811; RV32-V-NEXT: vsra.vi v8, v8, 1812; RV32-V-NEXT: vadd.vv v8, v8, v9813; RV32-V-NEXT: addi sp, sp, 16814; RV32-V-NEXT: .cfi_def_cfa_offset 0815; RV32-V-NEXT: ret816;817; ZVE64X-LABEL: vdiv_vi_nxv1i64_0:818; ZVE64X: # %bb.0:819; ZVE64X-NEXT: li a0, -7820; ZVE64X-NEXT: vsetvli a1, zero, e64, m1, ta, ma821; ZVE64X-NEXT: vdiv.vx v8, v8, a0822; ZVE64X-NEXT: ret823;824; RV64-V-LABEL: vdiv_vi_nxv1i64_0:825; RV64-V: # %bb.0:826; RV64-V-NEXT: lui a0, %hi(.LCPI58_0)827; RV64-V-NEXT: ld a0, %lo(.LCPI58_0)(a0)828; RV64-V-NEXT: vsetvli a1, zero, e64, m1, ta, ma829; RV64-V-NEXT: vmulh.vx v8, v8, a0830; RV64-V-NEXT: li a0, 63831; RV64-V-NEXT: vsrl.vx v9, v8, a0832; RV64-V-NEXT: vsra.vi v8, v8, 1833; RV64-V-NEXT: vadd.vv v8, v8, v9834; RV64-V-NEXT: ret835 %vc = sdiv <vscale x 1 x i64> %va, splat (i64 -7)836 ret <vscale x 1 x i64> %vc837}838 839define <vscale x 2 x i64> @vdiv_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) {840; CHECK-LABEL: vdiv_vv_nxv2i64:841; CHECK: # %bb.0:842; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma843; CHECK-NEXT: vdiv.vv v8, v8, v10844; CHECK-NEXT: ret845 %vc = sdiv <vscale x 2 x i64> %va, %vb846 ret <vscale x 2 x i64> %vc847}848 849define <vscale x 2 x i64> @vdiv_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {850; RV32-LABEL: vdiv_vx_nxv2i64:851; RV32: # %bb.0:852; RV32-NEXT: addi sp, sp, -16853; RV32-NEXT: .cfi_def_cfa_offset 16854; RV32-NEXT: sw a0, 8(sp)855; RV32-NEXT: sw a1, 12(sp)856; RV32-NEXT: addi a0, sp, 8857; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma858; RV32-NEXT: vlse64.v v10, (a0), zero859; RV32-NEXT: vdiv.vv v8, v8, v10860; RV32-NEXT: addi sp, sp, 16861; RV32-NEXT: .cfi_def_cfa_offset 0862; RV32-NEXT: ret863;864; RV64-LABEL: vdiv_vx_nxv2i64:865; RV64: # %bb.0:866; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, ma867; RV64-NEXT: vdiv.vx v8, v8, a0868; RV64-NEXT: ret869 %head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0870 %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer871 %vc = sdiv <vscale x 2 x i64> %va, %splat872 ret <vscale x 2 x i64> %vc873}874 875define <vscale x 2 x i64> @vdiv_vi_nxv2i64_0(<vscale x 2 x i64> %va) {876; RV32-V-LABEL: vdiv_vi_nxv2i64_0:877; RV32-V: # %bb.0:878; RV32-V-NEXT: addi sp, sp, -16879; RV32-V-NEXT: .cfi_def_cfa_offset 16880; RV32-V-NEXT: lui a0, 748983881; RV32-V-NEXT: lui a1, 898779882; RV32-V-NEXT: addi a0, a0, -586883; RV32-V-NEXT: addi a1, a1, 1755884; RV32-V-NEXT: sw a1, 8(sp)885; RV32-V-NEXT: sw a0, 12(sp)886; RV32-V-NEXT: addi a0, sp, 8887; RV32-V-NEXT: vsetvli a1, zero, e64, m2, ta, ma888; RV32-V-NEXT: vlse64.v v10, (a0), zero889; RV32-V-NEXT: li a0, 63890; RV32-V-NEXT: vmulh.vv v8, v8, v10891; RV32-V-NEXT: vsrl.vx v10, v8, a0892; RV32-V-NEXT: vsra.vi v8, v8, 1893; RV32-V-NEXT: vadd.vv v8, v8, v10894; RV32-V-NEXT: addi sp, sp, 16895; RV32-V-NEXT: .cfi_def_cfa_offset 0896; RV32-V-NEXT: ret897;898; ZVE64X-LABEL: vdiv_vi_nxv2i64_0:899; ZVE64X: # %bb.0:900; ZVE64X-NEXT: li a0, -7901; ZVE64X-NEXT: vsetvli a1, zero, e64, m2, ta, ma902; ZVE64X-NEXT: vdiv.vx v8, v8, a0903; ZVE64X-NEXT: ret904;905; RV64-V-LABEL: vdiv_vi_nxv2i64_0:906; RV64-V: # %bb.0:907; RV64-V-NEXT: lui a0, %hi(.LCPI61_0)908; RV64-V-NEXT: ld a0, %lo(.LCPI61_0)(a0)909; RV64-V-NEXT: vsetvli a1, zero, e64, m2, ta, ma910; RV64-V-NEXT: vmulh.vx v8, v8, a0911; RV64-V-NEXT: li a0, 63912; RV64-V-NEXT: vsrl.vx v10, v8, a0913; RV64-V-NEXT: vsra.vi v8, v8, 1914; RV64-V-NEXT: vadd.vv v8, v8, v10915; RV64-V-NEXT: ret916 %vc = sdiv <vscale x 2 x i64> %va, splat (i64 -7)917 ret <vscale x 2 x i64> %vc918}919 920define <vscale x 4 x i64> @vdiv_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) {921; CHECK-LABEL: vdiv_vv_nxv4i64:922; CHECK: # %bb.0:923; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma924; CHECK-NEXT: vdiv.vv v8, v8, v12925; CHECK-NEXT: ret926 %vc = sdiv <vscale x 4 x i64> %va, %vb927 ret <vscale x 4 x i64> %vc928}929 930define <vscale x 4 x i64> @vdiv_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {931; RV32-LABEL: vdiv_vx_nxv4i64:932; RV32: # %bb.0:933; RV32-NEXT: addi sp, sp, -16934; RV32-NEXT: .cfi_def_cfa_offset 16935; RV32-NEXT: sw a0, 8(sp)936; RV32-NEXT: sw a1, 12(sp)937; RV32-NEXT: addi a0, sp, 8938; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma939; RV32-NEXT: vlse64.v v12, (a0), zero940; RV32-NEXT: vdiv.vv v8, v8, v12941; RV32-NEXT: addi sp, sp, 16942; RV32-NEXT: .cfi_def_cfa_offset 0943; RV32-NEXT: ret944;945; RV64-LABEL: vdiv_vx_nxv4i64:946; RV64: # %bb.0:947; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, ma948; RV64-NEXT: vdiv.vx v8, v8, a0949; RV64-NEXT: ret950 %head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0951 %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer952 %vc = sdiv <vscale x 4 x i64> %va, %splat953 ret <vscale x 4 x i64> %vc954}955 956define <vscale x 4 x i64> @vdiv_vi_nxv4i64_0(<vscale x 4 x i64> %va) {957; RV32-V-LABEL: vdiv_vi_nxv4i64_0:958; RV32-V: # %bb.0:959; RV32-V-NEXT: addi sp, sp, -16960; RV32-V-NEXT: .cfi_def_cfa_offset 16961; RV32-V-NEXT: lui a0, 748983962; RV32-V-NEXT: lui a1, 898779963; RV32-V-NEXT: addi a0, a0, -586964; RV32-V-NEXT: addi a1, a1, 1755965; RV32-V-NEXT: sw a1, 8(sp)966; RV32-V-NEXT: sw a0, 12(sp)967; RV32-V-NEXT: addi a0, sp, 8968; RV32-V-NEXT: vsetvli a1, zero, e64, m4, ta, ma969; RV32-V-NEXT: vlse64.v v12, (a0), zero970; RV32-V-NEXT: li a0, 63971; RV32-V-NEXT: vmulh.vv v8, v8, v12972; RV32-V-NEXT: vsrl.vx v12, v8, a0973; RV32-V-NEXT: vsra.vi v8, v8, 1974; RV32-V-NEXT: vadd.vv v8, v8, v12975; RV32-V-NEXT: addi sp, sp, 16976; RV32-V-NEXT: .cfi_def_cfa_offset 0977; RV32-V-NEXT: ret978;979; ZVE64X-LABEL: vdiv_vi_nxv4i64_0:980; ZVE64X: # %bb.0:981; ZVE64X-NEXT: li a0, -7982; ZVE64X-NEXT: vsetvli a1, zero, e64, m4, ta, ma983; ZVE64X-NEXT: vdiv.vx v8, v8, a0984; ZVE64X-NEXT: ret985;986; RV64-V-LABEL: vdiv_vi_nxv4i64_0:987; RV64-V: # %bb.0:988; RV64-V-NEXT: lui a0, %hi(.LCPI64_0)989; RV64-V-NEXT: ld a0, %lo(.LCPI64_0)(a0)990; RV64-V-NEXT: vsetvli a1, zero, e64, m4, ta, ma991; RV64-V-NEXT: vmulh.vx v8, v8, a0992; RV64-V-NEXT: li a0, 63993; RV64-V-NEXT: vsrl.vx v12, v8, a0994; RV64-V-NEXT: vsra.vi v8, v8, 1995; RV64-V-NEXT: vadd.vv v8, v8, v12996; RV64-V-NEXT: ret997 %vc = sdiv <vscale x 4 x i64> %va, splat (i64 -7)998 ret <vscale x 4 x i64> %vc999}1000 1001define <vscale x 8 x i64> @vdiv_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {1002; CHECK-LABEL: vdiv_vv_nxv8i64:1003; CHECK: # %bb.0:1004; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma1005; CHECK-NEXT: vdiv.vv v8, v8, v161006; CHECK-NEXT: ret1007 %vc = sdiv <vscale x 8 x i64> %va, %vb1008 ret <vscale x 8 x i64> %vc1009}1010 1011define <vscale x 8 x i64> @vdiv_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {1012; RV32-LABEL: vdiv_vx_nxv8i64:1013; RV32: # %bb.0:1014; RV32-NEXT: addi sp, sp, -161015; RV32-NEXT: .cfi_def_cfa_offset 161016; RV32-NEXT: sw a0, 8(sp)1017; RV32-NEXT: sw a1, 12(sp)1018; RV32-NEXT: addi a0, sp, 81019; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma1020; RV32-NEXT: vlse64.v v16, (a0), zero1021; RV32-NEXT: vdiv.vv v8, v8, v161022; RV32-NEXT: addi sp, sp, 161023; RV32-NEXT: .cfi_def_cfa_offset 01024; RV32-NEXT: ret1025;1026; RV64-LABEL: vdiv_vx_nxv8i64:1027; RV64: # %bb.0:1028; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma1029; RV64-NEXT: vdiv.vx v8, v8, a01030; RV64-NEXT: ret1031 %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 01032 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer1033 %vc = sdiv <vscale x 8 x i64> %va, %splat1034 ret <vscale x 8 x i64> %vc1035}1036 1037define <vscale x 8 x i64> @vdiv_vi_nxv8i64_0(<vscale x 8 x i64> %va) {1038; RV32-V-LABEL: vdiv_vi_nxv8i64_0:1039; RV32-V: # %bb.0:1040; RV32-V-NEXT: addi sp, sp, -161041; RV32-V-NEXT: .cfi_def_cfa_offset 161042; RV32-V-NEXT: lui a0, 7489831043; RV32-V-NEXT: lui a1, 8987791044; RV32-V-NEXT: addi a0, a0, -5861045; RV32-V-NEXT: addi a1, a1, 17551046; RV32-V-NEXT: sw a1, 8(sp)1047; RV32-V-NEXT: sw a0, 12(sp)1048; RV32-V-NEXT: addi a0, sp, 81049; RV32-V-NEXT: vsetvli a1, zero, e64, m8, ta, ma1050; RV32-V-NEXT: vlse64.v v16, (a0), zero1051; RV32-V-NEXT: li a0, 631052; RV32-V-NEXT: vmulh.vv v8, v8, v161053; RV32-V-NEXT: vsrl.vx v16, v8, a01054; RV32-V-NEXT: vsra.vi v8, v8, 11055; RV32-V-NEXT: vadd.vv v8, v8, v161056; RV32-V-NEXT: addi sp, sp, 161057; RV32-V-NEXT: .cfi_def_cfa_offset 01058; RV32-V-NEXT: ret1059;1060; ZVE64X-LABEL: vdiv_vi_nxv8i64_0:1061; ZVE64X: # %bb.0:1062; ZVE64X-NEXT: li a0, -71063; ZVE64X-NEXT: vsetvli a1, zero, e64, m8, ta, ma1064; ZVE64X-NEXT: vdiv.vx v8, v8, a01065; ZVE64X-NEXT: ret1066;1067; RV64-V-LABEL: vdiv_vi_nxv8i64_0:1068; RV64-V: # %bb.0:1069; RV64-V-NEXT: lui a0, %hi(.LCPI67_0)1070; RV64-V-NEXT: ld a0, %lo(.LCPI67_0)(a0)1071; RV64-V-NEXT: vsetvli a1, zero, e64, m8, ta, ma1072; RV64-V-NEXT: vmulh.vx v8, v8, a01073; RV64-V-NEXT: li a0, 631074; RV64-V-NEXT: vsrl.vx v16, v8, a01075; RV64-V-NEXT: vsra.vi v8, v8, 11076; RV64-V-NEXT: vadd.vv v8, v8, v161077; RV64-V-NEXT: ret1078 %vc = sdiv <vscale x 8 x i64> %va, splat (i64 -7)1079 ret <vscale x 8 x i64> %vc1080}1081 1082define <vscale x 8 x i32> @vdiv_vv_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {1083; CHECK-LABEL: vdiv_vv_mask_nxv8i32:1084; CHECK: # %bb.0:1085; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma1086; CHECK-NEXT: vmv.v.i v16, 11087; CHECK-NEXT: vmerge.vvm v12, v16, v12, v01088; CHECK-NEXT: vdiv.vv v8, v8, v121089; CHECK-NEXT: ret1090 %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> splat (i32 1)1091 %vc = sdiv <vscale x 8 x i32> %va, %vs1092 ret <vscale x 8 x i32> %vc1093}1094 1095define <vscale x 8 x i32> @vdiv_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {1096; CHECK-LABEL: vdiv_vx_mask_nxv8i32:1097; CHECK: # %bb.0:1098; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma1099; CHECK-NEXT: vmv.v.i v12, 11100; CHECK-NEXT: vmerge.vxm v12, v12, a0, v01101; CHECK-NEXT: vdiv.vv v8, v8, v121102; CHECK-NEXT: ret1103 %head2 = insertelement <vscale x 8 x i32> poison, i32 %b, i32 01104 %splat = shufflevector <vscale x 8 x i32> %head2, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer1105 %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> splat (i32 1)1106 %vc = sdiv <vscale x 8 x i32> %va, %vs1107 ret <vscale x 8 x i32> %vc1108}1109 1110define <vscale x 8 x i32> @vdiv_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {1111; CHECK-LABEL: vdiv_vi_mask_nxv8i32:1112; CHECK: # %bb.0:1113; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma1114; CHECK-NEXT: vmv.v.i v12, 11115; CHECK-NEXT: vmerge.vim v12, v12, 7, v01116; CHECK-NEXT: vdiv.vv v8, v8, v121117; CHECK-NEXT: ret1118 %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> splat (i32 7), <vscale x 8 x i32> splat (i32 1)1119 %vc = sdiv <vscale x 8 x i32> %va, %vs1120 ret <vscale x 8 x i32> %vc1121}1122