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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32-V3; RUN: llc -mtriple=riscv32 -mattr=+zve64x -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,ZVE64X4; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64-V5; RUN: llc -mtriple=riscv64 -mattr=+zve64x -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,ZVE64X6 7define <vscale x 1 x i8> @vdivu_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) {8; CHECK-LABEL: vdivu_vv_nxv1i8:9; CHECK: # %bb.0:10; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma11; CHECK-NEXT: vdivu.vv v8, v8, v912; CHECK-NEXT: ret13 %vc = udiv <vscale x 1 x i8> %va, %vb14 ret <vscale x 1 x i8> %vc15}16 17define <vscale x 1 x i8> @vdivu_vx_nxv1i8(<vscale x 1 x i8> %va, i8 signext %b) {18; CHECK-LABEL: vdivu_vx_nxv1i8:19; CHECK: # %bb.0:20; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma21; CHECK-NEXT: vdivu.vx v8, v8, a022; CHECK-NEXT: ret23 %head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 024 %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer25 %vc = udiv <vscale x 1 x i8> %va, %splat26 ret <vscale x 1 x i8> %vc27}28 29define <vscale x 1 x i8> @vdivu_vi_nxv1i8_0(<vscale x 1 x i8> %va) {30; CHECK-LABEL: vdivu_vi_nxv1i8_0:31; CHECK: # %bb.0:32; CHECK-NEXT: li a0, 3333; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma34; CHECK-NEXT: vmulhu.vx v8, v8, a035; CHECK-NEXT: vsrl.vi v8, v8, 536; CHECK-NEXT: ret37 %vc = udiv <vscale x 1 x i8> %va, splat (i8 -7)38 ret <vscale x 1 x i8> %vc39}40 41; Test V/1 to see if we can optimize it away for scalable vectors.42define <vscale x 1 x i8> @vdivu_vi_nxv1i8_1(<vscale x 1 x i8> %va) {43; CHECK-LABEL: vdivu_vi_nxv1i8_1:44; CHECK: # %bb.0:45; CHECK-NEXT: ret46 %vc = udiv <vscale x 1 x i8> %va, splat (i8 1)47 ret <vscale x 1 x i8> %vc48}49 50; Test 0/V to see if we can optimize it away for scalable vectors.51define <vscale x 1 x i8> @vdivu_iv_nxv1i8_0(<vscale x 1 x i8> %va) {52; CHECK-LABEL: vdivu_iv_nxv1i8_0:53; CHECK: # %bb.0:54; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma55; CHECK-NEXT: vmv.v.i v8, 056; CHECK-NEXT: ret57 %vc = udiv <vscale x 1 x i8> splat (i8 0), %va58 ret <vscale x 1 x i8> %vc59}60 61define <vscale x 2 x i8> @vdivu_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb) {62; CHECK-LABEL: vdivu_vv_nxv2i8:63; CHECK: # %bb.0:64; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma65; CHECK-NEXT: vdivu.vv v8, v8, v966; CHECK-NEXT: ret67 %vc = udiv <vscale x 2 x i8> %va, %vb68 ret <vscale x 2 x i8> %vc69}70 71define <vscale x 2 x i8> @vdivu_vx_nxv2i8(<vscale x 2 x i8> %va, i8 signext %b) {72; CHECK-LABEL: vdivu_vx_nxv2i8:73; CHECK: # %bb.0:74; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma75; CHECK-NEXT: vdivu.vx v8, v8, a076; CHECK-NEXT: ret77 %head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 078 %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer79 %vc = udiv <vscale x 2 x i8> %va, %splat80 ret <vscale x 2 x i8> %vc81}82 83define <vscale x 2 x i8> @vdivu_vi_nxv2i8_0(<vscale x 2 x i8> %va) {84; CHECK-LABEL: vdivu_vi_nxv2i8_0:85; CHECK: # %bb.0:86; CHECK-NEXT: li a0, 3387; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma88; CHECK-NEXT: vmulhu.vx v8, v8, a089; CHECK-NEXT: vsrl.vi v8, v8, 590; CHECK-NEXT: ret91 %vc = udiv <vscale x 2 x i8> %va, splat (i8 -7)92 ret <vscale x 2 x i8> %vc93}94 95define <vscale x 4 x i8> @vdivu_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) {96; CHECK-LABEL: vdivu_vv_nxv4i8:97; CHECK: # %bb.0:98; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma99; CHECK-NEXT: vdivu.vv v8, v8, v9100; CHECK-NEXT: ret101 %vc = udiv <vscale x 4 x i8> %va, %vb102 ret <vscale x 4 x i8> %vc103}104 105define <vscale x 4 x i8> @vdivu_vx_nxv4i8(<vscale x 4 x i8> %va, i8 signext %b) {106; CHECK-LABEL: vdivu_vx_nxv4i8:107; CHECK: # %bb.0:108; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma109; CHECK-NEXT: vdivu.vx v8, v8, a0110; CHECK-NEXT: ret111 %head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0112 %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer113 %vc = udiv <vscale x 4 x i8> %va, %splat114 ret <vscale x 4 x i8> %vc115}116 117define <vscale x 4 x i8> @vdivu_vi_nxv4i8_0(<vscale x 4 x i8> %va) {118; CHECK-LABEL: vdivu_vi_nxv4i8_0:119; CHECK: # %bb.0:120; CHECK-NEXT: li a0, 33121; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma122; CHECK-NEXT: vmulhu.vx v8, v8, a0123; CHECK-NEXT: vsrl.vi v8, v8, 5124; CHECK-NEXT: ret125 %vc = udiv <vscale x 4 x i8> %va, splat (i8 -7)126 ret <vscale x 4 x i8> %vc127}128 129define <vscale x 8 x i8> @vdivu_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {130; CHECK-LABEL: vdivu_vv_nxv8i8:131; CHECK: # %bb.0:132; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma133; CHECK-NEXT: vdivu.vv v8, v8, v9134; CHECK-NEXT: ret135 %vc = udiv <vscale x 8 x i8> %va, %vb136 ret <vscale x 8 x i8> %vc137}138 139define <vscale x 8 x i8> @vdivu_vx_nxv8i8(<vscale x 8 x i8> %va, i8 signext %b) {140; CHECK-LABEL: vdivu_vx_nxv8i8:141; CHECK: # %bb.0:142; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma143; CHECK-NEXT: vdivu.vx v8, v8, a0144; CHECK-NEXT: ret145 %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0146 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer147 %vc = udiv <vscale x 8 x i8> %va, %splat148 ret <vscale x 8 x i8> %vc149}150 151define <vscale x 8 x i8> @vdivu_vi_nxv8i8_0(<vscale x 8 x i8> %va) {152; CHECK-LABEL: vdivu_vi_nxv8i8_0:153; CHECK: # %bb.0:154; CHECK-NEXT: li a0, 33155; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma156; CHECK-NEXT: vmulhu.vx v8, v8, a0157; CHECK-NEXT: vsrl.vi v8, v8, 5158; CHECK-NEXT: ret159 %vc = udiv <vscale x 8 x i8> %va, splat (i8 -7)160 ret <vscale x 8 x i8> %vc161}162 163define <vscale x 16 x i8> @vdivu_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb) {164; CHECK-LABEL: vdivu_vv_nxv16i8:165; CHECK: # %bb.0:166; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma167; CHECK-NEXT: vdivu.vv v8, v8, v10168; CHECK-NEXT: ret169 %vc = udiv <vscale x 16 x i8> %va, %vb170 ret <vscale x 16 x i8> %vc171}172 173define <vscale x 16 x i8> @vdivu_vx_nxv16i8(<vscale x 16 x i8> %va, i8 signext %b) {174; CHECK-LABEL: vdivu_vx_nxv16i8:175; CHECK: # %bb.0:176; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma177; CHECK-NEXT: vdivu.vx v8, v8, a0178; CHECK-NEXT: ret179 %head = insertelement <vscale x 16 x i8> poison, i8 %b, i32 0180 %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer181 %vc = udiv <vscale x 16 x i8> %va, %splat182 ret <vscale x 16 x i8> %vc183}184 185define <vscale x 16 x i8> @vdivu_vi_nxv16i8_0(<vscale x 16 x i8> %va) {186; CHECK-LABEL: vdivu_vi_nxv16i8_0:187; CHECK: # %bb.0:188; CHECK-NEXT: li a0, 33189; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma190; CHECK-NEXT: vmulhu.vx v8, v8, a0191; CHECK-NEXT: vsrl.vi v8, v8, 5192; CHECK-NEXT: ret193 %vc = udiv <vscale x 16 x i8> %va, splat (i8 -7)194 ret <vscale x 16 x i8> %vc195}196 197define <vscale x 32 x i8> @vdivu_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb) {198; CHECK-LABEL: vdivu_vv_nxv32i8:199; CHECK: # %bb.0:200; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma201; CHECK-NEXT: vdivu.vv v8, v8, v12202; CHECK-NEXT: ret203 %vc = udiv <vscale x 32 x i8> %va, %vb204 ret <vscale x 32 x i8> %vc205}206 207define <vscale x 32 x i8> @vdivu_vx_nxv32i8(<vscale x 32 x i8> %va, i8 signext %b) {208; CHECK-LABEL: vdivu_vx_nxv32i8:209; CHECK: # %bb.0:210; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma211; CHECK-NEXT: vdivu.vx v8, v8, a0212; CHECK-NEXT: ret213 %head = insertelement <vscale x 32 x i8> poison, i8 %b, i32 0214 %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer215 %vc = udiv <vscale x 32 x i8> %va, %splat216 ret <vscale x 32 x i8> %vc217}218 219define <vscale x 32 x i8> @vdivu_vi_nxv32i8_0(<vscale x 32 x i8> %va) {220; CHECK-LABEL: vdivu_vi_nxv32i8_0:221; CHECK: # %bb.0:222; CHECK-NEXT: li a0, 33223; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma224; CHECK-NEXT: vmulhu.vx v8, v8, a0225; CHECK-NEXT: vsrl.vi v8, v8, 5226; CHECK-NEXT: ret227 %vc = udiv <vscale x 32 x i8> %va, splat (i8 -7)228 ret <vscale x 32 x i8> %vc229}230 231define <vscale x 64 x i8> @vdivu_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb) {232; CHECK-LABEL: vdivu_vv_nxv64i8:233; CHECK: # %bb.0:234; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma235; CHECK-NEXT: vdivu.vv v8, v8, v16236; CHECK-NEXT: ret237 %vc = udiv <vscale x 64 x i8> %va, %vb238 ret <vscale x 64 x i8> %vc239}240 241define <vscale x 64 x i8> @vdivu_vx_nxv64i8(<vscale x 64 x i8> %va, i8 signext %b) {242; CHECK-LABEL: vdivu_vx_nxv64i8:243; CHECK: # %bb.0:244; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma245; CHECK-NEXT: vdivu.vx v8, v8, a0246; CHECK-NEXT: ret247 %head = insertelement <vscale x 64 x i8> poison, i8 %b, i32 0248 %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer249 %vc = udiv <vscale x 64 x i8> %va, %splat250 ret <vscale x 64 x i8> %vc251}252 253define <vscale x 64 x i8> @vdivu_vi_nxv64i8_0(<vscale x 64 x i8> %va) {254; CHECK-LABEL: vdivu_vi_nxv64i8_0:255; CHECK: # %bb.0:256; CHECK-NEXT: li a0, 33257; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma258; CHECK-NEXT: vmulhu.vx v8, v8, a0259; CHECK-NEXT: vsrl.vi v8, v8, 5260; CHECK-NEXT: ret261 %vc = udiv <vscale x 64 x i8> %va, splat (i8 -7)262 ret <vscale x 64 x i8> %vc263}264 265define <vscale x 1 x i16> @vdivu_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) {266; CHECK-LABEL: vdivu_vv_nxv1i16:267; CHECK: # %bb.0:268; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma269; CHECK-NEXT: vdivu.vv v8, v8, v9270; CHECK-NEXT: ret271 %vc = udiv <vscale x 1 x i16> %va, %vb272 ret <vscale x 1 x i16> %vc273}274 275define <vscale x 1 x i16> @vdivu_vx_nxv1i16(<vscale x 1 x i16> %va, i16 signext %b) {276; CHECK-LABEL: vdivu_vx_nxv1i16:277; CHECK: # %bb.0:278; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma279; CHECK-NEXT: vdivu.vx v8, v8, a0280; CHECK-NEXT: ret281 %head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0282 %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer283 %vc = udiv <vscale x 1 x i16> %va, %splat284 ret <vscale x 1 x i16> %vc285}286 287define <vscale x 1 x i16> @vdivu_vi_nxv1i16_0(<vscale x 1 x i16> %va) {288; CHECK-LABEL: vdivu_vi_nxv1i16_0:289; CHECK: # %bb.0:290; CHECK-NEXT: lui a0, 2291; CHECK-NEXT: addi a0, a0, 1292; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma293; CHECK-NEXT: vmulhu.vx v8, v8, a0294; CHECK-NEXT: vsrl.vi v8, v8, 13295; CHECK-NEXT: ret296 %vc = udiv <vscale x 1 x i16> %va, splat (i16 -7)297 ret <vscale x 1 x i16> %vc298}299 300define <vscale x 2 x i16> @vdivu_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) {301; CHECK-LABEL: vdivu_vv_nxv2i16:302; CHECK: # %bb.0:303; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma304; CHECK-NEXT: vdivu.vv v8, v8, v9305; CHECK-NEXT: ret306 %vc = udiv <vscale x 2 x i16> %va, %vb307 ret <vscale x 2 x i16> %vc308}309 310define <vscale x 2 x i16> @vdivu_vx_nxv2i16(<vscale x 2 x i16> %va, i16 signext %b) {311; CHECK-LABEL: vdivu_vx_nxv2i16:312; CHECK: # %bb.0:313; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma314; CHECK-NEXT: vdivu.vx v8, v8, a0315; CHECK-NEXT: ret316 %head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0317 %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer318 %vc = udiv <vscale x 2 x i16> %va, %splat319 ret <vscale x 2 x i16> %vc320}321 322define <vscale x 2 x i16> @vdivu_vi_nxv2i16_0(<vscale x 2 x i16> %va) {323; CHECK-LABEL: vdivu_vi_nxv2i16_0:324; CHECK: # %bb.0:325; CHECK-NEXT: lui a0, 2326; CHECK-NEXT: addi a0, a0, 1327; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma328; CHECK-NEXT: vmulhu.vx v8, v8, a0329; CHECK-NEXT: vsrl.vi v8, v8, 13330; CHECK-NEXT: ret331 %vc = udiv <vscale x 2 x i16> %va, splat (i16 -7)332 ret <vscale x 2 x i16> %vc333}334 335define <vscale x 4 x i16> @vdivu_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) {336; CHECK-LABEL: vdivu_vv_nxv4i16:337; CHECK: # %bb.0:338; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma339; CHECK-NEXT: vdivu.vv v8, v8, v9340; CHECK-NEXT: ret341 %vc = udiv <vscale x 4 x i16> %va, %vb342 ret <vscale x 4 x i16> %vc343}344 345define <vscale x 4 x i16> @vdivu_vx_nxv4i16(<vscale x 4 x i16> %va, i16 signext %b) {346; CHECK-LABEL: vdivu_vx_nxv4i16:347; CHECK: # %bb.0:348; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma349; CHECK-NEXT: vdivu.vx v8, v8, a0350; CHECK-NEXT: ret351 %head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0352 %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer353 %vc = udiv <vscale x 4 x i16> %va, %splat354 ret <vscale x 4 x i16> %vc355}356 357define <vscale x 4 x i16> @vdivu_vi_nxv4i16_0(<vscale x 4 x i16> %va) {358; CHECK-LABEL: vdivu_vi_nxv4i16_0:359; CHECK: # %bb.0:360; CHECK-NEXT: lui a0, 2361; CHECK-NEXT: addi a0, a0, 1362; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma363; CHECK-NEXT: vmulhu.vx v8, v8, a0364; CHECK-NEXT: vsrl.vi v8, v8, 13365; CHECK-NEXT: ret366 %vc = udiv <vscale x 4 x i16> %va, splat (i16 -7)367 ret <vscale x 4 x i16> %vc368}369 370define <vscale x 8 x i16> @vdivu_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {371; CHECK-LABEL: vdivu_vv_nxv8i16:372; CHECK: # %bb.0:373; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma374; CHECK-NEXT: vdivu.vv v8, v8, v10375; CHECK-NEXT: ret376 %vc = udiv <vscale x 8 x i16> %va, %vb377 ret <vscale x 8 x i16> %vc378}379 380define <vscale x 8 x i16> @vdivu_vx_nxv8i16(<vscale x 8 x i16> %va, i16 signext %b) {381; CHECK-LABEL: vdivu_vx_nxv8i16:382; CHECK: # %bb.0:383; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma384; CHECK-NEXT: vdivu.vx v8, v8, a0385; CHECK-NEXT: ret386 %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0387 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer388 %vc = udiv <vscale x 8 x i16> %va, %splat389 ret <vscale x 8 x i16> %vc390}391 392define <vscale x 8 x i16> @vdivu_vi_nxv8i16_0(<vscale x 8 x i16> %va) {393; CHECK-LABEL: vdivu_vi_nxv8i16_0:394; CHECK: # %bb.0:395; CHECK-NEXT: lui a0, 2396; CHECK-NEXT: addi a0, a0, 1397; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma398; CHECK-NEXT: vmulhu.vx v8, v8, a0399; CHECK-NEXT: vsrl.vi v8, v8, 13400; CHECK-NEXT: ret401 %vc = udiv <vscale x 8 x i16> %va, splat (i16 -7)402 ret <vscale x 8 x i16> %vc403}404 405define <vscale x 16 x i16> @vdivu_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb) {406; CHECK-LABEL: vdivu_vv_nxv16i16:407; CHECK: # %bb.0:408; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma409; CHECK-NEXT: vdivu.vv v8, v8, v12410; CHECK-NEXT: ret411 %vc = udiv <vscale x 16 x i16> %va, %vb412 ret <vscale x 16 x i16> %vc413}414 415define <vscale x 16 x i16> @vdivu_vx_nxv16i16(<vscale x 16 x i16> %va, i16 signext %b) {416; CHECK-LABEL: vdivu_vx_nxv16i16:417; CHECK: # %bb.0:418; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma419; CHECK-NEXT: vdivu.vx v8, v8, a0420; CHECK-NEXT: ret421 %head = insertelement <vscale x 16 x i16> poison, i16 %b, i32 0422 %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer423 %vc = udiv <vscale x 16 x i16> %va, %splat424 ret <vscale x 16 x i16> %vc425}426 427define <vscale x 16 x i16> @vdivu_vi_nxv16i16_0(<vscale x 16 x i16> %va) {428; CHECK-LABEL: vdivu_vi_nxv16i16_0:429; CHECK: # %bb.0:430; CHECK-NEXT: lui a0, 2431; CHECK-NEXT: addi a0, a0, 1432; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma433; CHECK-NEXT: vmulhu.vx v8, v8, a0434; CHECK-NEXT: vsrl.vi v8, v8, 13435; CHECK-NEXT: ret436 %vc = udiv <vscale x 16 x i16> %va, splat (i16 -7)437 ret <vscale x 16 x i16> %vc438}439 440define <vscale x 32 x i16> @vdivu_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb) {441; CHECK-LABEL: vdivu_vv_nxv32i16:442; CHECK: # %bb.0:443; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma444; CHECK-NEXT: vdivu.vv v8, v8, v16445; CHECK-NEXT: ret446 %vc = udiv <vscale x 32 x i16> %va, %vb447 ret <vscale x 32 x i16> %vc448}449 450define <vscale x 32 x i16> @vdivu_vx_nxv32i16(<vscale x 32 x i16> %va, i16 signext %b) {451; CHECK-LABEL: vdivu_vx_nxv32i16:452; CHECK: # %bb.0:453; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma454; CHECK-NEXT: vdivu.vx v8, v8, a0455; CHECK-NEXT: ret456 %head = insertelement <vscale x 32 x i16> poison, i16 %b, i32 0457 %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer458 %vc = udiv <vscale x 32 x i16> %va, %splat459 ret <vscale x 32 x i16> %vc460}461 462define <vscale x 32 x i16> @vdivu_vi_nxv32i16_0(<vscale x 32 x i16> %va) {463; CHECK-LABEL: vdivu_vi_nxv32i16_0:464; CHECK: # %bb.0:465; CHECK-NEXT: lui a0, 2466; CHECK-NEXT: addi a0, a0, 1467; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma468; CHECK-NEXT: vmulhu.vx v8, v8, a0469; CHECK-NEXT: vsrl.vi v8, v8, 13470; CHECK-NEXT: ret471 %vc = udiv <vscale x 32 x i16> %va, splat (i16 -7)472 ret <vscale x 32 x i16> %vc473}474 475define <vscale x 1 x i32> @vdivu_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {476; CHECK-LABEL: vdivu_vv_nxv1i32:477; CHECK: # %bb.0:478; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma479; CHECK-NEXT: vdivu.vv v8, v8, v9480; CHECK-NEXT: ret481 %vc = udiv <vscale x 1 x i32> %va, %vb482 ret <vscale x 1 x i32> %vc483}484 485define <vscale x 1 x i32> @vdivu_vx_nxv1i32(<vscale x 1 x i32> %va, i32 signext %b) {486; CHECK-LABEL: vdivu_vx_nxv1i32:487; CHECK: # %bb.0:488; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma489; CHECK-NEXT: vdivu.vx v8, v8, a0490; CHECK-NEXT: ret491 %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0492 %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer493 %vc = udiv <vscale x 1 x i32> %va, %splat494 ret <vscale x 1 x i32> %vc495}496 497define <vscale x 1 x i32> @vdivu_vi_nxv1i32_0(<vscale x 1 x i32> %va) {498; CHECK-LABEL: vdivu_vi_nxv1i32_0:499; CHECK: # %bb.0:500; CHECK-NEXT: lui a0, 131072501; CHECK-NEXT: addi a0, a0, 1502; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma503; CHECK-NEXT: vmulhu.vx v8, v8, a0504; CHECK-NEXT: vsrl.vi v8, v8, 29505; CHECK-NEXT: ret506 %vc = udiv <vscale x 1 x i32> %va, splat (i32 -7)507 ret <vscale x 1 x i32> %vc508}509 510define <vscale x 2 x i32> @vdivu_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {511; CHECK-LABEL: vdivu_vv_nxv2i32:512; CHECK: # %bb.0:513; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma514; CHECK-NEXT: vdivu.vv v8, v8, v9515; CHECK-NEXT: ret516 %vc = udiv <vscale x 2 x i32> %va, %vb517 ret <vscale x 2 x i32> %vc518}519 520define <vscale x 2 x i32> @vdivu_vx_nxv2i32(<vscale x 2 x i32> %va, i32 signext %b) {521; CHECK-LABEL: vdivu_vx_nxv2i32:522; CHECK: # %bb.0:523; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma524; CHECK-NEXT: vdivu.vx v8, v8, a0525; CHECK-NEXT: ret526 %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0527 %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer528 %vc = udiv <vscale x 2 x i32> %va, %splat529 ret <vscale x 2 x i32> %vc530}531 532define <vscale x 2 x i32> @vdivu_vi_nxv2i32_0(<vscale x 2 x i32> %va) {533; CHECK-LABEL: vdivu_vi_nxv2i32_0:534; CHECK: # %bb.0:535; CHECK-NEXT: lui a0, 131072536; CHECK-NEXT: addi a0, a0, 1537; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma538; CHECK-NEXT: vmulhu.vx v8, v8, a0539; CHECK-NEXT: vsrl.vi v8, v8, 29540; CHECK-NEXT: ret541 %vc = udiv <vscale x 2 x i32> %va, splat (i32 -7)542 ret <vscale x 2 x i32> %vc543}544 545define <vscale x 4 x i32> @vdivu_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {546; CHECK-LABEL: vdivu_vv_nxv4i32:547; CHECK: # %bb.0:548; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma549; CHECK-NEXT: vdivu.vv v8, v8, v10550; CHECK-NEXT: ret551 %vc = udiv <vscale x 4 x i32> %va, %vb552 ret <vscale x 4 x i32> %vc553}554 555define <vscale x 4 x i32> @vdivu_vx_nxv4i32(<vscale x 4 x i32> %va, i32 signext %b) {556; CHECK-LABEL: vdivu_vx_nxv4i32:557; CHECK: # %bb.0:558; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma559; CHECK-NEXT: vdivu.vx v8, v8, a0560; CHECK-NEXT: ret561 %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0562 %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer563 %vc = udiv <vscale x 4 x i32> %va, %splat564 ret <vscale x 4 x i32> %vc565}566 567define <vscale x 4 x i32> @vdivu_vi_nxv4i32_0(<vscale x 4 x i32> %va) {568; CHECK-LABEL: vdivu_vi_nxv4i32_0:569; CHECK: # %bb.0:570; CHECK-NEXT: lui a0, 131072571; CHECK-NEXT: addi a0, a0, 1572; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma573; CHECK-NEXT: vmulhu.vx v8, v8, a0574; CHECK-NEXT: vsrl.vi v8, v8, 29575; CHECK-NEXT: ret576 %vc = udiv <vscale x 4 x i32> %va, splat (i32 -7)577 ret <vscale x 4 x i32> %vc578}579 580define <vscale x 8 x i32> @vdivu_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {581; CHECK-LABEL: vdivu_vv_nxv8i32:582; CHECK: # %bb.0:583; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma584; CHECK-NEXT: vdivu.vv v8, v8, v12585; CHECK-NEXT: ret586 %vc = udiv <vscale x 8 x i32> %va, %vb587 ret <vscale x 8 x i32> %vc588}589 590define <vscale x 8 x i32> @vdivu_vx_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b) {591; CHECK-LABEL: vdivu_vx_nxv8i32:592; CHECK: # %bb.0:593; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma594; CHECK-NEXT: vdivu.vx v8, v8, a0595; CHECK-NEXT: ret596 %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0597 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer598 %vc = udiv <vscale x 8 x i32> %va, %splat599 ret <vscale x 8 x i32> %vc600}601 602define <vscale x 8 x i32> @vdivu_vi_nxv8i32_0(<vscale x 8 x i32> %va) {603; CHECK-LABEL: vdivu_vi_nxv8i32_0:604; CHECK: # %bb.0:605; CHECK-NEXT: lui a0, 131072606; CHECK-NEXT: addi a0, a0, 1607; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma608; CHECK-NEXT: vmulhu.vx v8, v8, a0609; CHECK-NEXT: vsrl.vi v8, v8, 29610; CHECK-NEXT: ret611 %vc = udiv <vscale x 8 x i32> %va, splat (i32 -7)612 ret <vscale x 8 x i32> %vc613}614 615define <vscale x 16 x i32> @vdivu_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb) {616; CHECK-LABEL: vdivu_vv_nxv16i32:617; CHECK: # %bb.0:618; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma619; CHECK-NEXT: vdivu.vv v8, v8, v16620; CHECK-NEXT: ret621 %vc = udiv <vscale x 16 x i32> %va, %vb622 ret <vscale x 16 x i32> %vc623}624 625define <vscale x 16 x i32> @vdivu_vx_nxv16i32(<vscale x 16 x i32> %va, i32 signext %b) {626; CHECK-LABEL: vdivu_vx_nxv16i32:627; CHECK: # %bb.0:628; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma629; CHECK-NEXT: vdivu.vx v8, v8, a0630; CHECK-NEXT: ret631 %head = insertelement <vscale x 16 x i32> poison, i32 %b, i32 0632 %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer633 %vc = udiv <vscale x 16 x i32> %va, %splat634 ret <vscale x 16 x i32> %vc635}636 637define <vscale x 16 x i32> @vdivu_vi_nxv16i32_0(<vscale x 16 x i32> %va) {638; CHECK-LABEL: vdivu_vi_nxv16i32_0:639; CHECK: # %bb.0:640; CHECK-NEXT: lui a0, 131072641; CHECK-NEXT: addi a0, a0, 1642; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma643; CHECK-NEXT: vmulhu.vx v8, v8, a0644; CHECK-NEXT: vsrl.vi v8, v8, 29645; CHECK-NEXT: ret646 %vc = udiv <vscale x 16 x i32> %va, splat (i32 -7)647 ret <vscale x 16 x i32> %vc648}649 650define <vscale x 1 x i64> @vdivu_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb) {651; CHECK-LABEL: vdivu_vv_nxv1i64:652; CHECK: # %bb.0:653; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma654; CHECK-NEXT: vdivu.vv v8, v8, v9655; CHECK-NEXT: ret656 %vc = udiv <vscale x 1 x i64> %va, %vb657 ret <vscale x 1 x i64> %vc658}659 660define <vscale x 1 x i64> @vdivu_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {661; RV32-LABEL: vdivu_vx_nxv1i64:662; RV32: # %bb.0:663; RV32-NEXT: addi sp, sp, -16664; RV32-NEXT: .cfi_def_cfa_offset 16665; RV32-NEXT: sw a0, 8(sp)666; RV32-NEXT: sw a1, 12(sp)667; RV32-NEXT: addi a0, sp, 8668; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma669; RV32-NEXT: vlse64.v v9, (a0), zero670; RV32-NEXT: vdivu.vv v8, v8, v9671; RV32-NEXT: addi sp, sp, 16672; RV32-NEXT: .cfi_def_cfa_offset 0673; RV32-NEXT: ret674;675; RV64-LABEL: vdivu_vx_nxv1i64:676; RV64: # %bb.0:677; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, ma678; RV64-NEXT: vdivu.vx v8, v8, a0679; RV64-NEXT: ret680 %head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0681 %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer682 %vc = udiv <vscale x 1 x i64> %va, %splat683 ret <vscale x 1 x i64> %vc684}685 686define <vscale x 1 x i64> @vdivu_vi_nxv1i64_0(<vscale x 1 x i64> %va) {687; RV32-V-LABEL: vdivu_vi_nxv1i64_0:688; RV32-V: # %bb.0:689; RV32-V-NEXT: addi sp, sp, -16690; RV32-V-NEXT: .cfi_def_cfa_offset 16691; RV32-V-NEXT: lui a0, 131072692; RV32-V-NEXT: li a1, 1693; RV32-V-NEXT: sw a1, 8(sp)694; RV32-V-NEXT: sw a0, 12(sp)695; RV32-V-NEXT: addi a0, sp, 8696; RV32-V-NEXT: vsetvli a1, zero, e64, m1, ta, ma697; RV32-V-NEXT: vlse64.v v9, (a0), zero698; RV32-V-NEXT: vmulhu.vv v8, v8, v9699; RV32-V-NEXT: li a0, 61700; RV32-V-NEXT: vsrl.vx v8, v8, a0701; RV32-V-NEXT: addi sp, sp, 16702; RV32-V-NEXT: .cfi_def_cfa_offset 0703; RV32-V-NEXT: ret704;705; ZVE64X-LABEL: vdivu_vi_nxv1i64_0:706; ZVE64X: # %bb.0:707; ZVE64X-NEXT: li a0, -7708; ZVE64X-NEXT: vsetvli a1, zero, e64, m1, ta, ma709; ZVE64X-NEXT: vdivu.vx v8, v8, a0710; ZVE64X-NEXT: ret711;712; RV64-V-LABEL: vdivu_vi_nxv1i64_0:713; RV64-V: # %bb.0:714; RV64-V-NEXT: li a0, 1715; RV64-V-NEXT: slli a0, a0, 61716; RV64-V-NEXT: addi a0, a0, 1717; RV64-V-NEXT: vsetvli a1, zero, e64, m1, ta, ma718; RV64-V-NEXT: vmulhu.vx v8, v8, a0719; RV64-V-NEXT: li a0, 61720; RV64-V-NEXT: vsrl.vx v8, v8, a0721; RV64-V-NEXT: ret722 %vc = udiv <vscale x 1 x i64> %va, splat (i64 -7)723 ret <vscale x 1 x i64> %vc724}725 726define <vscale x 1 x i64> @vdivu_vi_nxv1i64_1(<vscale x 1 x i64> %va) {727; CHECK-LABEL: vdivu_vi_nxv1i64_1:728; CHECK: # %bb.0:729; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma730; CHECK-NEXT: vsrl.vi v8, v8, 1731; CHECK-NEXT: ret732 %vc = udiv <vscale x 1 x i64> %va, splat (i64 2)733 ret <vscale x 1 x i64> %vc734}735 736; fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) if c is power of 2737define <vscale x 1 x i64> @vdivu_vi_nxv1i64_2(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb) {738; CHECK-LABEL: vdivu_vi_nxv1i64_2:739; CHECK: # %bb.0:740; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma741; CHECK-NEXT: vadd.vi v9, v9, 4742; CHECK-NEXT: vsrl.vv v8, v8, v9743; CHECK-NEXT: ret744 %vc = shl <vscale x 1 x i64> splat (i64 16), %vb745 %vd = udiv <vscale x 1 x i64> %va, %vc746 ret <vscale x 1 x i64> %vd747}748 749define <vscale x 2 x i64> @vdivu_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) {750; CHECK-LABEL: vdivu_vv_nxv2i64:751; CHECK: # %bb.0:752; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma753; CHECK-NEXT: vdivu.vv v8, v8, v10754; CHECK-NEXT: ret755 %vc = udiv <vscale x 2 x i64> %va, %vb756 ret <vscale x 2 x i64> %vc757}758 759define <vscale x 2 x i64> @vdivu_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {760; RV32-LABEL: vdivu_vx_nxv2i64:761; RV32: # %bb.0:762; RV32-NEXT: addi sp, sp, -16763; RV32-NEXT: .cfi_def_cfa_offset 16764; RV32-NEXT: sw a0, 8(sp)765; RV32-NEXT: sw a1, 12(sp)766; RV32-NEXT: addi a0, sp, 8767; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma768; RV32-NEXT: vlse64.v v10, (a0), zero769; RV32-NEXT: vdivu.vv v8, v8, v10770; RV32-NEXT: addi sp, sp, 16771; RV32-NEXT: .cfi_def_cfa_offset 0772; RV32-NEXT: ret773;774; RV64-LABEL: vdivu_vx_nxv2i64:775; RV64: # %bb.0:776; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, ma777; RV64-NEXT: vdivu.vx v8, v8, a0778; RV64-NEXT: ret779 %head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0780 %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer781 %vc = udiv <vscale x 2 x i64> %va, %splat782 ret <vscale x 2 x i64> %vc783}784 785define <vscale x 2 x i64> @vdivu_vi_nxv2i64_0(<vscale x 2 x i64> %va) {786; RV32-V-LABEL: vdivu_vi_nxv2i64_0:787; RV32-V: # %bb.0:788; RV32-V-NEXT: addi sp, sp, -16789; RV32-V-NEXT: .cfi_def_cfa_offset 16790; RV32-V-NEXT: lui a0, 131072791; RV32-V-NEXT: li a1, 1792; RV32-V-NEXT: sw a1, 8(sp)793; RV32-V-NEXT: sw a0, 12(sp)794; RV32-V-NEXT: addi a0, sp, 8795; RV32-V-NEXT: vsetvli a1, zero, e64, m2, ta, ma796; RV32-V-NEXT: vlse64.v v10, (a0), zero797; RV32-V-NEXT: vmulhu.vv v8, v8, v10798; RV32-V-NEXT: li a0, 61799; RV32-V-NEXT: vsrl.vx v8, v8, a0800; RV32-V-NEXT: addi sp, sp, 16801; RV32-V-NEXT: .cfi_def_cfa_offset 0802; RV32-V-NEXT: ret803;804; ZVE64X-LABEL: vdivu_vi_nxv2i64_0:805; ZVE64X: # %bb.0:806; ZVE64X-NEXT: li a0, -7807; ZVE64X-NEXT: vsetvli a1, zero, e64, m2, ta, ma808; ZVE64X-NEXT: vdivu.vx v8, v8, a0809; ZVE64X-NEXT: ret810;811; RV64-V-LABEL: vdivu_vi_nxv2i64_0:812; RV64-V: # %bb.0:813; RV64-V-NEXT: li a0, 1814; RV64-V-NEXT: slli a0, a0, 61815; RV64-V-NEXT: addi a0, a0, 1816; RV64-V-NEXT: vsetvli a1, zero, e64, m2, ta, ma817; RV64-V-NEXT: vmulhu.vx v8, v8, a0818; RV64-V-NEXT: li a0, 61819; RV64-V-NEXT: vsrl.vx v8, v8, a0820; RV64-V-NEXT: ret821 %vc = udiv <vscale x 2 x i64> %va, splat (i64 -7)822 ret <vscale x 2 x i64> %vc823}824 825define <vscale x 2 x i64> @vdivu_vi_nxv2i64_1(<vscale x 2 x i64> %va) {826; CHECK-LABEL: vdivu_vi_nxv2i64_1:827; CHECK: # %bb.0:828; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma829; CHECK-NEXT: vsrl.vi v8, v8, 1830; CHECK-NEXT: ret831 %vc = udiv <vscale x 2 x i64> %va, splat (i64 2)832 ret <vscale x 2 x i64> %vc833}834 835; fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) if c is power of 2836define <vscale x 2 x i64> @vdivu_vi_nxv2i64_2(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) {837; CHECK-LABEL: vdivu_vi_nxv2i64_2:838; CHECK: # %bb.0:839; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma840; CHECK-NEXT: vadd.vi v10, v10, 4841; CHECK-NEXT: vsrl.vv v8, v8, v10842; CHECK-NEXT: ret843 %vc = shl <vscale x 2 x i64> splat (i64 16), %vb844 %vd = udiv <vscale x 2 x i64> %va, %vc845 ret <vscale x 2 x i64> %vd846}847 848define <vscale x 4 x i64> @vdivu_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) {849; CHECK-LABEL: vdivu_vv_nxv4i64:850; CHECK: # %bb.0:851; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma852; CHECK-NEXT: vdivu.vv v8, v8, v12853; CHECK-NEXT: ret854 %vc = udiv <vscale x 4 x i64> %va, %vb855 ret <vscale x 4 x i64> %vc856}857 858define <vscale x 4 x i64> @vdivu_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {859; RV32-LABEL: vdivu_vx_nxv4i64:860; RV32: # %bb.0:861; RV32-NEXT: addi sp, sp, -16862; RV32-NEXT: .cfi_def_cfa_offset 16863; RV32-NEXT: sw a0, 8(sp)864; RV32-NEXT: sw a1, 12(sp)865; RV32-NEXT: addi a0, sp, 8866; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma867; RV32-NEXT: vlse64.v v12, (a0), zero868; RV32-NEXT: vdivu.vv v8, v8, v12869; RV32-NEXT: addi sp, sp, 16870; RV32-NEXT: .cfi_def_cfa_offset 0871; RV32-NEXT: ret872;873; RV64-LABEL: vdivu_vx_nxv4i64:874; RV64: # %bb.0:875; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, ma876; RV64-NEXT: vdivu.vx v8, v8, a0877; RV64-NEXT: ret878 %head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0879 %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer880 %vc = udiv <vscale x 4 x i64> %va, %splat881 ret <vscale x 4 x i64> %vc882}883 884define <vscale x 4 x i64> @vdivu_vi_nxv4i64_0(<vscale x 4 x i64> %va) {885; RV32-V-LABEL: vdivu_vi_nxv4i64_0:886; RV32-V: # %bb.0:887; RV32-V-NEXT: addi sp, sp, -16888; RV32-V-NEXT: .cfi_def_cfa_offset 16889; RV32-V-NEXT: lui a0, 131072890; RV32-V-NEXT: li a1, 1891; RV32-V-NEXT: sw a1, 8(sp)892; RV32-V-NEXT: sw a0, 12(sp)893; RV32-V-NEXT: addi a0, sp, 8894; RV32-V-NEXT: vsetvli a1, zero, e64, m4, ta, ma895; RV32-V-NEXT: vlse64.v v12, (a0), zero896; RV32-V-NEXT: vmulhu.vv v8, v8, v12897; RV32-V-NEXT: li a0, 61898; RV32-V-NEXT: vsrl.vx v8, v8, a0899; RV32-V-NEXT: addi sp, sp, 16900; RV32-V-NEXT: .cfi_def_cfa_offset 0901; RV32-V-NEXT: ret902;903; ZVE64X-LABEL: vdivu_vi_nxv4i64_0:904; ZVE64X: # %bb.0:905; ZVE64X-NEXT: li a0, -7906; ZVE64X-NEXT: vsetvli a1, zero, e64, m4, ta, ma907; ZVE64X-NEXT: vdivu.vx v8, v8, a0908; ZVE64X-NEXT: ret909;910; RV64-V-LABEL: vdivu_vi_nxv4i64_0:911; RV64-V: # %bb.0:912; RV64-V-NEXT: li a0, 1913; RV64-V-NEXT: slli a0, a0, 61914; RV64-V-NEXT: addi a0, a0, 1915; RV64-V-NEXT: vsetvli a1, zero, e64, m4, ta, ma916; RV64-V-NEXT: vmulhu.vx v8, v8, a0917; RV64-V-NEXT: li a0, 61918; RV64-V-NEXT: vsrl.vx v8, v8, a0919; RV64-V-NEXT: ret920 %vc = udiv <vscale x 4 x i64> %va, splat (i64 -7)921 ret <vscale x 4 x i64> %vc922}923 924define <vscale x 4 x i64> @vdivu_vi_nxv4i64_1(<vscale x 4 x i64> %va) {925; CHECK-LABEL: vdivu_vi_nxv4i64_1:926; CHECK: # %bb.0:927; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma928; CHECK-NEXT: vsrl.vi v8, v8, 1929; CHECK-NEXT: ret930 %vc = udiv <vscale x 4 x i64> %va, splat (i64 2)931 ret <vscale x 4 x i64> %vc932}933 934; fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) if c is power of 2935define <vscale x 4 x i64> @vdivu_vi_nxv4i64_2(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) {936; CHECK-LABEL: vdivu_vi_nxv4i64_2:937; CHECK: # %bb.0:938; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma939; CHECK-NEXT: vadd.vi v12, v12, 4940; CHECK-NEXT: vsrl.vv v8, v8, v12941; CHECK-NEXT: ret942 %vc = shl <vscale x 4 x i64> splat (i64 16), %vb943 %vd = udiv <vscale x 4 x i64> %va, %vc944 ret <vscale x 4 x i64> %vd945}946 947define <vscale x 8 x i64> @vdivu_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {948; CHECK-LABEL: vdivu_vv_nxv8i64:949; CHECK: # %bb.0:950; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma951; CHECK-NEXT: vdivu.vv v8, v8, v16952; CHECK-NEXT: ret953 %vc = udiv <vscale x 8 x i64> %va, %vb954 ret <vscale x 8 x i64> %vc955}956 957define <vscale x 8 x i64> @vdivu_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {958; RV32-LABEL: vdivu_vx_nxv8i64:959; RV32: # %bb.0:960; RV32-NEXT: addi sp, sp, -16961; RV32-NEXT: .cfi_def_cfa_offset 16962; RV32-NEXT: sw a0, 8(sp)963; RV32-NEXT: sw a1, 12(sp)964; RV32-NEXT: addi a0, sp, 8965; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma966; RV32-NEXT: vlse64.v v16, (a0), zero967; RV32-NEXT: vdivu.vv v8, v8, v16968; RV32-NEXT: addi sp, sp, 16969; RV32-NEXT: .cfi_def_cfa_offset 0970; RV32-NEXT: ret971;972; RV64-LABEL: vdivu_vx_nxv8i64:973; RV64: # %bb.0:974; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma975; RV64-NEXT: vdivu.vx v8, v8, a0976; RV64-NEXT: ret977 %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0978 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer979 %vc = udiv <vscale x 8 x i64> %va, %splat980 ret <vscale x 8 x i64> %vc981}982 983define <vscale x 8 x i64> @vdivu_vi_nxv8i64_0(<vscale x 8 x i64> %va) {984; RV32-V-LABEL: vdivu_vi_nxv8i64_0:985; RV32-V: # %bb.0:986; RV32-V-NEXT: addi sp, sp, -16987; RV32-V-NEXT: .cfi_def_cfa_offset 16988; RV32-V-NEXT: lui a0, 131072989; RV32-V-NEXT: li a1, 1990; RV32-V-NEXT: sw a1, 8(sp)991; RV32-V-NEXT: sw a0, 12(sp)992; RV32-V-NEXT: addi a0, sp, 8993; RV32-V-NEXT: vsetvli a1, zero, e64, m8, ta, ma994; RV32-V-NEXT: vlse64.v v16, (a0), zero995; RV32-V-NEXT: vmulhu.vv v8, v8, v16996; RV32-V-NEXT: li a0, 61997; RV32-V-NEXT: vsrl.vx v8, v8, a0998; RV32-V-NEXT: addi sp, sp, 16999; RV32-V-NEXT: .cfi_def_cfa_offset 01000; RV32-V-NEXT: ret1001;1002; ZVE64X-LABEL: vdivu_vi_nxv8i64_0:1003; ZVE64X: # %bb.0:1004; ZVE64X-NEXT: li a0, -71005; ZVE64X-NEXT: vsetvli a1, zero, e64, m8, ta, ma1006; ZVE64X-NEXT: vdivu.vx v8, v8, a01007; ZVE64X-NEXT: ret1008;1009; RV64-V-LABEL: vdivu_vi_nxv8i64_0:1010; RV64-V: # %bb.0:1011; RV64-V-NEXT: li a0, 11012; RV64-V-NEXT: slli a0, a0, 611013; RV64-V-NEXT: addi a0, a0, 11014; RV64-V-NEXT: vsetvli a1, zero, e64, m8, ta, ma1015; RV64-V-NEXT: vmulhu.vx v8, v8, a01016; RV64-V-NEXT: li a0, 611017; RV64-V-NEXT: vsrl.vx v8, v8, a01018; RV64-V-NEXT: ret1019 %vc = udiv <vscale x 8 x i64> %va, splat (i64 -7)1020 ret <vscale x 8 x i64> %vc1021}1022 1023define <vscale x 8 x i64> @vdivu_vi_nxv8i64_1(<vscale x 8 x i64> %va) {1024; CHECK-LABEL: vdivu_vi_nxv8i64_1:1025; CHECK: # %bb.0:1026; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma1027; CHECK-NEXT: vsrl.vi v8, v8, 11028; CHECK-NEXT: ret1029 %vc = udiv <vscale x 8 x i64> %va, splat (i64 2)1030 ret <vscale x 8 x i64> %vc1031}1032 1033; fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) if c is power of 21034define <vscale x 8 x i64> @vdivu_vi_nxv8i64_2(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {1035; CHECK-LABEL: vdivu_vi_nxv8i64_2:1036; CHECK: # %bb.0:1037; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma1038; CHECK-NEXT: vadd.vi v16, v16, 41039; CHECK-NEXT: vsrl.vv v8, v8, v161040; CHECK-NEXT: ret1041 %vc = shl <vscale x 8 x i64> splat (i64 16), %vb1042 %vd = udiv <vscale x 8 x i64> %va, %vc1043 ret <vscale x 8 x i64> %vd1044}1045 1046define <vscale x 8 x i32> @vdivu_vv_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {1047; CHECK-LABEL: vdivu_vv_mask_nxv8i32:1048; CHECK: # %bb.0:1049; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma1050; CHECK-NEXT: vmv.v.i v16, 11051; CHECK-NEXT: vmerge.vvm v12, v16, v12, v01052; CHECK-NEXT: vdivu.vv v8, v8, v121053; CHECK-NEXT: ret1054 %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> splat (i32 1)1055 %vc = udiv <vscale x 8 x i32> %va, %vs1056 ret <vscale x 8 x i32> %vc1057}1058 1059define <vscale x 8 x i32> @vdivu_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {1060; CHECK-LABEL: vdivu_vx_mask_nxv8i32:1061; CHECK: # %bb.0:1062; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma1063; CHECK-NEXT: vmv.v.i v12, 11064; CHECK-NEXT: vmerge.vxm v12, v12, a0, v01065; CHECK-NEXT: vdivu.vv v8, v8, v121066; CHECK-NEXT: ret1067 %head2 = insertelement <vscale x 8 x i32> poison, i32 %b, i32 01068 %splat = shufflevector <vscale x 8 x i32> %head2, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer1069 %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> splat (i32 1)1070 %vc = udiv <vscale x 8 x i32> %va, %vs1071 ret <vscale x 8 x i32> %vc1072}1073 1074define <vscale x 8 x i32> @vdivu_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {1075; CHECK-LABEL: vdivu_vi_mask_nxv8i32:1076; CHECK: # %bb.0:1077; CHECK-NEXT: lui a0, 1497971078; CHECK-NEXT: addi a0, a0, -17551079; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu1080; CHECK-NEXT: vmulhu.vx v12, v8, a01081; CHECK-NEXT: vsub.vv v16, v8, v121082; CHECK-NEXT: vsrl.vi v16, v16, 11083; CHECK-NEXT: vadd.vv v12, v16, v121084; CHECK-NEXT: vsrl.vi v8, v12, 2, v0.t1085; CHECK-NEXT: ret1086 %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> splat (i32 7), <vscale x 8 x i32> splat (i32 1)1087 %vc = udiv <vscale x 8 x i32> %va, %vs1088 ret <vscale x 8 x i32> %vc1089}1090