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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs \3; RUN: -riscv-v-vector-bits-min=0 < %s | FileCheck %s --check-prefix=RV324; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs \5; RUN: -riscv-v-vector-bits-min=0 < %s | FileCheck %s --check-prefix=RV646 7; This test would lead one of the DAGCombiner's visitVSELECT optimizations to8; call getSetCCResultType, from which we'd return an invalid MVT (<3 x i1>)9; upon seeing that the V extension is enabled. The invalid MVT has a null10; Type*, which then segfaulted when accessed (as an EVT).11define void @vec3_setcc_crash(ptr %in, ptr %out) {12; RV32-LABEL: vec3_setcc_crash:13; RV32: # %bb.0:14; RV32-NEXT: lw a0, 0(a0)15; RV32-NEXT: srli a2, a0, 1616; RV32-NEXT: srli a3, a0, 817; RV32-NEXT: slli a4, a0, 1618; RV32-NEXT: slli a5, a0, 2419; RV32-NEXT: slli a6, a0, 820; RV32-NEXT: srai a4, a4, 2421; RV32-NEXT: srai a5, a5, 2422; RV32-NEXT: srai a6, a6, 2423; RV32-NEXT: sgtz a6, a624; RV32-NEXT: sgtz a5, a525; RV32-NEXT: sgtz a4, a426; RV32-NEXT: neg a4, a427; RV32-NEXT: neg a5, a528; RV32-NEXT: neg a6, a629; RV32-NEXT: and a3, a4, a330; RV32-NEXT: and a0, a5, a031; RV32-NEXT: and a2, a6, a232; RV32-NEXT: slli a3, a3, 833; RV32-NEXT: zext.b a0, a034; RV32-NEXT: or a0, a0, a335; RV32-NEXT: sh a0, 0(a1)36; RV32-NEXT: sb a2, 2(a1)37; RV32-NEXT: ret38;39; RV64-LABEL: vec3_setcc_crash:40; RV64: # %bb.0:41; RV64-NEXT: lw a0, 0(a0)42; RV64-NEXT: srli a2, a0, 1643; RV64-NEXT: srli a3, a0, 844; RV64-NEXT: slli a4, a0, 4845; RV64-NEXT: slli a5, a0, 5646; RV64-NEXT: slli a6, a0, 4047; RV64-NEXT: srai a4, a4, 5648; RV64-NEXT: srai a5, a5, 5649; RV64-NEXT: srai a6, a6, 5650; RV64-NEXT: sgtz a6, a651; RV64-NEXT: sgtz a5, a552; RV64-NEXT: sgtz a4, a453; RV64-NEXT: neg a4, a454; RV64-NEXT: neg a5, a555; RV64-NEXT: neg a6, a656; RV64-NEXT: and a3, a4, a357; RV64-NEXT: and a0, a5, a058; RV64-NEXT: and a2, a6, a259; RV64-NEXT: slli a3, a3, 860; RV64-NEXT: zext.b a0, a061; RV64-NEXT: or a0, a0, a362; RV64-NEXT: sh a0, 0(a1)63; RV64-NEXT: sb a2, 2(a1)64; RV64-NEXT: ret65 %a = load <3 x i8>, ptr %in66 %cmp = icmp sgt <3 x i8> %a, zeroinitializer67 %c = select <3 x i1> %cmp, <3 x i8> %a, <3 x i8> zeroinitializer68 store <3 x i8> %c, ptr %out69 ret void70}71