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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+m,+zvfh | FileCheck %s --check-prefixes=CHECK,V,RV323; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+m,+zvfh | FileCheck %s --check-prefixes=CHECK,V,RV644; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+m,+zvfh,+experimental-xrivosvizip | FileCheck %s --check-prefixes=CHECK,ZIP5 6; Integers7 8define {<16 x i1>, <16 x i1>} @vector_deinterleave_v16i1_v32i1(<32 x i1> %vec) {9; CHECK-LABEL: vector_deinterleave_v16i1_v32i1:10; CHECK: # %bb.0:11; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma12; CHECK-NEXT: vmv.v.i v8, 013; CHECK-NEXT: vmerge.vim v9, v8, 1, v014; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma15; CHECK-NEXT: vslidedown.vi v0, v0, 216; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma17; CHECK-NEXT: vnsrl.wi v10, v9, 018; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma19; CHECK-NEXT: vmerge.vim v8, v8, 1, v020; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma21; CHECK-NEXT: vnsrl.wi v9, v9, 822; CHECK-NEXT: vnsrl.wi v11, v8, 023; CHECK-NEXT: vnsrl.wi v8, v8, 824; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma25; CHECK-NEXT: vslideup.vi v10, v11, 826; CHECK-NEXT: vslideup.vi v9, v8, 827; CHECK-NEXT: vmsne.vi v0, v10, 028; CHECK-NEXT: vmsne.vi v8, v9, 029; CHECK-NEXT: ret30%retval = call {<16 x i1>, <16 x i1>} @llvm.vector.deinterleave2.v32i1(<32 x i1> %vec)31ret {<16 x i1>, <16 x i1>} %retval32}33 34define {<16 x i8>, <16 x i8>} @vector_deinterleave_v16i8_v32i8(<32 x i8> %vec) {35; CHECK-LABEL: vector_deinterleave_v16i8_v32i8:36; CHECK: # %bb.0:37; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma38; CHECK-NEXT: vnsrl.wi v10, v8, 039; CHECK-NEXT: vnsrl.wi v11, v8, 840; CHECK-NEXT: vmv.v.v v8, v1041; CHECK-NEXT: vmv.v.v v9, v1142; CHECK-NEXT: ret43%retval = call {<16 x i8>, <16 x i8>} @llvm.vector.deinterleave2.v32i8(<32 x i8> %vec)44ret {<16 x i8>, <16 x i8>} %retval45}46 47define {<8 x i16>, <8 x i16>} @vector_deinterleave_v8i16_v16i16(<16 x i16> %vec) {48; CHECK-LABEL: vector_deinterleave_v8i16_v16i16:49; CHECK: # %bb.0:50; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma51; CHECK-NEXT: vnsrl.wi v10, v8, 052; CHECK-NEXT: vnsrl.wi v11, v8, 1653; CHECK-NEXT: vmv.v.v v8, v1054; CHECK-NEXT: vmv.v.v v9, v1155; CHECK-NEXT: ret56%retval = call {<8 x i16>, <8 x i16>} @llvm.vector.deinterleave2.v16i16(<16 x i16> %vec)57ret {<8 x i16>, <8 x i16>} %retval58}59 60define {<4 x i32>, <4 x i32>} @vector_deinterleave_v4i32_vv8i32(<8 x i32> %vec) {61; CHECK-LABEL: vector_deinterleave_v4i32_vv8i32:62; CHECK: # %bb.0:63; CHECK-NEXT: li a0, 3264; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma65; CHECK-NEXT: vnsrl.wx v10, v8, a066; CHECK-NEXT: vnsrl.wi v11, v8, 067; CHECK-NEXT: vmv.v.v v8, v1168; CHECK-NEXT: vmv.v.v v9, v1069; CHECK-NEXT: ret70%retval = call {<4 x i32>, <4 x i32>} @llvm.vector.deinterleave2.v8i32(<8 x i32> %vec)71ret {<4 x i32>, <4 x i32>} %retval72}73 74define {<2 x i64>, <2 x i64>} @vector_deinterleave_v2i64_v4i64(<4 x i64> %vec) {75; V-LABEL: vector_deinterleave_v2i64_v4i64:76; V: # %bb.0:77; V-NEXT: vsetivli zero, 2, e64, m2, ta, ma78; V-NEXT: vslidedown.vi v10, v8, 279; V-NEXT: vsetivli zero, 2, e64, m1, ta, mu80; V-NEXT: vmv.v.i v0, 181; V-NEXT: vmv1r.v v9, v1082; V-NEXT: vslidedown.vi v9, v8, 1, v0.t83; V-NEXT: vslideup.vi v8, v10, 184; V-NEXT: ret85;86; ZIP-LABEL: vector_deinterleave_v2i64_v4i64:87; ZIP: # %bb.0:88; ZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma89; ZIP-NEXT: ri.vunzip2a.vv v10, v8, v990; ZIP-NEXT: ri.vunzip2b.vv v11, v8, v991; ZIP-NEXT: vmv.v.v v8, v1092; ZIP-NEXT: vmv.v.v v9, v1193; ZIP-NEXT: ret94%retval = call {<2 x i64>, <2 x i64>} @llvm.vector.deinterleave2.v4i64(<4 x i64> %vec)95ret {<2 x i64>, <2 x i64>} %retval96}97 98define {<4 x i64>, <4 x i64>} @vector_deinterleave_v4i64_v8i64(<8 x i64> %vec) {99; V-LABEL: vector_deinterleave_v4i64_v8i64:100; V: # %bb.0:101; V-NEXT: vsetivli zero, 1, e8, mf8, ta, ma102; V-NEXT: vmv.v.i v0, 8103; V-NEXT: vsetivli zero, 4, e64, m4, ta, ma104; V-NEXT: vslidedown.vi v16, v8, 4105; V-NEXT: vsetivli zero, 1, e8, mf8, ta, ma106; V-NEXT: vmv.v.i v10, 2107; V-NEXT: vmv2r.v v12, v8108; V-NEXT: vmv.v.i v11, 12109; V-NEXT: vsetivli zero, 4, e64, m2, ta, mu110; V-NEXT: vslideup.vi v14, v16, 2111; V-NEXT: vslideup.vi v14, v16, 1, v0.t112; V-NEXT: vmv1r.v v0, v10113; V-NEXT: vslidedown.vi v12, v8, 1, v0.t114; V-NEXT: vmv1r.v v0, v11115; V-NEXT: vmerge.vvm v12, v12, v14, v0116; V-NEXT: vslidedown.vi v14, v8, 1117; V-NEXT: vmv1r.v v0, v10118; V-NEXT: vslidedown.vi v14, v8, 2, v0.t119; V-NEXT: vsetivli zero, 1, e8, mf8, ta, ma120; V-NEXT: vmv.v.i v0, 4121; V-NEXT: vmv2r.v v8, v16122; V-NEXT: vsetivli zero, 4, e64, m2, ta, mu123; V-NEXT: vslideup.vi v8, v16, 1, v0.t124; V-NEXT: vmv1r.v v0, v11125; V-NEXT: vmerge.vvm v10, v14, v8, v0126; V-NEXT: vmv2r.v v8, v12127; V-NEXT: ret128;129; ZIP-LABEL: vector_deinterleave_v4i64_v8i64:130; ZIP: # %bb.0:131; ZIP-NEXT: vsetivli zero, 4, e64, m2, ta, ma132; ZIP-NEXT: ri.vunzip2a.vv v12, v8, v10133; ZIP-NEXT: ri.vunzip2b.vv v14, v8, v10134; ZIP-NEXT: vmv.v.v v8, v12135; ZIP-NEXT: vmv.v.v v10, v14136; ZIP-NEXT: ret137 %retval = call {<4 x i64>, <4 x i64>} @llvm.vector.deinterleave2.v8i64(<8 x i64> %vec)138 ret {<4 x i64>, <4 x i64>} %retval139}140 141define {<8 x i64>, <8 x i64>} @vector_deinterleave_v8i64_v16i64(<16 x i64> %vec) {142; V-LABEL: vector_deinterleave_v8i64_v16i64:143; V: # %bb.0:144; V-NEXT: vsetivli zero, 8, e16, m1, ta, ma145; V-NEXT: vid.v v16146; V-NEXT: vsetivli zero, 8, e64, m8, ta, ma147; V-NEXT: vslidedown.vi v24, v8, 8148; V-NEXT: li a0, 85149; V-NEXT: vsetivli zero, 8, e16, m1, ta, ma150; V-NEXT: vmv.v.i v0, -16151; V-NEXT: vmv.s.x v12, a0152; V-NEXT: li a0, 170153; V-NEXT: vadd.vv v13, v16, v16154; V-NEXT: vmv.s.x v20, a0155; V-NEXT: vadd.vi v21, v13, -8156; V-NEXT: vsetvli zero, zero, e64, m4, ta, ma157; V-NEXT: vcompress.vm v16, v8, v12158; V-NEXT: vsetvli zero, zero, e16, m1, ta, ma159; V-NEXT: vadd.vi v22, v13, -7160; V-NEXT: vsetvli zero, zero, e64, m4, ta, mu161; V-NEXT: vcompress.vm v12, v8, v20162; V-NEXT: vrgatherei16.vv v16, v24, v21, v0.t163; V-NEXT: vrgatherei16.vv v12, v24, v22, v0.t164; V-NEXT: vmv.v.v v8, v16165; V-NEXT: ret166;167; ZIP-LABEL: vector_deinterleave_v8i64_v16i64:168; ZIP: # %bb.0:169; ZIP-NEXT: vsetivli zero, 8, e64, m4, ta, ma170; ZIP-NEXT: ri.vunzip2a.vv v16, v8, v12171; ZIP-NEXT: ri.vunzip2b.vv v20, v8, v12172; ZIP-NEXT: vmv.v.v v8, v16173; ZIP-NEXT: vmv.v.v v12, v20174; ZIP-NEXT: ret175 %retval = call {<8 x i64>, <8 x i64>} @llvm.vector.deinterleave2.v16i64(<16 x i64> %vec)176 ret {<8 x i64>, <8 x i64>} %retval177}178 179define {<2 x i32>, <2 x i32>, <2 x i32>} @vector_deinterleave3_v2i32_v6i32(<6 x i32> %v) nounwind {180; CHECK-LABEL: vector_deinterleave3_v2i32_v6i32:181; CHECK: # %bb.0:182; CHECK-NEXT: addi sp, sp, -16183; CHECK-NEXT: csrr a0, vlenb184; CHECK-NEXT: slli a0, a0, 1185; CHECK-NEXT: sub sp, sp, a0186; CHECK-NEXT: csrr a0, vlenb187; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma188; CHECK-NEXT: vslidedown.vi v12, v8, 2189; CHECK-NEXT: vsetivli zero, 2, e32, m2, ta, ma190; CHECK-NEXT: vslidedown.vi v10, v8, 4191; CHECK-NEXT: srli a0, a0, 3192; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma193; CHECK-NEXT: vslideup.vx v8, v12, a0194; CHECK-NEXT: addi a0, sp, 16195; CHECK-NEXT: vmv1r.v v9, v10196; CHECK-NEXT: vs2r.v v8, (a0)197; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma198; CHECK-NEXT: vlseg3e32.v v8, (a0)199; CHECK-NEXT: csrr a0, vlenb200; CHECK-NEXT: slli a0, a0, 1201; CHECK-NEXT: add sp, sp, a0202; CHECK-NEXT: addi sp, sp, 16203; CHECK-NEXT: ret204 %res = call {<2 x i32>, <2 x i32>, <2 x i32>} @llvm.vector.deinterleave3.v6i32(<6 x i32> %v)205 ret {<2 x i32>, <2 x i32>, <2 x i32>} %res206}207 208define {<2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>} @vector_deinterleave4_v2i32_v8i32(<8 x i32> %v) nounwind {209; CHECK-LABEL: vector_deinterleave4_v2i32_v8i32:210; CHECK: # %bb.0:211; CHECK-NEXT: addi sp, sp, -16212; CHECK-NEXT: csrr a0, vlenb213; CHECK-NEXT: slli a0, a0, 1214; CHECK-NEXT: sub sp, sp, a0215; CHECK-NEXT: csrr a0, vlenb216; CHECK-NEXT: vsetivli zero, 2, e32, m2, ta, ma217; CHECK-NEXT: vslidedown.vi v10, v8, 6218; CHECK-NEXT: vslidedown.vi v12, v8, 4219; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma220; CHECK-NEXT: vslidedown.vi v9, v8, 2221; CHECK-NEXT: srli a0, a0, 3222; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma223; CHECK-NEXT: vslideup.vx v12, v10, a0224; CHECK-NEXT: vslideup.vx v8, v9, a0225; CHECK-NEXT: addi a0, sp, 16226; CHECK-NEXT: vmv.v.v v9, v12227; CHECK-NEXT: vs2r.v v8, (a0)228; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma229; CHECK-NEXT: vlseg4e32.v v8, (a0)230; CHECK-NEXT: csrr a0, vlenb231; CHECK-NEXT: slli a0, a0, 1232; CHECK-NEXT: add sp, sp, a0233; CHECK-NEXT: addi sp, sp, 16234; CHECK-NEXT: ret235 %res = call {<2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>} @llvm.vector.deinterleave4.v8i32(<8 x i32> %v)236 ret {<2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>} %res237}238 239define {<2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>} @vector_deinterleave5_v2i16_v10i16(<10 x i16> %v) nounwind {240; CHECK-LABEL: vector_deinterleave5_v2i16_v10i16:241; CHECK: # %bb.0:242; CHECK-NEXT: addi sp, sp, -16243; CHECK-NEXT: csrr a0, vlenb244; CHECK-NEXT: slli a0, a0, 1245; CHECK-NEXT: sub sp, sp, a0246; CHECK-NEXT: csrr a0, vlenb247; CHECK-NEXT: vsetivli zero, 2, e16, m1, ta, ma248; CHECK-NEXT: vslidedown.vi v12, v8, 6249; CHECK-NEXT: vslidedown.vi v13, v8, 4250; CHECK-NEXT: vslidedown.vi v14, v8, 2251; CHECK-NEXT: vsetivli zero, 2, e16, m2, ta, ma252; CHECK-NEXT: vslidedown.vi v10, v8, 8253; CHECK-NEXT: srli a1, a0, 2254; CHECK-NEXT: srli a0, a0, 3255; CHECK-NEXT: vsetvli a2, zero, e16, mf2, ta, ma256; CHECK-NEXT: vslideup.vx v13, v12, a0257; CHECK-NEXT: vslideup.vx v8, v14, a0258; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma259; CHECK-NEXT: vslideup.vx v8, v13, a1260; CHECK-NEXT: addi a0, sp, 16261; CHECK-NEXT: vmv1r.v v9, v10262; CHECK-NEXT: vs2r.v v8, (a0)263; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma264; CHECK-NEXT: vlseg5e16.v v8, (a0)265; CHECK-NEXT: csrr a0, vlenb266; CHECK-NEXT: slli a0, a0, 1267; CHECK-NEXT: add sp, sp, a0268; CHECK-NEXT: addi sp, sp, 16269; CHECK-NEXT: ret270 %res = call {<2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>} @llvm.vector.deinterleave5.v10i16(<10 x i16> %v)271 ret {<2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>} %res272}273 274define {<2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>} @vector_deinterleave6_v2i16_v12i16(<12 x i16> %v) nounwind {275; CHECK-LABEL: vector_deinterleave6_v2i16_v12i16:276; CHECK: # %bb.0:277; CHECK-NEXT: addi sp, sp, -16278; CHECK-NEXT: csrr a0, vlenb279; CHECK-NEXT: slli a0, a0, 1280; CHECK-NEXT: sub sp, sp, a0281; CHECK-NEXT: csrr a0, vlenb282; CHECK-NEXT: vsetivli zero, 2, e16, m1, ta, ma283; CHECK-NEXT: vslidedown.vi v14, v8, 6284; CHECK-NEXT: vslidedown.vi v15, v8, 4285; CHECK-NEXT: vslidedown.vi v16, v8, 2286; CHECK-NEXT: vsetivli zero, 2, e16, m2, ta, ma287; CHECK-NEXT: vslidedown.vi v10, v8, 10288; CHECK-NEXT: vslidedown.vi v12, v8, 8289; CHECK-NEXT: srli a1, a0, 2290; CHECK-NEXT: srli a0, a0, 3291; CHECK-NEXT: vsetvli a2, zero, e16, mf2, ta, ma292; CHECK-NEXT: vslideup.vx v15, v14, a0293; CHECK-NEXT: vslideup.vx v8, v16, a0294; CHECK-NEXT: vslideup.vx v12, v10, a0295; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma296; CHECK-NEXT: vslideup.vx v8, v15, a1297; CHECK-NEXT: addi a0, sp, 16298; CHECK-NEXT: vmv1r.v v9, v12299; CHECK-NEXT: vs2r.v v8, (a0)300; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma301; CHECK-NEXT: vlseg6e16.v v8, (a0)302; CHECK-NEXT: csrr a0, vlenb303; CHECK-NEXT: slli a0, a0, 1304; CHECK-NEXT: add sp, sp, a0305; CHECK-NEXT: addi sp, sp, 16306; CHECK-NEXT: ret307 %res = call {<2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>} @llvm.vector.deinterleave6.v12i16(<12 x i16> %v)308 ret {<2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>, <2 x i16>} %res309}310 311define {<2 x i8>, <2 x i8>, <2 x i8>, <2 x i8>, <2 x i8>, <2 x i8>, <2 x i8>} @vector_deinterleave7_v14i8_v2i8(<14 x i8> %v) nounwind {312; CHECK-LABEL: vector_deinterleave7_v14i8_v2i8:313; CHECK: # %bb.0:314; CHECK-NEXT: addi sp, sp, -16315; CHECK-NEXT: csrr a0, vlenb316; CHECK-NEXT: sub sp, sp, a0317; CHECK-NEXT: csrr a0, vlenb318; CHECK-NEXT: vsetivli zero, 2, e8, m1, ta, ma319; CHECK-NEXT: vslidedown.vi v9, v8, 10320; CHECK-NEXT: vslidedown.vi v10, v8, 8321; CHECK-NEXT: vslidedown.vi v11, v8, 12322; CHECK-NEXT: vslidedown.vi v12, v8, 2323; CHECK-NEXT: vslidedown.vi v13, v8, 4324; CHECK-NEXT: vslidedown.vi v14, v8, 6325; CHECK-NEXT: srli a1, a0, 2326; CHECK-NEXT: srli a2, a0, 3327; CHECK-NEXT: srli a0, a0, 1328; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, ma329; CHECK-NEXT: vslideup.vx v10, v9, a2330; CHECK-NEXT: add a3, a1, a2331; CHECK-NEXT: vslideup.vx v8, v12, a2332; CHECK-NEXT: vsetvli zero, a3, e8, mf2, tu, ma333; CHECK-NEXT: vslideup.vx v10, v11, a1334; CHECK-NEXT: vslideup.vx v8, v13, a1335; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma336; CHECK-NEXT: vslideup.vx v8, v14, a3337; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma338; CHECK-NEXT: vslideup.vx v8, v10, a0339; CHECK-NEXT: addi a0, sp, 16340; CHECK-NEXT: vs1r.v v8, (a0)341; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma342; CHECK-NEXT: vlseg7e8.v v8, (a0)343; CHECK-NEXT: csrr a0, vlenb344; CHECK-NEXT: add sp, sp, a0345; CHECK-NEXT: addi sp, sp, 16346; CHECK-NEXT: ret347 %res = call {<2 x i8>, <2 x i8>, <2 x i8>, <2 x i8>, <2 x i8>, <2 x i8>, <2 x i8>} @llvm.vector.deinterleave7.v14i8(<14 x i8> %v)348 ret {<2 x i8>, <2 x i8>, <2 x i8>, <2 x i8>, <2 x i8>, <2 x i8>, <2 x i8>} %res349}350 351define {<2 x i8>, <2 x i8>, <2 x i8>, <2 x i8>, <2 x i8>, <2 x i8>, <2 x i8>, <2 x i8>} @vector_deinterleave8_v16i8_v2i8(<16 x i8> %v) nounwind {352; CHECK-LABEL: vector_deinterleave8_v16i8_v2i8:353; CHECK: # %bb.0:354; CHECK-NEXT: addi sp, sp, -16355; CHECK-NEXT: csrr a0, vlenb356; CHECK-NEXT: sub sp, sp, a0357; CHECK-NEXT: csrr a0, vlenb358; CHECK-NEXT: vsetivli zero, 2, e8, m1, ta, ma359; CHECK-NEXT: vslidedown.vi v9, v8, 10360; CHECK-NEXT: vslidedown.vi v10, v8, 8361; CHECK-NEXT: vslidedown.vi v11, v8, 12362; CHECK-NEXT: vslidedown.vi v12, v8, 14363; CHECK-NEXT: vslidedown.vi v13, v8, 2364; CHECK-NEXT: vslidedown.vi v14, v8, 4365; CHECK-NEXT: vslidedown.vi v15, v8, 6366; CHECK-NEXT: srli a1, a0, 2367; CHECK-NEXT: srli a2, a0, 3368; CHECK-NEXT: srli a0, a0, 1369; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, ma370; CHECK-NEXT: vslideup.vx v10, v9, a2371; CHECK-NEXT: add a3, a1, a2372; CHECK-NEXT: vslideup.vx v8, v13, a2373; CHECK-NEXT: vsetvli zero, a3, e8, mf2, tu, ma374; CHECK-NEXT: vslideup.vx v10, v11, a1375; CHECK-NEXT: vslideup.vx v8, v14, a1376; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma377; CHECK-NEXT: vslideup.vx v10, v12, a3378; CHECK-NEXT: vslideup.vx v8, v15, a3379; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma380; CHECK-NEXT: vslideup.vx v8, v10, a0381; CHECK-NEXT: addi a0, sp, 16382; CHECK-NEXT: vs1r.v v8, (a0)383; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma384; CHECK-NEXT: vlseg8e8.v v8, (a0)385; CHECK-NEXT: csrr a0, vlenb386; CHECK-NEXT: add sp, sp, a0387; CHECK-NEXT: addi sp, sp, 16388; CHECK-NEXT: ret389 %res = call {<2 x i8>, <2 x i8>, <2 x i8>, <2 x i8>, <2 x i8>, <2 x i8>, <2 x i8>, <2 x i8>} @llvm.vector.deinterleave8.v16i8(<16 x i8> %v)390 ret {<2 x i8>, <2 x i8>, <2 x i8>, <2 x i8>, <2 x i8>, <2 x i8>, <2 x i8>, <2 x i8>} %res391}392 393; Floats394 395define {<2 x half>, <2 x half>} @vector_deinterleave_v2f16_v4f16(<4 x half> %vec) {396; CHECK-LABEL: vector_deinterleave_v2f16_v4f16:397; CHECK: # %bb.0:398; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma399; CHECK-NEXT: vnsrl.wi v10, v8, 0400; CHECK-NEXT: vnsrl.wi v9, v8, 16401; CHECK-NEXT: vmv1r.v v8, v10402; CHECK-NEXT: ret403%retval = call {<2 x half>, <2 x half>} @llvm.vector.deinterleave2.v4f16(<4 x half> %vec)404ret {<2 x half>, <2 x half>} %retval405}406 407define {<4 x half>, <4 x half>} @vector_deinterleave_v4f16_v8f16(<8 x half> %vec) {408; CHECK-LABEL: vector_deinterleave_v4f16_v8f16:409; CHECK: # %bb.0:410; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma411; CHECK-NEXT: vnsrl.wi v10, v8, 0412; CHECK-NEXT: vnsrl.wi v9, v8, 16413; CHECK-NEXT: vmv1r.v v8, v10414; CHECK-NEXT: ret415%retval = call {<4 x half>, <4 x half>} @llvm.vector.deinterleave2.v8f16(<8 x half> %vec)416ret {<4 x half>, <4 x half>} %retval417}418 419define {<2 x float>, <2 x float>} @vector_deinterleave_v2f32_v4f32(<4 x float> %vec) {420; CHECK-LABEL: vector_deinterleave_v2f32_v4f32:421; CHECK: # %bb.0:422; CHECK-NEXT: li a0, 32423; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma424; CHECK-NEXT: vnsrl.wx v9, v8, a0425; CHECK-NEXT: vnsrl.wi v8, v8, 0426; CHECK-NEXT: ret427%retval = call {<2 x float>, <2 x float>} @llvm.vector.deinterleave2.v4f32(<4 x float> %vec)428ret {<2 x float>, <2 x float>} %retval429}430 431define {<8 x half>, <8 x half>} @vector_deinterleave_v8f16_v16f16(<16 x half> %vec) {432; CHECK-LABEL: vector_deinterleave_v8f16_v16f16:433; CHECK: # %bb.0:434; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma435; CHECK-NEXT: vnsrl.wi v10, v8, 0436; CHECK-NEXT: vnsrl.wi v11, v8, 16437; CHECK-NEXT: vmv.v.v v8, v10438; CHECK-NEXT: vmv.v.v v9, v11439; CHECK-NEXT: ret440%retval = call {<8 x half>, <8 x half>} @llvm.vector.deinterleave2.v16f16(<16 x half> %vec)441ret {<8 x half>, <8 x half>} %retval442}443 444define {<4 x float>, <4 x float>} @vector_deinterleave_v4f32_v8f32(<8 x float> %vec) {445; CHECK-LABEL: vector_deinterleave_v4f32_v8f32:446; CHECK: # %bb.0:447; CHECK-NEXT: li a0, 32448; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma449; CHECK-NEXT: vnsrl.wx v10, v8, a0450; CHECK-NEXT: vnsrl.wi v11, v8, 0451; CHECK-NEXT: vmv.v.v v8, v11452; CHECK-NEXT: vmv.v.v v9, v10453; CHECK-NEXT: ret454%retval = call {<4 x float>, <4 x float>} @llvm.vector.deinterleave2.v8f32(<8 x float> %vec)455ret {<4 x float>, <4 x float>} %retval456}457 458define {<2 x double>, <2 x double>} @vector_deinterleave_v2f64_v4f64(<4 x double> %vec) {459; V-LABEL: vector_deinterleave_v2f64_v4f64:460; V: # %bb.0:461; V-NEXT: vsetivli zero, 2, e64, m2, ta, ma462; V-NEXT: vslidedown.vi v10, v8, 2463; V-NEXT: vsetivli zero, 2, e64, m1, ta, mu464; V-NEXT: vmv.v.i v0, 1465; V-NEXT: vmv1r.v v9, v10466; V-NEXT: vslidedown.vi v9, v8, 1, v0.t467; V-NEXT: vslideup.vi v8, v10, 1468; V-NEXT: ret469;470; ZIP-LABEL: vector_deinterleave_v2f64_v4f64:471; ZIP: # %bb.0:472; ZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma473; ZIP-NEXT: ri.vunzip2a.vv v10, v8, v9474; ZIP-NEXT: ri.vunzip2b.vv v12, v8, v9475; ZIP-NEXT: vmv.v.v v8, v10476; ZIP-NEXT: vmv.v.v v9, v12477; ZIP-NEXT: ret478%retval = call {<2 x double>, <2 x double>} @llvm.vector.deinterleave2.v4f64(<4 x double> %vec)479ret {<2 x double>, <2 x double>} %retval480}481 482define {<4 x double>, <4 x double>} @vector_deinterleave_v4f64_v8f64(<8 x double> %vec) {483; V-LABEL: vector_deinterleave_v4f64_v8f64:484; V: # %bb.0:485; V-NEXT: vsetivli zero, 1, e8, mf8, ta, ma486; V-NEXT: vmv.v.i v0, 8487; V-NEXT: vsetivli zero, 4, e64, m4, ta, ma488; V-NEXT: vslidedown.vi v16, v8, 4489; V-NEXT: vsetivli zero, 1, e8, mf8, ta, ma490; V-NEXT: vmv.v.i v10, 2491; V-NEXT: vmv2r.v v12, v8492; V-NEXT: vmv.v.i v11, 12493; V-NEXT: vsetivli zero, 4, e64, m2, ta, mu494; V-NEXT: vslideup.vi v14, v16, 2495; V-NEXT: vslideup.vi v14, v16, 1, v0.t496; V-NEXT: vmv1r.v v0, v10497; V-NEXT: vslidedown.vi v12, v8, 1, v0.t498; V-NEXT: vmv1r.v v0, v11499; V-NEXT: vmerge.vvm v12, v12, v14, v0500; V-NEXT: vslidedown.vi v14, v8, 1501; V-NEXT: vmv1r.v v0, v10502; V-NEXT: vslidedown.vi v14, v8, 2, v0.t503; V-NEXT: vsetivli zero, 1, e8, mf8, ta, ma504; V-NEXT: vmv.v.i v0, 4505; V-NEXT: vmv2r.v v8, v16506; V-NEXT: vsetivli zero, 4, e64, m2, ta, mu507; V-NEXT: vslideup.vi v8, v16, 1, v0.t508; V-NEXT: vmv1r.v v0, v11509; V-NEXT: vmerge.vvm v10, v14, v8, v0510; V-NEXT: vmv2r.v v8, v12511; V-NEXT: ret512;513; ZIP-LABEL: vector_deinterleave_v4f64_v8f64:514; ZIP: # %bb.0:515; ZIP-NEXT: vsetivli zero, 4, e64, m2, ta, ma516; ZIP-NEXT: ri.vunzip2a.vv v12, v8, v10517; ZIP-NEXT: ri.vunzip2b.vv v16, v8, v10518; ZIP-NEXT: vmv.v.v v8, v12519; ZIP-NEXT: vmv.v.v v10, v16520; ZIP-NEXT: ret521%retval = call {<4 x double>, <4 x double>} @llvm.vector.deinterleave2.v8f64(<8 x double> %vec)522ret {<4 x double>, <4 x double>} %retval523}524 525define {<2 x float>, <2 x float>, <2 x float>} @vector_deinterleave3_v6f32_v2f32(<6 x float> %v) {526; CHECK-LABEL: vector_deinterleave3_v6f32_v2f32:527; CHECK: # %bb.0:528; CHECK-NEXT: addi sp, sp, -16529; CHECK-NEXT: .cfi_def_cfa_offset 16530; CHECK-NEXT: csrr a0, vlenb531; CHECK-NEXT: slli a0, a0, 1532; CHECK-NEXT: sub sp, sp, a0533; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 2 * vlenb534; CHECK-NEXT: csrr a0, vlenb535; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma536; CHECK-NEXT: vslidedown.vi v12, v8, 2537; CHECK-NEXT: vsetivli zero, 2, e32, m2, ta, ma538; CHECK-NEXT: vslidedown.vi v10, v8, 4539; CHECK-NEXT: srli a0, a0, 3540; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma541; CHECK-NEXT: vslideup.vx v8, v12, a0542; CHECK-NEXT: addi a0, sp, 16543; CHECK-NEXT: vmv1r.v v9, v10544; CHECK-NEXT: vs2r.v v8, (a0)545; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma546; CHECK-NEXT: vlseg3e32.v v8, (a0)547; CHECK-NEXT: csrr a0, vlenb548; CHECK-NEXT: slli a0, a0, 1549; CHECK-NEXT: add sp, sp, a0550; CHECK-NEXT: .cfi_def_cfa sp, 16551; CHECK-NEXT: addi sp, sp, 16552; CHECK-NEXT: .cfi_def_cfa_offset 0553; CHECK-NEXT: ret554 %res = call {<2 x float>, <2 x float>, <2 x float>} @llvm.vector.deinterleave3.v6f32(<6 x float> %v)555 ret {<2 x float>, <2 x float>, <2 x float>} %res556}557 558define {<2 x float>, <2 x float>, <2 x float>, <2 x float>} @vector_deinterleave4_v8f32_v2f32(<8 x float> %v) {559; CHECK-LABEL: vector_deinterleave4_v8f32_v2f32:560; CHECK: # %bb.0:561; CHECK-NEXT: addi sp, sp, -16562; CHECK-NEXT: .cfi_def_cfa_offset 16563; CHECK-NEXT: csrr a0, vlenb564; CHECK-NEXT: slli a0, a0, 1565; CHECK-NEXT: sub sp, sp, a0566; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 2 * vlenb567; CHECK-NEXT: csrr a0, vlenb568; CHECK-NEXT: vsetivli zero, 2, e32, m2, ta, ma569; CHECK-NEXT: vslidedown.vi v10, v8, 6570; CHECK-NEXT: vslidedown.vi v12, v8, 4571; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma572; CHECK-NEXT: vslidedown.vi v9, v8, 2573; CHECK-NEXT: srli a0, a0, 3574; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma575; CHECK-NEXT: vslideup.vx v12, v10, a0576; CHECK-NEXT: vslideup.vx v8, v9, a0577; CHECK-NEXT: addi a0, sp, 16578; CHECK-NEXT: vmv.v.v v9, v12579; CHECK-NEXT: vs2r.v v8, (a0)580; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma581; CHECK-NEXT: vlseg4e32.v v8, (a0)582; CHECK-NEXT: csrr a0, vlenb583; CHECK-NEXT: slli a0, a0, 1584; CHECK-NEXT: add sp, sp, a0585; CHECK-NEXT: .cfi_def_cfa sp, 16586; CHECK-NEXT: addi sp, sp, 16587; CHECK-NEXT: .cfi_def_cfa_offset 0588; CHECK-NEXT: ret589 %res = call {<2 x float>, <2 x float>, <2 x float>, <2 x float>} @llvm.vector.deinterleave4.v8f32(<8 x float> %v)590 ret {<2 x float>, <2 x float>, <2 x float>, <2 x float>} %res591}592 593define {<2 x half>, <2 x half>, <2 x half>, <2 x half>, <2 x half>} @vector_deinterleave5_v10f16_v2f16(<10 x half> %v) {594; CHECK-LABEL: vector_deinterleave5_v10f16_v2f16:595; CHECK: # %bb.0:596; CHECK-NEXT: addi sp, sp, -16597; CHECK-NEXT: .cfi_def_cfa_offset 16598; CHECK-NEXT: csrr a0, vlenb599; CHECK-NEXT: slli a0, a0, 1600; CHECK-NEXT: sub sp, sp, a0601; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 2 * vlenb602; CHECK-NEXT: csrr a0, vlenb603; CHECK-NEXT: vsetivli zero, 2, e16, m1, ta, ma604; CHECK-NEXT: vslidedown.vi v12, v8, 6605; CHECK-NEXT: vslidedown.vi v13, v8, 4606; CHECK-NEXT: vslidedown.vi v14, v8, 2607; CHECK-NEXT: vsetivli zero, 2, e16, m2, ta, ma608; CHECK-NEXT: vslidedown.vi v10, v8, 8609; CHECK-NEXT: srli a1, a0, 2610; CHECK-NEXT: srli a0, a0, 3611; CHECK-NEXT: vsetvli a2, zero, e16, mf2, ta, ma612; CHECK-NEXT: vslideup.vx v13, v12, a0613; CHECK-NEXT: vslideup.vx v8, v14, a0614; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma615; CHECK-NEXT: vslideup.vx v8, v13, a1616; CHECK-NEXT: addi a0, sp, 16617; CHECK-NEXT: vmv1r.v v9, v10618; CHECK-NEXT: vs2r.v v8, (a0)619; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma620; CHECK-NEXT: vlseg5e16.v v8, (a0)621; CHECK-NEXT: csrr a0, vlenb622; CHECK-NEXT: slli a0, a0, 1623; CHECK-NEXT: add sp, sp, a0624; CHECK-NEXT: .cfi_def_cfa sp, 16625; CHECK-NEXT: addi sp, sp, 16626; CHECK-NEXT: .cfi_def_cfa_offset 0627; CHECK-NEXT: ret628 %res = call {<2 x half>, <2 x half>, <2 x half>, <2 x half>, <2 x half>} @llvm.vector.deinterleave5.v10f16(<10 x half> %v)629 ret {<2 x half>, <2 x half>, <2 x half>, <2 x half>, <2 x half>} %res630}631 632define {<2 x half>, <2 x half>, <2 x half>, <2 x half>, <2 x half>, <2 x half>} @vector_deinterleave6_v12f16_v2f16(<12 x half> %v) {633; CHECK-LABEL: vector_deinterleave6_v12f16_v2f16:634; CHECK: # %bb.0:635; CHECK-NEXT: addi sp, sp, -16636; CHECK-NEXT: .cfi_def_cfa_offset 16637; CHECK-NEXT: csrr a0, vlenb638; CHECK-NEXT: slli a0, a0, 1639; CHECK-NEXT: sub sp, sp, a0640; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 2 * vlenb641; CHECK-NEXT: csrr a0, vlenb642; CHECK-NEXT: vsetivli zero, 2, e16, m1, ta, ma643; CHECK-NEXT: vslidedown.vi v14, v8, 6644; CHECK-NEXT: vslidedown.vi v15, v8, 4645; CHECK-NEXT: vslidedown.vi v16, v8, 2646; CHECK-NEXT: vsetivli zero, 2, e16, m2, ta, ma647; CHECK-NEXT: vslidedown.vi v10, v8, 10648; CHECK-NEXT: vslidedown.vi v12, v8, 8649; CHECK-NEXT: srli a1, a0, 2650; CHECK-NEXT: srli a0, a0, 3651; CHECK-NEXT: vsetvli a2, zero, e16, mf2, ta, ma652; CHECK-NEXT: vslideup.vx v15, v14, a0653; CHECK-NEXT: vslideup.vx v8, v16, a0654; CHECK-NEXT: vslideup.vx v12, v10, a0655; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma656; CHECK-NEXT: vslideup.vx v8, v15, a1657; CHECK-NEXT: addi a0, sp, 16658; CHECK-NEXT: vmv1r.v v9, v12659; CHECK-NEXT: vs2r.v v8, (a0)660; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma661; CHECK-NEXT: vlseg6e16.v v8, (a0)662; CHECK-NEXT: csrr a0, vlenb663; CHECK-NEXT: slli a0, a0, 1664; CHECK-NEXT: add sp, sp, a0665; CHECK-NEXT: .cfi_def_cfa sp, 16666; CHECK-NEXT: addi sp, sp, 16667; CHECK-NEXT: .cfi_def_cfa_offset 0668; CHECK-NEXT: ret669 %res = call {<2 x half>, <2 x half>, <2 x half>, <2 x half>, <2 x half>, <2 x half>} @llvm.vector.deinterleave6.v12f16(<12 x half> %v)670 ret {<2 x half>, <2 x half>, <2 x half>, <2 x half>, <2 x half>, <2 x half>} %res671}672 673define {<1 x half>, <1 x half>, <1 x half>, <1 x half>, <1 x half>, <1 x half>, <1 x half>} @vector_deinterleave7_v7f16_v1f16(<7 x half> %v) {674; CHECK-LABEL: vector_deinterleave7_v7f16_v1f16:675; CHECK: # %bb.0:676; CHECK-NEXT: addi sp, sp, -16677; CHECK-NEXT: .cfi_def_cfa_offset 16678; CHECK-NEXT: csrr a0, vlenb679; CHECK-NEXT: slli a0, a0, 1680; CHECK-NEXT: sub sp, sp, a0681; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 2 * vlenb682; CHECK-NEXT: csrr a0, vlenb683; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma684; CHECK-NEXT: vslidedown.vi v9, v8, 3685; CHECK-NEXT: vslidedown.vi v11, v8, 2686; CHECK-NEXT: vslidedown.vi v12, v8, 1687; CHECK-NEXT: vmv1r.v v10, v8688; CHECK-NEXT: vslidedown.vi v13, v8, 5689; CHECK-NEXT: vslidedown.vi v14, v8, 6690; CHECK-NEXT: srli a1, a0, 2691; CHECK-NEXT: srli a0, a0, 3692; CHECK-NEXT: vsetvli a2, zero, e16, mf2, ta, ma693; CHECK-NEXT: vslideup.vx v11, v9, a0694; CHECK-NEXT: vslideup.vx v10, v12, a0695; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, ma696; CHECK-NEXT: vslideup.vx v10, v11, a1697; CHECK-NEXT: vslidedown.vi v11, v8, 4698; CHECK-NEXT: vsetvli a2, zero, e16, mf2, ta, ma699; CHECK-NEXT: vslideup.vx v11, v13, a0700; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma701; CHECK-NEXT: vslideup.vx v11, v14, a1702; CHECK-NEXT: addi a0, sp, 16703; CHECK-NEXT: vs2r.v v10, (a0)704; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma705; CHECK-NEXT: vlseg7e16.v v8, (a0)706; CHECK-NEXT: csrr a0, vlenb707; CHECK-NEXT: slli a0, a0, 1708; CHECK-NEXT: add sp, sp, a0709; CHECK-NEXT: .cfi_def_cfa sp, 16710; CHECK-NEXT: addi sp, sp, 16711; CHECK-NEXT: .cfi_def_cfa_offset 0712; CHECK-NEXT: ret713 %res = call {<1 x half>, <1 x half>, <1 x half>, <1 x half>, <1 x half>, <1 x half>, <1 x half>} @llvm.vector.deinterleave7.v7f16(<7 x half> %v)714 ret {<1 x half>, <1 x half>, <1 x half>, <1 x half>, <1 x half>, <1 x half>, <1 x half>} %res715}716 717define {<1 x half>, <1 x half>, <1 x half>, <1 x half>, <1 x half>, <1 x half>, <1 x half>, <1 x half>} @vector_deinterleave8_v8f16_v1f16(<8 x half> %v) {718; CHECK-LABEL: vector_deinterleave8_v8f16_v1f16:719; CHECK: # %bb.0:720; CHECK-NEXT: addi sp, sp, -16721; CHECK-NEXT: .cfi_def_cfa_offset 16722; CHECK-NEXT: csrr a0, vlenb723; CHECK-NEXT: slli a0, a0, 1724; CHECK-NEXT: sub sp, sp, a0725; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 2 * vlenb726; CHECK-NEXT: csrr a0, vlenb727; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma728; CHECK-NEXT: vslidedown.vi v10, v8, 7729; CHECK-NEXT: vslidedown.vi v11, v8, 6730; CHECK-NEXT: vslidedown.vi v12, v8, 5731; CHECK-NEXT: srli a1, a0, 2732; CHECK-NEXT: srli a0, a0, 3733; CHECK-NEXT: vslidedown.vi v9, v8, 4734; CHECK-NEXT: vsetvli a2, zero, e16, mf2, ta, ma735; CHECK-NEXT: vslideup.vx v11, v10, a0736; CHECK-NEXT: vslideup.vx v9, v12, a0737; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, ma738; CHECK-NEXT: vslideup.vx v9, v11, a1739; CHECK-NEXT: vslidedown.vi v10, v8, 3740; CHECK-NEXT: vslidedown.vi v11, v8, 2741; CHECK-NEXT: vslidedown.vi v12, v8, 1742; CHECK-NEXT: vsetvli a2, zero, e16, mf2, ta, ma743; CHECK-NEXT: vslideup.vx v11, v10, a0744; CHECK-NEXT: vslideup.vx v8, v12, a0745; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma746; CHECK-NEXT: vslideup.vx v8, v11, a1747; CHECK-NEXT: addi a0, sp, 16748; CHECK-NEXT: vs2r.v v8, (a0)749; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma750; CHECK-NEXT: vlseg8e16.v v8, (a0)751; CHECK-NEXT: csrr a0, vlenb752; CHECK-NEXT: slli a0, a0, 1753; CHECK-NEXT: add sp, sp, a0754; CHECK-NEXT: .cfi_def_cfa sp, 16755; CHECK-NEXT: addi sp, sp, 16756; CHECK-NEXT: .cfi_def_cfa_offset 0757; CHECK-NEXT: ret758 %res = call {<1 x half>, <1 x half>, <1 x half>, <1 x half>, <1 x half>, <1 x half>, <1 x half>, <1 x half>} @llvm.vector.deinterleave8.v8f16(<8 x half> %v)759 ret {<1 x half>, <1 x half>, <1 x half>, <1 x half>, <1 x half>, <1 x half>, <1 x half>, <1 x half>} %res760}761;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:762; RV32: {{.*}}763; RV64: {{.*}}764