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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+v,+zvfhmin,+zvfbfmin | FileCheck %s --check-prefixes=CHECK,V3; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+v,+zvfhmin,+zvfbfmin | FileCheck %s --check-prefixes=CHECK,V4; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+v,+zvfhmin,+zvfbfmin,+experimental-xrivosvizip | FileCheck %s --check-prefixes=CHECK,ZIP5 6; Integers7 8define {<vscale x 16 x i1>, <vscale x 16 x i1>} @vector_deinterleave_nxv16i1_nxv32i1(<vscale x 32 x i1> %vec) {9; V-LABEL: vector_deinterleave_nxv16i1_nxv32i1:10; V:       # %bb.0:11; V-NEXT:    vsetvli a0, zero, e8, m2, ta, ma12; V-NEXT:    vmv.v.i v10, 013; V-NEXT:    csrr a0, vlenb14; V-NEXT:    vmerge.vim v8, v10, 1, v015; V-NEXT:    srli a0, a0, 216; V-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma17; V-NEXT:    vslidedown.vx v0, v0, a018; V-NEXT:    vsetvli a0, zero, e8, m2, ta, ma19; V-NEXT:    vmerge.vim v10, v10, 1, v020; V-NEXT:    vnsrl.wi v12, v8, 021; V-NEXT:    vnsrl.wi v14, v8, 822; V-NEXT:    vmsne.vi v0, v12, 023; V-NEXT:    vmsne.vi v8, v14, 024; V-NEXT:    ret25;26; ZIP-LABEL: vector_deinterleave_nxv16i1_nxv32i1:27; ZIP:       # %bb.0:28; ZIP-NEXT:    vsetvli a0, zero, e8, m2, ta, ma29; ZIP-NEXT:    vmv.v.i v8, 030; ZIP-NEXT:    csrr a0, vlenb31; ZIP-NEXT:    vmerge.vim v10, v8, 1, v032; ZIP-NEXT:    srli a0, a0, 233; ZIP-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma34; ZIP-NEXT:    vslidedown.vx v0, v0, a035; ZIP-NEXT:    vsetvli a0, zero, e8, m2, ta, ma36; ZIP-NEXT:    vmerge.vim v8, v8, 1, v037; ZIP-NEXT:    ri.vunzip2a.vv v12, v10, v838; ZIP-NEXT:    ri.vunzip2b.vv v14, v10, v839; ZIP-NEXT:    vmsne.vi v0, v12, 040; ZIP-NEXT:    vmsne.vi v8, v14, 041; ZIP-NEXT:    ret42%retval = call {<vscale x 16 x i1>, <vscale x 16 x i1>} @llvm.vector.deinterleave2.nxv32i1(<vscale x 32 x i1> %vec)43ret {<vscale x 16 x i1>, <vscale x 16 x i1>} %retval44}45 46define {<vscale x 16 x i8>, <vscale x 16 x i8>} @vector_deinterleave_nxv16i8_nxv32i8(<vscale x 32 x i8> %vec) {47; V-LABEL: vector_deinterleave_nxv16i8_nxv32i8:48; V:       # %bb.0:49; V-NEXT:    vsetvli a0, zero, e8, m2, ta, ma50; V-NEXT:    vnsrl.wi v12, v8, 051; V-NEXT:    vnsrl.wi v14, v8, 852; V-NEXT:    vmv.v.v v8, v1253; V-NEXT:    vmv.v.v v10, v1454; V-NEXT:    ret55;56; ZIP-LABEL: vector_deinterleave_nxv16i8_nxv32i8:57; ZIP:       # %bb.0:58; ZIP-NEXT:    vsetvli a0, zero, e8, m2, ta, ma59; ZIP-NEXT:    ri.vunzip2a.vv v12, v8, v1060; ZIP-NEXT:    ri.vunzip2b.vv v14, v8, v1061; ZIP-NEXT:    vmv.v.v v8, v1262; ZIP-NEXT:    vmv.v.v v10, v1463; ZIP-NEXT:    ret64%retval = call {<vscale x 16 x i8>, <vscale x 16 x i8>} @llvm.vector.deinterleave2.nxv32i8(<vscale x 32 x i8> %vec)65ret {<vscale x 16 x i8>, <vscale x 16 x i8>} %retval66}67 68define {<vscale x 8 x i16>, <vscale x 8 x i16>} @vector_deinterleave_nxv8i16_nxv16i16(<vscale x 16 x i16> %vec) {69; V-LABEL: vector_deinterleave_nxv8i16_nxv16i16:70; V:       # %bb.0:71; V-NEXT:    vsetvli a0, zero, e16, m2, ta, ma72; V-NEXT:    vnsrl.wi v12, v8, 073; V-NEXT:    vnsrl.wi v14, v8, 1674; V-NEXT:    vmv.v.v v8, v1275; V-NEXT:    vmv.v.v v10, v1476; V-NEXT:    ret77;78; ZIP-LABEL: vector_deinterleave_nxv8i16_nxv16i16:79; ZIP:       # %bb.0:80; ZIP-NEXT:    vsetvli a0, zero, e16, m2, ta, ma81; ZIP-NEXT:    ri.vunzip2a.vv v12, v8, v1082; ZIP-NEXT:    ri.vunzip2b.vv v14, v8, v1083; ZIP-NEXT:    vmv.v.v v8, v1284; ZIP-NEXT:    vmv.v.v v10, v1485; ZIP-NEXT:    ret86%retval = call {<vscale x 8 x i16>, <vscale x 8 x i16>} @llvm.vector.deinterleave2.nxv16i16(<vscale x 16 x i16> %vec)87ret {<vscale x 8 x i16>, <vscale x 8 x i16>} %retval88}89 90define {<vscale x 4 x i32>, <vscale x 4 x i32>} @vector_deinterleave_nxv4i32_nxvv8i32(<vscale x 8 x i32> %vec) {91; V-LABEL: vector_deinterleave_nxv4i32_nxvv8i32:92; V:       # %bb.0:93; V-NEXT:    li a0, 3294; V-NEXT:    vsetvli a1, zero, e32, m2, ta, ma95; V-NEXT:    vnsrl.wx v12, v8, a096; V-NEXT:    vnsrl.wi v14, v8, 097; V-NEXT:    vmv.v.v v8, v1498; V-NEXT:    vmv.v.v v10, v1299; V-NEXT:    ret100;101; ZIP-LABEL: vector_deinterleave_nxv4i32_nxvv8i32:102; ZIP:       # %bb.0:103; ZIP-NEXT:    vsetvli a0, zero, e32, m2, ta, ma104; ZIP-NEXT:    ri.vunzip2a.vv v12, v8, v10105; ZIP-NEXT:    ri.vunzip2b.vv v14, v8, v10106; ZIP-NEXT:    vmv.v.v v8, v12107; ZIP-NEXT:    vmv.v.v v10, v14108; ZIP-NEXT:    ret109%retval = call {<vscale x 4 x i32>, <vscale x 4 x i32>} @llvm.vector.deinterleave2.nxv8i32(<vscale x 8 x i32> %vec)110ret {<vscale x 4 x i32>, <vscale x 4 x i32>} %retval111}112 113define {<vscale x 2 x i64>, <vscale x 2 x i64>} @vector_deinterleave_nxv2i64_nxv4i64(<vscale x 4 x i64> %vec) {114; V-LABEL: vector_deinterleave_nxv2i64_nxv4i64:115; V:       # %bb.0:116; V-NEXT:    li a0, 85117; V-NEXT:    vsetvli a1, zero, e8, m1, ta, ma118; V-NEXT:    vmv.v.x v16, a0119; V-NEXT:    li a0, 170120; V-NEXT:    vmv.v.x v20, a0121; V-NEXT:    vsetvli a0, zero, e64, m4, ta, ma122; V-NEXT:    vcompress.vm v12, v8, v16123; V-NEXT:    vcompress.vm v16, v8, v20124; V-NEXT:    vmv2r.v v8, v12125; V-NEXT:    vmv2r.v v10, v16126; V-NEXT:    ret127;128; ZIP-LABEL: vector_deinterleave_nxv2i64_nxv4i64:129; ZIP:       # %bb.0:130; ZIP-NEXT:    vsetvli a0, zero, e64, m2, ta, ma131; ZIP-NEXT:    ri.vunzip2a.vv v12, v8, v10132; ZIP-NEXT:    ri.vunzip2b.vv v14, v8, v10133; ZIP-NEXT:    vmv.v.v v8, v12134; ZIP-NEXT:    vmv.v.v v10, v14135; ZIP-NEXT:    ret136%retval = call {<vscale x 2 x i64>, <vscale x 2 x i64>} @llvm.vector.deinterleave2.nxv4i64(<vscale x 4 x i64> %vec)137ret {<vscale x 2 x i64>, <vscale x 2 x i64>} %retval138}139 140define {<vscale x 4 x i64>, <vscale x 4 x i64>} @vector_deinterleave_nxv4i64_nxv8i64(<vscale x 8 x i64> %vec) {141; V-LABEL: vector_deinterleave_nxv4i64_nxv8i64:142; V:       # %bb.0:143; V-NEXT:    li a0, 85144; V-NEXT:    vsetvli a1, zero, e8, mf8, ta, ma145; V-NEXT:    vmv.v.x v24, a0146; V-NEXT:    li a0, 170147; V-NEXT:    vmv.v.x v7, a0148; V-NEXT:    vsetvli a0, zero, e64, m8, ta, ma149; V-NEXT:    vcompress.vm v16, v8, v24150; V-NEXT:    vcompress.vm v24, v8, v7151; V-NEXT:    vmv4r.v v8, v16152; V-NEXT:    vmv4r.v v12, v24153; V-NEXT:    ret154;155; ZIP-LABEL: vector_deinterleave_nxv4i64_nxv8i64:156; ZIP:       # %bb.0:157; ZIP-NEXT:    vsetvli a0, zero, e64, m4, ta, ma158; ZIP-NEXT:    ri.vunzip2a.vv v16, v8, v12159; ZIP-NEXT:    ri.vunzip2b.vv v20, v8, v12160; ZIP-NEXT:    vmv.v.v v8, v16161; ZIP-NEXT:    vmv.v.v v12, v20162; ZIP-NEXT:    ret163%retval = call {<vscale x 4 x i64>, <vscale x 4 x i64>} @llvm.vector.deinterleave2.nxv8i64(<vscale x 8 x i64> %vec)164ret {<vscale x 4 x i64>, <vscale x 4 x i64>} %retval165}166 167 168define {<vscale x 64 x i1>, <vscale x 64 x i1>} @vector_deinterleave_nxv64i1_nxv128i1(<vscale x 128 x i1> %vec) {169; V-LABEL: vector_deinterleave_nxv64i1_nxv128i1:170; V:       # %bb.0:171; V-NEXT:    vsetvli a0, zero, e8, m8, ta, ma172; V-NEXT:    vmv.v.i v24, 0173; V-NEXT:    vmerge.vim v16, v24, 1, v0174; V-NEXT:    vmv1r.v v0, v8175; V-NEXT:    vmerge.vim v24, v24, 1, v0176; V-NEXT:    vsetvli a0, zero, e8, m4, ta, ma177; V-NEXT:    vnsrl.wi v8, v16, 0178; V-NEXT:    vnsrl.wi v0, v16, 8179; V-NEXT:    vnsrl.wi v12, v24, 0180; V-NEXT:    vnsrl.wi v4, v24, 8181; V-NEXT:    vsetvli a0, zero, e8, m8, ta, ma182; V-NEXT:    vmsne.vi v16, v8, 0183; V-NEXT:    vmsne.vi v8, v0, 0184; V-NEXT:    vmv1r.v v0, v16185; V-NEXT:    ret186;187; ZIP-LABEL: vector_deinterleave_nxv64i1_nxv128i1:188; ZIP:       # %bb.0:189; ZIP-NEXT:    vsetvli a0, zero, e8, m8, ta, ma190; ZIP-NEXT:    vmv1r.v v9, v0191; ZIP-NEXT:    vmv1r.v v0, v8192; ZIP-NEXT:    vmv.v.i v24, 0193; ZIP-NEXT:    vmerge.vim v16, v24, 1, v0194; ZIP-NEXT:    vmv1r.v v0, v9195; ZIP-NEXT:    vmerge.vim v24, v24, 1, v0196; ZIP-NEXT:    vsetvli a0, zero, e8, m4, ta, ma197; ZIP-NEXT:    ri.vunzip2a.vv v12, v16, v20198; ZIP-NEXT:    ri.vunzip2b.vv v4, v16, v20199; ZIP-NEXT:    ri.vunzip2a.vv v8, v24, v28200; ZIP-NEXT:    ri.vunzip2b.vv v0, v24, v28201; ZIP-NEXT:    vsetvli a0, zero, e8, m8, ta, ma202; ZIP-NEXT:    vmsne.vi v16, v8, 0203; ZIP-NEXT:    vmsne.vi v8, v0, 0204; ZIP-NEXT:    vmv1r.v v0, v16205; ZIP-NEXT:    ret206%retval = call {<vscale x 64 x i1>, <vscale x 64 x i1>} @llvm.vector.deinterleave2.nxv128i1(<vscale x 128 x i1> %vec)207ret {<vscale x 64 x i1>, <vscale x 64 x i1>} %retval208}209 210define {<vscale x 64 x i8>, <vscale x 64 x i8>} @vector_deinterleave_nxv64i8_nxv128i8(<vscale x 128 x i8> %vec) {211; V-LABEL: vector_deinterleave_nxv64i8_nxv128i8:212; V:       # %bb.0:213; V-NEXT:    vsetvli a0, zero, e8, m4, ta, ma214; V-NEXT:    vmv8r.v v24, v8215; V-NEXT:    vnsrl.wi v8, v24, 0216; V-NEXT:    vnsrl.wi v0, v24, 8217; V-NEXT:    vnsrl.wi v12, v16, 0218; V-NEXT:    vnsrl.wi v4, v16, 8219; V-NEXT:    vmv8r.v v16, v0220; V-NEXT:    ret221;222; ZIP-LABEL: vector_deinterleave_nxv64i8_nxv128i8:223; ZIP:       # %bb.0:224; ZIP-NEXT:    vsetvli a0, zero, e8, m4, ta, ma225; ZIP-NEXT:    ri.vunzip2a.vv v28, v16, v20226; ZIP-NEXT:    ri.vunzip2b.vv v4, v16, v20227; ZIP-NEXT:    ri.vunzip2a.vv v24, v8, v12228; ZIP-NEXT:    ri.vunzip2b.vv v0, v8, v12229; ZIP-NEXT:    vmv8r.v v8, v24230; ZIP-NEXT:    vmv8r.v v16, v0231; ZIP-NEXT:    ret232%retval = call {<vscale x 64 x i8>, <vscale x 64 x i8>} @llvm.vector.deinterleave2.nxv128i8(<vscale x 128 x i8> %vec)233ret {<vscale x 64 x i8>, <vscale x 64 x i8>} %retval234}235 236define {<vscale x 32 x i16>, <vscale x 32 x i16>} @vector_deinterleave_nxv32i16_nxv64i16(<vscale x 64 x i16> %vec) {237; V-LABEL: vector_deinterleave_nxv32i16_nxv64i16:238; V:       # %bb.0:239; V-NEXT:    vsetvli a0, zero, e16, m4, ta, ma240; V-NEXT:    vmv8r.v v24, v8241; V-NEXT:    vnsrl.wi v8, v24, 0242; V-NEXT:    vnsrl.wi v0, v24, 16243; V-NEXT:    vnsrl.wi v12, v16, 0244; V-NEXT:    vnsrl.wi v4, v16, 16245; V-NEXT:    vmv8r.v v16, v0246; V-NEXT:    ret247;248; ZIP-LABEL: vector_deinterleave_nxv32i16_nxv64i16:249; ZIP:       # %bb.0:250; ZIP-NEXT:    vsetvli a0, zero, e16, m4, ta, ma251; ZIP-NEXT:    ri.vunzip2a.vv v28, v16, v20252; ZIP-NEXT:    ri.vunzip2b.vv v4, v16, v20253; ZIP-NEXT:    ri.vunzip2a.vv v24, v8, v12254; ZIP-NEXT:    ri.vunzip2b.vv v0, v8, v12255; ZIP-NEXT:    vmv8r.v v8, v24256; ZIP-NEXT:    vmv8r.v v16, v0257; ZIP-NEXT:    ret258%retval = call {<vscale x 32 x i16>, <vscale x 32 x i16>} @llvm.vector.deinterleave2.nxv64i16(<vscale x 64 x i16> %vec)259ret {<vscale x 32 x i16>, <vscale x 32 x i16>} %retval260}261 262define {<vscale x 16 x i32>, <vscale x 16 x i32>} @vector_deinterleave_nxv16i32_nxvv32i32(<vscale x 32 x i32> %vec) {263; V-LABEL: vector_deinterleave_nxv16i32_nxvv32i32:264; V:       # %bb.0:265; V-NEXT:    vsetvli a0, zero, e32, m4, ta, ma266; V-NEXT:    vmv8r.v v24, v16267; V-NEXT:    li a0, 32268; V-NEXT:    vnsrl.wx v20, v24, a0269; V-NEXT:    vnsrl.wx v16, v8, a0270; V-NEXT:    vnsrl.wi v0, v8, 0271; V-NEXT:    vnsrl.wi v4, v24, 0272; V-NEXT:    vmv8r.v v8, v0273; V-NEXT:    ret274;275; ZIP-LABEL: vector_deinterleave_nxv16i32_nxvv32i32:276; ZIP:       # %bb.0:277; ZIP-NEXT:    vsetvli a0, zero, e32, m4, ta, ma278; ZIP-NEXT:    ri.vunzip2a.vv v28, v16, v20279; ZIP-NEXT:    ri.vunzip2b.vv v4, v16, v20280; ZIP-NEXT:    ri.vunzip2a.vv v24, v8, v12281; ZIP-NEXT:    ri.vunzip2b.vv v0, v8, v12282; ZIP-NEXT:    vmv8r.v v8, v24283; ZIP-NEXT:    vmv8r.v v16, v0284; ZIP-NEXT:    ret285%retval = call {<vscale x 16 x i32>, <vscale x 16 x i32>} @llvm.vector.deinterleave2.nxv32i32(<vscale x 32 x i32> %vec)286ret {<vscale x 16 x i32>, <vscale x 16 x i32>} %retval287}288 289define {<vscale x 8 x i64>, <vscale x 8 x i64>} @vector_deinterleave_nxv8i64_nxv16i64(<vscale x 16 x i64> %vec) {290; V-LABEL: vector_deinterleave_nxv8i64_nxv16i64:291; V:       # %bb.0:292; V-NEXT:    addi sp, sp, -16293; V-NEXT:    .cfi_def_cfa_offset 16294; V-NEXT:    csrr a0, vlenb295; V-NEXT:    slli a0, a0, 4296; V-NEXT:    sub sp, sp, a0297; V-NEXT:    .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb298; V-NEXT:    li a0, 85299; V-NEXT:    vsetvli a1, zero, e8, mf8, ta, ma300; V-NEXT:    vmv.v.x v7, a0301; V-NEXT:    li a0, 170302; V-NEXT:    vmv.v.x v6, a0303; V-NEXT:    vsetvli a0, zero, e64, m8, ta, ma304; V-NEXT:    vcompress.vm v24, v8, v7305; V-NEXT:    vmv1r.v v28, v7306; V-NEXT:    vmv1r.v v29, v6307; V-NEXT:    vcompress.vm v0, v8, v29308; V-NEXT:    vcompress.vm v8, v16, v28309; V-NEXT:    addi a0, sp, 16310; V-NEXT:    vs8r.v v8, (a0) # vscale x 64-byte Folded Spill311; V-NEXT:    vcompress.vm v8, v16, v29312; V-NEXT:    csrr a0, vlenb313; V-NEXT:    slli a0, a0, 3314; V-NEXT:    add a0, sp, a0315; V-NEXT:    addi a0, a0, 16316; V-NEXT:    vs8r.v v8, (a0) # vscale x 64-byte Folded Spill317; V-NEXT:    addi a0, sp, 16318; V-NEXT:    vl8r.v v8, (a0) # vscale x 64-byte Folded Reload319; V-NEXT:    vmv4r.v v28, v8320; V-NEXT:    csrr a0, vlenb321; V-NEXT:    slli a0, a0, 3322; V-NEXT:    add a0, sp, a0323; V-NEXT:    addi a0, a0, 16324; V-NEXT:    vl8r.v v8, (a0) # vscale x 64-byte Folded Reload325; V-NEXT:    vmv4r.v v4, v8326; V-NEXT:    vmv8r.v v8, v24327; V-NEXT:    vmv8r.v v16, v0328; V-NEXT:    csrr a0, vlenb329; V-NEXT:    slli a0, a0, 4330; V-NEXT:    add sp, sp, a0331; V-NEXT:    .cfi_def_cfa sp, 16332; V-NEXT:    addi sp, sp, 16333; V-NEXT:    .cfi_def_cfa_offset 0334; V-NEXT:    ret335;336; ZIP-LABEL: vector_deinterleave_nxv8i64_nxv16i64:337; ZIP:       # %bb.0:338; ZIP-NEXT:    vsetvli a0, zero, e64, m4, ta, ma339; ZIP-NEXT:    ri.vunzip2a.vv v28, v16, v20340; ZIP-NEXT:    ri.vunzip2b.vv v4, v16, v20341; ZIP-NEXT:    ri.vunzip2a.vv v24, v8, v12342; ZIP-NEXT:    ri.vunzip2b.vv v0, v8, v12343; ZIP-NEXT:    vmv8r.v v8, v24344; ZIP-NEXT:    vmv8r.v v16, v0345; ZIP-NEXT:    ret346%retval = call {<vscale x 8 x i64>, <vscale x 8 x i64>} @llvm.vector.deinterleave2.nxv16i64(<vscale x 16 x i64> %vec)347ret {<vscale x 8 x i64>, <vscale x 8 x i64>} %retval348}349 350define {<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>} @vector_deinterleave_nxv16i1_nxv48i1(<vscale x 48 x i1> %vec) nounwind {351; CHECK-LABEL: vector_deinterleave_nxv16i1_nxv48i1:352; CHECK:       # %bb.0:353; CHECK-NEXT:    addi sp, sp, -16354; CHECK-NEXT:    csrr a0, vlenb355; CHECK-NEXT:    slli a0, a0, 3356; CHECK-NEXT:    sub sp, sp, a0357; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, ma358; CHECK-NEXT:    vmv1r.v v8, v0359; CHECK-NEXT:    vmv.v.i v10, 0360; CHECK-NEXT:    csrr a0, vlenb361; CHECK-NEXT:    vmerge.vim v16, v10, 1, v0362; CHECK-NEXT:    srli a1, a0, 2363; CHECK-NEXT:    vsetvli a2, zero, e8, m1, ta, ma364; CHECK-NEXT:    vslidedown.vx v0, v0, a1365; CHECK-NEXT:    srli a0, a0, 1366; CHECK-NEXT:    vsetvli a1, zero, e8, m2, ta, ma367; CHECK-NEXT:    vmerge.vim v18, v10, 1, v0368; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma369; CHECK-NEXT:    vslidedown.vx v0, v8, a0370; CHECK-NEXT:    addi a0, sp, 16371; CHECK-NEXT:    vsetvli a1, zero, e8, m2, ta, ma372; CHECK-NEXT:    vmerge.vim v20, v10, 1, v0373; CHECK-NEXT:    vs8r.v v16, (a0)374; CHECK-NEXT:    vlseg3e8.v v8, (a0)375; CHECK-NEXT:    vmsne.vi v0, v8, 0376; CHECK-NEXT:    vmsne.vi v8, v10, 0377; CHECK-NEXT:    vmsne.vi v9, v12, 0378; CHECK-NEXT:    csrr a0, vlenb379; CHECK-NEXT:    slli a0, a0, 3380; CHECK-NEXT:    add sp, sp, a0381; CHECK-NEXT:    addi sp, sp, 16382; CHECK-NEXT:    ret383  %retval = call {<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>} @llvm.vector.deinterleave3.nxv48i1(<vscale x 48 x i1> %vec)384  ret {<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>} %retval385}386 387 388define {<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>} @vector_deinterleave_nxv16i8_nxv48i8(<vscale x 48 x i8> %vec) nounwind {389; CHECK-LABEL: vector_deinterleave_nxv16i8_nxv48i8:390; CHECK:       # %bb.0:391; CHECK-NEXT:    addi sp, sp, -16392; CHECK-NEXT:    csrr a0, vlenb393; CHECK-NEXT:    slli a0, a0, 3394; CHECK-NEXT:    sub sp, sp, a0395; CHECK-NEXT:    addi a0, sp, 16396; CHECK-NEXT:    vs8r.v v8, (a0)397; CHECK-NEXT:    vsetvli a1, zero, e8, m2, ta, ma398; CHECK-NEXT:    vlseg3e8.v v8, (a0)399; CHECK-NEXT:    csrr a0, vlenb400; CHECK-NEXT:    slli a0, a0, 3401; CHECK-NEXT:    add sp, sp, a0402; CHECK-NEXT:    addi sp, sp, 16403; CHECK-NEXT:    ret404  %retval = call {<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>} @llvm.vector.deinterleave3.nxv48i8(<vscale x 48 x i8> %vec)405  ret {<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>} %retval406}407 408 409define {<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>} @vector_deinterleave_nxv8i16_nxv24i16(<vscale x 24 x i16> %vec) nounwind {410; CHECK-LABEL: vector_deinterleave_nxv8i16_nxv24i16:411; CHECK:       # %bb.0:412; CHECK-NEXT:    addi sp, sp, -16413; CHECK-NEXT:    csrr a0, vlenb414; CHECK-NEXT:    slli a0, a0, 3415; CHECK-NEXT:    sub sp, sp, a0416; CHECK-NEXT:    addi a0, sp, 16417; CHECK-NEXT:    vs8r.v v8, (a0)418; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma419; CHECK-NEXT:    vlseg3e16.v v8, (a0)420; CHECK-NEXT:    csrr a0, vlenb421; CHECK-NEXT:    slli a0, a0, 3422; CHECK-NEXT:    add sp, sp, a0423; CHECK-NEXT:    addi sp, sp, 16424; CHECK-NEXT:    ret425  %retval = call {<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>} @llvm.vector.deinterleave3.nxv24i16(<vscale x 24 x i16> %vec)426  ret {<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>} %retval427}428 429 430define {<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>} @vector_deinterleave_nxv4i32_nxv12i32(<vscale x 12 x i32> %vec) nounwind {431; CHECK-LABEL: vector_deinterleave_nxv4i32_nxv12i32:432; CHECK:       # %bb.0:433; CHECK-NEXT:    addi sp, sp, -16434; CHECK-NEXT:    csrr a0, vlenb435; CHECK-NEXT:    slli a0, a0, 3436; CHECK-NEXT:    sub sp, sp, a0437; CHECK-NEXT:    addi a0, sp, 16438; CHECK-NEXT:    vs8r.v v8, (a0)439; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, ma440; CHECK-NEXT:    vlseg3e32.v v8, (a0)441; CHECK-NEXT:    csrr a0, vlenb442; CHECK-NEXT:    slli a0, a0, 3443; CHECK-NEXT:    add sp, sp, a0444; CHECK-NEXT:    addi sp, sp, 16445; CHECK-NEXT:    ret446  %retval = call {<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>} @llvm.vector.deinterleave3.nxv12i32(<vscale x 12 x i32> %vec)447  ret {<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>} %retval448}449 450 451define {<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>} @vector_deinterleave_nxv2i64_nxv6i64(<vscale x 6 x i64> %vec) nounwind {452; CHECK-LABEL: vector_deinterleave_nxv2i64_nxv6i64:453; CHECK:       # %bb.0:454; CHECK-NEXT:    addi sp, sp, -16455; CHECK-NEXT:    csrr a0, vlenb456; CHECK-NEXT:    slli a0, a0, 3457; CHECK-NEXT:    sub sp, sp, a0458; CHECK-NEXT:    addi a0, sp, 16459; CHECK-NEXT:    vs8r.v v8, (a0)460; CHECK-NEXT:    vsetvli a1, zero, e64, m2, ta, ma461; CHECK-NEXT:    vlseg3e64.v v8, (a0)462; CHECK-NEXT:    csrr a0, vlenb463; CHECK-NEXT:    slli a0, a0, 3464; CHECK-NEXT:    add sp, sp, a0465; CHECK-NEXT:    addi sp, sp, 16466; CHECK-NEXT:    ret467  %retval = call {<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>} @llvm.vector.deinterleave3.nxv6i64(<vscale x 6 x i64> %vec)468  ret {<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>} %retval469}470 471define {<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>} @vector_deinterleave_nxv16i1_nxv64i1(<vscale x 64 x i1> %vec) nounwind {472; CHECK-LABEL: vector_deinterleave_nxv16i1_nxv64i1:473; CHECK:       # %bb.0:474; CHECK-NEXT:    addi sp, sp, -16475; CHECK-NEXT:    csrr a0, vlenb476; CHECK-NEXT:    slli a0, a0, 3477; CHECK-NEXT:    sub sp, sp, a0478; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, ma479; CHECK-NEXT:    vmv1r.v v8, v0480; CHECK-NEXT:    csrr a0, vlenb481; CHECK-NEXT:    vmv.v.i v10, 0482; CHECK-NEXT:    srli a1, a0, 2483; CHECK-NEXT:    sub a2, a0, a1484; CHECK-NEXT:    vsetvli a3, zero, e8, m1, ta, ma485; CHECK-NEXT:    vslidedown.vx v0, v0, a2486; CHECK-NEXT:    srli a0, a0, 1487; CHECK-NEXT:    vsetvli a2, zero, e8, m2, ta, ma488; CHECK-NEXT:    vmerge.vim v22, v10, 1, v0489; CHECK-NEXT:    vsetvli a2, zero, e8, m1, ta, ma490; CHECK-NEXT:    vslidedown.vx v0, v8, a0491; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, ma492; CHECK-NEXT:    vmerge.vim v20, v10, 1, v0493; CHECK-NEXT:    vmv1r.v v0, v8494; CHECK-NEXT:    vmerge.vim v16, v10, 1, v0495; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma496; CHECK-NEXT:    vslidedown.vx v0, v8, a1497; CHECK-NEXT:    addi a0, sp, 16498; CHECK-NEXT:    vsetvli a1, zero, e8, m2, ta, ma499; CHECK-NEXT:    vmerge.vim v18, v10, 1, v0500; CHECK-NEXT:    vs8r.v v16, (a0)501; CHECK-NEXT:    vlseg4e8.v v8, (a0)502; CHECK-NEXT:    vmsne.vi v0, v8, 0503; CHECK-NEXT:    vmsne.vi v8, v10, 0504; CHECK-NEXT:    vmsne.vi v9, v12, 0505; CHECK-NEXT:    vmsne.vi v10, v14, 0506; CHECK-NEXT:    csrr a0, vlenb507; CHECK-NEXT:    slli a0, a0, 3508; CHECK-NEXT:    add sp, sp, a0509; CHECK-NEXT:    addi sp, sp, 16510; CHECK-NEXT:    ret511  %retval = call {<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>} @llvm.vector.deinterleave4.nxv64i1(<vscale x 64 x i1> %vec)512  ret {<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>} %retval513}514 515define {<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>} @vector_deinterleave_nxv16i8_nxv64i8(<vscale x 64 x i8> %vec) nounwind {516; CHECK-LABEL: vector_deinterleave_nxv16i8_nxv64i8:517; CHECK:       # %bb.0:518; CHECK-NEXT:    addi sp, sp, -16519; CHECK-NEXT:    csrr a0, vlenb520; CHECK-NEXT:    slli a0, a0, 3521; CHECK-NEXT:    sub sp, sp, a0522; CHECK-NEXT:    addi a0, sp, 16523; CHECK-NEXT:    vs8r.v v8, (a0)524; CHECK-NEXT:    vsetvli a1, zero, e8, m2, ta, ma525; CHECK-NEXT:    vlseg4e8.v v8, (a0)526; CHECK-NEXT:    csrr a0, vlenb527; CHECK-NEXT:    slli a0, a0, 3528; CHECK-NEXT:    add sp, sp, a0529; CHECK-NEXT:    addi sp, sp, 16530; CHECK-NEXT:    ret531  %retval = call {<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>} @llvm.vector.deinterleave4.nxv48i8(<vscale x 64 x i8> %vec)532  ret {<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>} %retval533}534 535define {<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>} @vector_deinterleave_nxv8i16_nxv32i16(<vscale x 32 x i16> %vec) nounwind {536; CHECK-LABEL: vector_deinterleave_nxv8i16_nxv32i16:537; CHECK:       # %bb.0:538; CHECK-NEXT:    addi sp, sp, -16539; CHECK-NEXT:    csrr a0, vlenb540; CHECK-NEXT:    slli a0, a0, 3541; CHECK-NEXT:    sub sp, sp, a0542; CHECK-NEXT:    addi a0, sp, 16543; CHECK-NEXT:    vs8r.v v8, (a0)544; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma545; CHECK-NEXT:    vlseg4e16.v v8, (a0)546; CHECK-NEXT:    csrr a0, vlenb547; CHECK-NEXT:    slli a0, a0, 3548; CHECK-NEXT:    add sp, sp, a0549; CHECK-NEXT:    addi sp, sp, 16550; CHECK-NEXT:    ret551  %retval = call {<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>} @llvm.vector.deinterleave4.nxv32i16(<vscale x 32 x i16> %vec)552  ret {<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>} %retval553}554 555define {<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>} @vector_deinterleave_nxv4i32_nxv16i32(<vscale x 16 x i32> %vec) nounwind {556; CHECK-LABEL: vector_deinterleave_nxv4i32_nxv16i32:557; CHECK:       # %bb.0:558; CHECK-NEXT:    addi sp, sp, -16559; CHECK-NEXT:    csrr a0, vlenb560; CHECK-NEXT:    slli a0, a0, 3561; CHECK-NEXT:    sub sp, sp, a0562; CHECK-NEXT:    addi a0, sp, 16563; CHECK-NEXT:    vs8r.v v8, (a0)564; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, ma565; CHECK-NEXT:    vlseg4e32.v v8, (a0)566; CHECK-NEXT:    csrr a0, vlenb567; CHECK-NEXT:    slli a0, a0, 3568; CHECK-NEXT:    add sp, sp, a0569; CHECK-NEXT:    addi sp, sp, 16570; CHECK-NEXT:    ret571  %retval = call {<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>} @llvm.vector.deinterleave4.nxv16i32(<vscale x 16 x i32> %vec)572  ret {<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>} %retval573}574 575define {<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>} @vector_deinterleave_nxv2i64_nxv8i64(<vscale x 8 x i64> %vec) nounwind {576; CHECK-LABEL: vector_deinterleave_nxv2i64_nxv8i64:577; CHECK:       # %bb.0:578; CHECK-NEXT:    addi sp, sp, -16579; CHECK-NEXT:    csrr a0, vlenb580; CHECK-NEXT:    slli a0, a0, 3581; CHECK-NEXT:    sub sp, sp, a0582; CHECK-NEXT:    addi a0, sp, 16583; CHECK-NEXT:    vs8r.v v8, (a0)584; CHECK-NEXT:    vsetvli a1, zero, e64, m2, ta, ma585; CHECK-NEXT:    vlseg4e64.v v8, (a0)586; CHECK-NEXT:    csrr a0, vlenb587; CHECK-NEXT:    slli a0, a0, 3588; CHECK-NEXT:    add sp, sp, a0589; CHECK-NEXT:    addi sp, sp, 16590; CHECK-NEXT:    ret591  %retval = call {<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>} @llvm.vector.deinterleave4.nxv8i64(<vscale x 8 x i64> %vec)592  ret {<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>} %retval593}594 595define {<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>} @vector_deinterleave_nxv16i1_nxv80i1(<vscale x 80 x i1> %vec) nounwind {596; CHECK-LABEL: vector_deinterleave_nxv16i1_nxv80i1:597; CHECK:       # %bb.0:598; CHECK-NEXT:    addi sp, sp, -16599; CHECK-NEXT:    csrr a0, vlenb600; CHECK-NEXT:    slli a0, a0, 4601; CHECK-NEXT:    sub sp, sp, a0602; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, ma603; CHECK-NEXT:    vmv1r.v v9, v0604; CHECK-NEXT:    vmv.v.i v12, 0605; CHECK-NEXT:    csrr a0, vlenb606; CHECK-NEXT:    vmerge.vim v16, v12, 1, v0607; CHECK-NEXT:    srli a1, a0, 2608; CHECK-NEXT:    vsetvli a2, zero, e8, m1, ta, ma609; CHECK-NEXT:    vslidedown.vx v0, v0, a1610; CHECK-NEXT:    srli a2, a0, 1611; CHECK-NEXT:    vsetvli a3, zero, e8, m2, ta, ma612; CHECK-NEXT:    vmerge.vim v18, v12, 1, v0613; CHECK-NEXT:    vsetvli a3, zero, e8, m1, ta, ma614; CHECK-NEXT:    vslidedown.vx v0, v9, a2615; CHECK-NEXT:    sub a0, a0, a1616; CHECK-NEXT:    vsetvli a1, zero, e8, m2, ta, ma617; CHECK-NEXT:    vmerge.vim v20, v12, 1, v0618; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma619; CHECK-NEXT:    vslidedown.vx v0, v9, a0620; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, ma621; CHECK-NEXT:    vmerge.vim v14, v12, 1, v0622; CHECK-NEXT:    vmv1r.v v10, v15623; CHECK-NEXT:    vmv1r.v v0, v8624; CHECK-NEXT:    vmerge.vim v12, v12, 1, v0625; CHECK-NEXT:    vmv1r.v v11, v12626; CHECK-NEXT:    addi a0, sp, 16627; CHECK-NEXT:    vmv1r.v v8, v21628; CHECK-NEXT:    csrr a1, vlenb629; CHECK-NEXT:    slli a1, a1, 3630; CHECK-NEXT:    add a1, sp, a1631; CHECK-NEXT:    addi a1, a1, 16632; CHECK-NEXT:    vmv1r.v v9, v14633; CHECK-NEXT:    vs8r.v v16, (a0)634; CHECK-NEXT:    vmv1r.v v12, v13635; CHECK-NEXT:    vs8r.v v8, (a1)636; CHECK-NEXT:    vsetvli a2, zero, e8, m1, ta, ma637; CHECK-NEXT:    vlseg5e8.v v8, (a0)638; CHECK-NEXT:    vlseg5e8.v v14, (a1)639; CHECK-NEXT:    vmv2r.v v20, v8640; CHECK-NEXT:    vmv2r.v v22, v10641; CHECK-NEXT:    vmv1r.v v21, v14642; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, ma643; CHECK-NEXT:    vmsne.vi v0, v20, 0644; CHECK-NEXT:    vmv1r.v v14, v9645; CHECK-NEXT:    vmsne.vi v8, v14, 0646; CHECK-NEXT:    vmv1r.v v23, v16647; CHECK-NEXT:    vmsne.vi v9, v22, 0648; CHECK-NEXT:    vmv1r.v v16, v11649; CHECK-NEXT:    vmsne.vi v10, v16, 0650; CHECK-NEXT:    vmv1r.v v13, v18651; CHECK-NEXT:    vmsne.vi v11, v12, 0652; CHECK-NEXT:    csrr a0, vlenb653; CHECK-NEXT:    slli a0, a0, 4654; CHECK-NEXT:    add sp, sp, a0655; CHECK-NEXT:    addi sp, sp, 16656; CHECK-NEXT:    ret657  %retval = call {<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>} @llvm.vector.deinterleave5.nxv80i1(<vscale x 80 x i1> %vec)658  ret {<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>} %retval659}660 661 662define {<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>} @vector_deinterleave_nxv16i8_nxv80i8(<vscale x 80 x i8> %vec) nounwind {663; CHECK-LABEL: vector_deinterleave_nxv16i8_nxv80i8:664; CHECK:       # %bb.0:665; CHECK-NEXT:    addi sp, sp, -16666; CHECK-NEXT:    csrr a0, vlenb667; CHECK-NEXT:    slli a0, a0, 4668; CHECK-NEXT:    sub sp, sp, a0669; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma670; CHECK-NEXT:    vmv1r.v v26, v15671; CHECK-NEXT:    vmv1r.v v27, v16672; CHECK-NEXT:    addi a0, sp, 16673; CHECK-NEXT:    vmv1r.v v24, v13674; CHECK-NEXT:    csrr a1, vlenb675; CHECK-NEXT:    slli a1, a1, 3676; CHECK-NEXT:    add a1, sp, a1677; CHECK-NEXT:    addi a1, a1, 16678; CHECK-NEXT:    vmv1r.v v25, v14679; CHECK-NEXT:    vs8r.v v8, (a0)680; CHECK-NEXT:    vmv1r.v v28, v17681; CHECK-NEXT:    vs8r.v v24, (a1)682; CHECK-NEXT:    vlseg5e8.v v12, (a0)683; CHECK-NEXT:    vlseg5e8.v v18, (a1)684; CHECK-NEXT:    vmv2r.v v8, v12685; CHECK-NEXT:    vmv1r.v v9, v18686; CHECK-NEXT:    vmv1r.v v18, v13687; CHECK-NEXT:    vmv2r.v v12, v14688; CHECK-NEXT:    vmv1r.v v13, v20689; CHECK-NEXT:    vmv1r.v v20, v15690; CHECK-NEXT:    vmv1r.v v17, v22691; CHECK-NEXT:    vmv2r.v v10, v18692; CHECK-NEXT:    vmv2r.v v14, v20693; CHECK-NEXT:    csrr a0, vlenb694; CHECK-NEXT:    slli a0, a0, 4695; CHECK-NEXT:    add sp, sp, a0696; CHECK-NEXT:    addi sp, sp, 16697; CHECK-NEXT:    ret698  %retval = call {<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>} @llvm.vector.deinterleave5.nxv80i8(<vscale x 80 x i8> %vec)699  ret {<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>} %retval700}701 702 703define {<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>} @vector_deinterleave_nxv8i16_nxv40i16(<vscale x 40 x i16> %vec) nounwind {704; CHECK-LABEL: vector_deinterleave_nxv8i16_nxv40i16:705; CHECK:       # %bb.0:706; CHECK-NEXT:    addi sp, sp, -16707; CHECK-NEXT:    csrr a0, vlenb708; CHECK-NEXT:    slli a0, a0, 4709; CHECK-NEXT:    sub sp, sp, a0710; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma711; CHECK-NEXT:    vmv1r.v v26, v15712; CHECK-NEXT:    vmv1r.v v27, v16713; CHECK-NEXT:    addi a0, sp, 16714; CHECK-NEXT:    vmv1r.v v24, v13715; CHECK-NEXT:    csrr a1, vlenb716; CHECK-NEXT:    slli a1, a1, 3717; CHECK-NEXT:    add a1, sp, a1718; CHECK-NEXT:    addi a1, a1, 16719; CHECK-NEXT:    vmv1r.v v25, v14720; CHECK-NEXT:    vs8r.v v8, (a0)721; CHECK-NEXT:    vmv1r.v v28, v17722; CHECK-NEXT:    vs8r.v v24, (a1)723; CHECK-NEXT:    vlseg5e16.v v12, (a0)724; CHECK-NEXT:    vlseg5e16.v v18, (a1)725; CHECK-NEXT:    vmv2r.v v8, v12726; CHECK-NEXT:    vmv1r.v v9, v18727; CHECK-NEXT:    vmv1r.v v18, v13728; CHECK-NEXT:    vmv2r.v v12, v14729; CHECK-NEXT:    vmv1r.v v13, v20730; CHECK-NEXT:    vmv1r.v v20, v15731; CHECK-NEXT:    vmv1r.v v17, v22732; CHECK-NEXT:    vmv2r.v v10, v18733; CHECK-NEXT:    vmv2r.v v14, v20734; CHECK-NEXT:    csrr a0, vlenb735; CHECK-NEXT:    slli a0, a0, 4736; CHECK-NEXT:    add sp, sp, a0737; CHECK-NEXT:    addi sp, sp, 16738; CHECK-NEXT:    ret739  %retval = call {<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>} @llvm.vector.deinterleave5.nxv40i16(<vscale x 40 x i16> %vec)740  ret {<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>} %retval741}742 743 744define {<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>} @vector_deinterleave_nxv4i32_nxv20i32(<vscale x 20 x i32> %vec) nounwind {745; CHECK-LABEL: vector_deinterleave_nxv4i32_nxv20i32:746; CHECK:       # %bb.0:747; CHECK-NEXT:    addi sp, sp, -16748; CHECK-NEXT:    csrr a0, vlenb749; CHECK-NEXT:    slli a0, a0, 4750; CHECK-NEXT:    sub sp, sp, a0751; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma752; CHECK-NEXT:    vmv1r.v v26, v15753; CHECK-NEXT:    vmv1r.v v27, v16754; CHECK-NEXT:    addi a0, sp, 16755; CHECK-NEXT:    vmv1r.v v24, v13756; CHECK-NEXT:    csrr a1, vlenb757; CHECK-NEXT:    slli a1, a1, 3758; CHECK-NEXT:    add a1, sp, a1759; CHECK-NEXT:    addi a1, a1, 16760; CHECK-NEXT:    vmv1r.v v25, v14761; CHECK-NEXT:    vs8r.v v8, (a0)762; CHECK-NEXT:    vmv1r.v v28, v17763; CHECK-NEXT:    vs8r.v v24, (a1)764; CHECK-NEXT:    vlseg5e32.v v12, (a0)765; CHECK-NEXT:    vlseg5e32.v v18, (a1)766; CHECK-NEXT:    vmv2r.v v8, v12767; CHECK-NEXT:    vmv1r.v v9, v18768; CHECK-NEXT:    vmv1r.v v18, v13769; CHECK-NEXT:    vmv2r.v v12, v14770; CHECK-NEXT:    vmv1r.v v13, v20771; CHECK-NEXT:    vmv1r.v v20, v15772; CHECK-NEXT:    vmv1r.v v17, v22773; CHECK-NEXT:    vmv2r.v v10, v18774; CHECK-NEXT:    vmv2r.v v14, v20775; CHECK-NEXT:    csrr a0, vlenb776; CHECK-NEXT:    slli a0, a0, 4777; CHECK-NEXT:    add sp, sp, a0778; CHECK-NEXT:    addi sp, sp, 16779; CHECK-NEXT:    ret780  %retval = call {<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>} @llvm.vector.deinterleave5.nxv20i32(<vscale x 20 x i32> %vec)781  ret {<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>} %retval782}783 784 785define {<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>} @vector_deinterleave_nxv2i64_nxv10i64(<vscale x 10 x i64> %vec) nounwind {786; CHECK-LABEL: vector_deinterleave_nxv2i64_nxv10i64:787; CHECK:       # %bb.0:788; CHECK-NEXT:    addi sp, sp, -16789; CHECK-NEXT:    csrr a0, vlenb790; CHECK-NEXT:    slli a0, a0, 4791; CHECK-NEXT:    sub sp, sp, a0792; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, ma793; CHECK-NEXT:    vmv1r.v v26, v15794; CHECK-NEXT:    vmv1r.v v27, v16795; CHECK-NEXT:    addi a0, sp, 16796; CHECK-NEXT:    vmv1r.v v24, v13797; CHECK-NEXT:    csrr a1, vlenb798; CHECK-NEXT:    slli a1, a1, 3799; CHECK-NEXT:    add a1, sp, a1800; CHECK-NEXT:    addi a1, a1, 16801; CHECK-NEXT:    vmv1r.v v25, v14802; CHECK-NEXT:    vs8r.v v8, (a0)803; CHECK-NEXT:    vmv1r.v v28, v17804; CHECK-NEXT:    vs8r.v v24, (a1)805; CHECK-NEXT:    vlseg5e64.v v12, (a0)806; CHECK-NEXT:    vlseg5e64.v v18, (a1)807; CHECK-NEXT:    vmv2r.v v8, v12808; CHECK-NEXT:    vmv1r.v v9, v18809; CHECK-NEXT:    vmv1r.v v18, v13810; CHECK-NEXT:    vmv2r.v v12, v14811; CHECK-NEXT:    vmv1r.v v13, v20812; CHECK-NEXT:    vmv1r.v v20, v15813; CHECK-NEXT:    vmv1r.v v17, v22814; CHECK-NEXT:    vmv2r.v v10, v18815; CHECK-NEXT:    vmv2r.v v14, v20816; CHECK-NEXT:    csrr a0, vlenb817; CHECK-NEXT:    slli a0, a0, 4818; CHECK-NEXT:    add sp, sp, a0819; CHECK-NEXT:    addi sp, sp, 16820; CHECK-NEXT:    ret821  %retval = call {<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>} @llvm.vector.deinterleave5.nxv10i64(<vscale x 10 x i64> %vec)822  ret {<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>} %retval823}824 825define {<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>} @vector_deinterleave_nxv16i1_nxv96i1(<vscale x 96 x i1> %vec) nounwind {826; CHECK-LABEL: vector_deinterleave_nxv16i1_nxv96i1:827; CHECK:       # %bb.0:828; CHECK-NEXT:    addi sp, sp, -16829; CHECK-NEXT:    csrr a0, vlenb830; CHECK-NEXT:    slli a0, a0, 4831; CHECK-NEXT:    sub sp, sp, a0832; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, ma833; CHECK-NEXT:    vmv1r.v v9, v0834; CHECK-NEXT:    vmv.v.i v10, 0835; CHECK-NEXT:    csrr a0, vlenb836; CHECK-NEXT:    vmerge.vim v16, v10, 1, v0837; CHECK-NEXT:    srli a1, a0, 2838; CHECK-NEXT:    vsetvli a2, zero, e8, m1, ta, ma839; CHECK-NEXT:    vslidedown.vx v0, v0, a1840; CHECK-NEXT:    srli a2, a0, 1841; CHECK-NEXT:    vsetvli a3, zero, e8, m2, ta, ma842; CHECK-NEXT:    vmerge.vim v18, v10, 1, v0843; CHECK-NEXT:    vsetvli a3, zero, e8, m1, ta, ma844; CHECK-NEXT:    vslidedown.vx v0, v9, a2845; CHECK-NEXT:    addi a2, sp, 16846; CHECK-NEXT:    sub a0, a0, a1847; CHECK-NEXT:    vsetvli a3, zero, e8, m2, ta, ma848; CHECK-NEXT:    vmerge.vim v20, v10, 1, v0849; CHECK-NEXT:    vmv1r.v v0, v8850; CHECK-NEXT:    vmerge.vim v26, v10, 1, v0851; CHECK-NEXT:    vsetvli a3, zero, e8, m1, ta, ma852; CHECK-NEXT:    vslidedown.vx v0, v9, a0853; CHECK-NEXT:    vs8r.v v16, (a2)854; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, ma855; CHECK-NEXT:    vmerge.vim v24, v10, 1, v0856; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma857; CHECK-NEXT:    vslidedown.vx v0, v8, a1858; CHECK-NEXT:    csrr a0, vlenb859; CHECK-NEXT:    slli a0, a0, 3860; CHECK-NEXT:    add a0, sp, a0861; CHECK-NEXT:    addi a0, a0, 16862; CHECK-NEXT:    vsetvli a1, zero, e8, m2, ta, ma863; CHECK-NEXT:    vmerge.vim v28, v10, 1, v0864; CHECK-NEXT:    vs8r.v v24, (a0)865; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma866; CHECK-NEXT:    vlseg6e8.v v16, (a2)867; CHECK-NEXT:    vlseg6e8.v v10, (a0)868; CHECK-NEXT:    vmv2r.v v8, v16869; CHECK-NEXT:    vmv2r.v v22, v18870; CHECK-NEXT:    vmv2r.v v24, v20871; CHECK-NEXT:    vmv1r.v v9, v10872; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, ma873; CHECK-NEXT:    vmsne.vi v0, v8, 0874; CHECK-NEXT:    vmv1r.v v10, v17875; CHECK-NEXT:    vmsne.vi v8, v10, 0876; CHECK-NEXT:    vmv1r.v v23, v12877; CHECK-NEXT:    vmsne.vi v9, v22, 0878; CHECK-NEXT:    vmv1r.v v12, v19879; CHECK-NEXT:    vmsne.vi v10, v12, 0880; CHECK-NEXT:    vmv1r.v v25, v14881; CHECK-NEXT:    vmsne.vi v11, v24, 0882; CHECK-NEXT:    vmv1r.v v14, v21883; CHECK-NEXT:    vmsne.vi v12, v14, 0884; CHECK-NEXT:    csrr a0, vlenb885; CHECK-NEXT:    slli a0, a0, 4886; CHECK-NEXT:    add sp, sp, a0887; CHECK-NEXT:    addi sp, sp, 16888; CHECK-NEXT:    ret889  %retval = call {<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>} @llvm.vector.deinterleave6.nxv96i1(<vscale x 96 x i1> %vec)890  ret {<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>} %retval891}892 893define {<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>} @vector_deinterleave_nxv16i8_nxv96i8(<vscale x 96 x i8> %vec) nounwind {894; CHECK-LABEL: vector_deinterleave_nxv16i8_nxv96i8:895; CHECK:       # %bb.0:896; CHECK-NEXT:    addi sp, sp, -16897; CHECK-NEXT:    csrr a0, vlenb898; CHECK-NEXT:    slli a0, a0, 4899; CHECK-NEXT:    sub sp, sp, a0900; CHECK-NEXT:    addi a0, sp, 16901; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma902; CHECK-NEXT:    vmv2r.v v28, v18903; CHECK-NEXT:    csrr a1, vlenb904; CHECK-NEXT:    slli a1, a1, 3905; CHECK-NEXT:    add a1, sp, a1906; CHECK-NEXT:    addi a1, a1, 16907; CHECK-NEXT:    vmv2r.v v24, v14908; CHECK-NEXT:    vs8r.v v8, (a0)909; CHECK-NEXT:    vmv2r.v v26, v16910; CHECK-NEXT:    vs8r.v v24, (a1)911; CHECK-NEXT:    vlseg6e8.v v24, (a0)912; CHECK-NEXT:    vlseg6e8.v v18, (a1)913; CHECK-NEXT:    vmv2r.v v8, v24914; CHECK-NEXT:    vmv1r.v v9, v18915; CHECK-NEXT:    vmv1r.v v18, v25916; CHECK-NEXT:    vmv2r.v v12, v26917; CHECK-NEXT:    vmv1r.v v13, v20918; CHECK-NEXT:    vmv1r.v v20, v27919; CHECK-NEXT:    vmv2r.v v16, v28920; CHECK-NEXT:    vmv1r.v v17, v22921; CHECK-NEXT:    vmv1r.v v22, v29922; CHECK-NEXT:    vmv2r.v v10, v18923; CHECK-NEXT:    vmv2r.v v14, v20924; CHECK-NEXT:    vmv2r.v v18, v22925; CHECK-NEXT:    csrr a0, vlenb926; CHECK-NEXT:    slli a0, a0, 4927; CHECK-NEXT:    add sp, sp, a0928; CHECK-NEXT:    addi sp, sp, 16929; CHECK-NEXT:    ret930  %retval = call {<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>} @llvm.vector.deinterleave6.nxv96i8(<vscale x 96 x i8> %vec)931  ret {<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>} %retval932}933 934define {<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>} @vector_deinterleave_nxv8i16_nxv48i16(<vscale x 48 x i16> %vec) nounwind {935; CHECK-LABEL: vector_deinterleave_nxv8i16_nxv48i16:936; CHECK:       # %bb.0:937; CHECK-NEXT:    addi sp, sp, -16938; CHECK-NEXT:    csrr a0, vlenb939; CHECK-NEXT:    slli a0, a0, 4940; CHECK-NEXT:    sub sp, sp, a0941; CHECK-NEXT:    addi a0, sp, 16942; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, ma943; CHECK-NEXT:    vmv2r.v v28, v18944; CHECK-NEXT:    csrr a1, vlenb945; CHECK-NEXT:    slli a1, a1, 3946; CHECK-NEXT:    add a1, sp, a1947; CHECK-NEXT:    addi a1, a1, 16948; CHECK-NEXT:    vmv2r.v v24, v14949; CHECK-NEXT:    vs8r.v v8, (a0)950; CHECK-NEXT:    vmv2r.v v26, v16951; CHECK-NEXT:    vs8r.v v24, (a1)952; CHECK-NEXT:    vlseg6e16.v v24, (a0)953; CHECK-NEXT:    vlseg6e16.v v18, (a1)954; CHECK-NEXT:    vmv2r.v v8, v24955; CHECK-NEXT:    vmv1r.v v9, v18956; CHECK-NEXT:    vmv1r.v v18, v25957; CHECK-NEXT:    vmv2r.v v12, v26958; CHECK-NEXT:    vmv1r.v v13, v20959; CHECK-NEXT:    vmv1r.v v20, v27960; CHECK-NEXT:    vmv2r.v v16, v28961; CHECK-NEXT:    vmv1r.v v17, v22962; CHECK-NEXT:    vmv1r.v v22, v29963; CHECK-NEXT:    vmv2r.v v10, v18964; CHECK-NEXT:    vmv2r.v v14, v20965; CHECK-NEXT:    vmv2r.v v18, v22966; CHECK-NEXT:    csrr a0, vlenb967; CHECK-NEXT:    slli a0, a0, 4968; CHECK-NEXT:    add sp, sp, a0969; CHECK-NEXT:    addi sp, sp, 16970; CHECK-NEXT:    ret971  %retval = call {<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>} @llvm.vector.deinterleave6.nxv48i16(<vscale x 48 x i16> %vec)972  ret {<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>} %retval973}974 975define {<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>} @vector_deinterleave_nxv4i32_nxv24i32(<vscale x 24 x i32> %vec) nounwind {976; CHECK-LABEL: vector_deinterleave_nxv4i32_nxv24i32:977; CHECK:       # %bb.0:978; CHECK-NEXT:    addi sp, sp, -16979; CHECK-NEXT:    csrr a0, vlenb980; CHECK-NEXT:    slli a0, a0, 4981; CHECK-NEXT:    sub sp, sp, a0982; CHECK-NEXT:    addi a0, sp, 16983; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, ma984; CHECK-NEXT:    vmv2r.v v28, v18985; CHECK-NEXT:    csrr a1, vlenb986; CHECK-NEXT:    slli a1, a1, 3987; CHECK-NEXT:    add a1, sp, a1988; CHECK-NEXT:    addi a1, a1, 16989; CHECK-NEXT:    vmv2r.v v24, v14990; CHECK-NEXT:    vs8r.v v8, (a0)991; CHECK-NEXT:    vmv2r.v v26, v16992; CHECK-NEXT:    vs8r.v v24, (a1)993; CHECK-NEXT:    vlseg6e32.v v24, (a0)994; CHECK-NEXT:    vlseg6e32.v v18, (a1)995; CHECK-NEXT:    vmv2r.v v8, v24996; CHECK-NEXT:    vmv1r.v v9, v18997; CHECK-NEXT:    vmv1r.v v18, v25998; CHECK-NEXT:    vmv2r.v v12, v26999; CHECK-NEXT:    vmv1r.v v13, v201000; CHECK-NEXT:    vmv1r.v v20, v271001; CHECK-NEXT:    vmv2r.v v16, v281002; CHECK-NEXT:    vmv1r.v v17, v221003; CHECK-NEXT:    vmv1r.v v22, v291004; CHECK-NEXT:    vmv2r.v v10, v181005; CHECK-NEXT:    vmv2r.v v14, v201006; CHECK-NEXT:    vmv2r.v v18, v221007; CHECK-NEXT:    csrr a0, vlenb1008; CHECK-NEXT:    slli a0, a0, 41009; CHECK-NEXT:    add sp, sp, a01010; CHECK-NEXT:    addi sp, sp, 161011; CHECK-NEXT:    ret1012  %retval = call {<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>} @llvm.vector.deinterleave6.nxv24i32(<vscale x 24 x i32> %vec)1013  ret {<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>} %retval1014}1015 1016define {<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>} @vector_deinterleave_nxv2i64_nxv12i64(<vscale x 12 x i64> %vec) nounwind {1017; CHECK-LABEL: vector_deinterleave_nxv2i64_nxv12i64:1018; CHECK:       # %bb.0:1019; CHECK-NEXT:    addi sp, sp, -161020; CHECK-NEXT:    csrr a0, vlenb1021; CHECK-NEXT:    slli a0, a0, 41022; CHECK-NEXT:    sub sp, sp, a01023; CHECK-NEXT:    addi a0, sp, 161024; CHECK-NEXT:    vsetvli a1, zero, e64, m1, ta, ma1025; CHECK-NEXT:    vmv2r.v v28, v181026; CHECK-NEXT:    csrr a1, vlenb1027; CHECK-NEXT:    slli a1, a1, 31028; CHECK-NEXT:    add a1, sp, a11029; CHECK-NEXT:    addi a1, a1, 161030; CHECK-NEXT:    vmv2r.v v24, v141031; CHECK-NEXT:    vs8r.v v8, (a0)1032; CHECK-NEXT:    vmv2r.v v26, v161033; CHECK-NEXT:    vs8r.v v24, (a1)1034; CHECK-NEXT:    vlseg6e64.v v24, (a0)1035; CHECK-NEXT:    vlseg6e64.v v18, (a1)1036; CHECK-NEXT:    vmv2r.v v8, v241037; CHECK-NEXT:    vmv1r.v v9, v181038; CHECK-NEXT:    vmv1r.v v18, v251039; CHECK-NEXT:    vmv2r.v v12, v261040; CHECK-NEXT:    vmv1r.v v13, v201041; CHECK-NEXT:    vmv1r.v v20, v271042; CHECK-NEXT:    vmv2r.v v16, v281043; CHECK-NEXT:    vmv1r.v v17, v221044; CHECK-NEXT:    vmv1r.v v22, v291045; CHECK-NEXT:    vmv2r.v v10, v181046; CHECK-NEXT:    vmv2r.v v14, v201047; CHECK-NEXT:    vmv2r.v v18, v221048; CHECK-NEXT:    csrr a0, vlenb1049; CHECK-NEXT:    slli a0, a0, 41050; CHECK-NEXT:    add sp, sp, a01051; CHECK-NEXT:    addi sp, sp, 161052; CHECK-NEXT:    ret1053  %retval = call {<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>} @llvm.vector.deinterleave6.nxv12i64(<vscale x 12 x i64> %vec)1054  ret {<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>} %retval1055}1056 1057define {<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>} @vector_deinterleave_nxv16i1_nxv112i1(<vscale x 112 x i1> %vec) nounwind {1058; CHECK-LABEL: vector_deinterleave_nxv16i1_nxv112i1:1059; CHECK:       # %bb.0:1060; CHECK-NEXT:    addi sp, sp, -161061; CHECK-NEXT:    csrr a0, vlenb1062; CHECK-NEXT:    slli a0, a0, 41063; CHECK-NEXT:    sub sp, sp, a01064; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, ma1065; CHECK-NEXT:    vmv1r.v v9, v01066; CHECK-NEXT:    csrr a0, vlenb1067; CHECK-NEXT:    vmv.v.i v12, 01068; CHECK-NEXT:    srli a1, a0, 21069; CHECK-NEXT:    sub a2, a0, a11070; CHECK-NEXT:    vsetvli a3, zero, e8, m1, ta, ma1071; CHECK-NEXT:    vslidedown.vx v0, v0, a21072; CHECK-NEXT:    srli a0, a0, 11073; CHECK-NEXT:    vsetvli a2, zero, e8, m2, ta, ma1074; CHECK-NEXT:    vmerge.vim v22, v12, 1, v01075; CHECK-NEXT:    vsetvli a2, zero, e8, m1, ta, ma1076; CHECK-NEXT:    vslidedown.vx v0, v9, a01077; CHECK-NEXT:    vsetvli a2, zero, e8, m2, ta, ma1078; CHECK-NEXT:    vmerge.vim v20, v12, 1, v01079; CHECK-NEXT:    vmv1r.v v0, v91080; CHECK-NEXT:    vmerge.vim v16, v12, 1, v01081; CHECK-NEXT:    vsetvli a2, zero, e8, m1, ta, ma1082; CHECK-NEXT:    vslidedown.vx v0, v9, a11083; CHECK-NEXT:    vsetvli a2, zero, e8, m2, ta, ma1084; CHECK-NEXT:    vmerge.vim v18, v12, 1, v01085; CHECK-NEXT:    vmv1r.v v0, v81086; CHECK-NEXT:    vmerge.vim v14, v12, 1, v01087; CHECK-NEXT:    vsetvli a2, zero, e8, m1, ta, ma1088; CHECK-NEXT:    vslidedown.vx v0, v8, a11089; CHECK-NEXT:    vmv1r.v v10, v151090; CHECK-NEXT:    vsetvli a1, zero, e8, m2, ta, ma1091; CHECK-NEXT:    vmerge.vim v24, v12, 1, v01092; CHECK-NEXT:    vmv1r.v v11, v241093; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma1094; CHECK-NEXT:    vslidedown.vx v0, v8, a01095; CHECK-NEXT:    vmv1r.v v8, v231096; CHECK-NEXT:    addi a0, sp, 161097; CHECK-NEXT:    vmv1r.v v9, v141098; CHECK-NEXT:    vsetvli a1, zero, e8, m2, ta, ma1099; CHECK-NEXT:    vmerge.vim v14, v12, 1, v01100; CHECK-NEXT:    vmv1r.v v12, v251101; CHECK-NEXT:    csrr a1, vlenb1102; CHECK-NEXT:    slli a1, a1, 31103; CHECK-NEXT:    add a1, sp, a11104; CHECK-NEXT:    addi a1, a1, 161105; CHECK-NEXT:    vmv1r.v v13, v141106; CHECK-NEXT:    vs8r.v v16, (a0)1107; CHECK-NEXT:    vmv1r.v v14, v151108; CHECK-NEXT:    vs8r.v v8, (a1)1109; CHECK-NEXT:    vsetvli a2, zero, e8, m1, ta, ma1110; CHECK-NEXT:    vlseg7e8.v v8, (a0)1111; CHECK-NEXT:    vlseg7e8.v v16, (a1)1112; CHECK-NEXT:    vmv2r.v v24, v81113; CHECK-NEXT:    vmv2r.v v26, v101114; CHECK-NEXT:    vmv2r.v v28, v121115; CHECK-NEXT:    vmv1r.v v25, v161116; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, ma1117; CHECK-NEXT:    vmsne.vi v0, v24, 01118; CHECK-NEXT:    vmv1r.v v16, v91119; CHECK-NEXT:    vmsne.vi v8, v16, 01120; CHECK-NEXT:    vmv1r.v v27, v181121; CHECK-NEXT:    vmsne.vi v9, v26, 01122; CHECK-NEXT:    vmv1r.v v18, v111123; CHECK-NEXT:    vmsne.vi v10, v18, 01124; CHECK-NEXT:    vmv1r.v v29, v201125; CHECK-NEXT:    vmsne.vi v11, v28, 01126; CHECK-NEXT:    vmv1r.v v20, v131127; CHECK-NEXT:    vmsne.vi v12, v20, 01128; CHECK-NEXT:    vmv1r.v v15, v221129; CHECK-NEXT:    vmsne.vi v13, v14, 01130; CHECK-NEXT:    csrr a0, vlenb1131; CHECK-NEXT:    slli a0, a0, 41132; CHECK-NEXT:    add sp, sp, a01133; CHECK-NEXT:    addi sp, sp, 161134; CHECK-NEXT:    ret1135  %retval = call {<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>} @llvm.vector.deinterleave7.nxv112i1(<vscale x 112 x i1> %vec)1136  ret {<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>} %retval1137}1138 1139 1140define {<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>} @vector_deinterleave_nxv16i8_nxv112i8(<vscale x 112 x i8> %vec) nounwind {1141; CHECK-LABEL: vector_deinterleave_nxv16i8_nxv112i8:1142; CHECK:       # %bb.0:1143; CHECK-NEXT:    addi sp, sp, -161144; CHECK-NEXT:    csrr a0, vlenb1145; CHECK-NEXT:    slli a0, a0, 41146; CHECK-NEXT:    sub sp, sp, a01147; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma1148; CHECK-NEXT:    vmv1r.v v30, v211149; CHECK-NEXT:    vmv1r.v v28, v191150; CHECK-NEXT:    vmv1r.v v29, v201151; CHECK-NEXT:    vmv1r.v v26, v171152; CHECK-NEXT:    addi a0, sp, 161153; CHECK-NEXT:    vmv1r.v v27, v181154; CHECK-NEXT:    csrr a1, vlenb1155; CHECK-NEXT:    slli a1, a1, 31156; CHECK-NEXT:    add a1, sp, a11157; CHECK-NEXT:    addi a1, a1, 161158; CHECK-NEXT:    vmv1r.v v24, v151159; CHECK-NEXT:    vs8r.v v8, (a0)1160; CHECK-NEXT:    vmv1r.v v25, v161161; CHECK-NEXT:    vs8r.v v24, (a1)1162; CHECK-NEXT:    vlseg7e8.v v14, (a0)1163; CHECK-NEXT:    vlseg7e8.v v22, (a1)1164; CHECK-NEXT:    vmv2r.v v8, v141165; CHECK-NEXT:    vmv1r.v v9, v221166; CHECK-NEXT:    vmv1r.v v22, v151167; CHECK-NEXT:    vmv2r.v v12, v161168; CHECK-NEXT:    vmv1r.v v13, v241169; CHECK-NEXT:    vmv1r.v v24, v171170; CHECK-NEXT:    vmv2r.v v16, v181171; CHECK-NEXT:    vmv1r.v v17, v261172; CHECK-NEXT:    vmv1r.v v26, v191173; CHECK-NEXT:    vmv1r.v v21, v281174; CHECK-NEXT:    vmv2r.v v10, v221175; CHECK-NEXT:    vmv2r.v v14, v241176; CHECK-NEXT:    vmv2r.v v18, v261177; CHECK-NEXT:    csrr a0, vlenb1178; CHECK-NEXT:    slli a0, a0, 41179; CHECK-NEXT:    add sp, sp, a01180; CHECK-NEXT:    addi sp, sp, 161181; CHECK-NEXT:    ret1182  %retval = call {<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>} @llvm.vector.deinterleave7.nxv112i8(<vscale x 112 x i8> %vec)1183  ret {<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>} %retval1184}1185 1186 1187define {<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>} @vector_deinterleave_nxv8i16_nxv56i16(<vscale x 56 x i16> %vec) nounwind {1188; CHECK-LABEL: vector_deinterleave_nxv8i16_nxv56i16:1189; CHECK:       # %bb.0:1190; CHECK-NEXT:    addi sp, sp, -161191; CHECK-NEXT:    csrr a0, vlenb1192; CHECK-NEXT:    slli a0, a0, 41193; CHECK-NEXT:    sub sp, sp, a01194; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma1195; CHECK-NEXT:    vmv1r.v v30, v211196; CHECK-NEXT:    vmv1r.v v28, v191197; CHECK-NEXT:    vmv1r.v v29, v201198; CHECK-NEXT:    vmv1r.v v26, v171199; CHECK-NEXT:    addi a0, sp, 161200; CHECK-NEXT:    vmv1r.v v27, v181201; CHECK-NEXT:    csrr a1, vlenb1202; CHECK-NEXT:    slli a1, a1, 31203; CHECK-NEXT:    add a1, sp, a11204; CHECK-NEXT:    addi a1, a1, 161205; CHECK-NEXT:    vmv1r.v v24, v151206; CHECK-NEXT:    vs8r.v v8, (a0)1207; CHECK-NEXT:    vmv1r.v v25, v161208; CHECK-NEXT:    vs8r.v v24, (a1)1209; CHECK-NEXT:    vlseg7e16.v v14, (a0)1210; CHECK-NEXT:    vlseg7e16.v v22, (a1)1211; CHECK-NEXT:    vmv2r.v v8, v141212; CHECK-NEXT:    vmv1r.v v9, v221213; CHECK-NEXT:    vmv1r.v v22, v151214; CHECK-NEXT:    vmv2r.v v12, v161215; CHECK-NEXT:    vmv1r.v v13, v241216; CHECK-NEXT:    vmv1r.v v24, v171217; CHECK-NEXT:    vmv2r.v v16, v181218; CHECK-NEXT:    vmv1r.v v17, v261219; CHECK-NEXT:    vmv1r.v v26, v191220; CHECK-NEXT:    vmv1r.v v21, v281221; CHECK-NEXT:    vmv2r.v v10, v221222; CHECK-NEXT:    vmv2r.v v14, v241223; CHECK-NEXT:    vmv2r.v v18, v261224; CHECK-NEXT:    csrr a0, vlenb1225; CHECK-NEXT:    slli a0, a0, 41226; CHECK-NEXT:    add sp, sp, a01227; CHECK-NEXT:    addi sp, sp, 161228; CHECK-NEXT:    ret1229  %retval = call {<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>} @llvm.vector.deinterleave7.nxv56i16(<vscale x 56 x i16> %vec)1230  ret {<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>} %retval1231}1232 1233 1234define {<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>} @vector_deinterleave_nxv4i32_nxv28i32(<vscale x 28 x i32> %vec) nounwind {1235; CHECK-LABEL: vector_deinterleave_nxv4i32_nxv28i32:1236; CHECK:       # %bb.0:1237; CHECK-NEXT:    addi sp, sp, -161238; CHECK-NEXT:    csrr a0, vlenb1239; CHECK-NEXT:    slli a0, a0, 41240; CHECK-NEXT:    sub sp, sp, a01241; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma1242; CHECK-NEXT:    vmv1r.v v30, v211243; CHECK-NEXT:    vmv1r.v v28, v191244; CHECK-NEXT:    vmv1r.v v29, v201245; CHECK-NEXT:    vmv1r.v v26, v171246; CHECK-NEXT:    addi a0, sp, 161247; CHECK-NEXT:    vmv1r.v v27, v181248; CHECK-NEXT:    csrr a1, vlenb1249; CHECK-NEXT:    slli a1, a1, 31250; CHECK-NEXT:    add a1, sp, a11251; CHECK-NEXT:    addi a1, a1, 161252; CHECK-NEXT:    vmv1r.v v24, v151253; CHECK-NEXT:    vs8r.v v8, (a0)1254; CHECK-NEXT:    vmv1r.v v25, v161255; CHECK-NEXT:    vs8r.v v24, (a1)1256; CHECK-NEXT:    vlseg7e32.v v14, (a0)1257; CHECK-NEXT:    vlseg7e32.v v22, (a1)1258; CHECK-NEXT:    vmv2r.v v8, v141259; CHECK-NEXT:    vmv1r.v v9, v221260; CHECK-NEXT:    vmv1r.v v22, v151261; CHECK-NEXT:    vmv2r.v v12, v161262; CHECK-NEXT:    vmv1r.v v13, v241263; CHECK-NEXT:    vmv1r.v v24, v171264; CHECK-NEXT:    vmv2r.v v16, v181265; CHECK-NEXT:    vmv1r.v v17, v261266; CHECK-NEXT:    vmv1r.v v26, v191267; CHECK-NEXT:    vmv1r.v v21, v281268; CHECK-NEXT:    vmv2r.v v10, v221269; CHECK-NEXT:    vmv2r.v v14, v241270; CHECK-NEXT:    vmv2r.v v18, v261271; CHECK-NEXT:    csrr a0, vlenb1272; CHECK-NEXT:    slli a0, a0, 41273; CHECK-NEXT:    add sp, sp, a01274; CHECK-NEXT:    addi sp, sp, 161275; CHECK-NEXT:    ret1276  %retval = call {<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>} @llvm.vector.deinterleave7.nxv28i32(<vscale x 28 x i32> %vec)1277  ret {<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>} %retval1278}1279 1280 1281define {<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>} @vector_deinterleave_nxv2i64_nxv14i64(<vscale x 14 x i64> %vec) nounwind {1282; CHECK-LABEL: vector_deinterleave_nxv2i64_nxv14i64:1283; CHECK:       # %bb.0:1284; CHECK-NEXT:    addi sp, sp, -161285; CHECK-NEXT:    csrr a0, vlenb1286; CHECK-NEXT:    slli a0, a0, 41287; CHECK-NEXT:    sub sp, sp, a01288; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, ma1289; CHECK-NEXT:    vmv1r.v v30, v211290; CHECK-NEXT:    vmv1r.v v28, v191291; CHECK-NEXT:    vmv1r.v v29, v201292; CHECK-NEXT:    vmv1r.v v26, v171293; CHECK-NEXT:    addi a0, sp, 161294; CHECK-NEXT:    vmv1r.v v27, v181295; CHECK-NEXT:    csrr a1, vlenb1296; CHECK-NEXT:    slli a1, a1, 31297; CHECK-NEXT:    add a1, sp, a11298; CHECK-NEXT:    addi a1, a1, 161299; CHECK-NEXT:    vmv1r.v v24, v151300; CHECK-NEXT:    vs8r.v v8, (a0)1301; CHECK-NEXT:    vmv1r.v v25, v161302; CHECK-NEXT:    vs8r.v v24, (a1)1303; CHECK-NEXT:    vlseg7e64.v v14, (a0)1304; CHECK-NEXT:    vlseg7e64.v v22, (a1)1305; CHECK-NEXT:    vmv2r.v v8, v141306; CHECK-NEXT:    vmv1r.v v9, v221307; CHECK-NEXT:    vmv1r.v v22, v151308; CHECK-NEXT:    vmv2r.v v12, v161309; CHECK-NEXT:    vmv1r.v v13, v241310; CHECK-NEXT:    vmv1r.v v24, v171311; CHECK-NEXT:    vmv2r.v v16, v181312; CHECK-NEXT:    vmv1r.v v17, v261313; CHECK-NEXT:    vmv1r.v v26, v191314; CHECK-NEXT:    vmv1r.v v21, v281315; CHECK-NEXT:    vmv2r.v v10, v221316; CHECK-NEXT:    vmv2r.v v14, v241317; CHECK-NEXT:    vmv2r.v v18, v261318; CHECK-NEXT:    csrr a0, vlenb1319; CHECK-NEXT:    slli a0, a0, 41320; CHECK-NEXT:    add sp, sp, a01321; CHECK-NEXT:    addi sp, sp, 161322; CHECK-NEXT:    ret1323  %retval = call {<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>} @llvm.vector.deinterleave7.nxv14i64(<vscale x 14 x i64> %vec)1324  ret {<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>} %retval1325}1326 1327define {<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>} @vector_deinterleave_nxv16i1_nxv128i1(<vscale x 128 x i1> %vec) nounwind {1328; CHECK-LABEL: vector_deinterleave_nxv16i1_nxv128i1:1329; CHECK:       # %bb.0:1330; CHECK-NEXT:    addi sp, sp, -161331; CHECK-NEXT:    csrr a0, vlenb1332; CHECK-NEXT:    slli a0, a0, 41333; CHECK-NEXT:    sub sp, sp, a01334; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, ma1335; CHECK-NEXT:    vmv1r.v v9, v01336; CHECK-NEXT:    csrr a0, vlenb1337; CHECK-NEXT:    vmv.v.i v10, 01338; CHECK-NEXT:    srli a1, a0, 21339; CHECK-NEXT:    sub a2, a0, a11340; CHECK-NEXT:    vsetvli a3, zero, e8, m1, ta, ma1341; CHECK-NEXT:    vslidedown.vx v0, v0, a21342; CHECK-NEXT:    srli a0, a0, 11343; CHECK-NEXT:    vsetvli a3, zero, e8, m2, ta, ma1344; CHECK-NEXT:    vmerge.vim v22, v10, 1, v01345; CHECK-NEXT:    vsetvli a3, zero, e8, m1, ta, ma1346; CHECK-NEXT:    vslidedown.vx v0, v9, a01347; CHECK-NEXT:    vsetvli a3, zero, e8, m2, ta, ma1348; CHECK-NEXT:    vmerge.vim v20, v10, 1, v01349; CHECK-NEXT:    vmv1r.v v0, v91350; CHECK-NEXT:    vmerge.vim v16, v10, 1, v01351; CHECK-NEXT:    vsetvli a3, zero, e8, m1, ta, ma1352; CHECK-NEXT:    vslidedown.vx v0, v9, a11353; CHECK-NEXT:    vsetvli a3, zero, e8, m2, ta, ma1354; CHECK-NEXT:    vmerge.vim v18, v10, 1, v01355; CHECK-NEXT:    vsetvli a3, zero, e8, m1, ta, ma1356; CHECK-NEXT:    vslidedown.vx v0, v8, a21357; CHECK-NEXT:    addi a2, sp, 161358; CHECK-NEXT:    vsetvli a3, zero, e8, m2, ta, ma1359; CHECK-NEXT:    vmerge.vim v30, v10, 1, v01360; CHECK-NEXT:    vsetvli a3, zero, e8, m1, ta, ma1361; CHECK-NEXT:    vslidedown.vx v0, v8, a01362; CHECK-NEXT:    vs8r.v v16, (a2)1363; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, ma1364; CHECK-NEXT:    vmerge.vim v28, v10, 1, v01365; CHECK-NEXT:    vmv1r.v v0, v81366; CHECK-NEXT:    vmerge.vim v24, v10, 1, v01367; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma1368; CHECK-NEXT:    vslidedown.vx v0, v8, a11369; CHECK-NEXT:    csrr a0, vlenb1370; CHECK-NEXT:    slli a0, a0, 31371; CHECK-NEXT:    add a0, sp, a01372; CHECK-NEXT:    addi a0, a0, 161373; CHECK-NEXT:    vsetvli a1, zero, e8, m2, ta, ma1374; CHECK-NEXT:    vmerge.vim v26, v10, 1, v01375; CHECK-NEXT:    vs8r.v v24, (a0)1376; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma1377; CHECK-NEXT:    vlseg8e8.v v18, (a2)1378; CHECK-NEXT:    vlseg8e8.v v10, (a0)1379; CHECK-NEXT:    vmv2r.v v8, v181380; CHECK-NEXT:    vmv2r.v v26, v201381; CHECK-NEXT:    vmv2r.v v28, v221382; CHECK-NEXT:    vmv2r.v v30, v241383; CHECK-NEXT:    vmv1r.v v9, v101384; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, ma1385; CHECK-NEXT:    vmsne.vi v0, v8, 01386; CHECK-NEXT:    vmv1r.v v10, v191387; CHECK-NEXT:    vmsne.vi v8, v10, 01388; CHECK-NEXT:    vmv1r.v v27, v121389; CHECK-NEXT:    vmsne.vi v9, v26, 01390; CHECK-NEXT:    vmv1r.v v12, v211391; CHECK-NEXT:    vmsne.vi v10, v12, 01392; CHECK-NEXT:    vmv1r.v v29, v141393; CHECK-NEXT:    vmsne.vi v11, v28, 01394; CHECK-NEXT:    vmv1r.v v14, v231395; CHECK-NEXT:    vmsne.vi v12, v14, 01396; CHECK-NEXT:    vmv1r.v v31, v161397; CHECK-NEXT:    vmsne.vi v13, v30, 01398; CHECK-NEXT:    vmv1r.v v16, v251399; CHECK-NEXT:    vmsne.vi v14, v16, 01400; CHECK-NEXT:    csrr a0, vlenb1401; CHECK-NEXT:    slli a0, a0, 41402; CHECK-NEXT:    add sp, sp, a01403; CHECK-NEXT:    addi sp, sp, 161404; CHECK-NEXT:    ret1405  %retval = call {<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>} @llvm.vector.deinterleave8.nxv128i1(<vscale x 128 x i1> %vec)1406  ret {<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>} %retval1407}1408 1409define {<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>} @vector_deinterleave_nxv16i8_nxv128i8(<vscale x 128 x i8> %vec) nounwind {1410; CHECK-LABEL: vector_deinterleave_nxv16i8_nxv128i8:1411; CHECK:       # %bb.0:1412; CHECK-NEXT:    addi sp, sp, -161413; CHECK-NEXT:    csrr a0, vlenb1414; CHECK-NEXT:    slli a0, a0, 41415; CHECK-NEXT:    sub sp, sp, a01416; CHECK-NEXT:    addi a0, sp, 161417; CHECK-NEXT:    csrr a1, vlenb1418; CHECK-NEXT:    slli a1, a1, 31419; CHECK-NEXT:    add a1, sp, a11420; CHECK-NEXT:    addi a1, a1, 161421; CHECK-NEXT:    vs8r.v v8, (a0)1422; CHECK-NEXT:    vs8r.v v16, (a1)1423; CHECK-NEXT:    vsetvli a2, zero, e8, m1, ta, ma1424; CHECK-NEXT:    vlseg8e8.v v0, (a0)1425; CHECK-NEXT:    vlseg8e8.v v22, (a1)1426; CHECK-NEXT:    vmv2r.v v8, v01427; CHECK-NEXT:    vmv1r.v v9, v221428; CHECK-NEXT:    vmv1r.v v22, v11429; CHECK-NEXT:    vmv2r.v v12, v21430; CHECK-NEXT:    vmv1r.v v13, v241431; CHECK-NEXT:    vmv1r.v v24, v31432; CHECK-NEXT:    vmv2r.v v16, v41433; CHECK-NEXT:    vmv1r.v v17, v261434; CHECK-NEXT:    vmv1r.v v26, v51435; CHECK-NEXT:    vmv2r.v v20, v61436; CHECK-NEXT:    vmv1r.v v21, v281437; CHECK-NEXT:    vmv1r.v v28, v71438; CHECK-NEXT:    vmv2r.v v10, v221439; CHECK-NEXT:    vmv2r.v v14, v241440; CHECK-NEXT:    vmv2r.v v18, v261441; CHECK-NEXT:    vmv2r.v v22, v281442; CHECK-NEXT:    csrr a0, vlenb1443; CHECK-NEXT:    slli a0, a0, 41444; CHECK-NEXT:    add sp, sp, a01445; CHECK-NEXT:    addi sp, sp, 161446; CHECK-NEXT:    ret1447  %retval = call {<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>} @llvm.vector.deinterleave8.nxv128i8(<vscale x 128 x i8> %vec)1448  ret {<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>} %retval1449}1450 1451define {<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>} @vector_deinterleave_nxv8i16_nxv64i16(<vscale x 64 x i16> %vec) nounwind {1452; CHECK-LABEL: vector_deinterleave_nxv8i16_nxv64i16:1453; CHECK:       # %bb.0:1454; CHECK-NEXT:    addi sp, sp, -161455; CHECK-NEXT:    csrr a0, vlenb1456; CHECK-NEXT:    slli a0, a0, 41457; CHECK-NEXT:    sub sp, sp, a01458; CHECK-NEXT:    addi a0, sp, 161459; CHECK-NEXT:    csrr a1, vlenb1460; CHECK-NEXT:    slli a1, a1, 31461; CHECK-NEXT:    add a1, sp, a11462; CHECK-NEXT:    addi a1, a1, 161463; CHECK-NEXT:    vs8r.v v8, (a0)1464; CHECK-NEXT:    vs8r.v v16, (a1)1465; CHECK-NEXT:    vsetvli a2, zero, e16, m1, ta, ma1466; CHECK-NEXT:    vlseg8e16.v v0, (a0)1467; CHECK-NEXT:    vlseg8e16.v v22, (a1)1468; CHECK-NEXT:    vmv2r.v v8, v01469; CHECK-NEXT:    vmv1r.v v9, v221470; CHECK-NEXT:    vmv1r.v v22, v11471; CHECK-NEXT:    vmv2r.v v12, v21472; CHECK-NEXT:    vmv1r.v v13, v241473; CHECK-NEXT:    vmv1r.v v24, v31474; CHECK-NEXT:    vmv2r.v v16, v41475; CHECK-NEXT:    vmv1r.v v17, v261476; CHECK-NEXT:    vmv1r.v v26, v51477; CHECK-NEXT:    vmv2r.v v20, v61478; CHECK-NEXT:    vmv1r.v v21, v281479; CHECK-NEXT:    vmv1r.v v28, v71480; CHECK-NEXT:    vmv2r.v v10, v221481; CHECK-NEXT:    vmv2r.v v14, v241482; CHECK-NEXT:    vmv2r.v v18, v261483; CHECK-NEXT:    vmv2r.v v22, v281484; CHECK-NEXT:    csrr a0, vlenb1485; CHECK-NEXT:    slli a0, a0, 41486; CHECK-NEXT:    add sp, sp, a01487; CHECK-NEXT:    addi sp, sp, 161488; CHECK-NEXT:    ret1489  %retval = call {<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>} @llvm.vector.deinterleave8.nxv64i16(<vscale x 64 x i16> %vec)1490  ret {<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>} %retval1491}1492 1493define {<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>} @vector_deinterleave_nxv4i32_nxv32i32(<vscale x 32 x i32> %vec) nounwind {1494; CHECK-LABEL: vector_deinterleave_nxv4i32_nxv32i32:1495; CHECK:       # %bb.0:1496; CHECK-NEXT:    addi sp, sp, -161497; CHECK-NEXT:    csrr a0, vlenb1498; CHECK-NEXT:    slli a0, a0, 41499; CHECK-NEXT:    sub sp, sp, a01500; CHECK-NEXT:    addi a0, sp, 161501; CHECK-NEXT:    csrr a1, vlenb1502; CHECK-NEXT:    slli a1, a1, 31503; CHECK-NEXT:    add a1, sp, a11504; CHECK-NEXT:    addi a1, a1, 161505; CHECK-NEXT:    vs8r.v v8, (a0)1506; CHECK-NEXT:    vs8r.v v16, (a1)1507; CHECK-NEXT:    vsetvli a2, zero, e32, m1, ta, ma1508; CHECK-NEXT:    vlseg8e32.v v0, (a0)1509; CHECK-NEXT:    vlseg8e32.v v22, (a1)1510; CHECK-NEXT:    vmv2r.v v8, v01511; CHECK-NEXT:    vmv1r.v v9, v221512; CHECK-NEXT:    vmv1r.v v22, v11513; CHECK-NEXT:    vmv2r.v v12, v21514; CHECK-NEXT:    vmv1r.v v13, v241515; CHECK-NEXT:    vmv1r.v v24, v31516; CHECK-NEXT:    vmv2r.v v16, v41517; CHECK-NEXT:    vmv1r.v v17, v261518; CHECK-NEXT:    vmv1r.v v26, v51519; CHECK-NEXT:    vmv2r.v v20, v61520; CHECK-NEXT:    vmv1r.v v21, v281521; CHECK-NEXT:    vmv1r.v v28, v71522; CHECK-NEXT:    vmv2r.v v10, v221523; CHECK-NEXT:    vmv2r.v v14, v241524; CHECK-NEXT:    vmv2r.v v18, v261525; CHECK-NEXT:    vmv2r.v v22, v281526; CHECK-NEXT:    csrr a0, vlenb1527; CHECK-NEXT:    slli a0, a0, 41528; CHECK-NEXT:    add sp, sp, a01529; CHECK-NEXT:    addi sp, sp, 161530; CHECK-NEXT:    ret1531  %retval = call {<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>} @llvm.vector.deinterleave8.nxv32i32(<vscale x 32 x i32> %vec)1532  ret {<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>} %retval1533}1534 1535define {<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>} @vector_deinterleave_nxv2i64_nxv16i64(<vscale x 16 x i64> %vec) nounwind {1536; CHECK-LABEL: vector_deinterleave_nxv2i64_nxv16i64:1537; CHECK:       # %bb.0:1538; CHECK-NEXT:    addi sp, sp, -161539; CHECK-NEXT:    csrr a0, vlenb1540; CHECK-NEXT:    slli a0, a0, 41541; CHECK-NEXT:    sub sp, sp, a01542; CHECK-NEXT:    addi a0, sp, 161543; CHECK-NEXT:    csrr a1, vlenb1544; CHECK-NEXT:    slli a1, a1, 31545; CHECK-NEXT:    add a1, sp, a11546; CHECK-NEXT:    addi a1, a1, 161547; CHECK-NEXT:    vs8r.v v8, (a0)1548; CHECK-NEXT:    vs8r.v v16, (a1)1549; CHECK-NEXT:    vsetvli a2, zero, e64, m1, ta, ma1550; CHECK-NEXT:    vlseg8e64.v v0, (a0)1551; CHECK-NEXT:    vlseg8e64.v v22, (a1)1552; CHECK-NEXT:    vmv2r.v v8, v01553; CHECK-NEXT:    vmv1r.v v9, v221554; CHECK-NEXT:    vmv1r.v v22, v11555; CHECK-NEXT:    vmv2r.v v12, v21556; CHECK-NEXT:    vmv1r.v v13, v241557; CHECK-NEXT:    vmv1r.v v24, v31558; CHECK-NEXT:    vmv2r.v v16, v41559; CHECK-NEXT:    vmv1r.v v17, v261560; CHECK-NEXT:    vmv1r.v v26, v51561; CHECK-NEXT:    vmv2r.v v20, v61562; CHECK-NEXT:    vmv1r.v v21, v281563; CHECK-NEXT:    vmv1r.v v28, v71564; CHECK-NEXT:    vmv2r.v v10, v221565; CHECK-NEXT:    vmv2r.v v14, v241566; CHECK-NEXT:    vmv2r.v v18, v261567; CHECK-NEXT:    vmv2r.v v22, v281568; CHECK-NEXT:    csrr a0, vlenb1569; CHECK-NEXT:    slli a0, a0, 41570; CHECK-NEXT:    add sp, sp, a01571; CHECK-NEXT:    addi sp, sp, 161572; CHECK-NEXT:    ret1573  %retval = call {<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>} @llvm.vector.deinterleave8.nxv16i64(<vscale x 16 x i64> %vec)1574  ret {<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>} %retval1575}1576 1577; Floats1578 1579define {<vscale x 2 x bfloat>, <vscale x 2 x bfloat>} @vector_deinterleave_nxv2bf16_nxv4bf16(<vscale x 4 x bfloat> %vec) {1580; V-LABEL: vector_deinterleave_nxv2bf16_nxv4bf16:1581; V:       # %bb.0:1582; V-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma1583; V-NEXT:    vnsrl.wi v10, v8, 01584; V-NEXT:    vnsrl.wi v9, v8, 161585; V-NEXT:    vmv1r.v v8, v101586; V-NEXT:    ret1587;1588; ZIP-LABEL: vector_deinterleave_nxv2bf16_nxv4bf16:1589; ZIP:       # %bb.0:1590; ZIP-NEXT:    vsetvli a0, zero, e16, m1, ta, ma1591; ZIP-NEXT:    ri.vunzip2a.vv v10, v8, v91592; ZIP-NEXT:    ri.vunzip2b.vv v9, v8, v111593; ZIP-NEXT:    vmv.v.v v8, v101594; ZIP-NEXT:    ret1595%retval = call {<vscale x 2 x bfloat>, <vscale x 2 x bfloat>} @llvm.vector.deinterleave2.nxv4bf16(<vscale x 4 x bfloat> %vec)1596ret {<vscale x 2 x bfloat>, <vscale x 2 x bfloat>} %retval1597}1598 1599define {<vscale x 2 x half>, <vscale x 2 x half>} @vector_deinterleave_nxv2f16_nxv4f16(<vscale x 4 x half> %vec) {1600; V-LABEL: vector_deinterleave_nxv2f16_nxv4f16:1601; V:       # %bb.0:1602; V-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma1603; V-NEXT:    vnsrl.wi v10, v8, 01604; V-NEXT:    vnsrl.wi v9, v8, 161605; V-NEXT:    vmv1r.v v8, v101606; V-NEXT:    ret1607;1608; ZIP-LABEL: vector_deinterleave_nxv2f16_nxv4f16:1609; ZIP:       # %bb.0:1610; ZIP-NEXT:    vsetvli a0, zero, e16, m1, ta, ma1611; ZIP-NEXT:    ri.vunzip2a.vv v10, v8, v91612; ZIP-NEXT:    ri.vunzip2b.vv v9, v8, v111613; ZIP-NEXT:    vmv.v.v v8, v101614; ZIP-NEXT:    ret1615%retval = call {<vscale x 2 x half>, <vscale x 2 x half>} @llvm.vector.deinterleave2.nxv4f16(<vscale x 4 x half> %vec)1616ret {<vscale x 2 x half>, <vscale x 2 x half>} %retval1617}1618 1619define {<vscale x 4 x bfloat>, <vscale x 4 x bfloat>} @vector_deinterleave_nxv4bf16_nxv8bf16(<vscale x 8 x bfloat> %vec) {1620; V-LABEL: vector_deinterleave_nxv4bf16_nxv8bf16:1621; V:       # %bb.0:1622; V-NEXT:    vsetvli a0, zero, e16, m1, ta, ma1623; V-NEXT:    vnsrl.wi v10, v8, 01624; V-NEXT:    vnsrl.wi v11, v8, 161625; V-NEXT:    vmv.v.v v8, v101626; V-NEXT:    vmv.v.v v9, v111627; V-NEXT:    ret1628;1629; ZIP-LABEL: vector_deinterleave_nxv4bf16_nxv8bf16:1630; ZIP:       # %bb.0:1631; ZIP-NEXT:    vsetvli a0, zero, e16, m1, ta, ma1632; ZIP-NEXT:    ri.vunzip2a.vv v10, v8, v91633; ZIP-NEXT:    ri.vunzip2b.vv v11, v8, v91634; ZIP-NEXT:    vmv.v.v v8, v101635; ZIP-NEXT:    vmv.v.v v9, v111636; ZIP-NEXT:    ret1637%retval = call {<vscale x 4 x bfloat>, <vscale x 4 x bfloat>} @llvm.vector.deinterleave2.nxv8bf16(<vscale x 8 x bfloat> %vec)1638ret {<vscale x 4 x bfloat>, <vscale x 4 x bfloat>} %retval1639}1640 1641define {<vscale x 4 x half>, <vscale x 4 x half>} @vector_deinterleave_nxv4f16_nxv8f16(<vscale x 8 x half> %vec) {1642; V-LABEL: vector_deinterleave_nxv4f16_nxv8f16:1643; V:       # %bb.0:1644; V-NEXT:    vsetvli a0, zero, e16, m1, ta, ma1645; V-NEXT:    vnsrl.wi v10, v8, 01646; V-NEXT:    vnsrl.wi v11, v8, 161647; V-NEXT:    vmv.v.v v8, v101648; V-NEXT:    vmv.v.v v9, v111649; V-NEXT:    ret1650;1651; ZIP-LABEL: vector_deinterleave_nxv4f16_nxv8f16:1652; ZIP:       # %bb.0:1653; ZIP-NEXT:    vsetvli a0, zero, e16, m1, ta, ma1654; ZIP-NEXT:    ri.vunzip2a.vv v10, v8, v91655; ZIP-NEXT:    ri.vunzip2b.vv v11, v8, v91656; ZIP-NEXT:    vmv.v.v v8, v101657; ZIP-NEXT:    vmv.v.v v9, v111658; ZIP-NEXT:    ret1659%retval = call {<vscale x 4 x half>, <vscale x 4 x half>} @llvm.vector.deinterleave2.nxv8f16(<vscale x 8 x half> %vec)1660ret {<vscale x 4 x half>, <vscale x 4 x half>} %retval1661}1662 1663define {<vscale x 2 x float>, <vscale x 2 x float>} @vector_deinterleave_nxv2f32_nxv4f32(<vscale x 4 x float> %vec) {1664; V-LABEL: vector_deinterleave_nxv2f32_nxv4f32:1665; V:       # %bb.0:1666; V-NEXT:    li a0, 321667; V-NEXT:    vsetvli a1, zero, e32, m1, ta, ma1668; V-NEXT:    vnsrl.wx v10, v8, a01669; V-NEXT:    vnsrl.wi v11, v8, 01670; V-NEXT:    vmv.v.v v8, v111671; V-NEXT:    vmv.v.v v9, v101672; V-NEXT:    ret1673;1674; ZIP-LABEL: vector_deinterleave_nxv2f32_nxv4f32:1675; ZIP:       # %bb.0:1676; ZIP-NEXT:    vsetvli a0, zero, e32, m1, ta, ma1677; ZIP-NEXT:    ri.vunzip2a.vv v10, v8, v91678; ZIP-NEXT:    ri.vunzip2b.vv v11, v8, v91679; ZIP-NEXT:    vmv.v.v v8, v101680; ZIP-NEXT:    vmv.v.v v9, v111681; ZIP-NEXT:    ret1682%retval = call {<vscale x 2 x float>, <vscale x 2 x float>} @llvm.vector.deinterleave2.nxv4f32(<vscale x 4 x float> %vec)1683ret {<vscale x 2 x float>, <vscale x 2 x float>} %retval1684}1685 1686define {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>} @vector_deinterleave_nxv8bf16_nxv16bf16(<vscale x 16 x bfloat> %vec) {1687; V-LABEL: vector_deinterleave_nxv8bf16_nxv16bf16:1688; V:       # %bb.0:1689; V-NEXT:    vsetvli a0, zero, e16, m2, ta, ma1690; V-NEXT:    vnsrl.wi v12, v8, 01691; V-NEXT:    vnsrl.wi v14, v8, 161692; V-NEXT:    vmv.v.v v8, v121693; V-NEXT:    vmv.v.v v10, v141694; V-NEXT:    ret1695;1696; ZIP-LABEL: vector_deinterleave_nxv8bf16_nxv16bf16:1697; ZIP:       # %bb.0:1698; ZIP-NEXT:    vsetvli a0, zero, e16, m2, ta, ma1699; ZIP-NEXT:    ri.vunzip2a.vv v12, v8, v101700; ZIP-NEXT:    ri.vunzip2b.vv v14, v8, v101701; ZIP-NEXT:    vmv.v.v v8, v121702; ZIP-NEXT:    vmv.v.v v10, v141703; ZIP-NEXT:    ret1704%retval = call {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>} @llvm.vector.deinterleave2.nxv16bf16(<vscale x 16 x bfloat> %vec)1705ret {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>} %retval1706}1707 1708define {<vscale x 8 x half>, <vscale x 8 x half>} @vector_deinterleave_nxv8f16_nxv16f16(<vscale x 16 x half> %vec) {1709; V-LABEL: vector_deinterleave_nxv8f16_nxv16f16:1710; V:       # %bb.0:1711; V-NEXT:    vsetvli a0, zero, e16, m2, ta, ma1712; V-NEXT:    vnsrl.wi v12, v8, 01713; V-NEXT:    vnsrl.wi v14, v8, 161714; V-NEXT:    vmv.v.v v8, v121715; V-NEXT:    vmv.v.v v10, v141716; V-NEXT:    ret1717;1718; ZIP-LABEL: vector_deinterleave_nxv8f16_nxv16f16:1719; ZIP:       # %bb.0:1720; ZIP-NEXT:    vsetvli a0, zero, e16, m2, ta, ma1721; ZIP-NEXT:    ri.vunzip2a.vv v12, v8, v101722; ZIP-NEXT:    ri.vunzip2b.vv v14, v8, v101723; ZIP-NEXT:    vmv.v.v v8, v121724; ZIP-NEXT:    vmv.v.v v10, v141725; ZIP-NEXT:    ret1726%retval = call {<vscale x 8 x half>, <vscale x 8 x half>} @llvm.vector.deinterleave2.nxv16f16(<vscale x 16 x half> %vec)1727ret {<vscale x 8 x half>, <vscale x 8 x half>} %retval1728}1729 1730define {<vscale x 4 x float>, <vscale x 4 x float>} @vector_deinterleave_nxv4f32_nxv8f32(<vscale x 8 x float> %vec) {1731; V-LABEL: vector_deinterleave_nxv4f32_nxv8f32:1732; V:       # %bb.0:1733; V-NEXT:    li a0, 321734; V-NEXT:    vsetvli a1, zero, e32, m2, ta, ma1735; V-NEXT:    vnsrl.wx v12, v8, a01736; V-NEXT:    vnsrl.wi v14, v8, 01737; V-NEXT:    vmv.v.v v8, v141738; V-NEXT:    vmv.v.v v10, v121739; V-NEXT:    ret1740;1741; ZIP-LABEL: vector_deinterleave_nxv4f32_nxv8f32:1742; ZIP:       # %bb.0:1743; ZIP-NEXT:    vsetvli a0, zero, e32, m2, ta, ma1744; ZIP-NEXT:    ri.vunzip2a.vv v12, v8, v101745; ZIP-NEXT:    ri.vunzip2b.vv v14, v8, v101746; ZIP-NEXT:    vmv.v.v v8, v121747; ZIP-NEXT:    vmv.v.v v10, v141748; ZIP-NEXT:    ret1749%retval = call {<vscale x 4 x float>, <vscale x 4 x float>} @llvm.vector.deinterleave2.nxv8f32(<vscale x 8 x float> %vec)1750ret  {<vscale x 4 x float>, <vscale x 4 x float>} %retval1751}1752 1753define {<vscale x 2 x double>, <vscale x 2 x double>} @vector_deinterleave_nxv2f64_nxv4f64(<vscale x 4 x double> %vec) {1754; V-LABEL: vector_deinterleave_nxv2f64_nxv4f64:1755; V:       # %bb.0:1756; V-NEXT:    li a0, 851757; V-NEXT:    vsetvli a1, zero, e8, m1, ta, ma1758; V-NEXT:    vmv.v.x v16, a01759; V-NEXT:    li a0, 1701760; V-NEXT:    vmv.v.x v20, a01761; V-NEXT:    vsetvli a0, zero, e64, m4, ta, ma1762; V-NEXT:    vcompress.vm v12, v8, v161763; V-NEXT:    vcompress.vm v16, v8, v201764; V-NEXT:    vmv2r.v v8, v121765; V-NEXT:    vmv2r.v v10, v161766; V-NEXT:    ret1767;1768; ZIP-LABEL: vector_deinterleave_nxv2f64_nxv4f64:1769; ZIP:       # %bb.0:1770; ZIP-NEXT:    vsetvli a0, zero, e64, m2, ta, ma1771; ZIP-NEXT:    ri.vunzip2a.vv v12, v8, v101772; ZIP-NEXT:    ri.vunzip2b.vv v14, v8, v101773; ZIP-NEXT:    vmv.v.v v8, v121774; ZIP-NEXT:    vmv.v.v v10, v141775; ZIP-NEXT:    ret1776%retval = call {<vscale x 2 x double>, <vscale x 2 x double>} @llvm.vector.deinterleave2.nxv4f64(<vscale x 4 x double> %vec)1777ret {<vscale x 2 x double>, <vscale x 2 x double>} %retval1778}1779 1780 1781define {<vscale x 32 x bfloat>, <vscale x 32 x bfloat>} @vector_deinterleave_nxv32bf16_nxv64bf16(<vscale x 64 x bfloat> %vec) {1782; V-LABEL: vector_deinterleave_nxv32bf16_nxv64bf16:1783; V:       # %bb.0:1784; V-NEXT:    vsetvli a0, zero, e16, m4, ta, ma1785; V-NEXT:    vmv8r.v v24, v81786; V-NEXT:    vnsrl.wi v8, v24, 01787; V-NEXT:    vnsrl.wi v0, v24, 161788; V-NEXT:    vnsrl.wi v12, v16, 01789; V-NEXT:    vnsrl.wi v4, v16, 161790; V-NEXT:    vmv8r.v v16, v01791; V-NEXT:    ret1792;1793; ZIP-LABEL: vector_deinterleave_nxv32bf16_nxv64bf16:1794; ZIP:       # %bb.0:1795; ZIP-NEXT:    vsetvli a0, zero, e16, m4, ta, ma1796; ZIP-NEXT:    ri.vunzip2a.vv v28, v16, v201797; ZIP-NEXT:    ri.vunzip2b.vv v4, v16, v201798; ZIP-NEXT:    ri.vunzip2a.vv v24, v8, v121799; ZIP-NEXT:    ri.vunzip2b.vv v0, v8, v121800; ZIP-NEXT:    vmv8r.v v8, v241801; ZIP-NEXT:    vmv8r.v v16, v01802; ZIP-NEXT:    ret1803%retval = call {<vscale x 32 x bfloat>, <vscale x 32 x bfloat>} @llvm.vector.deinterleave2.nxv64bf16(<vscale x 64 x bfloat> %vec)1804ret {<vscale x 32 x bfloat>, <vscale x 32 x bfloat>} %retval1805}1806 1807define {<vscale x 32 x half>, <vscale x 32 x half>} @vector_deinterleave_nxv32f16_nxv64f16(<vscale x 64 x half> %vec) {1808; V-LABEL: vector_deinterleave_nxv32f16_nxv64f16:1809; V:       # %bb.0:1810; V-NEXT:    vsetvli a0, zero, e16, m4, ta, ma1811; V-NEXT:    vmv8r.v v24, v81812; V-NEXT:    vnsrl.wi v8, v24, 01813; V-NEXT:    vnsrl.wi v0, v24, 161814; V-NEXT:    vnsrl.wi v12, v16, 01815; V-NEXT:    vnsrl.wi v4, v16, 161816; V-NEXT:    vmv8r.v v16, v01817; V-NEXT:    ret1818;1819; ZIP-LABEL: vector_deinterleave_nxv32f16_nxv64f16:1820; ZIP:       # %bb.0:1821; ZIP-NEXT:    vsetvli a0, zero, e16, m4, ta, ma1822; ZIP-NEXT:    ri.vunzip2a.vv v28, v16, v201823; ZIP-NEXT:    ri.vunzip2b.vv v4, v16, v201824; ZIP-NEXT:    ri.vunzip2a.vv v24, v8, v121825; ZIP-NEXT:    ri.vunzip2b.vv v0, v8, v121826; ZIP-NEXT:    vmv8r.v v8, v241827; ZIP-NEXT:    vmv8r.v v16, v01828; ZIP-NEXT:    ret1829%retval = call {<vscale x 32 x half>, <vscale x 32 x half>} @llvm.vector.deinterleave2.nxv64f16(<vscale x 64 x half> %vec)1830ret {<vscale x 32 x half>, <vscale x 32 x half>} %retval1831}1832 1833define {<vscale x 16 x float>, <vscale x 16 x float>} @vector_deinterleave_nxv16f32_nxv32f32(<vscale x 32 x float> %vec) {1834; V-LABEL: vector_deinterleave_nxv16f32_nxv32f32:1835; V:       # %bb.0:1836; V-NEXT:    vsetvli a0, zero, e32, m4, ta, ma1837; V-NEXT:    vmv8r.v v24, v161838; V-NEXT:    li a0, 321839; V-NEXT:    vnsrl.wx v20, v24, a01840; V-NEXT:    vnsrl.wx v16, v8, a01841; V-NEXT:    vnsrl.wi v0, v8, 01842; V-NEXT:    vnsrl.wi v4, v24, 01843; V-NEXT:    vmv8r.v v8, v01844; V-NEXT:    ret1845;1846; ZIP-LABEL: vector_deinterleave_nxv16f32_nxv32f32:1847; ZIP:       # %bb.0:1848; ZIP-NEXT:    vsetvli a0, zero, e32, m4, ta, ma1849; ZIP-NEXT:    ri.vunzip2a.vv v28, v16, v201850; ZIP-NEXT:    ri.vunzip2b.vv v4, v16, v201851; ZIP-NEXT:    ri.vunzip2a.vv v24, v8, v121852; ZIP-NEXT:    ri.vunzip2b.vv v0, v8, v121853; ZIP-NEXT:    vmv8r.v v8, v241854; ZIP-NEXT:    vmv8r.v v16, v01855; ZIP-NEXT:    ret1856%retval = call {<vscale x 16 x float>, <vscale x 16 x float>} @llvm.vector.deinterleave2.nxv32f32(<vscale x 32 x float> %vec)1857ret  {<vscale x 16 x float>, <vscale x 16 x float>} %retval1858}1859 1860define {<vscale x 8 x double>, <vscale x 8 x double>} @vector_deinterleave_nxv8f64_nxv16f64(<vscale x 16 x double> %vec) {1861; V-LABEL: vector_deinterleave_nxv8f64_nxv16f64:1862; V:       # %bb.0:1863; V-NEXT:    addi sp, sp, -161864; V-NEXT:    .cfi_def_cfa_offset 161865; V-NEXT:    csrr a0, vlenb1866; V-NEXT:    slli a0, a0, 41867; V-NEXT:    sub sp, sp, a01868; V-NEXT:    .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb1869; V-NEXT:    li a0, 851870; V-NEXT:    vsetvli a1, zero, e8, mf8, ta, ma1871; V-NEXT:    vmv.v.x v7, a01872; V-NEXT:    li a0, 1701873; V-NEXT:    vmv.v.x v6, a01874; V-NEXT:    vsetvli a0, zero, e64, m8, ta, ma1875; V-NEXT:    vcompress.vm v24, v8, v71876; V-NEXT:    vmv1r.v v28, v71877; V-NEXT:    vmv1r.v v29, v61878; V-NEXT:    vcompress.vm v0, v8, v291879; V-NEXT:    vcompress.vm v8, v16, v281880; V-NEXT:    addi a0, sp, 161881; V-NEXT:    vs8r.v v8, (a0) # vscale x 64-byte Folded Spill1882; V-NEXT:    vcompress.vm v8, v16, v291883; V-NEXT:    csrr a0, vlenb1884; V-NEXT:    slli a0, a0, 31885; V-NEXT:    add a0, sp, a01886; V-NEXT:    addi a0, a0, 161887; V-NEXT:    vs8r.v v8, (a0) # vscale x 64-byte Folded Spill1888; V-NEXT:    addi a0, sp, 161889; V-NEXT:    vl8r.v v8, (a0) # vscale x 64-byte Folded Reload1890; V-NEXT:    vmv4r.v v28, v81891; V-NEXT:    csrr a0, vlenb1892; V-NEXT:    slli a0, a0, 31893; V-NEXT:    add a0, sp, a01894; V-NEXT:    addi a0, a0, 161895; V-NEXT:    vl8r.v v8, (a0) # vscale x 64-byte Folded Reload1896; V-NEXT:    vmv4r.v v4, v81897; V-NEXT:    vmv8r.v v8, v241898; V-NEXT:    vmv8r.v v16, v01899; V-NEXT:    csrr a0, vlenb1900; V-NEXT:    slli a0, a0, 41901; V-NEXT:    add sp, sp, a01902; V-NEXT:    .cfi_def_cfa sp, 161903; V-NEXT:    addi sp, sp, 161904; V-NEXT:    .cfi_def_cfa_offset 01905; V-NEXT:    ret1906;1907; ZIP-LABEL: vector_deinterleave_nxv8f64_nxv16f64:1908; ZIP:       # %bb.0:1909; ZIP-NEXT:    vsetvli a0, zero, e64, m4, ta, ma1910; ZIP-NEXT:    ri.vunzip2a.vv v28, v16, v201911; ZIP-NEXT:    ri.vunzip2b.vv v4, v16, v201912; ZIP-NEXT:    ri.vunzip2a.vv v24, v8, v121913; ZIP-NEXT:    ri.vunzip2b.vv v0, v8, v121914; ZIP-NEXT:    vmv8r.v v8, v241915; ZIP-NEXT:    vmv8r.v v16, v01916; ZIP-NEXT:    ret1917%retval = call {<vscale x 8 x double>, <vscale x 8 x double>} @llvm.vector.deinterleave2.nxv16f64(<vscale x 16 x double> %vec)1918ret {<vscale x 8 x double>, <vscale x 8 x double>} %retval1919}1920 1921define {<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>} @vector_deinterleave_nxv2f16_nxv6f16(<vscale x 6 x half> %arg) nounwind {1922; CHECK-LABEL: vector_deinterleave_nxv2f16_nxv6f16:1923; CHECK:       # %bb.0:1924; CHECK-NEXT:    addi sp, sp, -161925; CHECK-NEXT:    csrr a0, vlenb1926; CHECK-NEXT:    slli a0, a0, 11927; CHECK-NEXT:    sub sp, sp, a01928; CHECK-NEXT:    csrr a0, vlenb1929; CHECK-NEXT:    srli a0, a0, 21930; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, ma1931; CHECK-NEXT:    vslidedown.vx v10, v8, a01932; CHECK-NEXT:    vslideup.vx v8, v10, a01933; CHECK-NEXT:    addi a0, sp, 161934; CHECK-NEXT:    vs2r.v v8, (a0)1935; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma1936; CHECK-NEXT:    vlseg3e16.v v8, (a0)1937; CHECK-NEXT:    csrr a0, vlenb1938; CHECK-NEXT:    slli a0, a0, 11939; CHECK-NEXT:    add sp, sp, a01940; CHECK-NEXT:    addi sp, sp, 161941; CHECK-NEXT:    ret1942  %res = call {<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>} @llvm.vector.deinterleave3.nxv6f16(<vscale x 6 x half> %arg)1943  ret {<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>} %res1944}1945 1946define {<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>} @vector_deinterleave_nxv4f16_nxv12f16(<vscale x 12 x half> %arg) nounwind {1947; CHECK-LABEL: vector_deinterleave_nxv4f16_nxv12f16:1948; CHECK:       # %bb.0:1949; CHECK-NEXT:    addi sp, sp, -161950; CHECK-NEXT:    csrr a0, vlenb1951; CHECK-NEXT:    slli a0, a0, 21952; CHECK-NEXT:    sub sp, sp, a01953; CHECK-NEXT:    addi a0, sp, 161954; CHECK-NEXT:    vs4r.v v8, (a0)1955; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, ma1956; CHECK-NEXT:    vlseg3e16.v v8, (a0)1957; CHECK-NEXT:    csrr a0, vlenb1958; CHECK-NEXT:    slli a0, a0, 21959; CHECK-NEXT:    add sp, sp, a01960; CHECK-NEXT:    addi sp, sp, 161961; CHECK-NEXT:    ret1962  %res = call {<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>} @llvm.vector.deinterleave3.nxv12f16(<vscale x 12 x half> %arg)1963  ret {<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>} %res1964}1965 1966define {<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>} @vector_deinterleave_nxv8f16_nxv24f16(<vscale x 24 x half> %arg) nounwind {1967; CHECK-LABEL: vector_deinterleave_nxv8f16_nxv24f16:1968; CHECK:       # %bb.0:1969; CHECK-NEXT:    addi sp, sp, -161970; CHECK-NEXT:    csrr a0, vlenb1971; CHECK-NEXT:    slli a0, a0, 31972; CHECK-NEXT:    sub sp, sp, a01973; CHECK-NEXT:    addi a0, sp, 161974; CHECK-NEXT:    vs8r.v v8, (a0)1975; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma1976; CHECK-NEXT:    vlseg3e16.v v8, (a0)1977; CHECK-NEXT:    csrr a0, vlenb1978; CHECK-NEXT:    slli a0, a0, 31979; CHECK-NEXT:    add sp, sp, a01980; CHECK-NEXT:    addi sp, sp, 161981; CHECK-NEXT:    ret1982  %res = call {<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>} @llvm.vector.deinterleave3.nxv24f16(<vscale x 24 x half> %arg)1983  ret {<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>} %res1984}1985 1986define {<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>} @vector_deinterleave_nxv2bf16_nxv6bf16(<vscale x 6 x bfloat> %arg) nounwind {1987; CHECK-LABEL: vector_deinterleave_nxv2bf16_nxv6bf16:1988; CHECK:       # %bb.0:1989; CHECK-NEXT:    addi sp, sp, -161990; CHECK-NEXT:    csrr a0, vlenb1991; CHECK-NEXT:    slli a0, a0, 11992; CHECK-NEXT:    sub sp, sp, a01993; CHECK-NEXT:    csrr a0, vlenb1994; CHECK-NEXT:    srli a0, a0, 21995; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, ma1996; CHECK-NEXT:    vslidedown.vx v10, v8, a01997; CHECK-NEXT:    vslideup.vx v8, v10, a01998; CHECK-NEXT:    addi a0, sp, 161999; CHECK-NEXT:    vs2r.v v8, (a0)2000; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma2001; CHECK-NEXT:    vlseg3e16.v v8, (a0)2002; CHECK-NEXT:    csrr a0, vlenb2003; CHECK-NEXT:    slli a0, a0, 12004; CHECK-NEXT:    add sp, sp, a02005; CHECK-NEXT:    addi sp, sp, 162006; CHECK-NEXT:    ret2007  %res = call {<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>} @llvm.vector.deinterleave3.nxv6bf16(<vscale x 6 x bfloat> %arg)2008  ret {<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>} %res2009}2010 2011define {<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>} @vector_deinterleave_nxv4bf16_nxv12bf16(<vscale x 12 x bfloat> %arg) nounwind {2012; CHECK-LABEL: vector_deinterleave_nxv4bf16_nxv12bf16:2013; CHECK:       # %bb.0:2014; CHECK-NEXT:    addi sp, sp, -162015; CHECK-NEXT:    csrr a0, vlenb2016; CHECK-NEXT:    slli a0, a0, 22017; CHECK-NEXT:    sub sp, sp, a02018; CHECK-NEXT:    addi a0, sp, 162019; CHECK-NEXT:    vs4r.v v8, (a0)2020; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, ma2021; CHECK-NEXT:    vlseg3e16.v v8, (a0)2022; CHECK-NEXT:    csrr a0, vlenb2023; CHECK-NEXT:    slli a0, a0, 22024; CHECK-NEXT:    add sp, sp, a02025; CHECK-NEXT:    addi sp, sp, 162026; CHECK-NEXT:    ret2027  %res = call {<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>} @llvm.vector.deinterleave3.nxv12bf16(<vscale x 12 x bfloat> %arg)2028  ret {<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>} %res2029}2030 2031define {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>} @vector_deinterleave_nxv8bf16_nxv24bf16(<vscale x 24 x bfloat> %arg) nounwind {2032; CHECK-LABEL: vector_deinterleave_nxv8bf16_nxv24bf16:2033; CHECK:       # %bb.0:2034; CHECK-NEXT:    addi sp, sp, -162035; CHECK-NEXT:    csrr a0, vlenb2036; CHECK-NEXT:    slli a0, a0, 32037; CHECK-NEXT:    sub sp, sp, a02038; CHECK-NEXT:    addi a0, sp, 162039; CHECK-NEXT:    vs8r.v v8, (a0)2040; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma2041; CHECK-NEXT:    vlseg3e16.v v8, (a0)2042; CHECK-NEXT:    csrr a0, vlenb2043; CHECK-NEXT:    slli a0, a0, 32044; CHECK-NEXT:    add sp, sp, a02045; CHECK-NEXT:    addi sp, sp, 162046; CHECK-NEXT:    ret2047  %res = call {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>} @llvm.vector.deinterleave3.nxv24bf16(<vscale x 24 x bfloat> %arg)2048  ret {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>} %res2049}2050 2051define {<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>} @vector_deinterleave_nxv1f32_nxv3f32(<vscale x 3 x float> %arg) nounwind {2052; CHECK-LABEL: vector_deinterleave_nxv1f32_nxv3f32:2053; CHECK:       # %bb.0:2054; CHECK-NEXT:    addi sp, sp, -162055; CHECK-NEXT:    csrr a0, vlenb2056; CHECK-NEXT:    slli a0, a0, 12057; CHECK-NEXT:    sub sp, sp, a02058; CHECK-NEXT:    csrr a0, vlenb2059; CHECK-NEXT:    srli a0, a0, 32060; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, ma2061; CHECK-NEXT:    vslidedown.vx v10, v8, a02062; CHECK-NEXT:    vslideup.vx v8, v10, a02063; CHECK-NEXT:    addi a0, sp, 162064; CHECK-NEXT:    vs2r.v v8, (a0)2065; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, ma2066; CHECK-NEXT:    vlseg3e32.v v8, (a0)2067; CHECK-NEXT:    csrr a0, vlenb2068; CHECK-NEXT:    slli a0, a0, 12069; CHECK-NEXT:    add sp, sp, a02070; CHECK-NEXT:    addi sp, sp, 162071; CHECK-NEXT:    ret2072  %res = call {<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>} @llvm.vector.deinterleave3.nxv3f32(<vscale x 3 x float> %arg)2073  ret {<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>} %res2074}2075 2076define {<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>} @vector_deinterleave_nxv2f32_nxv6f32(<vscale x 6 x float> %arg) nounwind {2077; CHECK-LABEL: vector_deinterleave_nxv2f32_nxv6f32:2078; CHECK:       # %bb.0:2079; CHECK-NEXT:    addi sp, sp, -162080; CHECK-NEXT:    csrr a0, vlenb2081; CHECK-NEXT:    slli a0, a0, 22082; CHECK-NEXT:    sub sp, sp, a02083; CHECK-NEXT:    addi a0, sp, 162084; CHECK-NEXT:    vs4r.v v8, (a0)2085; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, ma2086; CHECK-NEXT:    vlseg3e32.v v8, (a0)2087; CHECK-NEXT:    csrr a0, vlenb2088; CHECK-NEXT:    slli a0, a0, 22089; CHECK-NEXT:    add sp, sp, a02090; CHECK-NEXT:    addi sp, sp, 162091; CHECK-NEXT:    ret2092  %res = call {<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>} @llvm.vector.deinterleave3.nxv6f32(<vscale x 6 x float> %arg)2093  ret {<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>} %res2094}2095 2096define {<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>} @vector_deinterleave_nxv4f32_nxv12f32(<vscale x 12 x float> %arg) nounwind {2097; CHECK-LABEL: vector_deinterleave_nxv4f32_nxv12f32:2098; CHECK:       # %bb.0:2099; CHECK-NEXT:    addi sp, sp, -162100; CHECK-NEXT:    csrr a0, vlenb2101; CHECK-NEXT:    slli a0, a0, 32102; CHECK-NEXT:    sub sp, sp, a02103; CHECK-NEXT:    addi a0, sp, 162104; CHECK-NEXT:    vs8r.v v8, (a0)2105; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, ma2106; CHECK-NEXT:    vlseg3e32.v v8, (a0)2107; CHECK-NEXT:    csrr a0, vlenb2108; CHECK-NEXT:    slli a0, a0, 32109; CHECK-NEXT:    add sp, sp, a02110; CHECK-NEXT:    addi sp, sp, 162111; CHECK-NEXT:    ret2112  %res = call {<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>} @llvm.vector.deinterleave3.nxv12f32(<vscale x 12 x float> %arg)2113  ret {<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>} %res2114}2115 2116define {<vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>} @vector_deinterleave_nxv1f64_nxv3f64(<vscale x 3 x double> %arg) nounwind {2117; CHECK-LABEL: vector_deinterleave_nxv1f64_nxv3f64:2118; CHECK:       # %bb.0:2119; CHECK-NEXT:    addi sp, sp, -162120; CHECK-NEXT:    csrr a0, vlenb2121; CHECK-NEXT:    slli a0, a0, 22122; CHECK-NEXT:    sub sp, sp, a02123; CHECK-NEXT:    addi a0, sp, 162124; CHECK-NEXT:    vs4r.v v8, (a0)2125; CHECK-NEXT:    vsetvli a1, zero, e64, m1, ta, ma2126; CHECK-NEXT:    vlseg3e64.v v8, (a0)2127; CHECK-NEXT:    csrr a0, vlenb2128; CHECK-NEXT:    slli a0, a0, 22129; CHECK-NEXT:    add sp, sp, a02130; CHECK-NEXT:    addi sp, sp, 162131; CHECK-NEXT:    ret2132  %res = call {<vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>} @llvm.vector.deinterleave3.nxv3f64(<vscale x 3 x double> %arg)2133  ret {<vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>} %res2134}2135 2136define {<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>} @vector_deinterleave_nxv2f64_nxv6f64(<vscale x 6 x double> %arg) nounwind {2137; CHECK-LABEL: vector_deinterleave_nxv2f64_nxv6f64:2138; CHECK:       # %bb.0:2139; CHECK-NEXT:    addi sp, sp, -162140; CHECK-NEXT:    csrr a0, vlenb2141; CHECK-NEXT:    slli a0, a0, 32142; CHECK-NEXT:    sub sp, sp, a02143; CHECK-NEXT:    addi a0, sp, 162144; CHECK-NEXT:    vs8r.v v8, (a0)2145; CHECK-NEXT:    vsetvli a1, zero, e64, m2, ta, ma2146; CHECK-NEXT:    vlseg3e64.v v8, (a0)2147; CHECK-NEXT:    csrr a0, vlenb2148; CHECK-NEXT:    slli a0, a0, 32149; CHECK-NEXT:    add sp, sp, a02150; CHECK-NEXT:    addi sp, sp, 162151; CHECK-NEXT:    ret2152  %res = call {<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>} @llvm.vector.deinterleave3.nxv6f64(<vscale x 6 x double> %arg)2153  ret {<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>} %res2154}2155 2156define {<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>} @vector_deinterleave_nxv2f16_nxv8f16(<vscale x 8 x half> %arg) nounwind {2157; CHECK-LABEL: vector_deinterleave_nxv2f16_nxv8f16:2158; CHECK:       # %bb.0:2159; CHECK-NEXT:    addi sp, sp, -162160; CHECK-NEXT:    csrr a0, vlenb2161; CHECK-NEXT:    slli a0, a0, 12162; CHECK-NEXT:    sub sp, sp, a02163; CHECK-NEXT:    addi a0, sp, 162164; CHECK-NEXT:    vs2r.v v8, (a0)2165; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma2166; CHECK-NEXT:    vlseg4e16.v v8, (a0)2167; CHECK-NEXT:    csrr a0, vlenb2168; CHECK-NEXT:    slli a0, a0, 12169; CHECK-NEXT:    add sp, sp, a02170; CHECK-NEXT:    addi sp, sp, 162171; CHECK-NEXT:    ret2172  %res = call {<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>} @llvm.vector.deinterleave4.nxv8f16(<vscale x 8 x half> %arg)2173  ret {<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>} %res2174}2175 2176define {<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>} @vector_deinterleave_nxv4f16_nxv16f16(<vscale x 16 x half> %arg) nounwind {2177; CHECK-LABEL: vector_deinterleave_nxv4f16_nxv16f16:2178; CHECK:       # %bb.0:2179; CHECK-NEXT:    addi sp, sp, -162180; CHECK-NEXT:    csrr a0, vlenb2181; CHECK-NEXT:    slli a0, a0, 22182; CHECK-NEXT:    sub sp, sp, a02183; CHECK-NEXT:    addi a0, sp, 162184; CHECK-NEXT:    vs4r.v v8, (a0)2185; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, ma2186; CHECK-NEXT:    vlseg4e16.v v8, (a0)2187; CHECK-NEXT:    csrr a0, vlenb2188; CHECK-NEXT:    slli a0, a0, 22189; CHECK-NEXT:    add sp, sp, a02190; CHECK-NEXT:    addi sp, sp, 162191; CHECK-NEXT:    ret2192  %res = call {<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>} @llvm.vector.deinterleave4.nxv16f16(<vscale x 16 x half> %arg)2193  ret {<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>} %res2194}2195 2196define {<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>} @vector_deinterleave_nxv8f16_nxv32f16(<vscale x 32 x half> %arg) nounwind {2197; CHECK-LABEL: vector_deinterleave_nxv8f16_nxv32f16:2198; CHECK:       # %bb.0:2199; CHECK-NEXT:    addi sp, sp, -162200; CHECK-NEXT:    csrr a0, vlenb2201; CHECK-NEXT:    slli a0, a0, 32202; CHECK-NEXT:    sub sp, sp, a02203; CHECK-NEXT:    addi a0, sp, 162204; CHECK-NEXT:    vs8r.v v8, (a0)2205; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma2206; CHECK-NEXT:    vlseg4e16.v v8, (a0)2207; CHECK-NEXT:    csrr a0, vlenb2208; CHECK-NEXT:    slli a0, a0, 32209; CHECK-NEXT:    add sp, sp, a02210; CHECK-NEXT:    addi sp, sp, 162211; CHECK-NEXT:    ret2212  %res = call {<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>} @llvm.vector.deinterleave4.nxv32f16(<vscale x 32 x half> %arg)2213  ret {<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>} %res2214}2215 2216define {<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>} @vector_deinterleave_nxv2bf16_nxv8bf16(<vscale x 8 x bfloat> %arg) nounwind {2217; CHECK-LABEL: vector_deinterleave_nxv2bf16_nxv8bf16:2218; CHECK:       # %bb.0:2219; CHECK-NEXT:    addi sp, sp, -162220; CHECK-NEXT:    csrr a0, vlenb2221; CHECK-NEXT:    slli a0, a0, 12222; CHECK-NEXT:    sub sp, sp, a02223; CHECK-NEXT:    addi a0, sp, 162224; CHECK-NEXT:    vs2r.v v8, (a0)2225; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma2226; CHECK-NEXT:    vlseg4e16.v v8, (a0)2227; CHECK-NEXT:    csrr a0, vlenb2228; CHECK-NEXT:    slli a0, a0, 12229; CHECK-NEXT:    add sp, sp, a02230; CHECK-NEXT:    addi sp, sp, 162231; CHECK-NEXT:    ret2232  %res = call {<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>} @llvm.vector.deinterleave4.nxv8bf16(<vscale x 8 x bfloat> %arg)2233  ret {<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>} %res2234}2235 2236define {<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>} @vector_deinterleave_nxv4bf16_nxv16bf16(<vscale x 16 x bfloat> %arg) nounwind {2237; CHECK-LABEL: vector_deinterleave_nxv4bf16_nxv16bf16:2238; CHECK:       # %bb.0:2239; CHECK-NEXT:    addi sp, sp, -162240; CHECK-NEXT:    csrr a0, vlenb2241; CHECK-NEXT:    slli a0, a0, 22242; CHECK-NEXT:    sub sp, sp, a02243; CHECK-NEXT:    addi a0, sp, 162244; CHECK-NEXT:    vs4r.v v8, (a0)2245; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, ma2246; CHECK-NEXT:    vlseg4e16.v v8, (a0)2247; CHECK-NEXT:    csrr a0, vlenb2248; CHECK-NEXT:    slli a0, a0, 22249; CHECK-NEXT:    add sp, sp, a02250; CHECK-NEXT:    addi sp, sp, 162251; CHECK-NEXT:    ret2252  %res = call {<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>} @llvm.vector.deinterleave4.nxv16bf16(<vscale x 16 x bfloat> %arg)2253  ret {<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>} %res2254}2255 2256define {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>} @vector_deinterleave_nxv8bf16_nxv32bf16(<vscale x 32 x bfloat> %arg) nounwind {2257; CHECK-LABEL: vector_deinterleave_nxv8bf16_nxv32bf16:2258; CHECK:       # %bb.0:2259; CHECK-NEXT:    addi sp, sp, -162260; CHECK-NEXT:    csrr a0, vlenb2261; CHECK-NEXT:    slli a0, a0, 32262; CHECK-NEXT:    sub sp, sp, a02263; CHECK-NEXT:    addi a0, sp, 162264; CHECK-NEXT:    vs8r.v v8, (a0)2265; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma2266; CHECK-NEXT:    vlseg4e16.v v8, (a0)2267; CHECK-NEXT:    csrr a0, vlenb2268; CHECK-NEXT:    slli a0, a0, 32269; CHECK-NEXT:    add sp, sp, a02270; CHECK-NEXT:    addi sp, sp, 162271; CHECK-NEXT:    ret2272  %res = call {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>} @llvm.vector.deinterleave4.nxv32bf16(<vscale x 32 x bfloat> %arg)2273  ret {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>} %res2274}2275 2276define {<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>} @vector_deinterleave_nxv1f32_nxv4f32(<vscale x 4 x float> %arg) nounwind {2277; CHECK-LABEL: vector_deinterleave_nxv1f32_nxv4f32:2278; CHECK:       # %bb.0:2279; CHECK-NEXT:    addi sp, sp, -162280; CHECK-NEXT:    csrr a0, vlenb2281; CHECK-NEXT:    slli a0, a0, 12282; CHECK-NEXT:    sub sp, sp, a02283; CHECK-NEXT:    addi a0, sp, 162284; CHECK-NEXT:    vs2r.v v8, (a0)2285; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, ma2286; CHECK-NEXT:    vlseg4e32.v v8, (a0)2287; CHECK-NEXT:    csrr a0, vlenb2288; CHECK-NEXT:    slli a0, a0, 12289; CHECK-NEXT:    add sp, sp, a02290; CHECK-NEXT:    addi sp, sp, 162291; CHECK-NEXT:    ret2292  %res = call {<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>} @llvm.vector.deinterleave4.nxv4f32(<vscale x 4 x float> %arg)2293  ret {<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>} %res2294}2295 2296define {<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>} @vector_deinterleave_nxv2f32_nxv8f32(<vscale x 8 x float> %arg) nounwind {2297; CHECK-LABEL: vector_deinterleave_nxv2f32_nxv8f32:2298; CHECK:       # %bb.0:2299; CHECK-NEXT:    addi sp, sp, -162300; CHECK-NEXT:    csrr a0, vlenb2301; CHECK-NEXT:    slli a0, a0, 22302; CHECK-NEXT:    sub sp, sp, a02303; CHECK-NEXT:    addi a0, sp, 162304; CHECK-NEXT:    vs4r.v v8, (a0)2305; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, ma2306; CHECK-NEXT:    vlseg4e32.v v8, (a0)2307; CHECK-NEXT:    csrr a0, vlenb2308; CHECK-NEXT:    slli a0, a0, 22309; CHECK-NEXT:    add sp, sp, a02310; CHECK-NEXT:    addi sp, sp, 162311; CHECK-NEXT:    ret2312  %res = call {<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>} @llvm.vector.deinterleave4.nxv6f32(<vscale x 8 x float> %arg)2313  ret {<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>} %res2314}2315 2316define {<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>} @vector_deinterleave_nxv4f32_nxv16f32(<vscale x 16 x float> %arg) nounwind {2317; CHECK-LABEL: vector_deinterleave_nxv4f32_nxv16f32:2318; CHECK:       # %bb.0:2319; CHECK-NEXT:    addi sp, sp, -162320; CHECK-NEXT:    csrr a0, vlenb2321; CHECK-NEXT:    slli a0, a0, 32322; CHECK-NEXT:    sub sp, sp, a02323; CHECK-NEXT:    addi a0, sp, 162324; CHECK-NEXT:    vs8r.v v8, (a0)2325; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, ma2326; CHECK-NEXT:    vlseg4e32.v v8, (a0)2327; CHECK-NEXT:    csrr a0, vlenb2328; CHECK-NEXT:    slli a0, a0, 32329; CHECK-NEXT:    add sp, sp, a02330; CHECK-NEXT:    addi sp, sp, 162331; CHECK-NEXT:    ret2332  %res = call {<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>} @llvm.vector.deinterleave4.nxv16f32(<vscale x 16 x float> %arg)2333  ret {<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>} %res2334}2335 2336define {<vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>} @vector_deinterleave_nxv1f64_nxv4f64(<vscale x 4 x double> %arg) nounwind {2337; CHECK-LABEL: vector_deinterleave_nxv1f64_nxv4f64:2338; CHECK:       # %bb.0:2339; CHECK-NEXT:    addi sp, sp, -162340; CHECK-NEXT:    csrr a0, vlenb2341; CHECK-NEXT:    slli a0, a0, 22342; CHECK-NEXT:    sub sp, sp, a02343; CHECK-NEXT:    addi a0, sp, 162344; CHECK-NEXT:    vs4r.v v8, (a0)2345; CHECK-NEXT:    vsetvli a1, zero, e64, m1, ta, ma2346; CHECK-NEXT:    vlseg4e64.v v8, (a0)2347; CHECK-NEXT:    csrr a0, vlenb2348; CHECK-NEXT:    slli a0, a0, 22349; CHECK-NEXT:    add sp, sp, a02350; CHECK-NEXT:    addi sp, sp, 162351; CHECK-NEXT:    ret2352  %res = call {<vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>} @llvm.vector.deinterleave4.nxv4f64(<vscale x 4 x double> %arg)2353  ret {<vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>} %res2354}2355 2356define {<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>} @vector_deinterleave_nxv2f64_nxv8f64(<vscale x 8 x double> %arg) nounwind {2357; CHECK-LABEL: vector_deinterleave_nxv2f64_nxv8f64:2358; CHECK:       # %bb.0:2359; CHECK-NEXT:    addi sp, sp, -162360; CHECK-NEXT:    csrr a0, vlenb2361; CHECK-NEXT:    slli a0, a0, 32362; CHECK-NEXT:    sub sp, sp, a02363; CHECK-NEXT:    addi a0, sp, 162364; CHECK-NEXT:    vs8r.v v8, (a0)2365; CHECK-NEXT:    vsetvli a1, zero, e64, m2, ta, ma2366; CHECK-NEXT:    vlseg4e64.v v8, (a0)2367; CHECK-NEXT:    csrr a0, vlenb2368; CHECK-NEXT:    slli a0, a0, 32369; CHECK-NEXT:    add sp, sp, a02370; CHECK-NEXT:    addi sp, sp, 162371; CHECK-NEXT:    ret2372  %res = call {<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>} @llvm.vector.deinterleave4.nxv8f64(<vscale x 8 x double> %arg)2373  ret {<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>} %res2374}2375 2376define {<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>} @vector_deinterleave_nxv2f16_nxv10f16(<vscale x 10 x half> %arg) nounwind {2377; CHECK-LABEL: vector_deinterleave_nxv2f16_nxv10f16:2378; CHECK:       # %bb.0:2379; CHECK-NEXT:    addi sp, sp, -162380; CHECK-NEXT:    csrr a0, vlenb2381; CHECK-NEXT:    slli a0, a0, 22382; CHECK-NEXT:    sub sp, sp, a02383; CHECK-NEXT:    csrr a0, vlenb2384; CHECK-NEXT:    srli a0, a0, 22385; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, ma2386; CHECK-NEXT:    vslidedown.vx v11, v9, a02387; CHECK-NEXT:    vslideup.vx v9, v11, a02388; CHECK-NEXT:    vslidedown.vx v11, v8, a02389; CHECK-NEXT:    vslideup.vx v8, v11, a02390; CHECK-NEXT:    addi a0, sp, 162391; CHECK-NEXT:    vs4r.v v8, (a0)2392; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma2393; CHECK-NEXT:    vlseg5e16.v v8, (a0)2394; CHECK-NEXT:    csrr a0, vlenb2395; CHECK-NEXT:    slli a0, a0, 22396; CHECK-NEXT:    add sp, sp, a02397; CHECK-NEXT:    addi sp, sp, 162398; CHECK-NEXT:    ret2399  %res = call {<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>} @llvm.vector.deinterleave5.nxv10f16(<vscale x 10 x half> %arg)2400  ret {<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>} %res2401}2402 2403define {<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>} @vector_deinterleave_nxv4f16_nxv20f16(<vscale x 20 x half> %arg) nounwind {2404; CHECK-LABEL: vector_deinterleave_nxv4f16_nxv20f16:2405; CHECK:       # %bb.0:2406; CHECK-NEXT:    addi sp, sp, -162407; CHECK-NEXT:    csrr a0, vlenb2408; CHECK-NEXT:    slli a0, a0, 32409; CHECK-NEXT:    sub sp, sp, a02410; CHECK-NEXT:    addi a0, sp, 162411; CHECK-NEXT:    vs8r.v v8, (a0)2412; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, ma2413; CHECK-NEXT:    vlseg5e16.v v8, (a0)2414; CHECK-NEXT:    csrr a0, vlenb2415; CHECK-NEXT:    slli a0, a0, 32416; CHECK-NEXT:    add sp, sp, a02417; CHECK-NEXT:    addi sp, sp, 162418; CHECK-NEXT:    ret2419  %res = call {<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>} @llvm.vector.deinterleave5.nxv20f16(<vscale x 20 x half> %arg)2420  ret {<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>} %res2421}2422 2423define {<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>} @vector_deinterleave_nxv8f16_nxv40f16(<vscale x 40 x half> %arg) nounwind {2424; CHECK-LABEL: vector_deinterleave_nxv8f16_nxv40f16:2425; CHECK:       # %bb.0:2426; CHECK-NEXT:    addi sp, sp, -162427; CHECK-NEXT:    csrr a0, vlenb2428; CHECK-NEXT:    slli a0, a0, 42429; CHECK-NEXT:    sub sp, sp, a02430; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma2431; CHECK-NEXT:    vmv1r.v v26, v152432; CHECK-NEXT:    vmv1r.v v27, v162433; CHECK-NEXT:    addi a0, sp, 162434; CHECK-NEXT:    vmv1r.v v24, v132435; CHECK-NEXT:    csrr a1, vlenb2436; CHECK-NEXT:    slli a1, a1, 32437; CHECK-NEXT:    add a1, sp, a12438; CHECK-NEXT:    addi a1, a1, 162439; CHECK-NEXT:    vmv1r.v v25, v142440; CHECK-NEXT:    vs8r.v v8, (a0)2441; CHECK-NEXT:    vmv1r.v v28, v172442; CHECK-NEXT:    vs8r.v v24, (a1)2443; CHECK-NEXT:    vlseg5e16.v v12, (a0)2444; CHECK-NEXT:    vlseg5e16.v v18, (a1)2445; CHECK-NEXT:    vmv2r.v v8, v122446; CHECK-NEXT:    vmv1r.v v9, v182447; CHECK-NEXT:    vmv1r.v v18, v132448; CHECK-NEXT:    vmv2r.v v12, v142449; CHECK-NEXT:    vmv1r.v v13, v202450; CHECK-NEXT:    vmv1r.v v20, v152451; CHECK-NEXT:    vmv1r.v v17, v222452; CHECK-NEXT:    vmv2r.v v10, v182453; CHECK-NEXT:    vmv2r.v v14, v202454; CHECK-NEXT:    csrr a0, vlenb2455; CHECK-NEXT:    slli a0, a0, 42456; CHECK-NEXT:    add sp, sp, a02457; CHECK-NEXT:    addi sp, sp, 162458; CHECK-NEXT:    ret2459  %res = call {<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>} @llvm.vector.deinterleave5.nxv40f16(<vscale x 40 x half> %arg)2460  ret {<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>} %res2461}2462 2463define {<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>} @vector_deinterleave_nxv2bf16_nxv10bf16(<vscale x 10 x bfloat> %arg) nounwind {2464; CHECK-LABEL: vector_deinterleave_nxv2bf16_nxv10bf16:2465; CHECK:       # %bb.0:2466; CHECK-NEXT:    addi sp, sp, -162467; CHECK-NEXT:    csrr a0, vlenb2468; CHECK-NEXT:    slli a0, a0, 22469; CHECK-NEXT:    sub sp, sp, a02470; CHECK-NEXT:    csrr a0, vlenb2471; CHECK-NEXT:    srli a0, a0, 22472; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, ma2473; CHECK-NEXT:    vslidedown.vx v11, v9, a02474; CHECK-NEXT:    vslideup.vx v9, v11, a02475; CHECK-NEXT:    vslidedown.vx v11, v8, a02476; CHECK-NEXT:    vslideup.vx v8, v11, a02477; CHECK-NEXT:    addi a0, sp, 162478; CHECK-NEXT:    vs4r.v v8, (a0)2479; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma2480; CHECK-NEXT:    vlseg5e16.v v8, (a0)2481; CHECK-NEXT:    csrr a0, vlenb2482; CHECK-NEXT:    slli a0, a0, 22483; CHECK-NEXT:    add sp, sp, a02484; CHECK-NEXT:    addi sp, sp, 162485; CHECK-NEXT:    ret2486  %res = call {<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>} @llvm.vector.deinterleave5.nxv10bf16(<vscale x 10 x bfloat> %arg)2487  ret {<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>} %res2488}2489 2490define {<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>} @vector_deinterleave_nxv4bf16_nxv20bf16(<vscale x 20 x bfloat> %arg) nounwind {2491; CHECK-LABEL: vector_deinterleave_nxv4bf16_nxv20bf16:2492; CHECK:       # %bb.0:2493; CHECK-NEXT:    addi sp, sp, -162494; CHECK-NEXT:    csrr a0, vlenb2495; CHECK-NEXT:    slli a0, a0, 32496; CHECK-NEXT:    sub sp, sp, a02497; CHECK-NEXT:    addi a0, sp, 162498; CHECK-NEXT:    vs8r.v v8, (a0)2499; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, ma2500; CHECK-NEXT:    vlseg5e16.v v8, (a0)2501; CHECK-NEXT:    csrr a0, vlenb2502; CHECK-NEXT:    slli a0, a0, 32503; CHECK-NEXT:    add sp, sp, a02504; CHECK-NEXT:    addi sp, sp, 162505; CHECK-NEXT:    ret2506  %res = call {<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>} @llvm.vector.deinterleave5.nxv20bf16(<vscale x 20 x bfloat> %arg)2507  ret {<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>} %res2508}2509 2510define {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>} @vector_deinterleave_nxv8bf16_nxv40bf16(<vscale x 40 x bfloat> %arg) nounwind {2511; CHECK-LABEL: vector_deinterleave_nxv8bf16_nxv40bf16:2512; CHECK:       # %bb.0:2513; CHECK-NEXT:    addi sp, sp, -162514; CHECK-NEXT:    csrr a0, vlenb2515; CHECK-NEXT:    slli a0, a0, 42516; CHECK-NEXT:    sub sp, sp, a02517; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma2518; CHECK-NEXT:    vmv1r.v v26, v152519; CHECK-NEXT:    vmv1r.v v27, v162520; CHECK-NEXT:    addi a0, sp, 162521; CHECK-NEXT:    vmv1r.v v24, v132522; CHECK-NEXT:    csrr a1, vlenb2523; CHECK-NEXT:    slli a1, a1, 32524; CHECK-NEXT:    add a1, sp, a12525; CHECK-NEXT:    addi a1, a1, 162526; CHECK-NEXT:    vmv1r.v v25, v142527; CHECK-NEXT:    vs8r.v v8, (a0)2528; CHECK-NEXT:    vmv1r.v v28, v172529; CHECK-NEXT:    vs8r.v v24, (a1)2530; CHECK-NEXT:    vlseg5e16.v v12, (a0)2531; CHECK-NEXT:    vlseg5e16.v v18, (a1)2532; CHECK-NEXT:    vmv2r.v v8, v122533; CHECK-NEXT:    vmv1r.v v9, v182534; CHECK-NEXT:    vmv1r.v v18, v132535; CHECK-NEXT:    vmv2r.v v12, v142536; CHECK-NEXT:    vmv1r.v v13, v202537; CHECK-NEXT:    vmv1r.v v20, v152538; CHECK-NEXT:    vmv1r.v v17, v222539; CHECK-NEXT:    vmv2r.v v10, v182540; CHECK-NEXT:    vmv2r.v v14, v202541; CHECK-NEXT:    csrr a0, vlenb2542; CHECK-NEXT:    slli a0, a0, 42543; CHECK-NEXT:    add sp, sp, a02544; CHECK-NEXT:    addi sp, sp, 162545; CHECK-NEXT:    ret2546  %res = call {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>} @llvm.vector.deinterleave5.nxv40bf16(<vscale x 40 x bfloat> %arg)2547  ret {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>} %res2548}2549 2550define {<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>} @vector_deinterleave_nxv1f32_nxv5f32(<vscale x 5 x float> %arg) nounwind {2551; CHECK-LABEL: vector_deinterleave_nxv1f32_nxv5f32:2552; CHECK:       # %bb.0:2553; CHECK-NEXT:    addi sp, sp, -162554; CHECK-NEXT:    csrr a0, vlenb2555; CHECK-NEXT:    slli a0, a0, 22556; CHECK-NEXT:    sub sp, sp, a02557; CHECK-NEXT:    csrr a0, vlenb2558; CHECK-NEXT:    srli a0, a0, 32559; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, ma2560; CHECK-NEXT:    vslidedown.vx v11, v9, a02561; CHECK-NEXT:    vslideup.vx v9, v11, a02562; CHECK-NEXT:    vslidedown.vx v11, v8, a02563; CHECK-NEXT:    vslideup.vx v8, v11, a02564; CHECK-NEXT:    addi a0, sp, 162565; CHECK-NEXT:    vs4r.v v8, (a0)2566; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, ma2567; CHECK-NEXT:    vlseg5e32.v v8, (a0)2568; CHECK-NEXT:    csrr a0, vlenb2569; CHECK-NEXT:    slli a0, a0, 22570; CHECK-NEXT:    add sp, sp, a02571; CHECK-NEXT:    addi sp, sp, 162572; CHECK-NEXT:    ret2573  %res = call {<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>} @llvm.vector.deinterleave5.nxv5f32(<vscale x 5 x float> %arg)2574  ret {<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>} %res2575}2576 2577define {<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>} @vector_deinterleave_nxv2f32_nxv10f32(<vscale x 10 x float> %arg) nounwind {2578; CHECK-LABEL: vector_deinterleave_nxv2f32_nxv10f32:2579; CHECK:       # %bb.0:2580; CHECK-NEXT:    addi sp, sp, -162581; CHECK-NEXT:    csrr a0, vlenb2582; CHECK-NEXT:    slli a0, a0, 32583; CHECK-NEXT:    sub sp, sp, a02584; CHECK-NEXT:    addi a0, sp, 162585; CHECK-NEXT:    vs8r.v v8, (a0)2586; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, ma2587; CHECK-NEXT:    vlseg5e32.v v8, (a0)2588; CHECK-NEXT:    csrr a0, vlenb2589; CHECK-NEXT:    slli a0, a0, 32590; CHECK-NEXT:    add sp, sp, a02591; CHECK-NEXT:    addi sp, sp, 162592; CHECK-NEXT:    ret2593  %res = call {<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>} @llvm.vector.deinterleave5.nxv10f32(<vscale x 10 x float> %arg)2594  ret {<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>} %res2595}2596 2597define {<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>} @vector_deinterleave_nxv4f32_nxv20f32(<vscale x 20 x float> %arg) nounwind {2598; CHECK-LABEL: vector_deinterleave_nxv4f32_nxv20f32:2599; CHECK:       # %bb.0:2600; CHECK-NEXT:    addi sp, sp, -162601; CHECK-NEXT:    csrr a0, vlenb2602; CHECK-NEXT:    slli a0, a0, 42603; CHECK-NEXT:    sub sp, sp, a02604; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma2605; CHECK-NEXT:    vmv1r.v v26, v152606; CHECK-NEXT:    vmv1r.v v27, v162607; CHECK-NEXT:    addi a0, sp, 162608; CHECK-NEXT:    vmv1r.v v24, v132609; CHECK-NEXT:    csrr a1, vlenb2610; CHECK-NEXT:    slli a1, a1, 32611; CHECK-NEXT:    add a1, sp, a12612; CHECK-NEXT:    addi a1, a1, 162613; CHECK-NEXT:    vmv1r.v v25, v142614; CHECK-NEXT:    vs8r.v v8, (a0)2615; CHECK-NEXT:    vmv1r.v v28, v172616; CHECK-NEXT:    vs8r.v v24, (a1)2617; CHECK-NEXT:    vlseg5e32.v v12, (a0)2618; CHECK-NEXT:    vlseg5e32.v v18, (a1)2619; CHECK-NEXT:    vmv2r.v v8, v122620; CHECK-NEXT:    vmv1r.v v9, v182621; CHECK-NEXT:    vmv1r.v v18, v132622; CHECK-NEXT:    vmv2r.v v12, v142623; CHECK-NEXT:    vmv1r.v v13, v202624; CHECK-NEXT:    vmv1r.v v20, v152625; CHECK-NEXT:    vmv1r.v v17, v222626; CHECK-NEXT:    vmv2r.v v10, v182627; CHECK-NEXT:    vmv2r.v v14, v202628; CHECK-NEXT:    csrr a0, vlenb2629; CHECK-NEXT:    slli a0, a0, 42630; CHECK-NEXT:    add sp, sp, a02631; CHECK-NEXT:    addi sp, sp, 162632; CHECK-NEXT:    ret2633  %res = call {<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>} @llvm.vector.deinterleave5.nxv20f32(<vscale x 20 x float> %arg)2634  ret {<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>} %res2635}2636 2637define {<vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>} @vector_deinterleave_nxv1f64_nxv5f64(<vscale x 5 x double> %arg) nounwind {2638; CHECK-LABEL: vector_deinterleave_nxv1f64_nxv5f64:2639; CHECK:       # %bb.0:2640; CHECK-NEXT:    addi sp, sp, -162641; CHECK-NEXT:    csrr a0, vlenb2642; CHECK-NEXT:    slli a0, a0, 32643; CHECK-NEXT:    sub sp, sp, a02644; CHECK-NEXT:    addi a0, sp, 162645; CHECK-NEXT:    vs8r.v v8, (a0)2646; CHECK-NEXT:    vsetvli a1, zero, e64, m1, ta, ma2647; CHECK-NEXT:    vlseg5e64.v v8, (a0)2648; CHECK-NEXT:    csrr a0, vlenb2649; CHECK-NEXT:    slli a0, a0, 32650; CHECK-NEXT:    add sp, sp, a02651; CHECK-NEXT:    addi sp, sp, 162652; CHECK-NEXT:    ret2653  %res = call {<vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>} @llvm.vector.deinterleave5.nxv5f64(<vscale x 5 x double> %arg)2654  ret {<vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>} %res2655}2656 2657define {<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>} @vector_deinterleave_nxv2f64_nxv10f64(<vscale x 10 x double> %arg) nounwind {2658; CHECK-LABEL: vector_deinterleave_nxv2f64_nxv10f64:2659; CHECK:       # %bb.0:2660; CHECK-NEXT:    addi sp, sp, -162661; CHECK-NEXT:    csrr a0, vlenb2662; CHECK-NEXT:    slli a0, a0, 42663; CHECK-NEXT:    sub sp, sp, a02664; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, ma2665; CHECK-NEXT:    vmv1r.v v26, v152666; CHECK-NEXT:    vmv1r.v v27, v162667; CHECK-NEXT:    addi a0, sp, 162668; CHECK-NEXT:    vmv1r.v v24, v132669; CHECK-NEXT:    csrr a1, vlenb2670; CHECK-NEXT:    slli a1, a1, 32671; CHECK-NEXT:    add a1, sp, a12672; CHECK-NEXT:    addi a1, a1, 162673; CHECK-NEXT:    vmv1r.v v25, v142674; CHECK-NEXT:    vs8r.v v8, (a0)2675; CHECK-NEXT:    vmv1r.v v28, v172676; CHECK-NEXT:    vs8r.v v24, (a1)2677; CHECK-NEXT:    vlseg5e64.v v12, (a0)2678; CHECK-NEXT:    vlseg5e64.v v18, (a1)2679; CHECK-NEXT:    vmv2r.v v8, v122680; CHECK-NEXT:    vmv1r.v v9, v182681; CHECK-NEXT:    vmv1r.v v18, v132682; CHECK-NEXT:    vmv2r.v v12, v142683; CHECK-NEXT:    vmv1r.v v13, v202684; CHECK-NEXT:    vmv1r.v v20, v152685; CHECK-NEXT:    vmv1r.v v17, v222686; CHECK-NEXT:    vmv2r.v v10, v182687; CHECK-NEXT:    vmv2r.v v14, v202688; CHECK-NEXT:    csrr a0, vlenb2689; CHECK-NEXT:    slli a0, a0, 42690; CHECK-NEXT:    add sp, sp, a02691; CHECK-NEXT:    addi sp, sp, 162692; CHECK-NEXT:    ret2693  %res = call {<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>} @llvm.vector.deinterleave5.nxv10f64(<vscale x 10 x double> %arg)2694  ret {<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>} %res2695}2696 2697define {<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>} @vector_deinterleave_nxv2f16_nxv12f16(<vscale x 12 x half> %arg) nounwind {2698; CHECK-LABEL: vector_deinterleave_nxv2f16_nxv12f16:2699; CHECK:       # %bb.0:2700; CHECK-NEXT:    addi sp, sp, -162701; CHECK-NEXT:    csrr a0, vlenb2702; CHECK-NEXT:    slli a0, a0, 22703; CHECK-NEXT:    sub sp, sp, a02704; CHECK-NEXT:    csrr a0, vlenb2705; CHECK-NEXT:    srli a0, a0, 22706; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, ma2707; CHECK-NEXT:    vslidedown.vx v11, v9, a02708; CHECK-NEXT:    vslideup.vx v9, v11, a02709; CHECK-NEXT:    vslidedown.vx v11, v8, a02710; CHECK-NEXT:    vslideup.vx v8, v11, a02711; CHECK-NEXT:    vslidedown.vx v11, v10, a02712; CHECK-NEXT:    vslideup.vx v10, v11, a02713; CHECK-NEXT:    addi a0, sp, 162714; CHECK-NEXT:    vs4r.v v8, (a0)2715; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma2716; CHECK-NEXT:    vlseg6e16.v v8, (a0)2717; CHECK-NEXT:    csrr a0, vlenb2718; CHECK-NEXT:    slli a0, a0, 22719; CHECK-NEXT:    add sp, sp, a02720; CHECK-NEXT:    addi sp, sp, 162721; CHECK-NEXT:    ret2722  %res = call {<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>} @llvm.vector.deinterleave6.nxv12f16(<vscale x 12 x half> %arg)2723  ret {<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>} %res2724}2725 2726define {<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>} @vector_deinterleave_nxv4f16_nxv24f16(<vscale x 24 x half> %arg) nounwind {2727; CHECK-LABEL: vector_deinterleave_nxv4f16_nxv24f16:2728; CHECK:       # %bb.0:2729; CHECK-NEXT:    addi sp, sp, -162730; CHECK-NEXT:    csrr a0, vlenb2731; CHECK-NEXT:    slli a0, a0, 32732; CHECK-NEXT:    sub sp, sp, a02733; CHECK-NEXT:    addi a0, sp, 162734; CHECK-NEXT:    vs8r.v v8, (a0)2735; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, ma2736; CHECK-NEXT:    vlseg6e16.v v8, (a0)2737; CHECK-NEXT:    csrr a0, vlenb2738; CHECK-NEXT:    slli a0, a0, 32739; CHECK-NEXT:    add sp, sp, a02740; CHECK-NEXT:    addi sp, sp, 162741; CHECK-NEXT:    ret2742  %res = call {<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>} @llvm.vector.deinterleave6.nxv24f16(<vscale x 24 x half> %arg)2743  ret {<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>} %res2744}2745 2746define {<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>} @vector_deinterleave_nxv8f16_nxv48f16(<vscale x 48 x half> %arg) nounwind {2747; CHECK-LABEL: vector_deinterleave_nxv8f16_nxv48f16:2748; CHECK:       # %bb.0:2749; CHECK-NEXT:    addi sp, sp, -162750; CHECK-NEXT:    csrr a0, vlenb2751; CHECK-NEXT:    slli a0, a0, 42752; CHECK-NEXT:    sub sp, sp, a02753; CHECK-NEXT:    addi a0, sp, 162754; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, ma2755; CHECK-NEXT:    vmv2r.v v28, v182756; CHECK-NEXT:    csrr a1, vlenb2757; CHECK-NEXT:    slli a1, a1, 32758; CHECK-NEXT:    add a1, sp, a12759; CHECK-NEXT:    addi a1, a1, 162760; CHECK-NEXT:    vmv2r.v v24, v142761; CHECK-NEXT:    vs8r.v v8, (a0)2762; CHECK-NEXT:    vmv2r.v v26, v162763; CHECK-NEXT:    vs8r.v v24, (a1)2764; CHECK-NEXT:    vlseg6e16.v v24, (a0)2765; CHECK-NEXT:    vlseg6e16.v v18, (a1)2766; CHECK-NEXT:    vmv2r.v v8, v242767; CHECK-NEXT:    vmv1r.v v9, v182768; CHECK-NEXT:    vmv1r.v v18, v252769; CHECK-NEXT:    vmv2r.v v12, v262770; CHECK-NEXT:    vmv1r.v v13, v202771; CHECK-NEXT:    vmv1r.v v20, v272772; CHECK-NEXT:    vmv2r.v v16, v282773; CHECK-NEXT:    vmv1r.v v17, v222774; CHECK-NEXT:    vmv1r.v v22, v292775; CHECK-NEXT:    vmv2r.v v10, v182776; CHECK-NEXT:    vmv2r.v v14, v202777; CHECK-NEXT:    vmv2r.v v18, v222778; CHECK-NEXT:    csrr a0, vlenb2779; CHECK-NEXT:    slli a0, a0, 42780; CHECK-NEXT:    add sp, sp, a02781; CHECK-NEXT:    addi sp, sp, 162782; CHECK-NEXT:    ret2783  %res = call {<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>} @llvm.vector.deinterleave6.nxv48f16(<vscale x 48 x half> %arg)2784  ret {<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>} %res2785}2786 2787define {<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>} @vector_deinterleave_nxv2bf16_nxv12bf16(<vscale x 12 x bfloat> %arg) nounwind {2788; CHECK-LABEL: vector_deinterleave_nxv2bf16_nxv12bf16:2789; CHECK:       # %bb.0:2790; CHECK-NEXT:    addi sp, sp, -162791; CHECK-NEXT:    csrr a0, vlenb2792; CHECK-NEXT:    slli a0, a0, 22793; CHECK-NEXT:    sub sp, sp, a02794; CHECK-NEXT:    csrr a0, vlenb2795; CHECK-NEXT:    srli a0, a0, 22796; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, ma2797; CHECK-NEXT:    vslidedown.vx v11, v9, a02798; CHECK-NEXT:    vslideup.vx v9, v11, a02799; CHECK-NEXT:    vslidedown.vx v11, v8, a02800; CHECK-NEXT:    vslideup.vx v8, v11, a02801; CHECK-NEXT:    vslidedown.vx v11, v10, a02802; CHECK-NEXT:    vslideup.vx v10, v11, a02803; CHECK-NEXT:    addi a0, sp, 162804; CHECK-NEXT:    vs4r.v v8, (a0)2805; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma2806; CHECK-NEXT:    vlseg6e16.v v8, (a0)2807; CHECK-NEXT:    csrr a0, vlenb2808; CHECK-NEXT:    slli a0, a0, 22809; CHECK-NEXT:    add sp, sp, a02810; CHECK-NEXT:    addi sp, sp, 162811; CHECK-NEXT:    ret2812  %res = call {<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>} @llvm.vector.deinterleave6.nxv12bf16(<vscale x 12 x bfloat> %arg)2813  ret {<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>} %res2814}2815 2816define {<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>} @vector_deinterleave_nxv4bf16_nxv24bf16(<vscale x 24 x bfloat> %arg) nounwind {2817; CHECK-LABEL: vector_deinterleave_nxv4bf16_nxv24bf16:2818; CHECK:       # %bb.0:2819; CHECK-NEXT:    addi sp, sp, -162820; CHECK-NEXT:    csrr a0, vlenb2821; CHECK-NEXT:    slli a0, a0, 32822; CHECK-NEXT:    sub sp, sp, a02823; CHECK-NEXT:    addi a0, sp, 162824; CHECK-NEXT:    vs8r.v v8, (a0)2825; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, ma2826; CHECK-NEXT:    vlseg6e16.v v8, (a0)2827; CHECK-NEXT:    csrr a0, vlenb2828; CHECK-NEXT:    slli a0, a0, 32829; CHECK-NEXT:    add sp, sp, a02830; CHECK-NEXT:    addi sp, sp, 162831; CHECK-NEXT:    ret2832  %res = call {<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>} @llvm.vector.deinterleave6.nxv24bf16(<vscale x 24 x bfloat> %arg)2833  ret {<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>} %res2834}2835 2836define {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>} @vector_deinterleave_nxv8bf16_nxv48bf16(<vscale x 48 x bfloat> %arg) nounwind {2837; CHECK-LABEL: vector_deinterleave_nxv8bf16_nxv48bf16:2838; CHECK:       # %bb.0:2839; CHECK-NEXT:    addi sp, sp, -162840; CHECK-NEXT:    csrr a0, vlenb2841; CHECK-NEXT:    slli a0, a0, 42842; CHECK-NEXT:    sub sp, sp, a02843; CHECK-NEXT:    addi a0, sp, 162844; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, ma2845; CHECK-NEXT:    vmv2r.v v28, v182846; CHECK-NEXT:    csrr a1, vlenb2847; CHECK-NEXT:    slli a1, a1, 32848; CHECK-NEXT:    add a1, sp, a12849; CHECK-NEXT:    addi a1, a1, 162850; CHECK-NEXT:    vmv2r.v v24, v142851; CHECK-NEXT:    vs8r.v v8, (a0)2852; CHECK-NEXT:    vmv2r.v v26, v162853; CHECK-NEXT:    vs8r.v v24, (a1)2854; CHECK-NEXT:    vlseg6e16.v v24, (a0)2855; CHECK-NEXT:    vlseg6e16.v v18, (a1)2856; CHECK-NEXT:    vmv2r.v v8, v242857; CHECK-NEXT:    vmv1r.v v9, v182858; CHECK-NEXT:    vmv1r.v v18, v252859; CHECK-NEXT:    vmv2r.v v12, v262860; CHECK-NEXT:    vmv1r.v v13, v202861; CHECK-NEXT:    vmv1r.v v20, v272862; CHECK-NEXT:    vmv2r.v v16, v282863; CHECK-NEXT:    vmv1r.v v17, v222864; CHECK-NEXT:    vmv1r.v v22, v292865; CHECK-NEXT:    vmv2r.v v10, v182866; CHECK-NEXT:    vmv2r.v v14, v202867; CHECK-NEXT:    vmv2r.v v18, v222868; CHECK-NEXT:    csrr a0, vlenb2869; CHECK-NEXT:    slli a0, a0, 42870; CHECK-NEXT:    add sp, sp, a02871; CHECK-NEXT:    addi sp, sp, 162872; CHECK-NEXT:    ret2873  %res = call {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>} @llvm.vector.deinterleave6.nxv48bf16(<vscale x 48 x bfloat> %arg)2874  ret {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>} %res2875}2876 2877define {<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>} @vector_deinterleave_nxv1f32_nxv6f32(<vscale x 6 x float> %arg) nounwind {2878; CHECK-LABEL: vector_deinterleave_nxv1f32_nxv6f32:2879; CHECK:       # %bb.0:2880; CHECK-NEXT:    addi sp, sp, -162881; CHECK-NEXT:    csrr a0, vlenb2882; CHECK-NEXT:    slli a0, a0, 22883; CHECK-NEXT:    sub sp, sp, a02884; CHECK-NEXT:    csrr a0, vlenb2885; CHECK-NEXT:    srli a0, a0, 32886; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, ma2887; CHECK-NEXT:    vslidedown.vx v11, v9, a02888; CHECK-NEXT:    vslideup.vx v9, v11, a02889; CHECK-NEXT:    vslidedown.vx v11, v8, a02890; CHECK-NEXT:    vslideup.vx v8, v11, a02891; CHECK-NEXT:    vslidedown.vx v11, v10, a02892; CHECK-NEXT:    vslideup.vx v10, v11, a02893; CHECK-NEXT:    addi a0, sp, 162894; CHECK-NEXT:    vs4r.v v8, (a0)2895; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, ma2896; CHECK-NEXT:    vlseg6e32.v v8, (a0)2897; CHECK-NEXT:    csrr a0, vlenb2898; CHECK-NEXT:    slli a0, a0, 22899; CHECK-NEXT:    add sp, sp, a02900; CHECK-NEXT:    addi sp, sp, 162901; CHECK-NEXT:    ret2902  %res = call {<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>} @llvm.vector.deinterleave6.nxv6f32(<vscale x 6 x float> %arg)2903  ret {<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>} %res2904}2905 2906define {<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>} @vector_deinterleave_nxv2f32_nxv12f32(<vscale x 12 x float> %arg) nounwind {2907; CHECK-LABEL: vector_deinterleave_nxv2f32_nxv12f32:2908; CHECK:       # %bb.0:2909; CHECK-NEXT:    addi sp, sp, -162910; CHECK-NEXT:    csrr a0, vlenb2911; CHECK-NEXT:    slli a0, a0, 32912; CHECK-NEXT:    sub sp, sp, a02913; CHECK-NEXT:    addi a0, sp, 162914; CHECK-NEXT:    vs8r.v v8, (a0)2915; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, ma2916; CHECK-NEXT:    vlseg6e32.v v8, (a0)2917; CHECK-NEXT:    csrr a0, vlenb2918; CHECK-NEXT:    slli a0, a0, 32919; CHECK-NEXT:    add sp, sp, a02920; CHECK-NEXT:    addi sp, sp, 162921; CHECK-NEXT:    ret2922  %res = call {<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>} @llvm.vector.deinterleave6.nxv12f32(<vscale x 12 x float> %arg)2923  ret {<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>} %res2924}2925 2926define {<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>} @vector_deinterleave_nxv4f32_nxv24f32(<vscale x 24 x float> %arg) nounwind {2927; CHECK-LABEL: vector_deinterleave_nxv4f32_nxv24f32:2928; CHECK:       # %bb.0:2929; CHECK-NEXT:    addi sp, sp, -162930; CHECK-NEXT:    csrr a0, vlenb2931; CHECK-NEXT:    slli a0, a0, 42932; CHECK-NEXT:    sub sp, sp, a02933; CHECK-NEXT:    addi a0, sp, 162934; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, ma2935; CHECK-NEXT:    vmv2r.v v28, v182936; CHECK-NEXT:    csrr a1, vlenb2937; CHECK-NEXT:    slli a1, a1, 32938; CHECK-NEXT:    add a1, sp, a12939; CHECK-NEXT:    addi a1, a1, 162940; CHECK-NEXT:    vmv2r.v v24, v142941; CHECK-NEXT:    vs8r.v v8, (a0)2942; CHECK-NEXT:    vmv2r.v v26, v162943; CHECK-NEXT:    vs8r.v v24, (a1)2944; CHECK-NEXT:    vlseg6e32.v v24, (a0)2945; CHECK-NEXT:    vlseg6e32.v v18, (a1)2946; CHECK-NEXT:    vmv2r.v v8, v242947; CHECK-NEXT:    vmv1r.v v9, v182948; CHECK-NEXT:    vmv1r.v v18, v252949; CHECK-NEXT:    vmv2r.v v12, v262950; CHECK-NEXT:    vmv1r.v v13, v202951; CHECK-NEXT:    vmv1r.v v20, v272952; CHECK-NEXT:    vmv2r.v v16, v282953; CHECK-NEXT:    vmv1r.v v17, v222954; CHECK-NEXT:    vmv1r.v v22, v292955; CHECK-NEXT:    vmv2r.v v10, v182956; CHECK-NEXT:    vmv2r.v v14, v202957; CHECK-NEXT:    vmv2r.v v18, v222958; CHECK-NEXT:    csrr a0, vlenb2959; CHECK-NEXT:    slli a0, a0, 42960; CHECK-NEXT:    add sp, sp, a02961; CHECK-NEXT:    addi sp, sp, 162962; CHECK-NEXT:    ret2963  %res = call {<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>} @llvm.vector.deinterleave6.nxv24f32(<vscale x 24 x float> %arg)2964  ret {<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>} %res2965}2966 2967define {<vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>} @vector_deinterleave_nxv1f64_nxv6f64(<vscale x 6 x double> %arg) nounwind {2968; CHECK-LABEL: vector_deinterleave_nxv1f64_nxv6f64:2969; CHECK:       # %bb.0:2970; CHECK-NEXT:    addi sp, sp, -162971; CHECK-NEXT:    csrr a0, vlenb2972; CHECK-NEXT:    slli a0, a0, 32973; CHECK-NEXT:    sub sp, sp, a02974; CHECK-NEXT:    addi a0, sp, 162975; CHECK-NEXT:    vs8r.v v8, (a0)2976; CHECK-NEXT:    vsetvli a1, zero, e64, m1, ta, ma2977; CHECK-NEXT:    vlseg6e64.v v8, (a0)2978; CHECK-NEXT:    csrr a0, vlenb2979; CHECK-NEXT:    slli a0, a0, 32980; CHECK-NEXT:    add sp, sp, a02981; CHECK-NEXT:    addi sp, sp, 162982; CHECK-NEXT:    ret2983  %res = call {<vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>} @llvm.vector.deinterleave6.nxv6f64(<vscale x 6 x double> %arg)2984  ret {<vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>} %res2985}2986 2987define {<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>} @vector_deinterleave_nxv2f64_nxv12f64(<vscale x 12 x double> %arg) nounwind {2988; CHECK-LABEL: vector_deinterleave_nxv2f64_nxv12f64:2989; CHECK:       # %bb.0:2990; CHECK-NEXT:    addi sp, sp, -162991; CHECK-NEXT:    csrr a0, vlenb2992; CHECK-NEXT:    slli a0, a0, 42993; CHECK-NEXT:    sub sp, sp, a02994; CHECK-NEXT:    addi a0, sp, 162995; CHECK-NEXT:    vsetvli a1, zero, e64, m1, ta, ma2996; CHECK-NEXT:    vmv2r.v v28, v182997; CHECK-NEXT:    csrr a1, vlenb2998; CHECK-NEXT:    slli a1, a1, 32999; CHECK-NEXT:    add a1, sp, a13000; CHECK-NEXT:    addi a1, a1, 163001; CHECK-NEXT:    vmv2r.v v24, v143002; CHECK-NEXT:    vs8r.v v8, (a0)3003; CHECK-NEXT:    vmv2r.v v26, v163004; CHECK-NEXT:    vs8r.v v24, (a1)3005; CHECK-NEXT:    vlseg6e64.v v24, (a0)3006; CHECK-NEXT:    vlseg6e64.v v18, (a1)3007; CHECK-NEXT:    vmv2r.v v8, v243008; CHECK-NEXT:    vmv1r.v v9, v183009; CHECK-NEXT:    vmv1r.v v18, v253010; CHECK-NEXT:    vmv2r.v v12, v263011; CHECK-NEXT:    vmv1r.v v13, v203012; CHECK-NEXT:    vmv1r.v v20, v273013; CHECK-NEXT:    vmv2r.v v16, v283014; CHECK-NEXT:    vmv1r.v v17, v223015; CHECK-NEXT:    vmv1r.v v22, v293016; CHECK-NEXT:    vmv2r.v v10, v183017; CHECK-NEXT:    vmv2r.v v14, v203018; CHECK-NEXT:    vmv2r.v v18, v223019; CHECK-NEXT:    csrr a0, vlenb3020; CHECK-NEXT:    slli a0, a0, 43021; CHECK-NEXT:    add sp, sp, a03022; CHECK-NEXT:    addi sp, sp, 163023; CHECK-NEXT:    ret3024  %res = call {<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>} @llvm.vector.deinterleave6.nxv12f64(<vscale x 12 x double> %arg)3025  ret {<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>} %res3026}3027 3028define {<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>} @vector_deinterleave_nxv2f16_nxv14f16(<vscale x 14 x half> %arg) nounwind {3029; CHECK-LABEL: vector_deinterleave_nxv2f16_nxv14f16:3030; CHECK:       # %bb.0:3031; CHECK-NEXT:    addi sp, sp, -163032; CHECK-NEXT:    csrr a0, vlenb3033; CHECK-NEXT:    slli a0, a0, 23034; CHECK-NEXT:    sub sp, sp, a03035; CHECK-NEXT:    csrr a0, vlenb3036; CHECK-NEXT:    srli a0, a0, 23037; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, ma3038; CHECK-NEXT:    vslidedown.vx v12, v9, a03039; CHECK-NEXT:    vslideup.vx v9, v12, a03040; CHECK-NEXT:    vslidedown.vx v12, v8, a03041; CHECK-NEXT:    vslideup.vx v8, v12, a03042; CHECK-NEXT:    vslidedown.vx v12, v10, a03043; CHECK-NEXT:    vslideup.vx v10, v12, a03044; CHECK-NEXT:    addi a0, sp, 163045; CHECK-NEXT:    vs4r.v v8, (a0)3046; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma3047; CHECK-NEXT:    vlseg7e16.v v8, (a0)3048; CHECK-NEXT:    csrr a0, vlenb3049; CHECK-NEXT:    slli a0, a0, 23050; CHECK-NEXT:    add sp, sp, a03051; CHECK-NEXT:    addi sp, sp, 163052; CHECK-NEXT:    ret3053  %res = call {<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>} @llvm.vector.deinterleave7.nxv14f16(<vscale x 14 x half> %arg)3054  ret {<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>} %res3055}3056 3057define {<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>} @vector_deinterleave_nxv4f16_nxv28f16(<vscale x 28 x half> %arg) nounwind {3058; CHECK-LABEL: vector_deinterleave_nxv4f16_nxv28f16:3059; CHECK:       # %bb.0:3060; CHECK-NEXT:    addi sp, sp, -163061; CHECK-NEXT:    csrr a0, vlenb3062; CHECK-NEXT:    slli a0, a0, 33063; CHECK-NEXT:    sub sp, sp, a03064; CHECK-NEXT:    addi a0, sp, 163065; CHECK-NEXT:    vs8r.v v8, (a0)3066; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, ma3067; CHECK-NEXT:    vlseg7e16.v v8, (a0)3068; CHECK-NEXT:    csrr a0, vlenb3069; CHECK-NEXT:    slli a0, a0, 33070; CHECK-NEXT:    add sp, sp, a03071; CHECK-NEXT:    addi sp, sp, 163072; CHECK-NEXT:    ret3073  %res = call {<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>} @llvm.vector.deinterleave7.nxv28f16(<vscale x 28 x half> %arg)3074  ret {<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>} %res3075}3076 3077define {<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>} @vector_deinterleave_nxv8f16_nxv56f16(<vscale x 56 x half> %arg) nounwind {3078; CHECK-LABEL: vector_deinterleave_nxv8f16_nxv56f16:3079; CHECK:       # %bb.0:3080; CHECK-NEXT:    addi sp, sp, -163081; CHECK-NEXT:    csrr a0, vlenb3082; CHECK-NEXT:    slli a0, a0, 43083; CHECK-NEXT:    sub sp, sp, a03084; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma3085; CHECK-NEXT:    vmv1r.v v30, v213086; CHECK-NEXT:    vmv1r.v v28, v193087; CHECK-NEXT:    vmv1r.v v29, v203088; CHECK-NEXT:    vmv1r.v v26, v173089; CHECK-NEXT:    addi a0, sp, 163090; CHECK-NEXT:    vmv1r.v v27, v183091; CHECK-NEXT:    csrr a1, vlenb3092; CHECK-NEXT:    slli a1, a1, 33093; CHECK-NEXT:    add a1, sp, a13094; CHECK-NEXT:    addi a1, a1, 163095; CHECK-NEXT:    vmv1r.v v24, v153096; CHECK-NEXT:    vs8r.v v8, (a0)3097; CHECK-NEXT:    vmv1r.v v25, v163098; CHECK-NEXT:    vs8r.v v24, (a1)3099; CHECK-NEXT:    vlseg7e16.v v14, (a0)3100; CHECK-NEXT:    vlseg7e16.v v22, (a1)3101; CHECK-NEXT:    vmv2r.v v8, v143102; CHECK-NEXT:    vmv1r.v v9, v223103; CHECK-NEXT:    vmv1r.v v22, v153104; CHECK-NEXT:    vmv2r.v v12, v163105; CHECK-NEXT:    vmv1r.v v13, v243106; CHECK-NEXT:    vmv1r.v v24, v173107; CHECK-NEXT:    vmv2r.v v16, v183108; CHECK-NEXT:    vmv1r.v v17, v263109; CHECK-NEXT:    vmv1r.v v26, v193110; CHECK-NEXT:    vmv1r.v v21, v283111; CHECK-NEXT:    vmv2r.v v10, v223112; CHECK-NEXT:    vmv2r.v v14, v243113; CHECK-NEXT:    vmv2r.v v18, v263114; CHECK-NEXT:    csrr a0, vlenb3115; CHECK-NEXT:    slli a0, a0, 43116; CHECK-NEXT:    add sp, sp, a03117; CHECK-NEXT:    addi sp, sp, 163118; CHECK-NEXT:    ret3119  %res = call {<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>} @llvm.vector.deinterleave7.nxv56f16(<vscale x 56 x half> %arg)3120  ret {<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>} %res3121}3122 3123define {<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>} @vector_deinterleave_nxv2bf16_nxv14bf16(<vscale x 14 x bfloat> %arg) nounwind {3124; CHECK-LABEL: vector_deinterleave_nxv2bf16_nxv14bf16:3125; CHECK:       # %bb.0:3126; CHECK-NEXT:    addi sp, sp, -163127; CHECK-NEXT:    csrr a0, vlenb3128; CHECK-NEXT:    slli a0, a0, 23129; CHECK-NEXT:    sub sp, sp, a03130; CHECK-NEXT:    csrr a0, vlenb3131; CHECK-NEXT:    srli a0, a0, 23132; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, ma3133; CHECK-NEXT:    vslidedown.vx v12, v9, a03134; CHECK-NEXT:    vslideup.vx v9, v12, a03135; CHECK-NEXT:    vslidedown.vx v12, v8, a03136; CHECK-NEXT:    vslideup.vx v8, v12, a03137; CHECK-NEXT:    vslidedown.vx v12, v10, a03138; CHECK-NEXT:    vslideup.vx v10, v12, a03139; CHECK-NEXT:    addi a0, sp, 163140; CHECK-NEXT:    vs4r.v v8, (a0)3141; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma3142; CHECK-NEXT:    vlseg7e16.v v8, (a0)3143; CHECK-NEXT:    csrr a0, vlenb3144; CHECK-NEXT:    slli a0, a0, 23145; CHECK-NEXT:    add sp, sp, a03146; CHECK-NEXT:    addi sp, sp, 163147; CHECK-NEXT:    ret3148  %res = call {<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>} @llvm.vector.deinterleave7.nxv14bf16(<vscale x 14 x bfloat> %arg)3149  ret {<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>} %res3150}3151 3152define {<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>} @vector_deinterleave_nxv4bf16_nxv28bf16(<vscale x 28 x bfloat> %arg) nounwind {3153; CHECK-LABEL: vector_deinterleave_nxv4bf16_nxv28bf16:3154; CHECK:       # %bb.0:3155; CHECK-NEXT:    addi sp, sp, -163156; CHECK-NEXT:    csrr a0, vlenb3157; CHECK-NEXT:    slli a0, a0, 33158; CHECK-NEXT:    sub sp, sp, a03159; CHECK-NEXT:    addi a0, sp, 163160; CHECK-NEXT:    vs8r.v v8, (a0)3161; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, ma3162; CHECK-NEXT:    vlseg7e16.v v8, (a0)3163; CHECK-NEXT:    csrr a0, vlenb3164; CHECK-NEXT:    slli a0, a0, 33165; CHECK-NEXT:    add sp, sp, a03166; CHECK-NEXT:    addi sp, sp, 163167; CHECK-NEXT:    ret3168  %res = call {<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>} @llvm.vector.deinterleave7.nxv28bf16(<vscale x 28 x bfloat> %arg)3169  ret {<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>} %res3170}3171 3172define {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>} @vector_deinterleave_nxv8bf16_nxv56bf16(<vscale x 56 x bfloat> %arg) nounwind {3173; CHECK-LABEL: vector_deinterleave_nxv8bf16_nxv56bf16:3174; CHECK:       # %bb.0:3175; CHECK-NEXT:    addi sp, sp, -163176; CHECK-NEXT:    csrr a0, vlenb3177; CHECK-NEXT:    slli a0, a0, 43178; CHECK-NEXT:    sub sp, sp, a03179; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma3180; CHECK-NEXT:    vmv1r.v v30, v213181; CHECK-NEXT:    vmv1r.v v28, v193182; CHECK-NEXT:    vmv1r.v v29, v203183; CHECK-NEXT:    vmv1r.v v26, v173184; CHECK-NEXT:    addi a0, sp, 163185; CHECK-NEXT:    vmv1r.v v27, v183186; CHECK-NEXT:    csrr a1, vlenb3187; CHECK-NEXT:    slli a1, a1, 33188; CHECK-NEXT:    add a1, sp, a13189; CHECK-NEXT:    addi a1, a1, 163190; CHECK-NEXT:    vmv1r.v v24, v153191; CHECK-NEXT:    vs8r.v v8, (a0)3192; CHECK-NEXT:    vmv1r.v v25, v163193; CHECK-NEXT:    vs8r.v v24, (a1)3194; CHECK-NEXT:    vlseg7e16.v v14, (a0)3195; CHECK-NEXT:    vlseg7e16.v v22, (a1)3196; CHECK-NEXT:    vmv2r.v v8, v143197; CHECK-NEXT:    vmv1r.v v9, v223198; CHECK-NEXT:    vmv1r.v v22, v153199; CHECK-NEXT:    vmv2r.v v12, v163200; CHECK-NEXT:    vmv1r.v v13, v243201; CHECK-NEXT:    vmv1r.v v24, v173202; CHECK-NEXT:    vmv2r.v v16, v183203; CHECK-NEXT:    vmv1r.v v17, v263204; CHECK-NEXT:    vmv1r.v v26, v193205; CHECK-NEXT:    vmv1r.v v21, v283206; CHECK-NEXT:    vmv2r.v v10, v223207; CHECK-NEXT:    vmv2r.v v14, v243208; CHECK-NEXT:    vmv2r.v v18, v263209; CHECK-NEXT:    csrr a0, vlenb3210; CHECK-NEXT:    slli a0, a0, 43211; CHECK-NEXT:    add sp, sp, a03212; CHECK-NEXT:    addi sp, sp, 163213; CHECK-NEXT:    ret3214  %res = call {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>} @llvm.vector.deinterleave7.nxv56bf16(<vscale x 56 x bfloat> %arg)3215  ret {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>} %res3216}3217 3218define {<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>} @vector_deinterleave_nxv1f32_nxv7f32(<vscale x 7 x float> %arg) nounwind {3219; CHECK-LABEL: vector_deinterleave_nxv1f32_nxv7f32:3220; CHECK:       # %bb.0:3221; CHECK-NEXT:    addi sp, sp, -163222; CHECK-NEXT:    csrr a0, vlenb3223; CHECK-NEXT:    slli a0, a0, 23224; CHECK-NEXT:    sub sp, sp, a03225; CHECK-NEXT:    csrr a0, vlenb3226; CHECK-NEXT:    srli a0, a0, 33227; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, ma3228; CHECK-NEXT:    vslidedown.vx v12, v9, a03229; CHECK-NEXT:    vslideup.vx v9, v12, a03230; CHECK-NEXT:    vslidedown.vx v12, v8, a03231; CHECK-NEXT:    vslideup.vx v8, v12, a03232; CHECK-NEXT:    vslidedown.vx v12, v10, a03233; CHECK-NEXT:    vslideup.vx v10, v12, a03234; CHECK-NEXT:    addi a0, sp, 163235; CHECK-NEXT:    vs4r.v v8, (a0)3236; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, ma3237; CHECK-NEXT:    vlseg7e32.v v8, (a0)3238; CHECK-NEXT:    csrr a0, vlenb3239; CHECK-NEXT:    slli a0, a0, 23240; CHECK-NEXT:    add sp, sp, a03241; CHECK-NEXT:    addi sp, sp, 163242; CHECK-NEXT:    ret3243  %res = call {<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>} @llvm.vector.deinterleave7.nxv7f32(<vscale x 7 x float> %arg)3244  ret {<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>} %res3245}3246 3247define {<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>} @vector_deinterleave_nxv2f32_nxv14f32(<vscale x 14 x float> %arg) nounwind {3248; CHECK-LABEL: vector_deinterleave_nxv2f32_nxv14f32:3249; CHECK:       # %bb.0:3250; CHECK-NEXT:    addi sp, sp, -163251; CHECK-NEXT:    csrr a0, vlenb3252; CHECK-NEXT:    slli a0, a0, 33253; CHECK-NEXT:    sub sp, sp, a03254; CHECK-NEXT:    addi a0, sp, 163255; CHECK-NEXT:    vs8r.v v8, (a0)3256; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, ma3257; CHECK-NEXT:    vlseg7e32.v v8, (a0)3258; CHECK-NEXT:    csrr a0, vlenb3259; CHECK-NEXT:    slli a0, a0, 33260; CHECK-NEXT:    add sp, sp, a03261; CHECK-NEXT:    addi sp, sp, 163262; CHECK-NEXT:    ret3263  %res = call {<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>} @llvm.vector.deinterleave7.nxv14f32(<vscale x 14 x float> %arg)3264  ret {<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>} %res3265}3266 3267define {<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>} @vector_deinterleave_nxv4f32_nxv28f32(<vscale x 28 x float> %arg) nounwind {3268; CHECK-LABEL: vector_deinterleave_nxv4f32_nxv28f32:3269; CHECK:       # %bb.0:3270; CHECK-NEXT:    addi sp, sp, -163271; CHECK-NEXT:    csrr a0, vlenb3272; CHECK-NEXT:    slli a0, a0, 43273; CHECK-NEXT:    sub sp, sp, a03274; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma3275; CHECK-NEXT:    vmv1r.v v30, v213276; CHECK-NEXT:    vmv1r.v v28, v193277; CHECK-NEXT:    vmv1r.v v29, v203278; CHECK-NEXT:    vmv1r.v v26, v173279; CHECK-NEXT:    addi a0, sp, 163280; CHECK-NEXT:    vmv1r.v v27, v183281; CHECK-NEXT:    csrr a1, vlenb3282; CHECK-NEXT:    slli a1, a1, 33283; CHECK-NEXT:    add a1, sp, a13284; CHECK-NEXT:    addi a1, a1, 163285; CHECK-NEXT:    vmv1r.v v24, v153286; CHECK-NEXT:    vs8r.v v8, (a0)3287; CHECK-NEXT:    vmv1r.v v25, v163288; CHECK-NEXT:    vs8r.v v24, (a1)3289; CHECK-NEXT:    vlseg7e32.v v14, (a0)3290; CHECK-NEXT:    vlseg7e32.v v22, (a1)3291; CHECK-NEXT:    vmv2r.v v8, v143292; CHECK-NEXT:    vmv1r.v v9, v223293; CHECK-NEXT:    vmv1r.v v22, v153294; CHECK-NEXT:    vmv2r.v v12, v163295; CHECK-NEXT:    vmv1r.v v13, v243296; CHECK-NEXT:    vmv1r.v v24, v173297; CHECK-NEXT:    vmv2r.v v16, v183298; CHECK-NEXT:    vmv1r.v v17, v263299; CHECK-NEXT:    vmv1r.v v26, v193300; CHECK-NEXT:    vmv1r.v v21, v283301; CHECK-NEXT:    vmv2r.v v10, v223302; CHECK-NEXT:    vmv2r.v v14, v243303; CHECK-NEXT:    vmv2r.v v18, v263304; CHECK-NEXT:    csrr a0, vlenb3305; CHECK-NEXT:    slli a0, a0, 43306; CHECK-NEXT:    add sp, sp, a03307; CHECK-NEXT:    addi sp, sp, 163308; CHECK-NEXT:    ret3309  %res = call {<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>} @llvm.vector.deinterleave7.nxv28f32(<vscale x 28 x float> %arg)3310  ret {<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>} %res3311}3312 3313define {<vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>} @vector_deinterleave_nxv1f64_nxv7f64(<vscale x 7 x double> %arg) nounwind {3314; CHECK-LABEL: vector_deinterleave_nxv1f64_nxv7f64:3315; CHECK:       # %bb.0:3316; CHECK-NEXT:    addi sp, sp, -163317; CHECK-NEXT:    csrr a0, vlenb3318; CHECK-NEXT:    slli a0, a0, 33319; CHECK-NEXT:    sub sp, sp, a03320; CHECK-NEXT:    addi a0, sp, 163321; CHECK-NEXT:    vs8r.v v8, (a0)3322; CHECK-NEXT:    vsetvli a1, zero, e64, m1, ta, ma3323; CHECK-NEXT:    vlseg7e64.v v8, (a0)3324; CHECK-NEXT:    csrr a0, vlenb3325; CHECK-NEXT:    slli a0, a0, 33326; CHECK-NEXT:    add sp, sp, a03327; CHECK-NEXT:    addi sp, sp, 163328; CHECK-NEXT:    ret3329  %res = call {<vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>} @llvm.vector.deinterleave7.nxv7f64(<vscale x 7 x double> %arg)3330  ret {<vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>} %res3331}3332 3333define {<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>} @vector_deinterleave_nxv2f64_nxv14f64(<vscale x 14 x double> %arg) nounwind {3334; CHECK-LABEL: vector_deinterleave_nxv2f64_nxv14f64:3335; CHECK:       # %bb.0:3336; CHECK-NEXT:    addi sp, sp, -163337; CHECK-NEXT:    csrr a0, vlenb3338; CHECK-NEXT:    slli a0, a0, 43339; CHECK-NEXT:    sub sp, sp, a03340; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, ma3341; CHECK-NEXT:    vmv1r.v v30, v213342; CHECK-NEXT:    vmv1r.v v28, v193343; CHECK-NEXT:    vmv1r.v v29, v203344; CHECK-NEXT:    vmv1r.v v26, v173345; CHECK-NEXT:    addi a0, sp, 163346; CHECK-NEXT:    vmv1r.v v27, v183347; CHECK-NEXT:    csrr a1, vlenb3348; CHECK-NEXT:    slli a1, a1, 33349; CHECK-NEXT:    add a1, sp, a13350; CHECK-NEXT:    addi a1, a1, 163351; CHECK-NEXT:    vmv1r.v v24, v153352; CHECK-NEXT:    vs8r.v v8, (a0)3353; CHECK-NEXT:    vmv1r.v v25, v163354; CHECK-NEXT:    vs8r.v v24, (a1)3355; CHECK-NEXT:    vlseg7e64.v v14, (a0)3356; CHECK-NEXT:    vlseg7e64.v v22, (a1)3357; CHECK-NEXT:    vmv2r.v v8, v143358; CHECK-NEXT:    vmv1r.v v9, v223359; CHECK-NEXT:    vmv1r.v v22, v153360; CHECK-NEXT:    vmv2r.v v12, v163361; CHECK-NEXT:    vmv1r.v v13, v243362; CHECK-NEXT:    vmv1r.v v24, v173363; CHECK-NEXT:    vmv2r.v v16, v183364; CHECK-NEXT:    vmv1r.v v17, v263365; CHECK-NEXT:    vmv1r.v v26, v193366; CHECK-NEXT:    vmv1r.v v21, v283367; CHECK-NEXT:    vmv2r.v v10, v223368; CHECK-NEXT:    vmv2r.v v14, v243369; CHECK-NEXT:    vmv2r.v v18, v263370; CHECK-NEXT:    csrr a0, vlenb3371; CHECK-NEXT:    slli a0, a0, 43372; CHECK-NEXT:    add sp, sp, a03373; CHECK-NEXT:    addi sp, sp, 163374; CHECK-NEXT:    ret3375  %res = call {<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>} @llvm.vector.deinterleave7.nxv14f64(<vscale x 14 x double> %arg)3376  ret {<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>} %res3377}3378 3379define {<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>} @vector_deinterleave_nxv2f16_nxv16f16(<vscale x 16 x half> %arg) nounwind {3380; CHECK-LABEL: vector_deinterleave_nxv2f16_nxv16f16:3381; CHECK:       # %bb.0:3382; CHECK-NEXT:    addi sp, sp, -163383; CHECK-NEXT:    csrr a0, vlenb3384; CHECK-NEXT:    slli a0, a0, 23385; CHECK-NEXT:    sub sp, sp, a03386; CHECK-NEXT:    addi a0, sp, 163387; CHECK-NEXT:    vs4r.v v8, (a0)3388; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma3389; CHECK-NEXT:    vlseg8e16.v v8, (a0)3390; CHECK-NEXT:    csrr a0, vlenb3391; CHECK-NEXT:    slli a0, a0, 23392; CHECK-NEXT:    add sp, sp, a03393; CHECK-NEXT:    addi sp, sp, 163394; CHECK-NEXT:    ret3395  %res = call {<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>} @llvm.vector.deinterleave8.nxv16f16(<vscale x 16 x half> %arg)3396  ret {<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x half>} %res3397}3398 3399define {<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>} @vector_deinterleave_nxv4f16_nxv32f16(<vscale x 32 x half> %arg) nounwind {3400; CHECK-LABEL: vector_deinterleave_nxv4f16_nxv32f16:3401; CHECK:       # %bb.0:3402; CHECK-NEXT:    addi sp, sp, -163403; CHECK-NEXT:    csrr a0, vlenb3404; CHECK-NEXT:    slli a0, a0, 33405; CHECK-NEXT:    sub sp, sp, a03406; CHECK-NEXT:    addi a0, sp, 163407; CHECK-NEXT:    vs8r.v v8, (a0)3408; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, ma3409; CHECK-NEXT:    vlseg8e16.v v8, (a0)3410; CHECK-NEXT:    csrr a0, vlenb3411; CHECK-NEXT:    slli a0, a0, 33412; CHECK-NEXT:    add sp, sp, a03413; CHECK-NEXT:    addi sp, sp, 163414; CHECK-NEXT:    ret3415  %res = call {<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>} @llvm.vector.deinterleave8.nxv32f16(<vscale x 32 x half> %arg)3416  ret {<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x half>} %res3417}3418 3419define {<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>} @vector_deinterleave_nxv8f16_nxv64f16(<vscale x 64 x half> %arg) nounwind {3420; CHECK-LABEL: vector_deinterleave_nxv8f16_nxv64f16:3421; CHECK:       # %bb.0:3422; CHECK-NEXT:    addi sp, sp, -163423; CHECK-NEXT:    csrr a0, vlenb3424; CHECK-NEXT:    slli a0, a0, 43425; CHECK-NEXT:    sub sp, sp, a03426; CHECK-NEXT:    addi a0, sp, 163427; CHECK-NEXT:    csrr a1, vlenb3428; CHECK-NEXT:    slli a1, a1, 33429; CHECK-NEXT:    add a1, sp, a13430; CHECK-NEXT:    addi a1, a1, 163431; CHECK-NEXT:    vs8r.v v8, (a0)3432; CHECK-NEXT:    vs8r.v v16, (a1)3433; CHECK-NEXT:    vsetvli a2, zero, e16, m1, ta, ma3434; CHECK-NEXT:    vlseg8e16.v v0, (a0)3435; CHECK-NEXT:    vlseg8e16.v v22, (a1)3436; CHECK-NEXT:    vmv2r.v v8, v03437; CHECK-NEXT:    vmv1r.v v9, v223438; CHECK-NEXT:    vmv1r.v v22, v13439; CHECK-NEXT:    vmv2r.v v12, v23440; CHECK-NEXT:    vmv1r.v v13, v243441; CHECK-NEXT:    vmv1r.v v24, v33442; CHECK-NEXT:    vmv2r.v v16, v43443; CHECK-NEXT:    vmv1r.v v17, v263444; CHECK-NEXT:    vmv1r.v v26, v53445; CHECK-NEXT:    vmv2r.v v20, v63446; CHECK-NEXT:    vmv1r.v v21, v283447; CHECK-NEXT:    vmv1r.v v28, v73448; CHECK-NEXT:    vmv2r.v v10, v223449; CHECK-NEXT:    vmv2r.v v14, v243450; CHECK-NEXT:    vmv2r.v v18, v263451; CHECK-NEXT:    vmv2r.v v22, v283452; CHECK-NEXT:    csrr a0, vlenb3453; CHECK-NEXT:    slli a0, a0, 43454; CHECK-NEXT:    add sp, sp, a03455; CHECK-NEXT:    addi sp, sp, 163456; CHECK-NEXT:    ret3457  %res = call {<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>} @llvm.vector.deinterleave8.nxv64f16(<vscale x 64 x half> %arg)3458  ret {<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>} %res3459}3460 3461define {<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>} @vector_deinterleave_nxv2bf16_nxv16bf16(<vscale x 16 x bfloat> %arg) nounwind {3462; CHECK-LABEL: vector_deinterleave_nxv2bf16_nxv16bf16:3463; CHECK:       # %bb.0:3464; CHECK-NEXT:    addi sp, sp, -163465; CHECK-NEXT:    csrr a0, vlenb3466; CHECK-NEXT:    slli a0, a0, 23467; CHECK-NEXT:    sub sp, sp, a03468; CHECK-NEXT:    addi a0, sp, 163469; CHECK-NEXT:    vs4r.v v8, (a0)3470; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma3471; CHECK-NEXT:    vlseg8e16.v v8, (a0)3472; CHECK-NEXT:    csrr a0, vlenb3473; CHECK-NEXT:    slli a0, a0, 23474; CHECK-NEXT:    add sp, sp, a03475; CHECK-NEXT:    addi sp, sp, 163476; CHECK-NEXT:    ret3477  %res = call {<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>} @llvm.vector.deinterleave8.nxv16bf16(<vscale x 16 x bfloat> %arg)3478  ret {<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>} %res3479}3480 3481define {<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>} @vector_deinterleave_nxv4bf16_nxv32bf16(<vscale x 32 x bfloat> %arg) nounwind {3482; CHECK-LABEL: vector_deinterleave_nxv4bf16_nxv32bf16:3483; CHECK:       # %bb.0:3484; CHECK-NEXT:    addi sp, sp, -163485; CHECK-NEXT:    csrr a0, vlenb3486; CHECK-NEXT:    slli a0, a0, 33487; CHECK-NEXT:    sub sp, sp, a03488; CHECK-NEXT:    addi a0, sp, 163489; CHECK-NEXT:    vs8r.v v8, (a0)3490; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, ma3491; CHECK-NEXT:    vlseg8e16.v v8, (a0)3492; CHECK-NEXT:    csrr a0, vlenb3493; CHECK-NEXT:    slli a0, a0, 33494; CHECK-NEXT:    add sp, sp, a03495; CHECK-NEXT:    addi sp, sp, 163496; CHECK-NEXT:    ret3497  %res = call {<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>} @llvm.vector.deinterleave8.nxv32bf16(<vscale x 32 x bfloat> %arg)3498  ret {<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>} %res3499}3500 3501define {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>} @vector_deinterleave_nxv8bf16_nxv64bf16(<vscale x 64 x bfloat> %arg) nounwind {3502; CHECK-LABEL: vector_deinterleave_nxv8bf16_nxv64bf16:3503; CHECK:       # %bb.0:3504; CHECK-NEXT:    addi sp, sp, -163505; CHECK-NEXT:    csrr a0, vlenb3506; CHECK-NEXT:    slli a0, a0, 43507; CHECK-NEXT:    sub sp, sp, a03508; CHECK-NEXT:    addi a0, sp, 163509; CHECK-NEXT:    csrr a1, vlenb3510; CHECK-NEXT:    slli a1, a1, 33511; CHECK-NEXT:    add a1, sp, a13512; CHECK-NEXT:    addi a1, a1, 163513; CHECK-NEXT:    vs8r.v v8, (a0)3514; CHECK-NEXT:    vs8r.v v16, (a1)3515; CHECK-NEXT:    vsetvli a2, zero, e16, m1, ta, ma3516; CHECK-NEXT:    vlseg8e16.v v0, (a0)3517; CHECK-NEXT:    vlseg8e16.v v22, (a1)3518; CHECK-NEXT:    vmv2r.v v8, v03519; CHECK-NEXT:    vmv1r.v v9, v223520; CHECK-NEXT:    vmv1r.v v22, v13521; CHECK-NEXT:    vmv2r.v v12, v23522; CHECK-NEXT:    vmv1r.v v13, v243523; CHECK-NEXT:    vmv1r.v v24, v33524; CHECK-NEXT:    vmv2r.v v16, v43525; CHECK-NEXT:    vmv1r.v v17, v263526; CHECK-NEXT:    vmv1r.v v26, v53527; CHECK-NEXT:    vmv2r.v v20, v63528; CHECK-NEXT:    vmv1r.v v21, v283529; CHECK-NEXT:    vmv1r.v v28, v73530; CHECK-NEXT:    vmv2r.v v10, v223531; CHECK-NEXT:    vmv2r.v v14, v243532; CHECK-NEXT:    vmv2r.v v18, v263533; CHECK-NEXT:    vmv2r.v v22, v283534; CHECK-NEXT:    csrr a0, vlenb3535; CHECK-NEXT:    slli a0, a0, 43536; CHECK-NEXT:    add sp, sp, a03537; CHECK-NEXT:    addi sp, sp, 163538; CHECK-NEXT:    ret3539  %res = call {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>} @llvm.vector.deinterleave8.nxv64bf16(<vscale x 64 x bfloat> %arg)3540  ret {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>} %res3541}3542 3543define {<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>} @vector_deinterleave_nxv1f32_nxv8f32(<vscale x 8 x float> %arg) nounwind {3544; CHECK-LABEL: vector_deinterleave_nxv1f32_nxv8f32:3545; CHECK:       # %bb.0:3546; CHECK-NEXT:    addi sp, sp, -163547; CHECK-NEXT:    csrr a0, vlenb3548; CHECK-NEXT:    slli a0, a0, 23549; CHECK-NEXT:    sub sp, sp, a03550; CHECK-NEXT:    addi a0, sp, 163551; CHECK-NEXT:    vs4r.v v8, (a0)3552; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, ma3553; CHECK-NEXT:    vlseg8e32.v v8, (a0)3554; CHECK-NEXT:    csrr a0, vlenb3555; CHECK-NEXT:    slli a0, a0, 23556; CHECK-NEXT:    add sp, sp, a03557; CHECK-NEXT:    addi sp, sp, 163558; CHECK-NEXT:    ret3559  %res = call {<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>} @llvm.vector.deinterleave8.nxv8f32(<vscale x 8 x float> %arg)3560  ret {<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>} %res3561}3562 3563define {<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>} @vector_deinterleave_nxv2f32_nxv16f32(<vscale x 16 x float> %arg) nounwind {3564; CHECK-LABEL: vector_deinterleave_nxv2f32_nxv16f32:3565; CHECK:       # %bb.0:3566; CHECK-NEXT:    addi sp, sp, -163567; CHECK-NEXT:    csrr a0, vlenb3568; CHECK-NEXT:    slli a0, a0, 33569; CHECK-NEXT:    sub sp, sp, a03570; CHECK-NEXT:    addi a0, sp, 163571; CHECK-NEXT:    vs8r.v v8, (a0)3572; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, ma3573; CHECK-NEXT:    vlseg8e32.v v8, (a0)3574; CHECK-NEXT:    csrr a0, vlenb3575; CHECK-NEXT:    slli a0, a0, 33576; CHECK-NEXT:    add sp, sp, a03577; CHECK-NEXT:    addi sp, sp, 163578; CHECK-NEXT:    ret3579  %res = call {<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>} @llvm.vector.deinterleave8.nxv16f32(<vscale x 16 x float> %arg)3580  ret {<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x float>} %res3581}3582 3583define {<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>} @vector_deinterleave_nxv4f32_nxv32f32(<vscale x 32 x float> %arg) nounwind {3584; CHECK-LABEL: vector_deinterleave_nxv4f32_nxv32f32:3585; CHECK:       # %bb.0:3586; CHECK-NEXT:    addi sp, sp, -163587; CHECK-NEXT:    csrr a0, vlenb3588; CHECK-NEXT:    slli a0, a0, 43589; CHECK-NEXT:    sub sp, sp, a03590; CHECK-NEXT:    addi a0, sp, 163591; CHECK-NEXT:    csrr a1, vlenb3592; CHECK-NEXT:    slli a1, a1, 33593; CHECK-NEXT:    add a1, sp, a13594; CHECK-NEXT:    addi a1, a1, 163595; CHECK-NEXT:    vs8r.v v8, (a0)3596; CHECK-NEXT:    vs8r.v v16, (a1)3597; CHECK-NEXT:    vsetvli a2, zero, e32, m1, ta, ma3598; CHECK-NEXT:    vlseg8e32.v v0, (a0)3599; CHECK-NEXT:    vlseg8e32.v v22, (a1)3600; CHECK-NEXT:    vmv2r.v v8, v03601; CHECK-NEXT:    vmv1r.v v9, v223602; CHECK-NEXT:    vmv1r.v v22, v13603; CHECK-NEXT:    vmv2r.v v12, v23604; CHECK-NEXT:    vmv1r.v v13, v243605; CHECK-NEXT:    vmv1r.v v24, v33606; CHECK-NEXT:    vmv2r.v v16, v43607; CHECK-NEXT:    vmv1r.v v17, v263608; CHECK-NEXT:    vmv1r.v v26, v53609; CHECK-NEXT:    vmv2r.v v20, v63610; CHECK-NEXT:    vmv1r.v v21, v283611; CHECK-NEXT:    vmv1r.v v28, v73612; CHECK-NEXT:    vmv2r.v v10, v223613; CHECK-NEXT:    vmv2r.v v14, v243614; CHECK-NEXT:    vmv2r.v v18, v263615; CHECK-NEXT:    vmv2r.v v22, v283616; CHECK-NEXT:    csrr a0, vlenb3617; CHECK-NEXT:    slli a0, a0, 43618; CHECK-NEXT:    add sp, sp, a03619; CHECK-NEXT:    addi sp, sp, 163620; CHECK-NEXT:    ret3621  %res = call {<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>} @llvm.vector.deinterleave8.nxv32f32(<vscale x 32 x float> %arg)3622  ret {<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>} %res3623}3624 3625define {<vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>} @vector_deinterleave_nxv1f64_nxv8f64(<vscale x 8 x double> %arg) nounwind {3626; CHECK-LABEL: vector_deinterleave_nxv1f64_nxv8f64:3627; CHECK:       # %bb.0:3628; CHECK-NEXT:    addi sp, sp, -163629; CHECK-NEXT:    csrr a0, vlenb3630; CHECK-NEXT:    slli a0, a0, 33631; CHECK-NEXT:    sub sp, sp, a03632; CHECK-NEXT:    addi a0, sp, 163633; CHECK-NEXT:    vs8r.v v8, (a0)3634; CHECK-NEXT:    vsetvli a1, zero, e64, m1, ta, ma3635; CHECK-NEXT:    vlseg8e64.v v8, (a0)3636; CHECK-NEXT:    csrr a0, vlenb3637; CHECK-NEXT:    slli a0, a0, 33638; CHECK-NEXT:    add sp, sp, a03639; CHECK-NEXT:    addi sp, sp, 163640; CHECK-NEXT:    ret3641  %res = call {<vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>} @llvm.vector.deinterleave8.nxv8f64(<vscale x 8 x double> %arg)3642  ret {<vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x double>} %res3643}3644 3645define {<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>} @vector_deinterleave_nxv2f64_nxv16f64(<vscale x 16 x double> %arg) nounwind {3646; CHECK-LABEL: vector_deinterleave_nxv2f64_nxv16f64:3647; CHECK:       # %bb.0:3648; CHECK-NEXT:    addi sp, sp, -163649; CHECK-NEXT:    csrr a0, vlenb3650; CHECK-NEXT:    slli a0, a0, 43651; CHECK-NEXT:    sub sp, sp, a03652; CHECK-NEXT:    addi a0, sp, 163653; CHECK-NEXT:    csrr a1, vlenb3654; CHECK-NEXT:    slli a1, a1, 33655; CHECK-NEXT:    add a1, sp, a13656; CHECK-NEXT:    addi a1, a1, 163657; CHECK-NEXT:    vs8r.v v8, (a0)3658; CHECK-NEXT:    vs8r.v v16, (a1)3659; CHECK-NEXT:    vsetvli a2, zero, e64, m1, ta, ma3660; CHECK-NEXT:    vlseg8e64.v v0, (a0)3661; CHECK-NEXT:    vlseg8e64.v v22, (a1)3662; CHECK-NEXT:    vmv2r.v v8, v03663; CHECK-NEXT:    vmv1r.v v9, v223664; CHECK-NEXT:    vmv1r.v v22, v13665; CHECK-NEXT:    vmv2r.v v12, v23666; CHECK-NEXT:    vmv1r.v v13, v243667; CHECK-NEXT:    vmv1r.v v24, v33668; CHECK-NEXT:    vmv2r.v v16, v43669; CHECK-NEXT:    vmv1r.v v17, v263670; CHECK-NEXT:    vmv1r.v v26, v53671; CHECK-NEXT:    vmv2r.v v20, v63672; CHECK-NEXT:    vmv1r.v v21, v283673; CHECK-NEXT:    vmv1r.v v28, v73674; CHECK-NEXT:    vmv2r.v v10, v223675; CHECK-NEXT:    vmv2r.v v14, v243676; CHECK-NEXT:    vmv2r.v v18, v263677; CHECK-NEXT:    vmv2r.v v22, v283678; CHECK-NEXT:    csrr a0, vlenb3679; CHECK-NEXT:    slli a0, a0, 43680; CHECK-NEXT:    add sp, sp, a03681; CHECK-NEXT:    addi sp, sp, 163682; CHECK-NEXT:    ret3683  %res = call {<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>} @llvm.vector.deinterleave8.nxv16f64(<vscale x 16 x double> %arg)3684  ret {<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>} %res3685}3686 3687define <vscale x 16 x i8> @vector_deinterleave_nxv16i8_nxv32i8_oneactive(<vscale x 32 x i8> %vec) {3688; V-LABEL: vector_deinterleave_nxv16i8_nxv32i8_oneactive:3689; V:       # %bb.0:3690; V-NEXT:    vsetvli a0, zero, e8, m2, ta, ma3691; V-NEXT:    vnsrl.wi v12, v8, 03692; V-NEXT:    vmv.v.v v8, v123693; V-NEXT:    ret3694;3695; ZIP-LABEL: vector_deinterleave_nxv16i8_nxv32i8_oneactive:3696; ZIP:       # %bb.0:3697; ZIP-NEXT:    vsetvli a0, zero, e8, m2, ta, ma3698; ZIP-NEXT:    ri.vunzip2a.vv v12, v8, v103699; ZIP-NEXT:    vmv.v.v v8, v123700; ZIP-NEXT:    ret3701  %retval = call {<vscale x 16 x i8>, <vscale x 16 x i8>} @llvm.vector.deinterleave2.nxv32i8(<vscale x 32 x i8> %vec)3702  %ext = extractvalue {<vscale x 16 x i8>, <vscale x 16 x i8>} %retval, 03703  ret <vscale x 16 x i8> %ext3704}3705 3706define <vscale x 1 x float> @vector_deinterleave_nxv1f32_nxv8f32_oneactive(<vscale x 8 x float> %arg) nounwind {3707; CHECK-LABEL: vector_deinterleave_nxv1f32_nxv8f32_oneactive:3708; CHECK:       # %bb.0:3709; CHECK-NEXT:    addi sp, sp, -163710; CHECK-NEXT:    csrr a0, vlenb3711; CHECK-NEXT:    slli a0, a0, 23712; CHECK-NEXT:    sub sp, sp, a03713; CHECK-NEXT:    addi a0, sp, 163714; CHECK-NEXT:    vs4r.v v8, (a0)3715; CHECK-NEXT:    li a1, 323716; CHECK-NEXT:    vsetvli a2, zero, e32, mf2, ta, ma3717; CHECK-NEXT:    vlse32.v v8, (a0), a13718; CHECK-NEXT:    csrr a0, vlenb3719; CHECK-NEXT:    slli a0, a0, 23720; CHECK-NEXT:    add sp, sp, a03721; CHECK-NEXT:    addi sp, sp, 163722; CHECK-NEXT:    ret3723  %res = call {<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>} @llvm.vector.deinterleave8.nxv8f32(<vscale x 8 x float> %arg)3724  %ext = extractvalue {<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>} %res, 03725  ret <vscale x 1 x float> %ext3726}3727 3728define <vscale x 1 x float> @vector_deinterleave_nxv1f32_nxv8f32_oneactive2(<vscale x 8 x float> %arg) nounwind {3729; CHECK-LABEL: vector_deinterleave_nxv1f32_nxv8f32_oneactive2:3730; CHECK:       # %bb.0:3731; CHECK-NEXT:    addi sp, sp, -163732; CHECK-NEXT:    csrr a0, vlenb3733; CHECK-NEXT:    slli a0, a0, 23734; CHECK-NEXT:    sub sp, sp, a03735; CHECK-NEXT:    addi a0, sp, 163736; CHECK-NEXT:    addi a1, sp, 363737; CHECK-NEXT:    vs4r.v v8, (a0)3738; CHECK-NEXT:    li a0, 323739; CHECK-NEXT:    vsetvli a2, zero, e32, mf2, ta, ma3740; CHECK-NEXT:    vlse32.v v8, (a1), a03741; CHECK-NEXT:    csrr a0, vlenb3742; CHECK-NEXT:    slli a0, a0, 23743; CHECK-NEXT:    add sp, sp, a03744; CHECK-NEXT:    addi sp, sp, 163745; CHECK-NEXT:    ret3746  %res = call {<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>} @llvm.vector.deinterleave8.nxv8f32(<vscale x 8 x float> %arg)3747  %ext = extractvalue {<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x float>} %res, 53748  ret <vscale x 1 x float> %ext3749}3750 3751 3752define { <8 x float>, <8 x float> } @interleave_deinterleave2(<8 x float> %a, <8 x float> %b) {3753; V-LABEL: interleave_deinterleave2:3754; V:       # %bb.0: # %entry3755; V-NEXT:    vsetivli zero, 8, e32, m2, ta, ma3756; V-NEXT:    vwaddu.vv v12, v8, v103757; V-NEXT:    li a0, -13758; V-NEXT:    vwmaccu.vx v12, a0, v103759; V-NEXT:    li a0, 323760; V-NEXT:    vnsrl.wx v10, v12, a03761; V-NEXT:    vnsrl.wi v8, v12, 03762; V-NEXT:    ret3763;3764; ZIP-LABEL: interleave_deinterleave2:3765; ZIP:       # %bb.0: # %entry3766; ZIP-NEXT:    vsetivli zero, 16, e32, m4, ta, ma3767; ZIP-NEXT:    vmv2r.v v12, v103768; ZIP-NEXT:    li a0, 323769; ZIP-NEXT:    ri.vzip2a.vv v16, v8, v123770; ZIP-NEXT:    vsetivli zero, 8, e32, m2, ta, ma3771; ZIP-NEXT:    vnsrl.wx v10, v16, a03772; ZIP-NEXT:    vnsrl.wi v8, v16, 03773; ZIP-NEXT:    ret3774entry:3775  %0 = call <16 x float> @llvm.vector.interleave2.v16f32(<8 x float> %a, <8 x float> %b)3776  %1 = call { <8 x float>, <8 x float> } @llvm.vector.deinterleave2.v16f32(<16 x float> %0)3777  ret { <8 x float>, <8 x float> } %13778}3779 3780define <16 x float> @deinterleave_interleave2(<16 x float> %arg) {3781; V-LABEL: deinterleave_interleave2:3782; V:       # %bb.0: # %entry3783; V-NEXT:    li a0, 323784; V-NEXT:    vsetivli zero, 8, e32, m2, ta, ma3785; V-NEXT:    vnsrl.wi v12, v8, 03786; V-NEXT:    vnsrl.wx v14, v8, a03787; V-NEXT:    vwaddu.vv v8, v12, v143788; V-NEXT:    li a0, -13789; V-NEXT:    vwmaccu.vx v8, a0, v143790; V-NEXT:    ret3791;3792; ZIP-LABEL: deinterleave_interleave2:3793; ZIP:       # %bb.0: # %entry3794; ZIP-NEXT:    vsetivli zero, 8, e32, m2, ta, ma3795; ZIP-NEXT:    vnsrl.wi v12, v8, 03796; ZIP-NEXT:    li a0, 323797; ZIP-NEXT:    vnsrl.wx v16, v8, a03798; ZIP-NEXT:    vsetivli zero, 16, e32, m4, ta, ma3799; ZIP-NEXT:    ri.vzip2a.vv v8, v12, v163800; ZIP-NEXT:    ret3801entry:3802  %0 = call { <8 x float>, <8 x float> } @llvm.vector.deinterleave2.v16f32(<16 x float> %arg)3803  %a = extractvalue { <8 x float>, <8 x float> } %0, 03804  %b = extractvalue { <8 x float>, <8 x float> } %0, 13805  %res = call <16 x float> @llvm.vector.interleave2.v16f32(<8 x float> %a, <8 x float> %b)3806  ret <16 x float> %res3807}3808