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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zvfh | FileCheck -check-prefixes=CHECK %s3; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvfh | FileCheck -check-prefixes=CHECK %s4; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zvbb,+zvfh | FileCheck %s --check-prefix=ZVBB5; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvbb,+zvfh | FileCheck %s --check-prefix=ZVBB6; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zvbb,+zvfh,+experimental-xrivosvizip | FileCheck %s --check-prefix=ZIP7; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvbb,+zvfh,+experimental-xrivosvizip | FileCheck %s --check-prefix=ZIP8 9; Integers10 11define <32 x i1> @vector_interleave_v32i1_v16i1(<16 x i1> %a, <16 x i1> %b) {12; CHECK-LABEL: vector_interleave_v32i1_v16i1:13; CHECK: # %bb.0:14; CHECK-NEXT: li a0, 3215; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma16; CHECK-NEXT: vslideup.vi v0, v8, 217; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma18; CHECK-NEXT: vmv.v.i v8, 019; CHECK-NEXT: vmerge.vim v8, v8, 1, v020; CHECK-NEXT: vsetivli zero, 16, e8, m2, ta, ma21; CHECK-NEXT: vslidedown.vi v10, v8, 1622; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma23; CHECK-NEXT: vwaddu.vv v12, v8, v1024; CHECK-NEXT: li a1, -125; CHECK-NEXT: vwmaccu.vx v12, a1, v1026; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma27; CHECK-NEXT: vmsne.vi v0, v12, 028; CHECK-NEXT: ret29;30; ZVBB-LABEL: vector_interleave_v32i1_v16i1:31; ZVBB: # %bb.0:32; ZVBB-NEXT: li a0, 3233; ZVBB-NEXT: vsetivli zero, 4, e8, mf4, ta, ma34; ZVBB-NEXT: vslideup.vi v0, v8, 235; ZVBB-NEXT: vsetvli zero, a0, e8, m2, ta, ma36; ZVBB-NEXT: vmv.v.i v8, 037; ZVBB-NEXT: vmerge.vim v8, v8, 1, v038; ZVBB-NEXT: vsetivli zero, 16, e8, m2, ta, ma39; ZVBB-NEXT: vslidedown.vi v10, v8, 1640; ZVBB-NEXT: vsetivli zero, 16, e8, m1, ta, ma41; ZVBB-NEXT: vwsll.vi v12, v10, 842; ZVBB-NEXT: vwaddu.wv v12, v12, v843; ZVBB-NEXT: vsetvli zero, a0, e8, m2, ta, ma44; ZVBB-NEXT: vmsne.vi v0, v12, 045; ZVBB-NEXT: ret46;47; ZIP-LABEL: vector_interleave_v32i1_v16i1:48; ZIP: # %bb.0:49; ZIP-NEXT: li a0, 3250; ZIP-NEXT: vsetivli zero, 4, e8, mf4, ta, ma51; ZIP-NEXT: vslideup.vi v0, v8, 252; ZIP-NEXT: vsetvli zero, a0, e8, m2, ta, ma53; ZIP-NEXT: vmv.v.i v8, 054; ZIP-NEXT: vmerge.vim v8, v8, 1, v055; ZIP-NEXT: vsetivli zero, 16, e8, m2, ta, ma56; ZIP-NEXT: vslidedown.vi v10, v8, 1657; ZIP-NEXT: vsetvli zero, a0, e8, m2, ta, ma58; ZIP-NEXT: ri.vzip2a.vv v12, v8, v1059; ZIP-NEXT: vmsne.vi v0, v12, 060; ZIP-NEXT: ret61 %res = call <32 x i1> @llvm.vector.interleave2.v32i1(<16 x i1> %a, <16 x i1> %b)62 ret <32 x i1> %res63}64 65define <16 x i16> @vector_interleave_v16i16_v8i16(<8 x i16> %a, <8 x i16> %b) {66; CHECK-LABEL: vector_interleave_v16i16_v8i16:67; CHECK: # %bb.0:68; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma69; CHECK-NEXT: vmv1r.v v10, v970; CHECK-NEXT: vmv1r.v v11, v871; CHECK-NEXT: vwaddu.vv v8, v11, v1072; CHECK-NEXT: li a0, -173; CHECK-NEXT: vwmaccu.vx v8, a0, v1074; CHECK-NEXT: ret75;76; ZVBB-LABEL: vector_interleave_v16i16_v8i16:77; ZVBB: # %bb.0:78; ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma79; ZVBB-NEXT: vmv1r.v v10, v980; ZVBB-NEXT: vmv1r.v v11, v881; ZVBB-NEXT: vwsll.vi v8, v10, 1682; ZVBB-NEXT: vwaddu.wv v8, v8, v1183; ZVBB-NEXT: ret84;85; ZIP-LABEL: vector_interleave_v16i16_v8i16:86; ZIP: # %bb.0:87; ZIP-NEXT: vsetivli zero, 16, e16, m2, ta, ma88; ZIP-NEXT: vmv1r.v v12, v989; ZIP-NEXT: ri.vzip2a.vv v10, v8, v1290; ZIP-NEXT: vmv.v.v v8, v1091; ZIP-NEXT: ret92 %res = call <16 x i16> @llvm.vector.interleave2.v16i16(<8 x i16> %a, <8 x i16> %b)93 ret <16 x i16> %res94}95 96define <8 x i32> @vector_interleave_v8i32_v4i32(<4 x i32> %a, <4 x i32> %b) {97; CHECK-LABEL: vector_interleave_v8i32_v4i32:98; CHECK: # %bb.0:99; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma100; CHECK-NEXT: vmv1r.v v10, v9101; CHECK-NEXT: vmv1r.v v11, v8102; CHECK-NEXT: vwaddu.vv v8, v11, v10103; CHECK-NEXT: li a0, -1104; CHECK-NEXT: vwmaccu.vx v8, a0, v10105; CHECK-NEXT: ret106;107; ZVBB-LABEL: vector_interleave_v8i32_v4i32:108; ZVBB: # %bb.0:109; ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma110; ZVBB-NEXT: vmv1r.v v10, v9111; ZVBB-NEXT: vmv1r.v v11, v8112; ZVBB-NEXT: li a0, 32113; ZVBB-NEXT: vwsll.vx v8, v10, a0114; ZVBB-NEXT: vwaddu.wv v8, v8, v11115; ZVBB-NEXT: ret116;117; ZIP-LABEL: vector_interleave_v8i32_v4i32:118; ZIP: # %bb.0:119; ZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma120; ZIP-NEXT: vmv1r.v v12, v9121; ZIP-NEXT: ri.vzip2a.vv v10, v8, v12122; ZIP-NEXT: vmv.v.v v8, v10123; ZIP-NEXT: ret124 %res = call <8 x i32> @llvm.vector.interleave2.v8i32(<4 x i32> %a, <4 x i32> %b)125 ret <8 x i32> %res126}127 128define <4 x i64> @vector_interleave_v4i64_v2i64(<2 x i64> %a, <2 x i64> %b) {129; CHECK-LABEL: vector_interleave_v4i64_v2i64:130; CHECK: # %bb.0:131; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma132; CHECK-NEXT: vmv1r.v v10, v9133; CHECK-NEXT: lui a0, 12304134; CHECK-NEXT: addi a0, a0, 512135; CHECK-NEXT: vslideup.vi v8, v10, 2136; CHECK-NEXT: vmv.s.x v10, a0137; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma138; CHECK-NEXT: vsext.vf2 v12, v10139; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma140; CHECK-NEXT: vrgatherei16.vv v10, v8, v12141; CHECK-NEXT: vmv.v.v v8, v10142; CHECK-NEXT: ret143;144; ZVBB-LABEL: vector_interleave_v4i64_v2i64:145; ZVBB: # %bb.0:146; ZVBB-NEXT: vsetivli zero, 4, e64, m2, ta, ma147; ZVBB-NEXT: vmv1r.v v10, v9148; ZVBB-NEXT: lui a0, 12304149; ZVBB-NEXT: addi a0, a0, 512150; ZVBB-NEXT: vslideup.vi v8, v10, 2151; ZVBB-NEXT: vmv.s.x v10, a0152; ZVBB-NEXT: vsetvli zero, zero, e16, mf2, ta, ma153; ZVBB-NEXT: vsext.vf2 v12, v10154; ZVBB-NEXT: vsetvli zero, zero, e64, m2, ta, ma155; ZVBB-NEXT: vrgatherei16.vv v10, v8, v12156; ZVBB-NEXT: vmv.v.v v8, v10157; ZVBB-NEXT: ret158;159; ZIP-LABEL: vector_interleave_v4i64_v2i64:160; ZIP: # %bb.0:161; ZIP-NEXT: vsetivli zero, 4, e64, m2, ta, ma162; ZIP-NEXT: vmv1r.v v12, v9163; ZIP-NEXT: ri.vzip2a.vv v10, v8, v12164; ZIP-NEXT: vmv.v.v v8, v10165; ZIP-NEXT: ret166 %res = call <4 x i64> @llvm.vector.interleave2.v4i64(<2 x i64> %a, <2 x i64> %b)167 ret <4 x i64> %res168}169 170define <6 x i32> @vector_interleave3_v6i32_v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) nounwind {171; CHECK-LABEL: vector_interleave3_v6i32_v2i32:172; CHECK: # %bb.0:173; CHECK-NEXT: addi sp, sp, -16174; CHECK-NEXT: csrr a0, vlenb175; CHECK-NEXT: slli a0, a0, 1176; CHECK-NEXT: sub sp, sp, a0177; CHECK-NEXT: addi a0, sp, 16178; CHECK-NEXT: csrr a1, vlenb179; CHECK-NEXT: srli a1, a1, 1180; CHECK-NEXT: vsetvli a2, zero, e32, mf2, ta, ma181; CHECK-NEXT: vsseg3e32.v v8, (a0)182; CHECK-NEXT: add a2, a0, a1183; CHECK-NEXT: vle32.v v9, (a2)184; CHECK-NEXT: vle32.v v8, (a0)185; CHECK-NEXT: add a1, a2, a1186; CHECK-NEXT: vle32.v v10, (a1)187; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma188; CHECK-NEXT: vslideup.vi v8, v9, 2189; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma190; CHECK-NEXT: vslideup.vi v8, v10, 4191; CHECK-NEXT: csrr a0, vlenb192; CHECK-NEXT: slli a0, a0, 1193; CHECK-NEXT: add sp, sp, a0194; CHECK-NEXT: addi sp, sp, 16195; CHECK-NEXT: ret196;197; ZVBB-LABEL: vector_interleave3_v6i32_v2i32:198; ZVBB: # %bb.0:199; ZVBB-NEXT: addi sp, sp, -16200; ZVBB-NEXT: csrr a0, vlenb201; ZVBB-NEXT: slli a0, a0, 1202; ZVBB-NEXT: sub sp, sp, a0203; ZVBB-NEXT: addi a0, sp, 16204; ZVBB-NEXT: csrr a1, vlenb205; ZVBB-NEXT: srli a1, a1, 1206; ZVBB-NEXT: vsetvli a2, zero, e32, mf2, ta, ma207; ZVBB-NEXT: vsseg3e32.v v8, (a0)208; ZVBB-NEXT: add a2, a0, a1209; ZVBB-NEXT: vle32.v v9, (a2)210; ZVBB-NEXT: vle32.v v8, (a0)211; ZVBB-NEXT: add a1, a2, a1212; ZVBB-NEXT: vle32.v v10, (a1)213; ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma214; ZVBB-NEXT: vslideup.vi v8, v9, 2215; ZVBB-NEXT: vsetivli zero, 8, e32, m2, ta, ma216; ZVBB-NEXT: vslideup.vi v8, v10, 4217; ZVBB-NEXT: csrr a0, vlenb218; ZVBB-NEXT: slli a0, a0, 1219; ZVBB-NEXT: add sp, sp, a0220; ZVBB-NEXT: addi sp, sp, 16221; ZVBB-NEXT: ret222;223; ZIP-LABEL: vector_interleave3_v6i32_v2i32:224; ZIP: # %bb.0:225; ZIP-NEXT: addi sp, sp, -16226; ZIP-NEXT: csrr a0, vlenb227; ZIP-NEXT: slli a0, a0, 1228; ZIP-NEXT: sub sp, sp, a0229; ZIP-NEXT: addi a0, sp, 16230; ZIP-NEXT: csrr a1, vlenb231; ZIP-NEXT: srli a1, a1, 1232; ZIP-NEXT: vsetvli a2, zero, e32, mf2, ta, ma233; ZIP-NEXT: vsseg3e32.v v8, (a0)234; ZIP-NEXT: add a2, a0, a1235; ZIP-NEXT: vle32.v v9, (a2)236; ZIP-NEXT: vle32.v v8, (a0)237; ZIP-NEXT: add a1, a2, a1238; ZIP-NEXT: vle32.v v10, (a1)239; ZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma240; ZIP-NEXT: vslideup.vi v8, v9, 2241; ZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma242; ZIP-NEXT: vslideup.vi v8, v10, 4243; ZIP-NEXT: csrr a0, vlenb244; ZIP-NEXT: slli a0, a0, 1245; ZIP-NEXT: add sp, sp, a0246; ZIP-NEXT: addi sp, sp, 16247; ZIP-NEXT: ret248 %res = call <6 x i32> @llvm.vector.interleave3.v6i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c)249 ret <6 x i32> %res250}251 252define <8 x i32> @vector_interleave4_v8i32_v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c, <2 x i32> %d) nounwind {253; CHECK-LABEL: vector_interleave4_v8i32_v2i32:254; CHECK: # %bb.0:255; CHECK-NEXT: addi sp, sp, -16256; CHECK-NEXT: csrr a0, vlenb257; CHECK-NEXT: slli a0, a0, 1258; CHECK-NEXT: sub sp, sp, a0259; CHECK-NEXT: addi a0, sp, 16260; CHECK-NEXT: csrr a1, vlenb261; CHECK-NEXT: srli a1, a1, 1262; CHECK-NEXT: add a2, a0, a1263; CHECK-NEXT: vsetvli a3, zero, e32, mf2, ta, ma264; CHECK-NEXT: vsseg4e32.v v8, (a0)265; CHECK-NEXT: add a3, a2, a1266; CHECK-NEXT: add a1, a3, a1267; CHECK-NEXT: vle32.v v10, (a3)268; CHECK-NEXT: vle32.v v9, (a2)269; CHECK-NEXT: vle32.v v11, (a1)270; CHECK-NEXT: vle32.v v8, (a0)271; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma272; CHECK-NEXT: vslideup.vi v10, v11, 2273; CHECK-NEXT: vslideup.vi v8, v9, 2274; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma275; CHECK-NEXT: vslideup.vi v8, v10, 4276; CHECK-NEXT: csrr a0, vlenb277; CHECK-NEXT: slli a0, a0, 1278; CHECK-NEXT: add sp, sp, a0279; CHECK-NEXT: addi sp, sp, 16280; CHECK-NEXT: ret281;282; ZVBB-LABEL: vector_interleave4_v8i32_v2i32:283; ZVBB: # %bb.0:284; ZVBB-NEXT: addi sp, sp, -16285; ZVBB-NEXT: csrr a0, vlenb286; ZVBB-NEXT: slli a0, a0, 1287; ZVBB-NEXT: sub sp, sp, a0288; ZVBB-NEXT: addi a0, sp, 16289; ZVBB-NEXT: csrr a1, vlenb290; ZVBB-NEXT: srli a1, a1, 1291; ZVBB-NEXT: add a2, a0, a1292; ZVBB-NEXT: vsetvli a3, zero, e32, mf2, ta, ma293; ZVBB-NEXT: vsseg4e32.v v8, (a0)294; ZVBB-NEXT: add a3, a2, a1295; ZVBB-NEXT: add a1, a3, a1296; ZVBB-NEXT: vle32.v v10, (a3)297; ZVBB-NEXT: vle32.v v9, (a2)298; ZVBB-NEXT: vle32.v v11, (a1)299; ZVBB-NEXT: vle32.v v8, (a0)300; ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma301; ZVBB-NEXT: vslideup.vi v10, v11, 2302; ZVBB-NEXT: vslideup.vi v8, v9, 2303; ZVBB-NEXT: vsetivli zero, 8, e32, m2, ta, ma304; ZVBB-NEXT: vslideup.vi v8, v10, 4305; ZVBB-NEXT: csrr a0, vlenb306; ZVBB-NEXT: slli a0, a0, 1307; ZVBB-NEXT: add sp, sp, a0308; ZVBB-NEXT: addi sp, sp, 16309; ZVBB-NEXT: ret310;311; ZIP-LABEL: vector_interleave4_v8i32_v2i32:312; ZIP: # %bb.0:313; ZIP-NEXT: addi sp, sp, -16314; ZIP-NEXT: csrr a0, vlenb315; ZIP-NEXT: slli a0, a0, 1316; ZIP-NEXT: sub sp, sp, a0317; ZIP-NEXT: addi a0, sp, 16318; ZIP-NEXT: csrr a1, vlenb319; ZIP-NEXT: srli a1, a1, 1320; ZIP-NEXT: add a2, a0, a1321; ZIP-NEXT: vsetvli a3, zero, e32, mf2, ta, ma322; ZIP-NEXT: vsseg4e32.v v8, (a0)323; ZIP-NEXT: add a3, a2, a1324; ZIP-NEXT: add a1, a3, a1325; ZIP-NEXT: vle32.v v10, (a3)326; ZIP-NEXT: vle32.v v9, (a2)327; ZIP-NEXT: vle32.v v11, (a1)328; ZIP-NEXT: vle32.v v8, (a0)329; ZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma330; ZIP-NEXT: vslideup.vi v10, v11, 2331; ZIP-NEXT: vslideup.vi v8, v9, 2332; ZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma333; ZIP-NEXT: vslideup.vi v8, v10, 4334; ZIP-NEXT: csrr a0, vlenb335; ZIP-NEXT: slli a0, a0, 1336; ZIP-NEXT: add sp, sp, a0337; ZIP-NEXT: addi sp, sp, 16338; ZIP-NEXT: ret339 %res = call <8 x i32> @llvm.vector.interleave4.v8i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c, <2 x i32> %d)340 ret <8 x i32> %res341}342 343define <10 x i16> @vector_interleave5_v10i16_v2i16(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c, <2 x i16> %d, <2 x i16> %e) nounwind {344; CHECK-LABEL: vector_interleave5_v10i16_v2i16:345; CHECK: # %bb.0:346; CHECK-NEXT: addi sp, sp, -16347; CHECK-NEXT: csrr a0, vlenb348; CHECK-NEXT: slli a0, a0, 1349; CHECK-NEXT: sub sp, sp, a0350; CHECK-NEXT: addi a0, sp, 16351; CHECK-NEXT: csrr a1, vlenb352; CHECK-NEXT: srli a1, a1, 2353; CHECK-NEXT: add a2, a0, a1354; CHECK-NEXT: add a3, a2, a1355; CHECK-NEXT: vsetvli a4, zero, e16, mf4, ta, ma356; CHECK-NEXT: vsseg5e16.v v8, (a0)357; CHECK-NEXT: add a4, a3, a1358; CHECK-NEXT: vle16.v v9, (a2)359; CHECK-NEXT: vle16.v v11, (a4)360; CHECK-NEXT: vle16.v v12, (a3)361; CHECK-NEXT: vle16.v v8, (a0)362; CHECK-NEXT: add a1, a4, a1363; CHECK-NEXT: vle16.v v10, (a1)364; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma365; CHECK-NEXT: vslideup.vi v12, v11, 2366; CHECK-NEXT: vslideup.vi v8, v9, 2367; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma368; CHECK-NEXT: vslideup.vi v8, v12, 4369; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma370; CHECK-NEXT: vslideup.vi v8, v10, 8371; CHECK-NEXT: csrr a0, vlenb372; CHECK-NEXT: slli a0, a0, 1373; CHECK-NEXT: add sp, sp, a0374; CHECK-NEXT: addi sp, sp, 16375; CHECK-NEXT: ret376;377; ZVBB-LABEL: vector_interleave5_v10i16_v2i16:378; ZVBB: # %bb.0:379; ZVBB-NEXT: addi sp, sp, -16380; ZVBB-NEXT: csrr a0, vlenb381; ZVBB-NEXT: slli a0, a0, 1382; ZVBB-NEXT: sub sp, sp, a0383; ZVBB-NEXT: addi a0, sp, 16384; ZVBB-NEXT: csrr a1, vlenb385; ZVBB-NEXT: srli a1, a1, 2386; ZVBB-NEXT: add a2, a0, a1387; ZVBB-NEXT: add a3, a2, a1388; ZVBB-NEXT: vsetvli a4, zero, e16, mf4, ta, ma389; ZVBB-NEXT: vsseg5e16.v v8, (a0)390; ZVBB-NEXT: add a4, a3, a1391; ZVBB-NEXT: vle16.v v9, (a2)392; ZVBB-NEXT: vle16.v v11, (a4)393; ZVBB-NEXT: vle16.v v12, (a3)394; ZVBB-NEXT: vle16.v v8, (a0)395; ZVBB-NEXT: add a1, a4, a1396; ZVBB-NEXT: vle16.v v10, (a1)397; ZVBB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma398; ZVBB-NEXT: vslideup.vi v12, v11, 2399; ZVBB-NEXT: vslideup.vi v8, v9, 2400; ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma401; ZVBB-NEXT: vslideup.vi v8, v12, 4402; ZVBB-NEXT: vsetivli zero, 16, e16, m2, ta, ma403; ZVBB-NEXT: vslideup.vi v8, v10, 8404; ZVBB-NEXT: csrr a0, vlenb405; ZVBB-NEXT: slli a0, a0, 1406; ZVBB-NEXT: add sp, sp, a0407; ZVBB-NEXT: addi sp, sp, 16408; ZVBB-NEXT: ret409;410; ZIP-LABEL: vector_interleave5_v10i16_v2i16:411; ZIP: # %bb.0:412; ZIP-NEXT: addi sp, sp, -16413; ZIP-NEXT: csrr a0, vlenb414; ZIP-NEXT: slli a0, a0, 1415; ZIP-NEXT: sub sp, sp, a0416; ZIP-NEXT: addi a0, sp, 16417; ZIP-NEXT: csrr a1, vlenb418; ZIP-NEXT: srli a1, a1, 2419; ZIP-NEXT: add a2, a0, a1420; ZIP-NEXT: add a3, a2, a1421; ZIP-NEXT: vsetvli a4, zero, e16, mf4, ta, ma422; ZIP-NEXT: vsseg5e16.v v8, (a0)423; ZIP-NEXT: add a4, a3, a1424; ZIP-NEXT: vle16.v v9, (a2)425; ZIP-NEXT: vle16.v v11, (a4)426; ZIP-NEXT: vle16.v v12, (a3)427; ZIP-NEXT: vle16.v v8, (a0)428; ZIP-NEXT: add a1, a4, a1429; ZIP-NEXT: vle16.v v10, (a1)430; ZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma431; ZIP-NEXT: vslideup.vi v12, v11, 2432; ZIP-NEXT: vslideup.vi v8, v9, 2433; ZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma434; ZIP-NEXT: vslideup.vi v8, v12, 4435; ZIP-NEXT: vsetivli zero, 16, e16, m2, ta, ma436; ZIP-NEXT: vslideup.vi v8, v10, 8437; ZIP-NEXT: csrr a0, vlenb438; ZIP-NEXT: slli a0, a0, 1439; ZIP-NEXT: add sp, sp, a0440; ZIP-NEXT: addi sp, sp, 16441; ZIP-NEXT: ret442 %res = call <10 x i16> @llvm.vector.interleave5.v10i16(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c, <2 x i16> %d, <2 x i16> %e)443 ret <10 x i16> %res444}445 446define <12 x i16> @vector_interleave6_v12i16_v2i16(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c, <2 x i16> %d, <2 x i16> %e, <2 x i16> %f) nounwind {447; CHECK-LABEL: vector_interleave6_v12i16_v2i16:448; CHECK: # %bb.0:449; CHECK-NEXT: addi sp, sp, -16450; CHECK-NEXT: csrr a0, vlenb451; CHECK-NEXT: slli a0, a0, 1452; CHECK-NEXT: sub sp, sp, a0453; CHECK-NEXT: addi a0, sp, 16454; CHECK-NEXT: csrr a1, vlenb455; CHECK-NEXT: srli a1, a1, 2456; CHECK-NEXT: add a2, a0, a1457; CHECK-NEXT: add a3, a2, a1458; CHECK-NEXT: vsetvli a4, zero, e16, mf4, ta, ma459; CHECK-NEXT: vsseg6e16.v v8, (a0)460; CHECK-NEXT: vle16.v v9, (a2)461; CHECK-NEXT: add a2, a3, a1462; CHECK-NEXT: vle16.v v11, (a2)463; CHECK-NEXT: add a2, a2, a1464; CHECK-NEXT: vle16.v v12, (a3)465; CHECK-NEXT: add a1, a2, a1466; CHECK-NEXT: vle16.v v10, (a2)467; CHECK-NEXT: vle16.v v8, (a0)468; CHECK-NEXT: vle16.v v13, (a1)469; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma470; CHECK-NEXT: vslideup.vi v12, v11, 2471; CHECK-NEXT: vslideup.vi v8, v9, 2472; CHECK-NEXT: vslideup.vi v10, v13, 2473; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma474; CHECK-NEXT: vslideup.vi v8, v12, 4475; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma476; CHECK-NEXT: vslideup.vi v8, v10, 8477; CHECK-NEXT: csrr a0, vlenb478; CHECK-NEXT: slli a0, a0, 1479; CHECK-NEXT: add sp, sp, a0480; CHECK-NEXT: addi sp, sp, 16481; CHECK-NEXT: ret482;483; ZVBB-LABEL: vector_interleave6_v12i16_v2i16:484; ZVBB: # %bb.0:485; ZVBB-NEXT: addi sp, sp, -16486; ZVBB-NEXT: csrr a0, vlenb487; ZVBB-NEXT: slli a0, a0, 1488; ZVBB-NEXT: sub sp, sp, a0489; ZVBB-NEXT: addi a0, sp, 16490; ZVBB-NEXT: csrr a1, vlenb491; ZVBB-NEXT: srli a1, a1, 2492; ZVBB-NEXT: add a2, a0, a1493; ZVBB-NEXT: add a3, a2, a1494; ZVBB-NEXT: vsetvli a4, zero, e16, mf4, ta, ma495; ZVBB-NEXT: vsseg6e16.v v8, (a0)496; ZVBB-NEXT: vle16.v v9, (a2)497; ZVBB-NEXT: add a2, a3, a1498; ZVBB-NEXT: vle16.v v11, (a2)499; ZVBB-NEXT: add a2, a2, a1500; ZVBB-NEXT: vle16.v v12, (a3)501; ZVBB-NEXT: add a1, a2, a1502; ZVBB-NEXT: vle16.v v10, (a2)503; ZVBB-NEXT: vle16.v v8, (a0)504; ZVBB-NEXT: vle16.v v13, (a1)505; ZVBB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma506; ZVBB-NEXT: vslideup.vi v12, v11, 2507; ZVBB-NEXT: vslideup.vi v8, v9, 2508; ZVBB-NEXT: vslideup.vi v10, v13, 2509; ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma510; ZVBB-NEXT: vslideup.vi v8, v12, 4511; ZVBB-NEXT: vsetivli zero, 16, e16, m2, ta, ma512; ZVBB-NEXT: vslideup.vi v8, v10, 8513; ZVBB-NEXT: csrr a0, vlenb514; ZVBB-NEXT: slli a0, a0, 1515; ZVBB-NEXT: add sp, sp, a0516; ZVBB-NEXT: addi sp, sp, 16517; ZVBB-NEXT: ret518;519; ZIP-LABEL: vector_interleave6_v12i16_v2i16:520; ZIP: # %bb.0:521; ZIP-NEXT: addi sp, sp, -16522; ZIP-NEXT: csrr a0, vlenb523; ZIP-NEXT: slli a0, a0, 1524; ZIP-NEXT: sub sp, sp, a0525; ZIP-NEXT: addi a0, sp, 16526; ZIP-NEXT: csrr a1, vlenb527; ZIP-NEXT: srli a1, a1, 2528; ZIP-NEXT: add a2, a0, a1529; ZIP-NEXT: add a3, a2, a1530; ZIP-NEXT: vsetvli a4, zero, e16, mf4, ta, ma531; ZIP-NEXT: vsseg6e16.v v8, (a0)532; ZIP-NEXT: vle16.v v9, (a2)533; ZIP-NEXT: add a2, a3, a1534; ZIP-NEXT: vle16.v v11, (a2)535; ZIP-NEXT: add a2, a2, a1536; ZIP-NEXT: vle16.v v12, (a3)537; ZIP-NEXT: add a1, a2, a1538; ZIP-NEXT: vle16.v v10, (a2)539; ZIP-NEXT: vle16.v v8, (a0)540; ZIP-NEXT: vle16.v v13, (a1)541; ZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma542; ZIP-NEXT: vslideup.vi v12, v11, 2543; ZIP-NEXT: vslideup.vi v8, v9, 2544; ZIP-NEXT: vslideup.vi v10, v13, 2545; ZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma546; ZIP-NEXT: vslideup.vi v8, v12, 4547; ZIP-NEXT: vsetivli zero, 16, e16, m2, ta, ma548; ZIP-NEXT: vslideup.vi v8, v10, 8549; ZIP-NEXT: csrr a0, vlenb550; ZIP-NEXT: slli a0, a0, 1551; ZIP-NEXT: add sp, sp, a0552; ZIP-NEXT: addi sp, sp, 16553; ZIP-NEXT: ret554 %res = call <12 x i16> @llvm.vector.interleave6.v12i16(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c, <2 x i16> %d, <2 x i16> %e, <2 x i16> %f)555 ret <12 x i16> %res556}557 558define <14 x i8> @vector_interleave7_v14i8_v2i8(<2 x i8> %a, <2 x i8> %b, <2 x i8> %c, <2 x i8> %d, <2 x i8> %e, <2 x i8> %f, <2 x i8> %g) nounwind {559; CHECK-LABEL: vector_interleave7_v14i8_v2i8:560; CHECK: # %bb.0:561; CHECK-NEXT: addi sp, sp, -16562; CHECK-NEXT: csrr a0, vlenb563; CHECK-NEXT: sub sp, sp, a0564; CHECK-NEXT: addi a0, sp, 16565; CHECK-NEXT: csrr a1, vlenb566; CHECK-NEXT: srli a1, a1, 3567; CHECK-NEXT: add a2, a0, a1568; CHECK-NEXT: add a3, a2, a1569; CHECK-NEXT: add a4, a3, a1570; CHECK-NEXT: vsetvli a5, zero, e8, mf8, ta, ma571; CHECK-NEXT: vsseg7e8.v v8, (a0)572; CHECK-NEXT: vle8.v v9, (a4)573; CHECK-NEXT: add a4, a4, a1574; CHECK-NEXT: vle8.v v10, (a2)575; CHECK-NEXT: add a2, a4, a1576; CHECK-NEXT: add a1, a2, a1577; CHECK-NEXT: vle8.v v11, (a2)578; CHECK-NEXT: vle8.v v12, (a4)579; CHECK-NEXT: vle8.v v8, (a0)580; CHECK-NEXT: vle8.v v13, (a1)581; CHECK-NEXT: vle8.v v14, (a3)582; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, ma583; CHECK-NEXT: vslideup.vi v12, v11, 2584; CHECK-NEXT: vslideup.vi v8, v10, 2585; CHECK-NEXT: vsetivli zero, 6, e8, mf2, tu, ma586; CHECK-NEXT: vslideup.vi v12, v13, 4587; CHECK-NEXT: vslideup.vi v8, v14, 4588; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma589; CHECK-NEXT: vslideup.vi v8, v9, 6590; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma591; CHECK-NEXT: vslideup.vi v8, v12, 8592; CHECK-NEXT: csrr a0, vlenb593; CHECK-NEXT: add sp, sp, a0594; CHECK-NEXT: addi sp, sp, 16595; CHECK-NEXT: ret596;597; ZVBB-LABEL: vector_interleave7_v14i8_v2i8:598; ZVBB: # %bb.0:599; ZVBB-NEXT: addi sp, sp, -16600; ZVBB-NEXT: csrr a0, vlenb601; ZVBB-NEXT: sub sp, sp, a0602; ZVBB-NEXT: addi a0, sp, 16603; ZVBB-NEXT: csrr a1, vlenb604; ZVBB-NEXT: srli a1, a1, 3605; ZVBB-NEXT: add a2, a0, a1606; ZVBB-NEXT: add a3, a2, a1607; ZVBB-NEXT: add a4, a3, a1608; ZVBB-NEXT: vsetvli a5, zero, e8, mf8, ta, ma609; ZVBB-NEXT: vsseg7e8.v v8, (a0)610; ZVBB-NEXT: vle8.v v9, (a4)611; ZVBB-NEXT: add a4, a4, a1612; ZVBB-NEXT: vle8.v v10, (a2)613; ZVBB-NEXT: add a2, a4, a1614; ZVBB-NEXT: add a1, a2, a1615; ZVBB-NEXT: vle8.v v11, (a2)616; ZVBB-NEXT: vle8.v v12, (a4)617; ZVBB-NEXT: vle8.v v8, (a0)618; ZVBB-NEXT: vle8.v v13, (a1)619; ZVBB-NEXT: vle8.v v14, (a3)620; ZVBB-NEXT: vsetivli zero, 4, e8, mf2, tu, ma621; ZVBB-NEXT: vslideup.vi v12, v11, 2622; ZVBB-NEXT: vslideup.vi v8, v10, 2623; ZVBB-NEXT: vsetivli zero, 6, e8, mf2, tu, ma624; ZVBB-NEXT: vslideup.vi v12, v13, 4625; ZVBB-NEXT: vslideup.vi v8, v14, 4626; ZVBB-NEXT: vsetivli zero, 8, e8, mf2, ta, ma627; ZVBB-NEXT: vslideup.vi v8, v9, 6628; ZVBB-NEXT: vsetivli zero, 16, e8, m1, ta, ma629; ZVBB-NEXT: vslideup.vi v8, v12, 8630; ZVBB-NEXT: csrr a0, vlenb631; ZVBB-NEXT: add sp, sp, a0632; ZVBB-NEXT: addi sp, sp, 16633; ZVBB-NEXT: ret634;635; ZIP-LABEL: vector_interleave7_v14i8_v2i8:636; ZIP: # %bb.0:637; ZIP-NEXT: addi sp, sp, -16638; ZIP-NEXT: csrr a0, vlenb639; ZIP-NEXT: sub sp, sp, a0640; ZIP-NEXT: addi a0, sp, 16641; ZIP-NEXT: csrr a1, vlenb642; ZIP-NEXT: srli a1, a1, 3643; ZIP-NEXT: add a2, a0, a1644; ZIP-NEXT: add a3, a2, a1645; ZIP-NEXT: add a4, a3, a1646; ZIP-NEXT: vsetvli a5, zero, e8, mf8, ta, ma647; ZIP-NEXT: vsseg7e8.v v8, (a0)648; ZIP-NEXT: vle8.v v9, (a4)649; ZIP-NEXT: add a4, a4, a1650; ZIP-NEXT: vle8.v v10, (a2)651; ZIP-NEXT: add a2, a4, a1652; ZIP-NEXT: add a1, a2, a1653; ZIP-NEXT: vle8.v v11, (a2)654; ZIP-NEXT: vle8.v v12, (a4)655; ZIP-NEXT: vle8.v v8, (a0)656; ZIP-NEXT: vle8.v v13, (a1)657; ZIP-NEXT: vle8.v v14, (a3)658; ZIP-NEXT: vsetivli zero, 4, e8, mf2, tu, ma659; ZIP-NEXT: vslideup.vi v12, v11, 2660; ZIP-NEXT: vslideup.vi v8, v10, 2661; ZIP-NEXT: vsetivli zero, 6, e8, mf2, tu, ma662; ZIP-NEXT: vslideup.vi v12, v13, 4663; ZIP-NEXT: vslideup.vi v8, v14, 4664; ZIP-NEXT: vsetivli zero, 8, e8, mf2, ta, ma665; ZIP-NEXT: vslideup.vi v8, v9, 6666; ZIP-NEXT: vsetivli zero, 16, e8, m1, ta, ma667; ZIP-NEXT: vslideup.vi v8, v12, 8668; ZIP-NEXT: csrr a0, vlenb669; ZIP-NEXT: add sp, sp, a0670; ZIP-NEXT: addi sp, sp, 16671; ZIP-NEXT: ret672 %res = call <14 x i8> @llvm.vector.interleave7.v14i8(<2 x i8> %a, <2 x i8> %b, <2 x i8> %c, <2 x i8> %d, <2 x i8> %e, <2 x i8> %f, <2 x i8> %g)673 ret <14 x i8> %res674}675 676define <16 x i8> @vector_interleave8_v16i8_v2i8(<2 x i8> %a, <2 x i8> %b, <2 x i8> %c, <2 x i8> %d, <2 x i8> %e, <2 x i8> %f, <2 x i8> %g, <2 x i8> %h) nounwind {677; CHECK-LABEL: vector_interleave8_v16i8_v2i8:678; CHECK: # %bb.0:679; CHECK-NEXT: addi sp, sp, -16680; CHECK-NEXT: csrr a0, vlenb681; CHECK-NEXT: sub sp, sp, a0682; CHECK-NEXT: addi a0, sp, 16683; CHECK-NEXT: csrr a1, vlenb684; CHECK-NEXT: srli a1, a1, 3685; CHECK-NEXT: add a2, a0, a1686; CHECK-NEXT: add a3, a2, a1687; CHECK-NEXT: add a4, a3, a1688; CHECK-NEXT: add a5, a4, a1689; CHECK-NEXT: add a6, a5, a1690; CHECK-NEXT: vsetvli a7, zero, e8, mf8, ta, ma691; CHECK-NEXT: vsseg8e8.v v8, (a0)692; CHECK-NEXT: vle8.v v9, (a6)693; CHECK-NEXT: add a6, a6, a1694; CHECK-NEXT: vle8.v v10, (a5)695; CHECK-NEXT: vle8.v v11, (a6)696; CHECK-NEXT: add a1, a6, a1697; CHECK-NEXT: vle8.v v12, (a2)698; CHECK-NEXT: vle8.v v8, (a0)699; CHECK-NEXT: vle8.v v13, (a3)700; CHECK-NEXT: vle8.v v14, (a4)701; CHECK-NEXT: vle8.v v15, (a1)702; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, ma703; CHECK-NEXT: vslideup.vi v10, v9, 2704; CHECK-NEXT: vslideup.vi v8, v12, 2705; CHECK-NEXT: vsetivli zero, 6, e8, mf2, tu, ma706; CHECK-NEXT: vslideup.vi v10, v11, 4707; CHECK-NEXT: vslideup.vi v8, v13, 4708; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma709; CHECK-NEXT: vslideup.vi v10, v15, 6710; CHECK-NEXT: vslideup.vi v8, v14, 6711; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma712; CHECK-NEXT: vslideup.vi v8, v10, 8713; CHECK-NEXT: csrr a0, vlenb714; CHECK-NEXT: add sp, sp, a0715; CHECK-NEXT: addi sp, sp, 16716; CHECK-NEXT: ret717;718; ZVBB-LABEL: vector_interleave8_v16i8_v2i8:719; ZVBB: # %bb.0:720; ZVBB-NEXT: addi sp, sp, -16721; ZVBB-NEXT: csrr a0, vlenb722; ZVBB-NEXT: sub sp, sp, a0723; ZVBB-NEXT: addi a0, sp, 16724; ZVBB-NEXT: csrr a1, vlenb725; ZVBB-NEXT: srli a1, a1, 3726; ZVBB-NEXT: add a2, a0, a1727; ZVBB-NEXT: add a3, a2, a1728; ZVBB-NEXT: add a4, a3, a1729; ZVBB-NEXT: add a5, a4, a1730; ZVBB-NEXT: add a6, a5, a1731; ZVBB-NEXT: vsetvli a7, zero, e8, mf8, ta, ma732; ZVBB-NEXT: vsseg8e8.v v8, (a0)733; ZVBB-NEXT: vle8.v v9, (a6)734; ZVBB-NEXT: add a6, a6, a1735; ZVBB-NEXT: vle8.v v10, (a5)736; ZVBB-NEXT: vle8.v v11, (a6)737; ZVBB-NEXT: add a1, a6, a1738; ZVBB-NEXT: vle8.v v12, (a2)739; ZVBB-NEXT: vle8.v v8, (a0)740; ZVBB-NEXT: vle8.v v13, (a3)741; ZVBB-NEXT: vle8.v v14, (a4)742; ZVBB-NEXT: vle8.v v15, (a1)743; ZVBB-NEXT: vsetivli zero, 4, e8, mf2, tu, ma744; ZVBB-NEXT: vslideup.vi v10, v9, 2745; ZVBB-NEXT: vslideup.vi v8, v12, 2746; ZVBB-NEXT: vsetivli zero, 6, e8, mf2, tu, ma747; ZVBB-NEXT: vslideup.vi v10, v11, 4748; ZVBB-NEXT: vslideup.vi v8, v13, 4749; ZVBB-NEXT: vsetivli zero, 8, e8, mf2, ta, ma750; ZVBB-NEXT: vslideup.vi v10, v15, 6751; ZVBB-NEXT: vslideup.vi v8, v14, 6752; ZVBB-NEXT: vsetivli zero, 16, e8, m1, ta, ma753; ZVBB-NEXT: vslideup.vi v8, v10, 8754; ZVBB-NEXT: csrr a0, vlenb755; ZVBB-NEXT: add sp, sp, a0756; ZVBB-NEXT: addi sp, sp, 16757; ZVBB-NEXT: ret758;759; ZIP-LABEL: vector_interleave8_v16i8_v2i8:760; ZIP: # %bb.0:761; ZIP-NEXT: addi sp, sp, -16762; ZIP-NEXT: csrr a0, vlenb763; ZIP-NEXT: sub sp, sp, a0764; ZIP-NEXT: addi a0, sp, 16765; ZIP-NEXT: csrr a1, vlenb766; ZIP-NEXT: srli a1, a1, 3767; ZIP-NEXT: add a2, a0, a1768; ZIP-NEXT: add a3, a2, a1769; ZIP-NEXT: add a4, a3, a1770; ZIP-NEXT: add a5, a4, a1771; ZIP-NEXT: add a6, a5, a1772; ZIP-NEXT: vsetvli a7, zero, e8, mf8, ta, ma773; ZIP-NEXT: vsseg8e8.v v8, (a0)774; ZIP-NEXT: vle8.v v9, (a6)775; ZIP-NEXT: add a6, a6, a1776; ZIP-NEXT: vle8.v v10, (a5)777; ZIP-NEXT: vle8.v v11, (a6)778; ZIP-NEXT: add a1, a6, a1779; ZIP-NEXT: vle8.v v12, (a2)780; ZIP-NEXT: vle8.v v8, (a0)781; ZIP-NEXT: vle8.v v13, (a3)782; ZIP-NEXT: vle8.v v14, (a4)783; ZIP-NEXT: vle8.v v15, (a1)784; ZIP-NEXT: vsetivli zero, 4, e8, mf2, tu, ma785; ZIP-NEXT: vslideup.vi v10, v9, 2786; ZIP-NEXT: vslideup.vi v8, v12, 2787; ZIP-NEXT: vsetivli zero, 6, e8, mf2, tu, ma788; ZIP-NEXT: vslideup.vi v10, v11, 4789; ZIP-NEXT: vslideup.vi v8, v13, 4790; ZIP-NEXT: vsetivli zero, 8, e8, mf2, ta, ma791; ZIP-NEXT: vslideup.vi v10, v15, 6792; ZIP-NEXT: vslideup.vi v8, v14, 6793; ZIP-NEXT: vsetivli zero, 16, e8, m1, ta, ma794; ZIP-NEXT: vslideup.vi v8, v10, 8795; ZIP-NEXT: csrr a0, vlenb796; ZIP-NEXT: add sp, sp, a0797; ZIP-NEXT: addi sp, sp, 16798; ZIP-NEXT: ret799 %res = call <16 x i8> @llvm.vector.interleave8.v16i8(<2 x i8> %a, <2 x i8> %b, <2 x i8> %c, <2 x i8> %d, <2 x i8> %e, <2 x i8> %f, <2 x i8> %g, <2 x i8> %h)800 ret <16 x i8> %res801}802 803; Floats804 805define <4 x half> @vector_interleave_v4f16_v2f16(<2 x half> %a, <2 x half> %b) {806; CHECK-LABEL: vector_interleave_v4f16_v2f16:807; CHECK: # %bb.0:808; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma809; CHECK-NEXT: vwaddu.vv v10, v8, v9810; CHECK-NEXT: li a0, -1811; CHECK-NEXT: vwmaccu.vx v10, a0, v9812; CHECK-NEXT: vmv1r.v v8, v10813; CHECK-NEXT: ret814;815; ZVBB-LABEL: vector_interleave_v4f16_v2f16:816; ZVBB: # %bb.0:817; ZVBB-NEXT: vsetivli zero, 2, e16, mf4, ta, ma818; ZVBB-NEXT: vwsll.vi v10, v9, 16819; ZVBB-NEXT: vwaddu.wv v10, v10, v8820; ZVBB-NEXT: vmv1r.v v8, v10821; ZVBB-NEXT: ret822;823; ZIP-LABEL: vector_interleave_v4f16_v2f16:824; ZIP: # %bb.0:825; ZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma826; ZIP-NEXT: ri.vzip2a.vv v10, v8, v9827; ZIP-NEXT: vmv1r.v v8, v10828; ZIP-NEXT: ret829 %res = call <4 x half> @llvm.vector.interleave2.v4f16(<2 x half> %a, <2 x half> %b)830 ret <4 x half> %res831}832 833define <8 x half> @vector_interleave_v8f16_v4f16(<4 x half> %a, <4 x half> %b) {834; CHECK-LABEL: vector_interleave_v8f16_v4f16:835; CHECK: # %bb.0:836; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma837; CHECK-NEXT: vwaddu.vv v10, v8, v9838; CHECK-NEXT: li a0, -1839; CHECK-NEXT: vwmaccu.vx v10, a0, v9840; CHECK-NEXT: vmv1r.v v8, v10841; CHECK-NEXT: ret842;843; ZVBB-LABEL: vector_interleave_v8f16_v4f16:844; ZVBB: # %bb.0:845; ZVBB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma846; ZVBB-NEXT: vwsll.vi v10, v9, 16847; ZVBB-NEXT: vwaddu.wv v10, v10, v8848; ZVBB-NEXT: vmv1r.v v8, v10849; ZVBB-NEXT: ret850;851; ZIP-LABEL: vector_interleave_v8f16_v4f16:852; ZIP: # %bb.0:853; ZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma854; ZIP-NEXT: ri.vzip2a.vv v10, v8, v9855; ZIP-NEXT: vmv.v.v v8, v10856; ZIP-NEXT: ret857 %res = call <8 x half> @llvm.vector.interleave2.v8f16(<4 x half> %a, <4 x half> %b)858 ret <8 x half> %res859}860 861define <4 x float> @vector_interleave_v4f32_v2f32(<2 x float> %a, <2 x float> %b) {862; CHECK-LABEL: vector_interleave_v4f32_v2f32:863; CHECK: # %bb.0:864; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma865; CHECK-NEXT: vwaddu.vv v10, v8, v9866; CHECK-NEXT: li a0, -1867; CHECK-NEXT: vwmaccu.vx v10, a0, v9868; CHECK-NEXT: vmv1r.v v8, v10869; CHECK-NEXT: ret870;871; ZVBB-LABEL: vector_interleave_v4f32_v2f32:872; ZVBB: # %bb.0:873; ZVBB-NEXT: li a0, 32874; ZVBB-NEXT: vsetivli zero, 2, e32, mf2, ta, ma875; ZVBB-NEXT: vwsll.vx v10, v9, a0876; ZVBB-NEXT: vwaddu.wv v10, v10, v8877; ZVBB-NEXT: vmv1r.v v8, v10878; ZVBB-NEXT: ret879;880; ZIP-LABEL: vector_interleave_v4f32_v2f32:881; ZIP: # %bb.0:882; ZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma883; ZIP-NEXT: ri.vzip2a.vv v10, v8, v9884; ZIP-NEXT: vmv.v.v v8, v10885; ZIP-NEXT: ret886 %res = call <4 x float> @llvm.vector.interleave2.v4f32(<2 x float> %a, <2 x float> %b)887 ret <4 x float> %res888}889 890define <16 x half> @vector_interleave_v16f16_v8f16(<8 x half> %a, <8 x half> %b) {891; CHECK-LABEL: vector_interleave_v16f16_v8f16:892; CHECK: # %bb.0:893; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma894; CHECK-NEXT: vmv1r.v v10, v9895; CHECK-NEXT: vmv1r.v v11, v8896; CHECK-NEXT: vwaddu.vv v8, v11, v10897; CHECK-NEXT: li a0, -1898; CHECK-NEXT: vwmaccu.vx v8, a0, v10899; CHECK-NEXT: ret900;901; ZVBB-LABEL: vector_interleave_v16f16_v8f16:902; ZVBB: # %bb.0:903; ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma904; ZVBB-NEXT: vmv1r.v v10, v9905; ZVBB-NEXT: vmv1r.v v11, v8906; ZVBB-NEXT: vwsll.vi v8, v10, 16907; ZVBB-NEXT: vwaddu.wv v8, v8, v11908; ZVBB-NEXT: ret909;910; ZIP-LABEL: vector_interleave_v16f16_v8f16:911; ZIP: # %bb.0:912; ZIP-NEXT: vsetivli zero, 16, e16, m2, ta, ma913; ZIP-NEXT: vmv1r.v v12, v9914; ZIP-NEXT: ri.vzip2a.vv v10, v8, v12915; ZIP-NEXT: vmv.v.v v8, v10916; ZIP-NEXT: ret917 %res = call <16 x half> @llvm.vector.interleave2.v16f16(<8 x half> %a, <8 x half> %b)918 ret <16 x half> %res919}920 921define <8 x float> @vector_interleave_v8f32_v4f32(<4 x float> %a, <4 x float> %b) {922; CHECK-LABEL: vector_interleave_v8f32_v4f32:923; CHECK: # %bb.0:924; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma925; CHECK-NEXT: vmv1r.v v10, v9926; CHECK-NEXT: vmv1r.v v11, v8927; CHECK-NEXT: vwaddu.vv v8, v11, v10928; CHECK-NEXT: li a0, -1929; CHECK-NEXT: vwmaccu.vx v8, a0, v10930; CHECK-NEXT: ret931;932; ZVBB-LABEL: vector_interleave_v8f32_v4f32:933; ZVBB: # %bb.0:934; ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma935; ZVBB-NEXT: vmv1r.v v10, v9936; ZVBB-NEXT: vmv1r.v v11, v8937; ZVBB-NEXT: li a0, 32938; ZVBB-NEXT: vwsll.vx v8, v10, a0939; ZVBB-NEXT: vwaddu.wv v8, v8, v11940; ZVBB-NEXT: ret941;942; ZIP-LABEL: vector_interleave_v8f32_v4f32:943; ZIP: # %bb.0:944; ZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma945; ZIP-NEXT: vmv1r.v v12, v9946; ZIP-NEXT: ri.vzip2a.vv v10, v8, v12947; ZIP-NEXT: vmv.v.v v8, v10948; ZIP-NEXT: ret949 %res = call <8 x float> @llvm.vector.interleave2.v8f32(<4 x float> %a, <4 x float> %b)950 ret <8 x float> %res951}952 953define <4 x double> @vector_interleave_v4f64_v2f64(<2 x double> %a, <2 x double> %b) {954; CHECK-LABEL: vector_interleave_v4f64_v2f64:955; CHECK: # %bb.0:956; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma957; CHECK-NEXT: vmv1r.v v10, v9958; CHECK-NEXT: lui a0, 12304959; CHECK-NEXT: addi a0, a0, 512960; CHECK-NEXT: vslideup.vi v8, v10, 2961; CHECK-NEXT: vmv.s.x v10, a0962; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma963; CHECK-NEXT: vsext.vf2 v12, v10964; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma965; CHECK-NEXT: vrgatherei16.vv v10, v8, v12966; CHECK-NEXT: vmv.v.v v8, v10967; CHECK-NEXT: ret968;969; ZVBB-LABEL: vector_interleave_v4f64_v2f64:970; ZVBB: # %bb.0:971; ZVBB-NEXT: vsetivli zero, 4, e64, m2, ta, ma972; ZVBB-NEXT: vmv1r.v v10, v9973; ZVBB-NEXT: lui a0, 12304974; ZVBB-NEXT: addi a0, a0, 512975; ZVBB-NEXT: vslideup.vi v8, v10, 2976; ZVBB-NEXT: vmv.s.x v10, a0977; ZVBB-NEXT: vsetvli zero, zero, e16, mf2, ta, ma978; ZVBB-NEXT: vsext.vf2 v12, v10979; ZVBB-NEXT: vsetvli zero, zero, e64, m2, ta, ma980; ZVBB-NEXT: vrgatherei16.vv v10, v8, v12981; ZVBB-NEXT: vmv.v.v v8, v10982; ZVBB-NEXT: ret983;984; ZIP-LABEL: vector_interleave_v4f64_v2f64:985; ZIP: # %bb.0:986; ZIP-NEXT: vsetivli zero, 4, e64, m2, ta, ma987; ZIP-NEXT: vmv1r.v v12, v9988; ZIP-NEXT: ri.vzip2a.vv v10, v8, v12989; ZIP-NEXT: vmv.v.v v8, v10990; ZIP-NEXT: ret991 %res = call <4 x double> @llvm.vector.interleave2.v4f64(<2 x double> %a, <2 x double> %b)992 ret <4 x double> %res993}994 995define <6 x float> @vector_interleave3_v6f32_v2f32(<2 x float> %a, <2 x float> %b, <2 x float> %c) nounwind {996; CHECK-LABEL: vector_interleave3_v6f32_v2f32:997; CHECK: # %bb.0:998; CHECK-NEXT: addi sp, sp, -16999; CHECK-NEXT: csrr a0, vlenb1000; CHECK-NEXT: slli a0, a0, 11001; CHECK-NEXT: sub sp, sp, a01002; CHECK-NEXT: addi a0, sp, 161003; CHECK-NEXT: csrr a1, vlenb1004; CHECK-NEXT: srli a1, a1, 11005; CHECK-NEXT: vsetvli a2, zero, e32, mf2, ta, ma1006; CHECK-NEXT: vsseg3e32.v v8, (a0)1007; CHECK-NEXT: add a2, a0, a11008; CHECK-NEXT: vle32.v v9, (a2)1009; CHECK-NEXT: vle32.v v8, (a0)1010; CHECK-NEXT: add a1, a2, a11011; CHECK-NEXT: vle32.v v10, (a1)1012; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma1013; CHECK-NEXT: vslideup.vi v8, v9, 21014; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma1015; CHECK-NEXT: vslideup.vi v8, v10, 41016; CHECK-NEXT: csrr a0, vlenb1017; CHECK-NEXT: slli a0, a0, 11018; CHECK-NEXT: add sp, sp, a01019; CHECK-NEXT: addi sp, sp, 161020; CHECK-NEXT: ret1021;1022; ZVBB-LABEL: vector_interleave3_v6f32_v2f32:1023; ZVBB: # %bb.0:1024; ZVBB-NEXT: addi sp, sp, -161025; ZVBB-NEXT: csrr a0, vlenb1026; ZVBB-NEXT: slli a0, a0, 11027; ZVBB-NEXT: sub sp, sp, a01028; ZVBB-NEXT: addi a0, sp, 161029; ZVBB-NEXT: csrr a1, vlenb1030; ZVBB-NEXT: srli a1, a1, 11031; ZVBB-NEXT: vsetvli a2, zero, e32, mf2, ta, ma1032; ZVBB-NEXT: vsseg3e32.v v8, (a0)1033; ZVBB-NEXT: add a2, a0, a11034; ZVBB-NEXT: vle32.v v9, (a2)1035; ZVBB-NEXT: vle32.v v8, (a0)1036; ZVBB-NEXT: add a1, a2, a11037; ZVBB-NEXT: vle32.v v10, (a1)1038; ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma1039; ZVBB-NEXT: vslideup.vi v8, v9, 21040; ZVBB-NEXT: vsetivli zero, 8, e32, m2, ta, ma1041; ZVBB-NEXT: vslideup.vi v8, v10, 41042; ZVBB-NEXT: csrr a0, vlenb1043; ZVBB-NEXT: slli a0, a0, 11044; ZVBB-NEXT: add sp, sp, a01045; ZVBB-NEXT: addi sp, sp, 161046; ZVBB-NEXT: ret1047;1048; ZIP-LABEL: vector_interleave3_v6f32_v2f32:1049; ZIP: # %bb.0:1050; ZIP-NEXT: addi sp, sp, -161051; ZIP-NEXT: csrr a0, vlenb1052; ZIP-NEXT: slli a0, a0, 11053; ZIP-NEXT: sub sp, sp, a01054; ZIP-NEXT: addi a0, sp, 161055; ZIP-NEXT: csrr a1, vlenb1056; ZIP-NEXT: srli a1, a1, 11057; ZIP-NEXT: vsetvli a2, zero, e32, mf2, ta, ma1058; ZIP-NEXT: vsseg3e32.v v8, (a0)1059; ZIP-NEXT: add a2, a0, a11060; ZIP-NEXT: vle32.v v9, (a2)1061; ZIP-NEXT: vle32.v v8, (a0)1062; ZIP-NEXT: add a1, a2, a11063; ZIP-NEXT: vle32.v v10, (a1)1064; ZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma1065; ZIP-NEXT: vslideup.vi v8, v9, 21066; ZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma1067; ZIP-NEXT: vslideup.vi v8, v10, 41068; ZIP-NEXT: csrr a0, vlenb1069; ZIP-NEXT: slli a0, a0, 11070; ZIP-NEXT: add sp, sp, a01071; ZIP-NEXT: addi sp, sp, 161072; ZIP-NEXT: ret1073 %res = call <6 x float> @llvm.vector.interleave3.v6f32(<2 x float> %a, <2 x float> %b, <2 x float> %c)1074 ret <6 x float> %res1075}1076 1077define <8 x float> @vector_interleave4_v8f32_v2f32(<2 x float> %a, <2 x float> %b, <2 x float> %c, <2 x float> %d) nounwind {1078; CHECK-LABEL: vector_interleave4_v8f32_v2f32:1079; CHECK: # %bb.0:1080; CHECK-NEXT: addi sp, sp, -161081; CHECK-NEXT: csrr a0, vlenb1082; CHECK-NEXT: slli a0, a0, 11083; CHECK-NEXT: sub sp, sp, a01084; CHECK-NEXT: addi a0, sp, 161085; CHECK-NEXT: csrr a1, vlenb1086; CHECK-NEXT: srli a1, a1, 11087; CHECK-NEXT: add a2, a0, a11088; CHECK-NEXT: vsetvli a3, zero, e32, mf2, ta, ma1089; CHECK-NEXT: vsseg4e32.v v8, (a0)1090; CHECK-NEXT: add a3, a2, a11091; CHECK-NEXT: add a1, a3, a11092; CHECK-NEXT: vle32.v v10, (a3)1093; CHECK-NEXT: vle32.v v9, (a2)1094; CHECK-NEXT: vle32.v v11, (a1)1095; CHECK-NEXT: vle32.v v8, (a0)1096; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma1097; CHECK-NEXT: vslideup.vi v10, v11, 21098; CHECK-NEXT: vslideup.vi v8, v9, 21099; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma1100; CHECK-NEXT: vslideup.vi v8, v10, 41101; CHECK-NEXT: csrr a0, vlenb1102; CHECK-NEXT: slli a0, a0, 11103; CHECK-NEXT: add sp, sp, a01104; CHECK-NEXT: addi sp, sp, 161105; CHECK-NEXT: ret1106;1107; ZVBB-LABEL: vector_interleave4_v8f32_v2f32:1108; ZVBB: # %bb.0:1109; ZVBB-NEXT: addi sp, sp, -161110; ZVBB-NEXT: csrr a0, vlenb1111; ZVBB-NEXT: slli a0, a0, 11112; ZVBB-NEXT: sub sp, sp, a01113; ZVBB-NEXT: addi a0, sp, 161114; ZVBB-NEXT: csrr a1, vlenb1115; ZVBB-NEXT: srli a1, a1, 11116; ZVBB-NEXT: add a2, a0, a11117; ZVBB-NEXT: vsetvli a3, zero, e32, mf2, ta, ma1118; ZVBB-NEXT: vsseg4e32.v v8, (a0)1119; ZVBB-NEXT: add a3, a2, a11120; ZVBB-NEXT: add a1, a3, a11121; ZVBB-NEXT: vle32.v v10, (a3)1122; ZVBB-NEXT: vle32.v v9, (a2)1123; ZVBB-NEXT: vle32.v v11, (a1)1124; ZVBB-NEXT: vle32.v v8, (a0)1125; ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma1126; ZVBB-NEXT: vslideup.vi v10, v11, 21127; ZVBB-NEXT: vslideup.vi v8, v9, 21128; ZVBB-NEXT: vsetivli zero, 8, e32, m2, ta, ma1129; ZVBB-NEXT: vslideup.vi v8, v10, 41130; ZVBB-NEXT: csrr a0, vlenb1131; ZVBB-NEXT: slli a0, a0, 11132; ZVBB-NEXT: add sp, sp, a01133; ZVBB-NEXT: addi sp, sp, 161134; ZVBB-NEXT: ret1135;1136; ZIP-LABEL: vector_interleave4_v8f32_v2f32:1137; ZIP: # %bb.0:1138; ZIP-NEXT: addi sp, sp, -161139; ZIP-NEXT: csrr a0, vlenb1140; ZIP-NEXT: slli a0, a0, 11141; ZIP-NEXT: sub sp, sp, a01142; ZIP-NEXT: addi a0, sp, 161143; ZIP-NEXT: csrr a1, vlenb1144; ZIP-NEXT: srli a1, a1, 11145; ZIP-NEXT: add a2, a0, a11146; ZIP-NEXT: vsetvli a3, zero, e32, mf2, ta, ma1147; ZIP-NEXT: vsseg4e32.v v8, (a0)1148; ZIP-NEXT: add a3, a2, a11149; ZIP-NEXT: add a1, a3, a11150; ZIP-NEXT: vle32.v v10, (a3)1151; ZIP-NEXT: vle32.v v9, (a2)1152; ZIP-NEXT: vle32.v v11, (a1)1153; ZIP-NEXT: vle32.v v8, (a0)1154; ZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma1155; ZIP-NEXT: vslideup.vi v10, v11, 21156; ZIP-NEXT: vslideup.vi v8, v9, 21157; ZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma1158; ZIP-NEXT: vslideup.vi v8, v10, 41159; ZIP-NEXT: csrr a0, vlenb1160; ZIP-NEXT: slli a0, a0, 11161; ZIP-NEXT: add sp, sp, a01162; ZIP-NEXT: addi sp, sp, 161163; ZIP-NEXT: ret1164 %res = call <8 x float> @llvm.vector.interleave4.v8f32(<2 x float> %a, <2 x float> %b, <2 x float> %c, <2 x float> %d)1165 ret <8 x float> %res1166}1167 1168define <10 x half> @vector_interleave5_v10f16_v2f16(<2 x half> %a, <2 x half> %b, <2 x half> %c, <2 x half> %d, <2 x half> %e) nounwind {1169; CHECK-LABEL: vector_interleave5_v10f16_v2f16:1170; CHECK: # %bb.0:1171; CHECK-NEXT: addi sp, sp, -161172; CHECK-NEXT: csrr a0, vlenb1173; CHECK-NEXT: slli a0, a0, 11174; CHECK-NEXT: sub sp, sp, a01175; CHECK-NEXT: addi a0, sp, 161176; CHECK-NEXT: csrr a1, vlenb1177; CHECK-NEXT: srli a1, a1, 21178; CHECK-NEXT: add a2, a0, a11179; CHECK-NEXT: add a3, a2, a11180; CHECK-NEXT: vsetvli a4, zero, e16, mf4, ta, ma1181; CHECK-NEXT: vsseg5e16.v v8, (a0)1182; CHECK-NEXT: add a4, a3, a11183; CHECK-NEXT: vle16.v v9, (a2)1184; CHECK-NEXT: vle16.v v11, (a4)1185; CHECK-NEXT: vle16.v v12, (a3)1186; CHECK-NEXT: vle16.v v8, (a0)1187; CHECK-NEXT: add a1, a4, a11188; CHECK-NEXT: vle16.v v10, (a1)1189; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma1190; CHECK-NEXT: vslideup.vi v12, v11, 21191; CHECK-NEXT: vslideup.vi v8, v9, 21192; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma1193; CHECK-NEXT: vslideup.vi v8, v12, 41194; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma1195; CHECK-NEXT: vslideup.vi v8, v10, 81196; CHECK-NEXT: csrr a0, vlenb1197; CHECK-NEXT: slli a0, a0, 11198; CHECK-NEXT: add sp, sp, a01199; CHECK-NEXT: addi sp, sp, 161200; CHECK-NEXT: ret1201;1202; ZVBB-LABEL: vector_interleave5_v10f16_v2f16:1203; ZVBB: # %bb.0:1204; ZVBB-NEXT: addi sp, sp, -161205; ZVBB-NEXT: csrr a0, vlenb1206; ZVBB-NEXT: slli a0, a0, 11207; ZVBB-NEXT: sub sp, sp, a01208; ZVBB-NEXT: addi a0, sp, 161209; ZVBB-NEXT: csrr a1, vlenb1210; ZVBB-NEXT: srli a1, a1, 21211; ZVBB-NEXT: add a2, a0, a11212; ZVBB-NEXT: add a3, a2, a11213; ZVBB-NEXT: vsetvli a4, zero, e16, mf4, ta, ma1214; ZVBB-NEXT: vsseg5e16.v v8, (a0)1215; ZVBB-NEXT: add a4, a3, a11216; ZVBB-NEXT: vle16.v v9, (a2)1217; ZVBB-NEXT: vle16.v v11, (a4)1218; ZVBB-NEXT: vle16.v v12, (a3)1219; ZVBB-NEXT: vle16.v v8, (a0)1220; ZVBB-NEXT: add a1, a4, a11221; ZVBB-NEXT: vle16.v v10, (a1)1222; ZVBB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma1223; ZVBB-NEXT: vslideup.vi v12, v11, 21224; ZVBB-NEXT: vslideup.vi v8, v9, 21225; ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma1226; ZVBB-NEXT: vslideup.vi v8, v12, 41227; ZVBB-NEXT: vsetivli zero, 16, e16, m2, ta, ma1228; ZVBB-NEXT: vslideup.vi v8, v10, 81229; ZVBB-NEXT: csrr a0, vlenb1230; ZVBB-NEXT: slli a0, a0, 11231; ZVBB-NEXT: add sp, sp, a01232; ZVBB-NEXT: addi sp, sp, 161233; ZVBB-NEXT: ret1234;1235; ZIP-LABEL: vector_interleave5_v10f16_v2f16:1236; ZIP: # %bb.0:1237; ZIP-NEXT: addi sp, sp, -161238; ZIP-NEXT: csrr a0, vlenb1239; ZIP-NEXT: slli a0, a0, 11240; ZIP-NEXT: sub sp, sp, a01241; ZIP-NEXT: addi a0, sp, 161242; ZIP-NEXT: csrr a1, vlenb1243; ZIP-NEXT: srli a1, a1, 21244; ZIP-NEXT: add a2, a0, a11245; ZIP-NEXT: add a3, a2, a11246; ZIP-NEXT: vsetvli a4, zero, e16, mf4, ta, ma1247; ZIP-NEXT: vsseg5e16.v v8, (a0)1248; ZIP-NEXT: add a4, a3, a11249; ZIP-NEXT: vle16.v v9, (a2)1250; ZIP-NEXT: vle16.v v11, (a4)1251; ZIP-NEXT: vle16.v v12, (a3)1252; ZIP-NEXT: vle16.v v8, (a0)1253; ZIP-NEXT: add a1, a4, a11254; ZIP-NEXT: vle16.v v10, (a1)1255; ZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma1256; ZIP-NEXT: vslideup.vi v12, v11, 21257; ZIP-NEXT: vslideup.vi v8, v9, 21258; ZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma1259; ZIP-NEXT: vslideup.vi v8, v12, 41260; ZIP-NEXT: vsetivli zero, 16, e16, m2, ta, ma1261; ZIP-NEXT: vslideup.vi v8, v10, 81262; ZIP-NEXT: csrr a0, vlenb1263; ZIP-NEXT: slli a0, a0, 11264; ZIP-NEXT: add sp, sp, a01265; ZIP-NEXT: addi sp, sp, 161266; ZIP-NEXT: ret1267 %res = call <10 x half> @llvm.vector.interleave5.v10f16(<2 x half> %a, <2 x half> %b, <2 x half> %c, <2 x half> %d, <2 x half> %e)1268 ret <10 x half> %res1269}1270 1271define <12 x half> @vector_interleave6_v12f16_v2f16(<2 x half> %a, <2 x half> %b, <2 x half> %c, <2 x half> %d, <2 x half> %e, <2 x half> %f) nounwind {1272; CHECK-LABEL: vector_interleave6_v12f16_v2f16:1273; CHECK: # %bb.0:1274; CHECK-NEXT: addi sp, sp, -161275; CHECK-NEXT: csrr a0, vlenb1276; CHECK-NEXT: slli a0, a0, 11277; CHECK-NEXT: sub sp, sp, a01278; CHECK-NEXT: addi a0, sp, 161279; CHECK-NEXT: csrr a1, vlenb1280; CHECK-NEXT: srli a1, a1, 21281; CHECK-NEXT: add a2, a0, a11282; CHECK-NEXT: add a3, a2, a11283; CHECK-NEXT: vsetvli a4, zero, e16, mf4, ta, ma1284; CHECK-NEXT: vsseg6e16.v v8, (a0)1285; CHECK-NEXT: vle16.v v9, (a2)1286; CHECK-NEXT: add a2, a3, a11287; CHECK-NEXT: vle16.v v11, (a2)1288; CHECK-NEXT: add a2, a2, a11289; CHECK-NEXT: vle16.v v12, (a3)1290; CHECK-NEXT: add a1, a2, a11291; CHECK-NEXT: vle16.v v10, (a2)1292; CHECK-NEXT: vle16.v v8, (a0)1293; CHECK-NEXT: vle16.v v13, (a1)1294; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma1295; CHECK-NEXT: vslideup.vi v12, v11, 21296; CHECK-NEXT: vslideup.vi v8, v9, 21297; CHECK-NEXT: vslideup.vi v10, v13, 21298; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma1299; CHECK-NEXT: vslideup.vi v8, v12, 41300; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma1301; CHECK-NEXT: vslideup.vi v8, v10, 81302; CHECK-NEXT: csrr a0, vlenb1303; CHECK-NEXT: slli a0, a0, 11304; CHECK-NEXT: add sp, sp, a01305; CHECK-NEXT: addi sp, sp, 161306; CHECK-NEXT: ret1307;1308; ZVBB-LABEL: vector_interleave6_v12f16_v2f16:1309; ZVBB: # %bb.0:1310; ZVBB-NEXT: addi sp, sp, -161311; ZVBB-NEXT: csrr a0, vlenb1312; ZVBB-NEXT: slli a0, a0, 11313; ZVBB-NEXT: sub sp, sp, a01314; ZVBB-NEXT: addi a0, sp, 161315; ZVBB-NEXT: csrr a1, vlenb1316; ZVBB-NEXT: srli a1, a1, 21317; ZVBB-NEXT: add a2, a0, a11318; ZVBB-NEXT: add a3, a2, a11319; ZVBB-NEXT: vsetvli a4, zero, e16, mf4, ta, ma1320; ZVBB-NEXT: vsseg6e16.v v8, (a0)1321; ZVBB-NEXT: vle16.v v9, (a2)1322; ZVBB-NEXT: add a2, a3, a11323; ZVBB-NEXT: vle16.v v11, (a2)1324; ZVBB-NEXT: add a2, a2, a11325; ZVBB-NEXT: vle16.v v12, (a3)1326; ZVBB-NEXT: add a1, a2, a11327; ZVBB-NEXT: vle16.v v10, (a2)1328; ZVBB-NEXT: vle16.v v8, (a0)1329; ZVBB-NEXT: vle16.v v13, (a1)1330; ZVBB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma1331; ZVBB-NEXT: vslideup.vi v12, v11, 21332; ZVBB-NEXT: vslideup.vi v8, v9, 21333; ZVBB-NEXT: vslideup.vi v10, v13, 21334; ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma1335; ZVBB-NEXT: vslideup.vi v8, v12, 41336; ZVBB-NEXT: vsetivli zero, 16, e16, m2, ta, ma1337; ZVBB-NEXT: vslideup.vi v8, v10, 81338; ZVBB-NEXT: csrr a0, vlenb1339; ZVBB-NEXT: slli a0, a0, 11340; ZVBB-NEXT: add sp, sp, a01341; ZVBB-NEXT: addi sp, sp, 161342; ZVBB-NEXT: ret1343;1344; ZIP-LABEL: vector_interleave6_v12f16_v2f16:1345; ZIP: # %bb.0:1346; ZIP-NEXT: addi sp, sp, -161347; ZIP-NEXT: csrr a0, vlenb1348; ZIP-NEXT: slli a0, a0, 11349; ZIP-NEXT: sub sp, sp, a01350; ZIP-NEXT: addi a0, sp, 161351; ZIP-NEXT: csrr a1, vlenb1352; ZIP-NEXT: srli a1, a1, 21353; ZIP-NEXT: add a2, a0, a11354; ZIP-NEXT: add a3, a2, a11355; ZIP-NEXT: vsetvli a4, zero, e16, mf4, ta, ma1356; ZIP-NEXT: vsseg6e16.v v8, (a0)1357; ZIP-NEXT: vle16.v v9, (a2)1358; ZIP-NEXT: add a2, a3, a11359; ZIP-NEXT: vle16.v v11, (a2)1360; ZIP-NEXT: add a2, a2, a11361; ZIP-NEXT: vle16.v v12, (a3)1362; ZIP-NEXT: add a1, a2, a11363; ZIP-NEXT: vle16.v v10, (a2)1364; ZIP-NEXT: vle16.v v8, (a0)1365; ZIP-NEXT: vle16.v v13, (a1)1366; ZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma1367; ZIP-NEXT: vslideup.vi v12, v11, 21368; ZIP-NEXT: vslideup.vi v8, v9, 21369; ZIP-NEXT: vslideup.vi v10, v13, 21370; ZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma1371; ZIP-NEXT: vslideup.vi v8, v12, 41372; ZIP-NEXT: vsetivli zero, 16, e16, m2, ta, ma1373; ZIP-NEXT: vslideup.vi v8, v10, 81374; ZIP-NEXT: csrr a0, vlenb1375; ZIP-NEXT: slli a0, a0, 11376; ZIP-NEXT: add sp, sp, a01377; ZIP-NEXT: addi sp, sp, 161378; ZIP-NEXT: ret1379 %res = call <12 x half> @llvm.vector.interleave6.v12f16(<2 x half> %a, <2 x half> %b, <2 x half> %c, <2 x half> %d, <2 x half> %e, <2 x half> %f)1380 ret <12 x half> %res1381}1382 1383define <7 x half> @vector_interleave7_v7f16_v1f16(<1 x half> %a, <1 x half> %b, <1 x half> %c, <1 x half> %d, <1 x half> %e, <1 x half> %f, <1 x half> %g) nounwind {1384; CHECK-LABEL: vector_interleave7_v7f16_v1f16:1385; CHECK: # %bb.0:1386; CHECK-NEXT: addi sp, sp, -161387; CHECK-NEXT: csrr a0, vlenb1388; CHECK-NEXT: slli a0, a0, 11389; CHECK-NEXT: sub sp, sp, a01390; CHECK-NEXT: addi a0, sp, 161391; CHECK-NEXT: csrr a1, vlenb1392; CHECK-NEXT: srli a1, a1, 21393; CHECK-NEXT: add a2, a0, a11394; CHECK-NEXT: add a3, a2, a11395; CHECK-NEXT: add a4, a3, a11396; CHECK-NEXT: vsetvli a5, zero, e16, mf4, ta, ma1397; CHECK-NEXT: vsseg7e16.v v8, (a0)1398; CHECK-NEXT: vle16.v v9, (a4)1399; CHECK-NEXT: add a4, a4, a11400; CHECK-NEXT: vle16.v v10, (a2)1401; CHECK-NEXT: add a2, a4, a11402; CHECK-NEXT: add a1, a2, a11403; CHECK-NEXT: vle16.v v11, (a2)1404; CHECK-NEXT: vle16.v v12, (a4)1405; CHECK-NEXT: vle16.v v8, (a0)1406; CHECK-NEXT: vle16.v v13, (a1)1407; CHECK-NEXT: vle16.v v14, (a3)1408; CHECK-NEXT: vsetivli zero, 2, e16, mf2, tu, ma1409; CHECK-NEXT: vslideup.vi v12, v11, 11410; CHECK-NEXT: vslideup.vi v8, v10, 11411; CHECK-NEXT: vsetivli zero, 3, e16, mf2, tu, ma1412; CHECK-NEXT: vslideup.vi v12, v13, 21413; CHECK-NEXT: vslideup.vi v8, v14, 21414; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma1415; CHECK-NEXT: vslideup.vi v8, v9, 31416; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma1417; CHECK-NEXT: vslideup.vi v8, v12, 41418; CHECK-NEXT: csrr a0, vlenb1419; CHECK-NEXT: slli a0, a0, 11420; CHECK-NEXT: add sp, sp, a01421; CHECK-NEXT: addi sp, sp, 161422; CHECK-NEXT: ret1423;1424; ZVBB-LABEL: vector_interleave7_v7f16_v1f16:1425; ZVBB: # %bb.0:1426; ZVBB-NEXT: addi sp, sp, -161427; ZVBB-NEXT: csrr a0, vlenb1428; ZVBB-NEXT: slli a0, a0, 11429; ZVBB-NEXT: sub sp, sp, a01430; ZVBB-NEXT: addi a0, sp, 161431; ZVBB-NEXT: csrr a1, vlenb1432; ZVBB-NEXT: srli a1, a1, 21433; ZVBB-NEXT: add a2, a0, a11434; ZVBB-NEXT: add a3, a2, a11435; ZVBB-NEXT: add a4, a3, a11436; ZVBB-NEXT: vsetvli a5, zero, e16, mf4, ta, ma1437; ZVBB-NEXT: vsseg7e16.v v8, (a0)1438; ZVBB-NEXT: vle16.v v9, (a4)1439; ZVBB-NEXT: add a4, a4, a11440; ZVBB-NEXT: vle16.v v10, (a2)1441; ZVBB-NEXT: add a2, a4, a11442; ZVBB-NEXT: add a1, a2, a11443; ZVBB-NEXT: vle16.v v11, (a2)1444; ZVBB-NEXT: vle16.v v12, (a4)1445; ZVBB-NEXT: vle16.v v8, (a0)1446; ZVBB-NEXT: vle16.v v13, (a1)1447; ZVBB-NEXT: vle16.v v14, (a3)1448; ZVBB-NEXT: vsetivli zero, 2, e16, mf2, tu, ma1449; ZVBB-NEXT: vslideup.vi v12, v11, 11450; ZVBB-NEXT: vslideup.vi v8, v10, 11451; ZVBB-NEXT: vsetivli zero, 3, e16, mf2, tu, ma1452; ZVBB-NEXT: vslideup.vi v12, v13, 21453; ZVBB-NEXT: vslideup.vi v8, v14, 21454; ZVBB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma1455; ZVBB-NEXT: vslideup.vi v8, v9, 31456; ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma1457; ZVBB-NEXT: vslideup.vi v8, v12, 41458; ZVBB-NEXT: csrr a0, vlenb1459; ZVBB-NEXT: slli a0, a0, 11460; ZVBB-NEXT: add sp, sp, a01461; ZVBB-NEXT: addi sp, sp, 161462; ZVBB-NEXT: ret1463;1464; ZIP-LABEL: vector_interleave7_v7f16_v1f16:1465; ZIP: # %bb.0:1466; ZIP-NEXT: addi sp, sp, -161467; ZIP-NEXT: csrr a0, vlenb1468; ZIP-NEXT: slli a0, a0, 11469; ZIP-NEXT: sub sp, sp, a01470; ZIP-NEXT: addi a0, sp, 161471; ZIP-NEXT: csrr a1, vlenb1472; ZIP-NEXT: srli a1, a1, 21473; ZIP-NEXT: add a2, a0, a11474; ZIP-NEXT: add a3, a2, a11475; ZIP-NEXT: add a4, a3, a11476; ZIP-NEXT: vsetvli a5, zero, e16, mf4, ta, ma1477; ZIP-NEXT: vsseg7e16.v v8, (a0)1478; ZIP-NEXT: vle16.v v9, (a4)1479; ZIP-NEXT: add a4, a4, a11480; ZIP-NEXT: vle16.v v10, (a2)1481; ZIP-NEXT: add a2, a4, a11482; ZIP-NEXT: add a1, a2, a11483; ZIP-NEXT: vle16.v v11, (a2)1484; ZIP-NEXT: vle16.v v12, (a4)1485; ZIP-NEXT: vle16.v v8, (a0)1486; ZIP-NEXT: vle16.v v13, (a1)1487; ZIP-NEXT: vle16.v v14, (a3)1488; ZIP-NEXT: vsetivli zero, 2, e16, mf2, tu, ma1489; ZIP-NEXT: vslideup.vi v12, v11, 11490; ZIP-NEXT: vslideup.vi v8, v10, 11491; ZIP-NEXT: vsetivli zero, 3, e16, mf2, tu, ma1492; ZIP-NEXT: vslideup.vi v12, v13, 21493; ZIP-NEXT: vslideup.vi v8, v14, 21494; ZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma1495; ZIP-NEXT: vslideup.vi v8, v9, 31496; ZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma1497; ZIP-NEXT: vslideup.vi v8, v12, 41498; ZIP-NEXT: csrr a0, vlenb1499; ZIP-NEXT: slli a0, a0, 11500; ZIP-NEXT: add sp, sp, a01501; ZIP-NEXT: addi sp, sp, 161502; ZIP-NEXT: ret1503 %res = call <7 x half> @llvm.vector.interleave7.v7f16(<1 x half> %a, <1 x half> %b, <1 x half> %c, <1 x half> %d, <1 x half> %e, <1 x half> %f, <1 x half> %g)1504 ret <7 x half> %res1505}1506 1507define <8 x half> @vector_interleave8_v8f16_v1f16(<1 x half> %a, <1 x half> %b, <1 x half> %c, <1 x half> %d, <1 x half> %e, <1 x half> %f, <1 x half> %g, <1 x half> %h) nounwind {1508; CHECK-LABEL: vector_interleave8_v8f16_v1f16:1509; CHECK: # %bb.0:1510; CHECK-NEXT: addi sp, sp, -161511; CHECK-NEXT: csrr a0, vlenb1512; CHECK-NEXT: slli a0, a0, 11513; CHECK-NEXT: sub sp, sp, a01514; CHECK-NEXT: addi a0, sp, 161515; CHECK-NEXT: csrr a1, vlenb1516; CHECK-NEXT: srli a1, a1, 21517; CHECK-NEXT: add a2, a0, a11518; CHECK-NEXT: add a3, a2, a11519; CHECK-NEXT: add a4, a3, a11520; CHECK-NEXT: add a5, a4, a11521; CHECK-NEXT: add a6, a5, a11522; CHECK-NEXT: vsetvli a7, zero, e16, mf4, ta, ma1523; CHECK-NEXT: vsseg8e16.v v8, (a0)1524; CHECK-NEXT: vle16.v v9, (a6)1525; CHECK-NEXT: add a6, a6, a11526; CHECK-NEXT: vle16.v v10, (a5)1527; CHECK-NEXT: vle16.v v11, (a6)1528; CHECK-NEXT: add a1, a6, a11529; CHECK-NEXT: vle16.v v12, (a2)1530; CHECK-NEXT: vle16.v v8, (a0)1531; CHECK-NEXT: vle16.v v13, (a3)1532; CHECK-NEXT: vle16.v v14, (a4)1533; CHECK-NEXT: vle16.v v15, (a1)1534; CHECK-NEXT: vsetivli zero, 2, e16, mf2, tu, ma1535; CHECK-NEXT: vslideup.vi v10, v9, 11536; CHECK-NEXT: vslideup.vi v8, v12, 11537; CHECK-NEXT: vsetivli zero, 3, e16, mf2, tu, ma1538; CHECK-NEXT: vslideup.vi v10, v11, 21539; CHECK-NEXT: vslideup.vi v8, v13, 21540; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma1541; CHECK-NEXT: vslideup.vi v10, v15, 31542; CHECK-NEXT: vslideup.vi v8, v14, 31543; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma1544; CHECK-NEXT: vslideup.vi v8, v10, 41545; CHECK-NEXT: csrr a0, vlenb1546; CHECK-NEXT: slli a0, a0, 11547; CHECK-NEXT: add sp, sp, a01548; CHECK-NEXT: addi sp, sp, 161549; CHECK-NEXT: ret1550;1551; ZVBB-LABEL: vector_interleave8_v8f16_v1f16:1552; ZVBB: # %bb.0:1553; ZVBB-NEXT: addi sp, sp, -161554; ZVBB-NEXT: csrr a0, vlenb1555; ZVBB-NEXT: slli a0, a0, 11556; ZVBB-NEXT: sub sp, sp, a01557; ZVBB-NEXT: addi a0, sp, 161558; ZVBB-NEXT: csrr a1, vlenb1559; ZVBB-NEXT: srli a1, a1, 21560; ZVBB-NEXT: add a2, a0, a11561; ZVBB-NEXT: add a3, a2, a11562; ZVBB-NEXT: add a4, a3, a11563; ZVBB-NEXT: add a5, a4, a11564; ZVBB-NEXT: add a6, a5, a11565; ZVBB-NEXT: vsetvli a7, zero, e16, mf4, ta, ma1566; ZVBB-NEXT: vsseg8e16.v v8, (a0)1567; ZVBB-NEXT: vle16.v v9, (a6)1568; ZVBB-NEXT: add a6, a6, a11569; ZVBB-NEXT: vle16.v v10, (a5)1570; ZVBB-NEXT: vle16.v v11, (a6)1571; ZVBB-NEXT: add a1, a6, a11572; ZVBB-NEXT: vle16.v v12, (a2)1573; ZVBB-NEXT: vle16.v v8, (a0)1574; ZVBB-NEXT: vle16.v v13, (a3)1575; ZVBB-NEXT: vle16.v v14, (a4)1576; ZVBB-NEXT: vle16.v v15, (a1)1577; ZVBB-NEXT: vsetivli zero, 2, e16, mf2, tu, ma1578; ZVBB-NEXT: vslideup.vi v10, v9, 11579; ZVBB-NEXT: vslideup.vi v8, v12, 11580; ZVBB-NEXT: vsetivli zero, 3, e16, mf2, tu, ma1581; ZVBB-NEXT: vslideup.vi v10, v11, 21582; ZVBB-NEXT: vslideup.vi v8, v13, 21583; ZVBB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma1584; ZVBB-NEXT: vslideup.vi v10, v15, 31585; ZVBB-NEXT: vslideup.vi v8, v14, 31586; ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma1587; ZVBB-NEXT: vslideup.vi v8, v10, 41588; ZVBB-NEXT: csrr a0, vlenb1589; ZVBB-NEXT: slli a0, a0, 11590; ZVBB-NEXT: add sp, sp, a01591; ZVBB-NEXT: addi sp, sp, 161592; ZVBB-NEXT: ret1593;1594; ZIP-LABEL: vector_interleave8_v8f16_v1f16:1595; ZIP: # %bb.0:1596; ZIP-NEXT: addi sp, sp, -161597; ZIP-NEXT: csrr a0, vlenb1598; ZIP-NEXT: slli a0, a0, 11599; ZIP-NEXT: sub sp, sp, a01600; ZIP-NEXT: addi a0, sp, 161601; ZIP-NEXT: csrr a1, vlenb1602; ZIP-NEXT: srli a1, a1, 21603; ZIP-NEXT: add a2, a0, a11604; ZIP-NEXT: add a3, a2, a11605; ZIP-NEXT: add a4, a3, a11606; ZIP-NEXT: add a5, a4, a11607; ZIP-NEXT: add a6, a5, a11608; ZIP-NEXT: vsetvli a7, zero, e16, mf4, ta, ma1609; ZIP-NEXT: vsseg8e16.v v8, (a0)1610; ZIP-NEXT: vle16.v v9, (a6)1611; ZIP-NEXT: add a6, a6, a11612; ZIP-NEXT: vle16.v v10, (a5)1613; ZIP-NEXT: vle16.v v11, (a6)1614; ZIP-NEXT: add a1, a6, a11615; ZIP-NEXT: vle16.v v12, (a2)1616; ZIP-NEXT: vle16.v v8, (a0)1617; ZIP-NEXT: vle16.v v13, (a3)1618; ZIP-NEXT: vle16.v v14, (a4)1619; ZIP-NEXT: vle16.v v15, (a1)1620; ZIP-NEXT: vsetivli zero, 2, e16, mf2, tu, ma1621; ZIP-NEXT: vslideup.vi v10, v9, 11622; ZIP-NEXT: vslideup.vi v8, v12, 11623; ZIP-NEXT: vsetivli zero, 3, e16, mf2, tu, ma1624; ZIP-NEXT: vslideup.vi v10, v11, 21625; ZIP-NEXT: vslideup.vi v8, v13, 21626; ZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma1627; ZIP-NEXT: vslideup.vi v10, v15, 31628; ZIP-NEXT: vslideup.vi v8, v14, 31629; ZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma1630; ZIP-NEXT: vslideup.vi v8, v10, 41631; ZIP-NEXT: csrr a0, vlenb1632; ZIP-NEXT: slli a0, a0, 11633; ZIP-NEXT: add sp, sp, a01634; ZIP-NEXT: addi sp, sp, 161635; ZIP-NEXT: ret1636 %res = call <8 x half> @llvm.vector.interleave8.v8f16(<1 x half> %a, <1 x half> %b, <1 x half> %c, <1 x half> %d, <1 x half> %e, <1 x half> %f, <1 x half> %g, <1 x half> %h)1637 ret <8 x half> %res1638}1639 1640define <8 x i16> @interleave4_const_splat_v8i16(<2 x i16> %a) {1641; CHECK-LABEL: interleave4_const_splat_v8i16:1642; CHECK: # %bb.0:1643; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma1644; CHECK-NEXT: vmv.v.i v8, 31645; CHECK-NEXT: ret1646;1647; ZVBB-LABEL: interleave4_const_splat_v8i16:1648; ZVBB: # %bb.0:1649; ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma1650; ZVBB-NEXT: vmv.v.i v8, 31651; ZVBB-NEXT: ret1652;1653; ZIP-LABEL: interleave4_const_splat_v8i16:1654; ZIP: # %bb.0:1655; ZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma1656; ZIP-NEXT: vmv.v.i v8, 31657; ZIP-NEXT: ret1658 %retval = call <8 x i16> @llvm.vector.interleave4.v8i16(<2 x i16> splat(i16 3), <2 x i16> splat(i16 3), <2 x i16> splat(i16 3), <2 x i16> splat(i16 3))1659 ret <8 x i16> %retval1660}1661 1662define <8 x i16> @interleave4_same_nonconst_splat_v8i16(i16 %a) {1663; CHECK-LABEL: interleave4_same_nonconst_splat_v8i16:1664; CHECK: # %bb.0:1665; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma1666; CHECK-NEXT: vmv.v.x v8, a01667; CHECK-NEXT: ret1668;1669; ZVBB-LABEL: interleave4_same_nonconst_splat_v8i16:1670; ZVBB: # %bb.0:1671; ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma1672; ZVBB-NEXT: vmv.v.x v8, a01673; ZVBB-NEXT: ret1674;1675; ZIP-LABEL: interleave4_same_nonconst_splat_v8i16:1676; ZIP: # %bb.0:1677; ZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma1678; ZIP-NEXT: vmv.v.x v8, a01679; ZIP-NEXT: ret1680 %ins = insertelement <2 x i16> poison, i16 %a, i32 01681 %splat = shufflevector <2 x i16> %ins, <2 x i16> poison, <2 x i32> zeroinitializer1682 %retval = call <8 x i16> @llvm.vector.interleave4.v8i16(<2 x i16> %splat, <2 x i16> %splat, <2 x i16> %splat, <2 x i16> %splat)1683 ret <8 x i16> %retval1684}1685