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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zvfh,+zvfbfmin | FileCheck --check-prefixes=CHECK,RV32 %s3; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvfh,+zvfbfmin | FileCheck --check-prefixes=CHECK,RV64 %s4; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zvfhmin,+zvfbfmin | FileCheck --check-prefixes=CHECK,RV32 %s5; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvfhmin,+zvfbfmin | FileCheck --check-prefixes=CHECK,RV64 %s6 7; Integers8 9define void @vector_interleave_store_nxv32i1_nxv16i1(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b, ptr %p) {10; CHECK-LABEL: vector_interleave_store_nxv32i1_nxv16i1:11; CHECK: # %bb.0:12; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma13; CHECK-NEXT: vmv1r.v v9, v014; CHECK-NEXT: vmv1r.v v0, v815; CHECK-NEXT: vmv.v.i v10, 016; CHECK-NEXT: li a1, -117; CHECK-NEXT: vmerge.vim v12, v10, 1, v018; CHECK-NEXT: vmv1r.v v0, v919; CHECK-NEXT: vmerge.vim v14, v10, 1, v020; CHECK-NEXT: vwaddu.vv v8, v14, v1221; CHECK-NEXT: vwmaccu.vx v8, a1, v1222; CHECK-NEXT: csrr a1, vlenb23; CHECK-NEXT: vmsne.vi v12, v10, 024; CHECK-NEXT: vmsne.vi v10, v8, 025; CHECK-NEXT: srli a1, a1, 226; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma27; CHECK-NEXT: vslideup.vx v10, v12, a128; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma29; CHECK-NEXT: vsm.v v10, (a0)30; CHECK-NEXT: ret31 %res = call <vscale x 32 x i1> @llvm.vector.interleave2.nxv32i1(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b)32 store <vscale x 32 x i1> %res, ptr %p33 ret void34}35 36; Shouldn't be lowered to vsseg because it's unaligned37define void @vector_interleave_store_nxv16i16_nxv8i16_align1(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, ptr %p) {38; CHECK-LABEL: vector_interleave_store_nxv16i16_nxv8i16_align1:39; CHECK: # %bb.0:40; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma41; CHECK-NEXT: vwaddu.vv v12, v8, v1042; CHECK-NEXT: li a1, -143; CHECK-NEXT: vwmaccu.vx v12, a1, v1044; CHECK-NEXT: vs4r.v v12, (a0)45; CHECK-NEXT: ret46 %res = call <vscale x 16 x i16> @llvm.vector.interleave2.nxv16i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b)47 store <vscale x 16 x i16> %res, ptr %p, align 148 ret void49}50 51define void @vector_interleave_store_nxv16i16_nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, ptr %p) {52; CHECK-LABEL: vector_interleave_store_nxv16i16_nxv8i16:53; CHECK: # %bb.0:54; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma55; CHECK-NEXT: vsseg2e16.v v8, (a0)56; CHECK-NEXT: ret57 %res = call <vscale x 16 x i16> @llvm.vector.interleave2.nxv16i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b)58 store <vscale x 16 x i16> %res, ptr %p59 ret void60}61 62define void @vector_interleave_store_nxv8i32_nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, ptr %p) {63; CHECK-LABEL: vector_interleave_store_nxv8i32_nxv4i32:64; CHECK: # %bb.0:65; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma66; CHECK-NEXT: vsseg2e32.v v8, (a0)67; CHECK-NEXT: ret68 %res = call <vscale x 8 x i32> @llvm.vector.interleave2.nxv8i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b)69 store <vscale x 8 x i32> %res, ptr %p70 ret void71}72 73define void @vector_interleave_store_nxv4i64_nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, ptr %p) {74; CHECK-LABEL: vector_interleave_store_nxv4i64_nxv2i64:75; CHECK: # %bb.0:76; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma77; CHECK-NEXT: vsseg2e64.v v8, (a0)78; CHECK-NEXT: ret79 %res = call <vscale x 4 x i64> @llvm.vector.interleave2.nxv4i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b)80 store <vscale x 4 x i64> %res, ptr %p81 ret void82}83 84define void @vector_interleave_store_nxv8i64_nxv4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b, ptr %p) {85; CHECK-LABEL: vector_interleave_store_nxv8i64_nxv4i64:86; CHECK: # %bb.0:87; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, ma88; CHECK-NEXT: vsseg2e64.v v8, (a0)89; CHECK-NEXT: ret90 %res = call <vscale x 8 x i64> @llvm.vector.interleave2.nxv8i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b)91 store <vscale x 8 x i64> %res, ptr %p92 ret void93}94 95; This shouldn't be lowered to a vsseg because EMUL * NFIELDS >= 896define void @vector_interleave_store_nxv16i64_nxv8i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %b, ptr %p) {97; CHECK-LABEL: vector_interleave_store_nxv16i64_nxv8i64:98; CHECK: # %bb.0:99; CHECK-NEXT: csrr a1, vlenb100; CHECK-NEXT: vsetvli a2, zero, e16, m2, ta, mu101; CHECK-NEXT: vid.v v6102; CHECK-NEXT: vmv8r.v v24, v8103; CHECK-NEXT: srli a2, a1, 1104; CHECK-NEXT: vmv4r.v v28, v16105; CHECK-NEXT: vmv4r.v v16, v12106; CHECK-NEXT: vsrl.vi v4, v6, 1107; CHECK-NEXT: vand.vi v8, v6, 1108; CHECK-NEXT: slli a1, a1, 3109; CHECK-NEXT: vmsne.vi v0, v8, 0110; CHECK-NEXT: add a1, a0, a1111; CHECK-NEXT: vadd.vx v4, v4, a2, v0.t112; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma113; CHECK-NEXT: vrgatherei16.vv v8, v24, v4114; CHECK-NEXT: vrgatherei16.vv v24, v16, v4115; CHECK-NEXT: vs8r.v v24, (a1)116; CHECK-NEXT: vs8r.v v8, (a0)117; CHECK-NEXT: ret118 %res = call <vscale x 16 x i64> @llvm.vector.interleave2.nxv16i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %b)119 store <vscale x 16 x i64> %res, ptr %p120 ret void121}122 123; Floats124 125define void @vector_interleave_store_nxv4bf16_nxv2bf16(<vscale x 2 x bfloat> %a, <vscale x 2 x bfloat> %b, ptr %p) {126; CHECK-LABEL: vector_interleave_store_nxv4bf16_nxv2bf16:127; CHECK: # %bb.0:128; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma129; CHECK-NEXT: vsseg2e16.v v8, (a0)130; CHECK-NEXT: ret131 %res = call <vscale x 4 x bfloat> @llvm.vector.interleave2.nxv4bf16(<vscale x 2 x bfloat> %a, <vscale x 2 x bfloat> %b)132 store <vscale x 4 x bfloat> %res, ptr %p133 ret void134}135 136define void @vector_interleave_store_nxv8bf16_nxv4bf16(<vscale x 4 x bfloat> %a, <vscale x 4 x bfloat> %b, ptr %p) {137; CHECK-LABEL: vector_interleave_store_nxv8bf16_nxv4bf16:138; CHECK: # %bb.0:139; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma140; CHECK-NEXT: vsseg2e16.v v8, (a0)141; CHECK-NEXT: ret142 %res = call <vscale x 8 x bfloat> @llvm.vector.interleave2.nxv8bf16(<vscale x 4 x bfloat> %a, <vscale x 4 x bfloat> %b)143 store <vscale x 8 x bfloat> %res, ptr %p144 ret void145}146 147define void @vector_interleave_store_nxv4f16_nxv2f16(<vscale x 2 x half> %a, <vscale x 2 x half> %b, ptr %p) {148; CHECK-LABEL: vector_interleave_store_nxv4f16_nxv2f16:149; CHECK: # %bb.0:150; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma151; CHECK-NEXT: vsseg2e16.v v8, (a0)152; CHECK-NEXT: ret153 %res = call <vscale x 4 x half> @llvm.vector.interleave2.nxv4f16(<vscale x 2 x half> %a, <vscale x 2 x half> %b)154 store <vscale x 4 x half> %res, ptr %p155 ret void156}157 158define void @vector_interleave_store_nxv8f16_nxv4f16(<vscale x 4 x half> %a, <vscale x 4 x half> %b, ptr %p) {159; CHECK-LABEL: vector_interleave_store_nxv8f16_nxv4f16:160; CHECK: # %bb.0:161; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma162; CHECK-NEXT: vsseg2e16.v v8, (a0)163; CHECK-NEXT: ret164 %res = call <vscale x 8 x half> @llvm.vector.interleave2.nxv8f16(<vscale x 4 x half> %a, <vscale x 4 x half> %b)165 store <vscale x 8 x half> %res, ptr %p166 ret void167}168 169define void @vector_interleave_store_nxv4f32_nxv2f32(<vscale x 2 x float> %a, <vscale x 2 x float> %b, ptr %p) {170; CHECK-LABEL: vector_interleave_store_nxv4f32_nxv2f32:171; CHECK: # %bb.0:172; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma173; CHECK-NEXT: vsseg2e32.v v8, (a0)174; CHECK-NEXT: ret175 %res = call <vscale x 4 x float> @llvm.vector.interleave2.nxv4f32(<vscale x 2 x float> %a, <vscale x 2 x float> %b)176 store <vscale x 4 x float> %res, ptr %p177 ret void178}179 180define void @vector_interleave_store_nxv16bf16_nxv8bf16(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b, ptr %p) {181; CHECK-LABEL: vector_interleave_store_nxv16bf16_nxv8bf16:182; CHECK: # %bb.0:183; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma184; CHECK-NEXT: vsseg2e16.v v8, (a0)185; CHECK-NEXT: ret186 %res = call <vscale x 16 x bfloat> @llvm.vector.interleave2.nxv16bf16(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b)187 store <vscale x 16 x bfloat> %res, ptr %p188 ret void189}190 191define void @vector_interleave_store_nxv16f16_nxv8f16(<vscale x 8 x half> %a, <vscale x 8 x half> %b, ptr %p) {192; CHECK-LABEL: vector_interleave_store_nxv16f16_nxv8f16:193; CHECK: # %bb.0:194; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma195; CHECK-NEXT: vsseg2e16.v v8, (a0)196; CHECK-NEXT: ret197 %res = call <vscale x 16 x half> @llvm.vector.interleave2.nxv16f16(<vscale x 8 x half> %a, <vscale x 8 x half> %b)198 store <vscale x 16 x half> %res, ptr %p199 ret void200}201 202define void @vector_interleave_store_nxv8f32_nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x float> %b, ptr %p) {203; CHECK-LABEL: vector_interleave_store_nxv8f32_nxv4f32:204; CHECK: # %bb.0:205; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma206; CHECK-NEXT: vsseg2e32.v v8, (a0)207; CHECK-NEXT: ret208 %res = call <vscale x 8 x float> @llvm.vector.interleave2.nxv8f32(<vscale x 4 x float> %a, <vscale x 4 x float> %b)209 store <vscale x 8 x float> %res, ptr %p210 ret void211}212 213define void @vector_interleave_store_nxv4f64_nxv2f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b, ptr %p) {214; CHECK-LABEL: vector_interleave_store_nxv4f64_nxv2f64:215; CHECK: # %bb.0:216; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma217; CHECK-NEXT: vsseg2e64.v v8, (a0)218; CHECK-NEXT: ret219 %res = call <vscale x 4 x double> @llvm.vector.interleave2.nxv4f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b)220 store <vscale x 4 x double> %res, ptr %p221 ret void222}223 224define void @vector_interleave_store_nxv4p0_nxv2p0(<vscale x 2 x ptr> %a, <vscale x 2 x ptr> %b, ptr %p) {225; RV32-LABEL: vector_interleave_store_nxv4p0_nxv2p0:226; RV32: # %bb.0:227; RV32-NEXT: vsetvli a1, zero, e32, m1, ta, ma228; RV32-NEXT: vsseg2e32.v v8, (a0)229; RV32-NEXT: ret230;231; RV64-LABEL: vector_interleave_store_nxv4p0_nxv2p0:232; RV64: # %bb.0:233; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, ma234; RV64-NEXT: vsseg2e64.v v8, (a0)235; RV64-NEXT: ret236 %res = call <vscale x 4 x ptr> @llvm.vector.interleave2.nxv4p0(<vscale x 2 x ptr> %a, <vscale x 2 x ptr> %b)237 store <vscale x 4 x ptr> %res, ptr %p238 ret void239}240 241define void @vector_interleave_store_factor3(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b, <vscale x 2 x i32> %c, ptr %p) {242; CHECK-LABEL: vector_interleave_store_factor3:243; CHECK: # %bb.0:244; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma245; CHECK-NEXT: vsseg3e32.v v8, (a0)246; CHECK-NEXT: ret247 %v = call <vscale x 6 x i32> @llvm.vector.interleave3(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b, <vscale x 2 x i32> %c)248 store <vscale x 6 x i32> %v, ptr %p249 ret void250}251 252define void @vector_interleave_store_factor4(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b, <vscale x 2 x i32> %c, <vscale x 2 x i32> %d, ptr %p) {253; CHECK-LABEL: vector_interleave_store_factor4:254; CHECK: # %bb.0:255; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma256; CHECK-NEXT: vsseg4e32.v v8, (a0)257; CHECK-NEXT: ret258 %v = call <vscale x 8 x i32> @llvm.vector.interleave4(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b, <vscale x 2 x i32> %c, <vscale x 2 x i32> %d)259 store <vscale x 8 x i32> %v, ptr %p260 ret void261}262 263define void @vector_interleave_store_factor5(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b, <vscale x 2 x i32> %c, <vscale x 2 x i32> %d, <vscale x 2 x i32> %e, ptr %p) {264; CHECK-LABEL: vector_interleave_store_factor5:265; CHECK: # %bb.0:266; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma267; CHECK-NEXT: vsseg5e32.v v8, (a0)268; CHECK-NEXT: ret269 %v = call <vscale x 10 x i32> @llvm.vector.interleave5(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b, <vscale x 2 x i32> %c, <vscale x 2 x i32> %d, <vscale x 2 x i32> %e)270 store <vscale x 10 x i32> %v, ptr %p271 ret void272}273 274define void @vector_interleave_store_factor6(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b, <vscale x 2 x i32> %c, <vscale x 2 x i32> %d, <vscale x 2 x i32> %e, <vscale x 2 x i32> %f, ptr %p) {275; CHECK-LABEL: vector_interleave_store_factor6:276; CHECK: # %bb.0:277; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma278; CHECK-NEXT: vsseg6e32.v v8, (a0)279; CHECK-NEXT: ret280 %v = call <vscale x 12 x i32> @llvm.vector.interleave6(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b, <vscale x 2 x i32> %c, <vscale x 2 x i32> %d, <vscale x 2 x i32> %e, <vscale x 2 x i32> %f)281 store <vscale x 12 x i32> %v, ptr %p282 ret void283}284 285define void @vector_interleave_store_factor7(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b, <vscale x 2 x i32> %c, <vscale x 2 x i32> %d, <vscale x 2 x i32> %e, <vscale x 2 x i32> %f, <vscale x 2 x i32> %g, ptr %p) {286; CHECK-LABEL: vector_interleave_store_factor7:287; CHECK: # %bb.0:288; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma289; CHECK-NEXT: vsseg7e32.v v8, (a0)290; CHECK-NEXT: ret291 %v = call <vscale x 14 x i32> @llvm.vector.interleave7(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b, <vscale x 2 x i32> %c, <vscale x 2 x i32> %d, <vscale x 2 x i32> %e, <vscale x 2 x i32> %f, <vscale x 2 x i32> %g)292 store <vscale x 14 x i32> %v, ptr %p293 ret void294}295 296define void @vector_interleave_store_factor8(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b, <vscale x 2 x i32> %c, <vscale x 2 x i32> %d, <vscale x 2 x i32> %e, <vscale x 2 x i32> %f, <vscale x 2 x i32> %g, <vscale x 2 x i32> %h, ptr %p) {297; CHECK-LABEL: vector_interleave_store_factor8:298; CHECK: # %bb.0:299; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma300; CHECK-NEXT: vsseg8e32.v v8, (a0)301; CHECK-NEXT: ret302 %v = call <vscale x 16 x i32> @llvm.vector.interleave8(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b, <vscale x 2 x i32> %c, <vscale x 2 x i32> %d, <vscale x 2 x i32> %e, <vscale x 2 x i32> %f, <vscale x 2 x i32> %g, <vscale x 2 x i32> %h)303 store <vscale x 16 x i32> %v, ptr %p304 ret void305}306 307define void @masked_store_factor3(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b, <vscale x 2 x i32> %c, ptr %p) {308; CHECK-LABEL: masked_store_factor3:309; CHECK: # %bb.0:310; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma311; CHECK-NEXT: vsseg3e32.v v8, (a0)312; CHECK-NEXT: ret313 %v = call <vscale x 6 x i32> @llvm.vector.interleave3(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b, <vscale x 2 x i32> %c)314 call void @llvm.masked.store(<vscale x 6 x i32> %v, ptr %p, i32 4, <vscale x 6 x i1> splat (i1 true))315 ret void316}317 318define void @masked_store_factor3_masked(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b, <vscale x 2 x i32> %c, ptr %p, <vscale x 2 x i1> %m) {319; CHECK-LABEL: masked_store_factor3_masked:320; CHECK: # %bb.0:321; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma322; CHECK-NEXT: vsseg3e32.v v8, (a0), v0.t323; CHECK-NEXT: ret324 %interleaved.mask = call <vscale x 6 x i1> @llvm.vector.interleave3(<vscale x 2 x i1> %m, <vscale x 2 x i1> %m, <vscale x 2 x i1> %m)325 %v = call <vscale x 6 x i32> @llvm.vector.interleave3(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b, <vscale x 2 x i32> %c)326 call void @llvm.masked.store(<vscale x 6 x i32> %v, ptr %p, i32 4, <vscale x 6 x i1> %interleaved.mask)327 ret void328}329 330define void @store_factor2_oneactive(<vscale x 2 x i32> %a, ptr %p) {331; CHECK-LABEL: store_factor2_oneactive:332; CHECK: # %bb.0:333; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma334; CHECK-NEXT: vsseg2e32.v v8, (a0)335; CHECK-NEXT: ret336 %v = call <vscale x 4 x i32> @llvm.vector.interleave2(<vscale x 2 x i32> %a, <vscale x 2 x i32> poison)337 store <vscale x 4 x i32> %v, ptr %p338 ret void339}340 341define void @store_factor3_oneactive(<vscale x 2 x i32> %a, ptr %p) {342; CHECK-LABEL: store_factor3_oneactive:343; CHECK: # %bb.0:344; CHECK-NEXT: li a1, 12345; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, ma346; CHECK-NEXT: vsse32.v v8, (a0), a1347; CHECK-NEXT: ret348 %v = call <vscale x 6 x i32> @llvm.vector.interleave3(<vscale x 2 x i32> %a, <vscale x 2 x i32> poison, <vscale x 2 x i32> poison)349 store <vscale x 6 x i32> %v, ptr %p350 ret void351}352 353define void @store_factor7_oneactive(<vscale x 2 x i32> %a, ptr %p) {354; CHECK-LABEL: store_factor7_oneactive:355; CHECK: # %bb.0:356; CHECK-NEXT: addi a0, a0, 24357; CHECK-NEXT: li a1, 28358; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, ma359; CHECK-NEXT: vsse32.v v8, (a0), a1360; CHECK-NEXT: ret361 %v = call <vscale x 14 x i32> @llvm.vector.interleave7(<vscale x 2 x i32> poison, <vscale x 2 x i32> poison, <vscale x 2 x i32> poison, <vscale x 2 x i32> poison, <vscale x 2 x i32> poison, <vscale x 2 x i32> poison, <vscale x 2 x i32> %a)362 store <vscale x 14 x i32> %v, ptr %p363 ret void364}365