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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+v,+zvfh,+zvfbfmin | FileCheck %s --check-prefixes=CHECK,V,RV323; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+v,+zvfh,+zvfbfmin | FileCheck %s --check-prefixes=CHECK,V,RV644; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+v,+zvfhmin,+zvfbfmin | FileCheck %s --check-prefixes=CHECK,V,RV325; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+v,+zvfhmin,+zvfbfmin | FileCheck %s --check-prefixes=CHECK,V,RV646; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+v,+zvbb,+zvfh,+zvfbfmin | FileCheck %s --check-prefixes=ZVBB,ZVBB-RV327; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+v,+zvbb,+zvfh,+zvfbfmin | FileCheck %s --check-prefixes=ZVBB,ZVBB-RV648; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+v,+zvfhmin,+zvfbfmin,+experimental-xrivosvizip | FileCheck %s --check-prefixes=CHECK,ZIP9 10; Integers11 12define <vscale x 32 x i1> @vector_interleave_nxv32i1_nxv16i1(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {13; V-LABEL: vector_interleave_nxv32i1_nxv16i1:14; V:       # %bb.0:15; V-NEXT:    vsetvli a0, zero, e8, m2, ta, ma16; V-NEXT:    vmv1r.v v9, v017; V-NEXT:    vmv1r.v v0, v818; V-NEXT:    vmv.v.i v10, 019; V-NEXT:    li a0, -120; V-NEXT:    vmerge.vim v12, v10, 1, v021; V-NEXT:    vmv1r.v v0, v922; V-NEXT:    vmerge.vim v14, v10, 1, v023; V-NEXT:    vwaddu.vv v8, v14, v1224; V-NEXT:    vwmaccu.vx v8, a0, v1225; V-NEXT:    csrr a0, vlenb26; V-NEXT:    vmsne.vi v12, v10, 027; V-NEXT:    vmsne.vi v0, v8, 028; V-NEXT:    srli a0, a0, 229; V-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma30; V-NEXT:    vslideup.vx v0, v12, a031; V-NEXT:    ret32;33; ZVBB-LABEL: vector_interleave_nxv32i1_nxv16i1:34; ZVBB:       # %bb.0:35; ZVBB-NEXT:    vsetvli a0, zero, e8, m2, ta, mu36; ZVBB-NEXT:    vmv1r.v v9, v037; ZVBB-NEXT:    vmv1r.v v0, v838; ZVBB-NEXT:    vmv.v.i v10, 039; ZVBB-NEXT:    li a0, 140; ZVBB-NEXT:    vmerge.vim v10, v10, 1, v041; ZVBB-NEXT:    vwsll.vi v12, v10, 842; ZVBB-NEXT:    vmv1r.v v0, v943; ZVBB-NEXT:    vwaddu.wx v12, v12, a0, v0.t44; ZVBB-NEXT:    csrr a0, vlenb45; ZVBB-NEXT:    vmsne.vi v8, v14, 046; ZVBB-NEXT:    vmsne.vi v0, v12, 047; ZVBB-NEXT:    srli a0, a0, 248; ZVBB-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma49; ZVBB-NEXT:    vslideup.vx v0, v8, a050; ZVBB-NEXT:    ret51;52; ZIP-LABEL: vector_interleave_nxv32i1_nxv16i1:53; ZIP:       # %bb.0:54; ZIP-NEXT:    vsetvli a0, zero, e8, m2, ta, ma55; ZIP-NEXT:    vmv1r.v v9, v056; ZIP-NEXT:    vmv1r.v v0, v857; ZIP-NEXT:    vmv.v.i v10, 058; ZIP-NEXT:    csrr a0, vlenb59; ZIP-NEXT:    vmerge.vim v12, v10, 1, v060; ZIP-NEXT:    vmv1r.v v0, v961; ZIP-NEXT:    vmerge.vim v8, v10, 1, v062; ZIP-NEXT:    ri.vzip2b.vv v10, v8, v1263; ZIP-NEXT:    ri.vzip2a.vv v14, v8, v1264; ZIP-NEXT:    vmsne.vi v8, v10, 065; ZIP-NEXT:    vmsne.vi v0, v14, 066; ZIP-NEXT:    srli a0, a0, 267; ZIP-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma68; ZIP-NEXT:    vslideup.vx v0, v8, a069; ZIP-NEXT:    ret70  %res = call <vscale x 32 x i1> @llvm.vector.interleave2.nxv32i1(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b)71  ret <vscale x 32 x i1> %res72}73 74define <vscale x 32 x i8> @vector_interleave_nxv32i8_nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {75; V-LABEL: vector_interleave_nxv32i8_nxv16i8:76; V:       # %bb.0:77; V-NEXT:    vsetvli a0, zero, e8, m2, ta, ma78; V-NEXT:    vmv2r.v v12, v1079; V-NEXT:    vmv2r.v v14, v880; V-NEXT:    vwaddu.vv v8, v14, v1281; V-NEXT:    li a0, -182; V-NEXT:    vwmaccu.vx v8, a0, v1283; V-NEXT:    ret84;85; ZVBB-LABEL: vector_interleave_nxv32i8_nxv16i8:86; ZVBB:       # %bb.0:87; ZVBB-NEXT:    vsetvli a0, zero, e8, m2, ta, ma88; ZVBB-NEXT:    vmv2r.v v12, v1089; ZVBB-NEXT:    vmv2r.v v14, v890; ZVBB-NEXT:    vwsll.vi v8, v12, 891; ZVBB-NEXT:    vwaddu.wv v8, v8, v1492; ZVBB-NEXT:    ret93;94; ZIP-LABEL: vector_interleave_nxv32i8_nxv16i8:95; ZIP:       # %bb.0:96; ZIP-NEXT:    vsetvli a0, zero, e8, m2, ta, ma97; ZIP-NEXT:    vmv2r.v v12, v1098; ZIP-NEXT:    vmv2r.v v14, v899; ZIP-NEXT:    ri.vzip2b.vv v10, v8, v12100; ZIP-NEXT:    ri.vzip2a.vv v8, v14, v12101; ZIP-NEXT:    ret102  %res = call <vscale x 32 x i8> @llvm.vector.interleave2.nxv32i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b)103  ret <vscale x 32 x i8> %res104}105 106define <vscale x 16 x i16> @vector_interleave_nxv16i16_nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {107; V-LABEL: vector_interleave_nxv16i16_nxv8i16:108; V:       # %bb.0:109; V-NEXT:    vsetvli a0, zero, e16, m2, ta, ma110; V-NEXT:    vmv2r.v v12, v10111; V-NEXT:    vmv2r.v v14, v8112; V-NEXT:    vwaddu.vv v8, v14, v12113; V-NEXT:    li a0, -1114; V-NEXT:    vwmaccu.vx v8, a0, v12115; V-NEXT:    ret116;117; ZVBB-LABEL: vector_interleave_nxv16i16_nxv8i16:118; ZVBB:       # %bb.0:119; ZVBB-NEXT:    vsetvli a0, zero, e16, m2, ta, ma120; ZVBB-NEXT:    vmv2r.v v12, v10121; ZVBB-NEXT:    vmv2r.v v14, v8122; ZVBB-NEXT:    vwsll.vi v8, v12, 16123; ZVBB-NEXT:    vwaddu.wv v8, v8, v14124; ZVBB-NEXT:    ret125;126; ZIP-LABEL: vector_interleave_nxv16i16_nxv8i16:127; ZIP:       # %bb.0:128; ZIP-NEXT:    vsetvli a0, zero, e16, m2, ta, ma129; ZIP-NEXT:    vmv2r.v v12, v10130; ZIP-NEXT:    vmv2r.v v14, v8131; ZIP-NEXT:    ri.vzip2b.vv v10, v8, v12132; ZIP-NEXT:    ri.vzip2a.vv v8, v14, v12133; ZIP-NEXT:    ret134  %res = call <vscale x 16 x i16> @llvm.vector.interleave2.nxv16i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b)135  ret <vscale x 16 x i16> %res136}137 138define <vscale x 8 x i32> @vector_interleave_nxv8i32_nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {139; V-LABEL: vector_interleave_nxv8i32_nxv4i32:140; V:       # %bb.0:141; V-NEXT:    vsetvli a0, zero, e32, m2, ta, ma142; V-NEXT:    vmv2r.v v12, v10143; V-NEXT:    vmv2r.v v14, v8144; V-NEXT:    vwaddu.vv v8, v14, v12145; V-NEXT:    li a0, -1146; V-NEXT:    vwmaccu.vx v8, a0, v12147; V-NEXT:    ret148;149; ZVBB-LABEL: vector_interleave_nxv8i32_nxv4i32:150; ZVBB:       # %bb.0:151; ZVBB-NEXT:    vsetvli a0, zero, e32, m2, ta, ma152; ZVBB-NEXT:    vmv2r.v v12, v10153; ZVBB-NEXT:    vmv2r.v v14, v8154; ZVBB-NEXT:    li a0, 32155; ZVBB-NEXT:    vwsll.vx v8, v12, a0156; ZVBB-NEXT:    vwaddu.wv v8, v8, v14157; ZVBB-NEXT:    ret158;159; ZIP-LABEL: vector_interleave_nxv8i32_nxv4i32:160; ZIP:       # %bb.0:161; ZIP-NEXT:    vsetvli a0, zero, e32, m2, ta, ma162; ZIP-NEXT:    vmv2r.v v12, v10163; ZIP-NEXT:    vmv2r.v v14, v8164; ZIP-NEXT:    ri.vzip2b.vv v10, v8, v12165; ZIP-NEXT:    ri.vzip2a.vv v8, v14, v12166; ZIP-NEXT:    ret167  %res = call <vscale x 8 x i32> @llvm.vector.interleave2.nxv8i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b)168  ret <vscale x 8 x i32> %res169}170 171define <vscale x 4 x i64> @vector_interleave_nxv4i64_nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {172; V-LABEL: vector_interleave_nxv4i64_nxv2i64:173; V:       # %bb.0:174; V-NEXT:    csrr a0, vlenb175; V-NEXT:    vsetvli a1, zero, e16, m1, ta, mu176; V-NEXT:    vid.v v12177; V-NEXT:    srli a0, a0, 2178; V-NEXT:    vand.vi v13, v12, 1179; V-NEXT:    vmsne.vi v0, v13, 0180; V-NEXT:    vsrl.vi v16, v12, 1181; V-NEXT:    vadd.vx v16, v16, a0, v0.t182; V-NEXT:    vsetvli zero, zero, e64, m4, ta, ma183; V-NEXT:    vrgatherei16.vv v12, v8, v16184; V-NEXT:    vmv.v.v v8, v12185; V-NEXT:    ret186;187; ZVBB-LABEL: vector_interleave_nxv4i64_nxv2i64:188; ZVBB:       # %bb.0:189; ZVBB-NEXT:    csrr a0, vlenb190; ZVBB-NEXT:    vsetvli a1, zero, e16, m1, ta, mu191; ZVBB-NEXT:    vid.v v12192; ZVBB-NEXT:    srli a0, a0, 2193; ZVBB-NEXT:    vand.vi v13, v12, 1194; ZVBB-NEXT:    vmsne.vi v0, v13, 0195; ZVBB-NEXT:    vsrl.vi v16, v12, 1196; ZVBB-NEXT:    vadd.vx v16, v16, a0, v0.t197; ZVBB-NEXT:    vsetvli zero, zero, e64, m4, ta, ma198; ZVBB-NEXT:    vrgatherei16.vv v12, v8, v16199; ZVBB-NEXT:    vmv.v.v v8, v12200; ZVBB-NEXT:    ret201;202; ZIP-LABEL: vector_interleave_nxv4i64_nxv2i64:203; ZIP:       # %bb.0:204; ZIP-NEXT:    vsetvli a0, zero, e64, m2, ta, ma205; ZIP-NEXT:    vmv2r.v v12, v10206; ZIP-NEXT:    vmv2r.v v14, v8207; ZIP-NEXT:    ri.vzip2b.vv v10, v8, v12208; ZIP-NEXT:    ri.vzip2a.vv v8, v14, v12209; ZIP-NEXT:    ret210  %res = call <vscale x 4 x i64> @llvm.vector.interleave2.nxv4i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b)211  ret <vscale x 4 x i64> %res212}213 214 215define <vscale x 128 x i1> @vector_interleave_nxv128i1_nxv64i1(<vscale x 64 x i1> %a, <vscale x 64 x i1> %b) {216; V-LABEL: vector_interleave_nxv128i1_nxv64i1:217; V:       # %bb.0:218; V-NEXT:    vsetvli a0, zero, e8, m8, ta, ma219; V-NEXT:    vmv1r.v v9, v0220; V-NEXT:    vmv1r.v v0, v8221; V-NEXT:    vmv.v.i v24, 0222; V-NEXT:    li a0, -1223; V-NEXT:    vmerge.vim v16, v24, 1, v0224; V-NEXT:    vmv1r.v v0, v9225; V-NEXT:    vmerge.vim v24, v24, 1, v0226; V-NEXT:    vsetvli a1, zero, e8, m4, ta, ma227; V-NEXT:    vwaddu.vv v8, v24, v16228; V-NEXT:    vwaddu.vv v0, v28, v20229; V-NEXT:    vwmaccu.vx v8, a0, v16230; V-NEXT:    vwmaccu.vx v0, a0, v20231; V-NEXT:    vsetvli a0, zero, e8, m8, ta, ma232; V-NEXT:    vmsne.vi v16, v8, 0233; V-NEXT:    vmsne.vi v8, v0, 0234; V-NEXT:    vmv1r.v v0, v16235; V-NEXT:    ret236;237; ZVBB-LABEL: vector_interleave_nxv128i1_nxv64i1:238; ZVBB:       # %bb.0:239; ZVBB-NEXT:    vsetvli a0, zero, e8, m8, ta, ma240; ZVBB-NEXT:    vmv.v.i v24, 0241; ZVBB-NEXT:    vmerge.vim v16, v24, 1, v0242; ZVBB-NEXT:    vmv1r.v v0, v8243; ZVBB-NEXT:    vmerge.vim v24, v24, 1, v0244; ZVBB-NEXT:    vsetvli a0, zero, e8, m4, ta, ma245; ZVBB-NEXT:    vwsll.vi v8, v24, 8246; ZVBB-NEXT:    vwsll.vi v0, v28, 8247; ZVBB-NEXT:    vwaddu.wv v8, v8, v16248; ZVBB-NEXT:    vwaddu.wv v0, v0, v20249; ZVBB-NEXT:    vsetvli a0, zero, e8, m8, ta, ma250; ZVBB-NEXT:    vmsne.vi v16, v8, 0251; ZVBB-NEXT:    vmsne.vi v8, v0, 0252; ZVBB-NEXT:    vmv1r.v v0, v16253; ZVBB-NEXT:    ret254;255; ZIP-LABEL: vector_interleave_nxv128i1_nxv64i1:256; ZIP:       # %bb.0:257; ZIP-NEXT:    vsetvli a0, zero, e8, m8, ta, ma258; ZIP-NEXT:    vmv1r.v v9, v0259; ZIP-NEXT:    vmv1r.v v0, v8260; ZIP-NEXT:    vmv.v.i v24, 0261; ZIP-NEXT:    vmerge.vim v16, v24, 1, v0262; ZIP-NEXT:    vmv1r.v v0, v9263; ZIP-NEXT:    vmerge.vim v8, v24, 1, v0264; ZIP-NEXT:    vsetvli a0, zero, e8, m4, ta, ma265; ZIP-NEXT:    ri.vzip2b.vv v4, v8, v16266; ZIP-NEXT:    ri.vzip2b.vv v28, v12, v20267; ZIP-NEXT:    ri.vzip2a.vv v0, v8, v16268; ZIP-NEXT:    ri.vzip2a.vv v24, v12, v20269; ZIP-NEXT:    vsetvli a0, zero, e8, m8, ta, ma270; ZIP-NEXT:    vmsne.vi v9, v0, 0271; ZIP-NEXT:    vmsne.vi v8, v24, 0272; ZIP-NEXT:    vmv1r.v v0, v9273; ZIP-NEXT:    ret274  %res = call <vscale x 128 x i1> @llvm.vector.interleave2.nxv128i1(<vscale x 64 x i1> %a, <vscale x 64 x i1> %b)275  ret <vscale x 128 x i1> %res276}277 278define <vscale x 128 x i8> @vector_interleave_nxv128i8_nxv64i8(<vscale x 64 x i8> %a, <vscale x 64 x i8> %b) {279; V-LABEL: vector_interleave_nxv128i8_nxv64i8:280; V:       # %bb.0:281; V-NEXT:    vsetvli a0, zero, e8, m4, ta, ma282; V-NEXT:    vmv8r.v v24, v8283; V-NEXT:    vwaddu.vv v8, v24, v16284; V-NEXT:    li a0, -1285; V-NEXT:    vwaddu.vv v0, v28, v20286; V-NEXT:    vwmaccu.vx v8, a0, v16287; V-NEXT:    vwmaccu.vx v0, a0, v20288; V-NEXT:    vmv8r.v v16, v0289; V-NEXT:    ret290;291; ZVBB-LABEL: vector_interleave_nxv128i8_nxv64i8:292; ZVBB:       # %bb.0:293; ZVBB-NEXT:    vsetvli a0, zero, e8, m4, ta, ma294; ZVBB-NEXT:    vwsll.vi v24, v16, 8295; ZVBB-NEXT:    vwsll.vi v0, v20, 8296; ZVBB-NEXT:    vwaddu.wv v24, v24, v8297; ZVBB-NEXT:    vwaddu.wv v0, v0, v12298; ZVBB-NEXT:    vmv8r.v v8, v24299; ZVBB-NEXT:    vmv8r.v v16, v0300; ZVBB-NEXT:    ret301;302; ZIP-LABEL: vector_interleave_nxv128i8_nxv64i8:303; ZIP:       # %bb.0:304; ZIP-NEXT:    vsetvli a0, zero, e8, m4, ta, ma305; ZIP-NEXT:    ri.vzip2b.vv v28, v8, v16306; ZIP-NEXT:    ri.vzip2b.vv v4, v12, v20307; ZIP-NEXT:    ri.vzip2a.vv v24, v8, v16308; ZIP-NEXT:    ri.vzip2a.vv v0, v12, v20309; ZIP-NEXT:    vmv8r.v v8, v24310; ZIP-NEXT:    vmv8r.v v16, v0311; ZIP-NEXT:    ret312  %res = call <vscale x 128 x i8> @llvm.vector.interleave2.nxv128i8(<vscale x 64 x i8> %a, <vscale x 64 x i8> %b)313  ret <vscale x 128 x i8> %res314}315 316define <vscale x 64 x i16> @vector_interleave_nxv64i16_nxv32i16(<vscale x 32 x i16> %a, <vscale x 32 x i16> %b) {317; V-LABEL: vector_interleave_nxv64i16_nxv32i16:318; V:       # %bb.0:319; V-NEXT:    vsetvli a0, zero, e16, m4, ta, ma320; V-NEXT:    vmv8r.v v24, v8321; V-NEXT:    vwaddu.vv v8, v24, v16322; V-NEXT:    li a0, -1323; V-NEXT:    vwaddu.vv v0, v28, v20324; V-NEXT:    vwmaccu.vx v8, a0, v16325; V-NEXT:    vwmaccu.vx v0, a0, v20326; V-NEXT:    vmv8r.v v16, v0327; V-NEXT:    ret328;329; ZVBB-LABEL: vector_interleave_nxv64i16_nxv32i16:330; ZVBB:       # %bb.0:331; ZVBB-NEXT:    vsetvli a0, zero, e16, m4, ta, ma332; ZVBB-NEXT:    vwsll.vi v24, v16, 16333; ZVBB-NEXT:    vwsll.vi v0, v20, 16334; ZVBB-NEXT:    vwaddu.wv v24, v24, v8335; ZVBB-NEXT:    vwaddu.wv v0, v0, v12336; ZVBB-NEXT:    vmv8r.v v8, v24337; ZVBB-NEXT:    vmv8r.v v16, v0338; ZVBB-NEXT:    ret339;340; ZIP-LABEL: vector_interleave_nxv64i16_nxv32i16:341; ZIP:       # %bb.0:342; ZIP-NEXT:    vsetvli a0, zero, e16, m4, ta, ma343; ZIP-NEXT:    ri.vzip2b.vv v28, v8, v16344; ZIP-NEXT:    ri.vzip2b.vv v4, v12, v20345; ZIP-NEXT:    ri.vzip2a.vv v24, v8, v16346; ZIP-NEXT:    ri.vzip2a.vv v0, v12, v20347; ZIP-NEXT:    vmv8r.v v8, v24348; ZIP-NEXT:    vmv8r.v v16, v0349; ZIP-NEXT:    ret350  %res = call <vscale x 64 x i16> @llvm.vector.interleave2.nxv64i16(<vscale x 32 x i16> %a, <vscale x 32 x i16> %b)351  ret <vscale x 64 x i16> %res352}353 354define <vscale x 32 x i32> @vector_interleave_nxv32i32_nxv16i32(<vscale x 16 x i32> %a, <vscale x 16 x i32> %b) {355; V-LABEL: vector_interleave_nxv32i32_nxv16i32:356; V:       # %bb.0:357; V-NEXT:    vsetvli a0, zero, e32, m4, ta, ma358; V-NEXT:    vmv8r.v v24, v8359; V-NEXT:    vwaddu.vv v8, v24, v16360; V-NEXT:    li a0, -1361; V-NEXT:    vwaddu.vv v0, v28, v20362; V-NEXT:    vwmaccu.vx v8, a0, v16363; V-NEXT:    vwmaccu.vx v0, a0, v20364; V-NEXT:    vmv8r.v v16, v0365; V-NEXT:    ret366;367; ZVBB-LABEL: vector_interleave_nxv32i32_nxv16i32:368; ZVBB:       # %bb.0:369; ZVBB-NEXT:    li a0, 32370; ZVBB-NEXT:    vsetvli a1, zero, e32, m4, ta, ma371; ZVBB-NEXT:    vwsll.vx v24, v16, a0372; ZVBB-NEXT:    vwsll.vx v0, v20, a0373; ZVBB-NEXT:    vwaddu.wv v24, v24, v8374; ZVBB-NEXT:    vwaddu.wv v0, v0, v12375; ZVBB-NEXT:    vmv8r.v v8, v24376; ZVBB-NEXT:    vmv8r.v v16, v0377; ZVBB-NEXT:    ret378;379; ZIP-LABEL: vector_interleave_nxv32i32_nxv16i32:380; ZIP:       # %bb.0:381; ZIP-NEXT:    vsetvli a0, zero, e32, m4, ta, ma382; ZIP-NEXT:    ri.vzip2b.vv v28, v8, v16383; ZIP-NEXT:    ri.vzip2b.vv v4, v12, v20384; ZIP-NEXT:    ri.vzip2a.vv v24, v8, v16385; ZIP-NEXT:    ri.vzip2a.vv v0, v12, v20386; ZIP-NEXT:    vmv8r.v v8, v24387; ZIP-NEXT:    vmv8r.v v16, v0388; ZIP-NEXT:    ret389  %res = call <vscale x 32 x i32> @llvm.vector.interleave2.nxv32i32(<vscale x 16 x i32> %a, <vscale x 16 x i32> %b)390  ret <vscale x 32 x i32> %res391}392 393define <vscale x 16 x i64> @vector_interleave_nxv16i64_nxv8i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %b) {394; V-LABEL: vector_interleave_nxv16i64_nxv8i64:395; V:       # %bb.0:396; V-NEXT:    csrr a0, vlenb397; V-NEXT:    vsetvli a1, zero, e16, m2, ta, mu398; V-NEXT:    vid.v v6399; V-NEXT:    vmv8r.v v24, v8400; V-NEXT:    srli a0, a0, 1401; V-NEXT:    vmv4r.v v28, v16402; V-NEXT:    vmv4r.v v16, v12403; V-NEXT:    vand.vi v8, v6, 1404; V-NEXT:    vmsne.vi v0, v8, 0405; V-NEXT:    vsrl.vi v6, v6, 1406; V-NEXT:    vadd.vx v6, v6, a0, v0.t407; V-NEXT:    vsetvli zero, zero, e64, m8, ta, ma408; V-NEXT:    vrgatherei16.vv v8, v24, v6409; V-NEXT:    vrgatherei16.vv v24, v16, v6410; V-NEXT:    vmv.v.v v16, v24411; V-NEXT:    ret412;413; ZVBB-LABEL: vector_interleave_nxv16i64_nxv8i64:414; ZVBB:       # %bb.0:415; ZVBB-NEXT:    csrr a0, vlenb416; ZVBB-NEXT:    vsetvli a1, zero, e16, m2, ta, mu417; ZVBB-NEXT:    vid.v v6418; ZVBB-NEXT:    vmv8r.v v24, v8419; ZVBB-NEXT:    srli a0, a0, 1420; ZVBB-NEXT:    vmv4r.v v28, v16421; ZVBB-NEXT:    vmv4r.v v16, v12422; ZVBB-NEXT:    vand.vi v8, v6, 1423; ZVBB-NEXT:    vmsne.vi v0, v8, 0424; ZVBB-NEXT:    vsrl.vi v6, v6, 1425; ZVBB-NEXT:    vadd.vx v6, v6, a0, v0.t426; ZVBB-NEXT:    vsetvli zero, zero, e64, m8, ta, ma427; ZVBB-NEXT:    vrgatherei16.vv v8, v24, v6428; ZVBB-NEXT:    vrgatherei16.vv v24, v16, v6429; ZVBB-NEXT:    vmv.v.v v16, v24430; ZVBB-NEXT:    ret431;432; ZIP-LABEL: vector_interleave_nxv16i64_nxv8i64:433; ZIP:       # %bb.0:434; ZIP-NEXT:    vsetvli a0, zero, e64, m4, ta, ma435; ZIP-NEXT:    ri.vzip2b.vv v28, v8, v16436; ZIP-NEXT:    ri.vzip2b.vv v4, v12, v20437; ZIP-NEXT:    ri.vzip2a.vv v24, v8, v16438; ZIP-NEXT:    ri.vzip2a.vv v0, v12, v20439; ZIP-NEXT:    vmv8r.v v8, v24440; ZIP-NEXT:    vmv8r.v v16, v0441; ZIP-NEXT:    ret442  %res = call <vscale x 16 x i64> @llvm.vector.interleave2.nxv16i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %b)443  ret <vscale x 16 x i64> %res444}445 446define <vscale x 8 x i32> @vector_interleave_nxv8i32_nxv4i32_poison(<vscale x 4 x i32> %a) {447; CHECK-LABEL: vector_interleave_nxv8i32_nxv4i32_poison:448; CHECK:       # %bb.0:449; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, ma450; CHECK-NEXT:    vmv2r.v v12, v8451; CHECK-NEXT:    vzext.vf2 v8, v12452; CHECK-NEXT:    ret453;454; ZVBB-LABEL: vector_interleave_nxv8i32_nxv4i32_poison:455; ZVBB:       # %bb.0:456; ZVBB-NEXT:    vsetvli a0, zero, e64, m4, ta, ma457; ZVBB-NEXT:    vmv2r.v v12, v8458; ZVBB-NEXT:    vzext.vf2 v8, v12459; ZVBB-NEXT:    ret460  %res = call <vscale x 8 x i32> @llvm.vector.interleave2.nxv8i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> poison)461  ret <vscale x 8 x i32> %res462}463 464define <vscale x 8 x i32> @vector_interleave_nxv8i32_nxv4i32_poison2(<vscale x 4 x i32> %a) {465; CHECK-LABEL: vector_interleave_nxv8i32_nxv4i32_poison2:466; CHECK:       # %bb.0:467; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, ma468; CHECK-NEXT:    vzext.vf2 v12, v8469; CHECK-NEXT:    li a0, 32470; CHECK-NEXT:    vsll.vx v8, v12, a0471; CHECK-NEXT:    ret472;473; ZVBB-LABEL: vector_interleave_nxv8i32_nxv4i32_poison2:474; ZVBB:       # %bb.0:475; ZVBB-NEXT:    vsetvli a0, zero, e32, m2, ta, ma476; ZVBB-NEXT:    vmv2r.v v12, v8477; ZVBB-NEXT:    li a0, 32478; ZVBB-NEXT:    vwsll.vx v8, v12, a0479; ZVBB-NEXT:    ret480  %res = call <vscale x 8 x i32> @llvm.vector.interleave2.nxv8i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a)481  ret <vscale x 8 x i32> %res482}483 484define <vscale x 48 x i1> @vector_interleave_nxv48i1_nxv16i1(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b, <vscale x 16 x i1> %c) nounwind {485; CHECK-LABEL: vector_interleave_nxv48i1_nxv16i1:486; CHECK:       # %bb.0:487; CHECK-NEXT:    addi sp, sp, -16488; CHECK-NEXT:    csrr a0, vlenb489; CHECK-NEXT:    li a1, 6490; CHECK-NEXT:    mul a0, a0, a1491; CHECK-NEXT:    sub sp, sp, a0492; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, ma493; CHECK-NEXT:    vmv1r.v v10, v0494; CHECK-NEXT:    vmv1r.v v0, v8495; CHECK-NEXT:    vmv.v.i v12, 0496; CHECK-NEXT:    addi a0, sp, 16497; CHECK-NEXT:    csrr a1, vlenb498; CHECK-NEXT:    vmerge.vim v16, v12, 1, v0499; CHECK-NEXT:    slli a2, a1, 1500; CHECK-NEXT:    vmv1r.v v0, v10501; CHECK-NEXT:    vmerge.vim v14, v12, 1, v0502; CHECK-NEXT:    add a3, a0, a2503; CHECK-NEXT:    vmv1r.v v0, v9504; CHECK-NEXT:    vmerge.vim v18, v12, 1, v0505; CHECK-NEXT:    add a2, a3, a2506; CHECK-NEXT:    vsseg3e8.v v14, (a0)507; CHECK-NEXT:    vl2r.v v8, (a2)508; CHECK-NEXT:    srli a2, a1, 1509; CHECK-NEXT:    vl2r.v v10, (a3)510; CHECK-NEXT:    vl2r.v v12, (a0)511; CHECK-NEXT:    srli a1, a1, 2512; CHECK-NEXT:    vmsne.vi v14, v8, 0513; CHECK-NEXT:    vmsne.vi v8, v10, 0514; CHECK-NEXT:    vmsne.vi v0, v12, 0515; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma516; CHECK-NEXT:    vslideup.vx v0, v8, a1517; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma518; CHECK-NEXT:    vslideup.vx v0, v14, a2519; CHECK-NEXT:    csrr a0, vlenb520; CHECK-NEXT:    li a1, 6521; CHECK-NEXT:    mul a0, a0, a1522; CHECK-NEXT:    add sp, sp, a0523; CHECK-NEXT:    addi sp, sp, 16524; CHECK-NEXT:    ret525;526; ZVBB-LABEL: vector_interleave_nxv48i1_nxv16i1:527; ZVBB:       # %bb.0:528; ZVBB-NEXT:    addi sp, sp, -16529; ZVBB-NEXT:    csrr a0, vlenb530; ZVBB-NEXT:    li a1, 6531; ZVBB-NEXT:    mul a0, a0, a1532; ZVBB-NEXT:    sub sp, sp, a0533; ZVBB-NEXT:    vsetvli a0, zero, e8, m2, ta, ma534; ZVBB-NEXT:    vmv1r.v v10, v0535; ZVBB-NEXT:    vmv1r.v v0, v8536; ZVBB-NEXT:    vmv.v.i v12, 0537; ZVBB-NEXT:    addi a0, sp, 16538; ZVBB-NEXT:    csrr a1, vlenb539; ZVBB-NEXT:    vmerge.vim v16, v12, 1, v0540; ZVBB-NEXT:    slli a2, a1, 1541; ZVBB-NEXT:    vmv1r.v v0, v10542; ZVBB-NEXT:    vmerge.vim v14, v12, 1, v0543; ZVBB-NEXT:    add a3, a0, a2544; ZVBB-NEXT:    vmv1r.v v0, v9545; ZVBB-NEXT:    vmerge.vim v18, v12, 1, v0546; ZVBB-NEXT:    add a2, a3, a2547; ZVBB-NEXT:    vsseg3e8.v v14, (a0)548; ZVBB-NEXT:    vl2r.v v8, (a2)549; ZVBB-NEXT:    srli a2, a1, 1550; ZVBB-NEXT:    vl2r.v v10, (a3)551; ZVBB-NEXT:    vl2r.v v12, (a0)552; ZVBB-NEXT:    srli a1, a1, 2553; ZVBB-NEXT:    vmsne.vi v14, v8, 0554; ZVBB-NEXT:    vmsne.vi v8, v10, 0555; ZVBB-NEXT:    vmsne.vi v0, v12, 0556; ZVBB-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma557; ZVBB-NEXT:    vslideup.vx v0, v8, a1558; ZVBB-NEXT:    vsetvli a0, zero, e8, m1, ta, ma559; ZVBB-NEXT:    vslideup.vx v0, v14, a2560; ZVBB-NEXT:    csrr a0, vlenb561; ZVBB-NEXT:    li a1, 6562; ZVBB-NEXT:    mul a0, a0, a1563; ZVBB-NEXT:    add sp, sp, a0564; ZVBB-NEXT:    addi sp, sp, 16565; ZVBB-NEXT:    ret566  %res = call <vscale x 48 x i1> @llvm.vector.interleave3.nxv48i1(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b, <vscale x 16 x i1> %c)567  ret <vscale x 48 x i1> %res568}569 570 571define <vscale x 48 x i8> @vector_interleave_nxv48i8_nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) nounwind {572; CHECK-LABEL: vector_interleave_nxv48i8_nxv16i8:573; CHECK:       # %bb.0:574; CHECK-NEXT:    addi sp, sp, -16575; CHECK-NEXT:    csrr a0, vlenb576; CHECK-NEXT:    li a1, 6577; CHECK-NEXT:    mul a0, a0, a1578; CHECK-NEXT:    sub sp, sp, a0579; CHECK-NEXT:    addi a0, sp, 16580; CHECK-NEXT:    csrr a1, vlenb581; CHECK-NEXT:    slli a1, a1, 1582; CHECK-NEXT:    vsetvli a2, zero, e8, m2, ta, ma583; CHECK-NEXT:    vsseg3e8.v v8, (a0)584; CHECK-NEXT:    vl2r.v v8, (a0)585; CHECK-NEXT:    add a0, a0, a1586; CHECK-NEXT:    vl2r.v v10, (a0)587; CHECK-NEXT:    add a0, a0, a1588; CHECK-NEXT:    vl2r.v v12, (a0)589; CHECK-NEXT:    csrr a0, vlenb590; CHECK-NEXT:    li a1, 6591; CHECK-NEXT:    mul a0, a0, a1592; CHECK-NEXT:    add sp, sp, a0593; CHECK-NEXT:    addi sp, sp, 16594; CHECK-NEXT:    ret595;596; ZVBB-LABEL: vector_interleave_nxv48i8_nxv16i8:597; ZVBB:       # %bb.0:598; ZVBB-NEXT:    addi sp, sp, -16599; ZVBB-NEXT:    csrr a0, vlenb600; ZVBB-NEXT:    li a1, 6601; ZVBB-NEXT:    mul a0, a0, a1602; ZVBB-NEXT:    sub sp, sp, a0603; ZVBB-NEXT:    addi a0, sp, 16604; ZVBB-NEXT:    csrr a1, vlenb605; ZVBB-NEXT:    slli a1, a1, 1606; ZVBB-NEXT:    vsetvli a2, zero, e8, m2, ta, ma607; ZVBB-NEXT:    vsseg3e8.v v8, (a0)608; ZVBB-NEXT:    vl2r.v v8, (a0)609; ZVBB-NEXT:    add a0, a0, a1610; ZVBB-NEXT:    vl2r.v v10, (a0)611; ZVBB-NEXT:    add a0, a0, a1612; ZVBB-NEXT:    vl2r.v v12, (a0)613; ZVBB-NEXT:    csrr a0, vlenb614; ZVBB-NEXT:    li a1, 6615; ZVBB-NEXT:    mul a0, a0, a1616; ZVBB-NEXT:    add sp, sp, a0617; ZVBB-NEXT:    addi sp, sp, 16618; ZVBB-NEXT:    ret619  %res = call <vscale x 48 x i8> @llvm.vector.interleave3.nxv48i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c)620  ret <vscale x 48 x i8> %res621}622 623 624define <vscale x 24 x i16> @vector_interleave_nxv24i16_nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) nounwind {625; CHECK-LABEL: vector_interleave_nxv24i16_nxv8i16:626; CHECK:       # %bb.0:627; CHECK-NEXT:    addi sp, sp, -16628; CHECK-NEXT:    csrr a0, vlenb629; CHECK-NEXT:    li a1, 6630; CHECK-NEXT:    mul a0, a0, a1631; CHECK-NEXT:    sub sp, sp, a0632; CHECK-NEXT:    addi a0, sp, 16633; CHECK-NEXT:    csrr a1, vlenb634; CHECK-NEXT:    slli a1, a1, 1635; CHECK-NEXT:    vsetvli a2, zero, e16, m2, ta, ma636; CHECK-NEXT:    vsseg3e16.v v8, (a0)637; CHECK-NEXT:    vl2re16.v v8, (a0)638; CHECK-NEXT:    add a0, a0, a1639; CHECK-NEXT:    vl2re16.v v10, (a0)640; CHECK-NEXT:    add a0, a0, a1641; CHECK-NEXT:    vl2re16.v v12, (a0)642; CHECK-NEXT:    csrr a0, vlenb643; CHECK-NEXT:    li a1, 6644; CHECK-NEXT:    mul a0, a0, a1645; CHECK-NEXT:    add sp, sp, a0646; CHECK-NEXT:    addi sp, sp, 16647; CHECK-NEXT:    ret648;649; ZVBB-LABEL: vector_interleave_nxv24i16_nxv8i16:650; ZVBB:       # %bb.0:651; ZVBB-NEXT:    addi sp, sp, -16652; ZVBB-NEXT:    csrr a0, vlenb653; ZVBB-NEXT:    li a1, 6654; ZVBB-NEXT:    mul a0, a0, a1655; ZVBB-NEXT:    sub sp, sp, a0656; ZVBB-NEXT:    addi a0, sp, 16657; ZVBB-NEXT:    csrr a1, vlenb658; ZVBB-NEXT:    slli a1, a1, 1659; ZVBB-NEXT:    vsetvli a2, zero, e16, m2, ta, ma660; ZVBB-NEXT:    vsseg3e16.v v8, (a0)661; ZVBB-NEXT:    vl2re16.v v8, (a0)662; ZVBB-NEXT:    add a0, a0, a1663; ZVBB-NEXT:    vl2re16.v v10, (a0)664; ZVBB-NEXT:    add a0, a0, a1665; ZVBB-NEXT:    vl2re16.v v12, (a0)666; ZVBB-NEXT:    csrr a0, vlenb667; ZVBB-NEXT:    li a1, 6668; ZVBB-NEXT:    mul a0, a0, a1669; ZVBB-NEXT:    add sp, sp, a0670; ZVBB-NEXT:    addi sp, sp, 16671; ZVBB-NEXT:    ret672  %res = call <vscale x 24 x i16> @llvm.vector.interleave3.nxv24i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c)673  ret <vscale x 24 x i16> %res674}675 676 677define <vscale x 12 x i32> @vector_interleave_nxv12i32_nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) nounwind {678; CHECK-LABEL: vector_interleave_nxv12i32_nxv4i32:679; CHECK:       # %bb.0:680; CHECK-NEXT:    addi sp, sp, -16681; CHECK-NEXT:    csrr a0, vlenb682; CHECK-NEXT:    li a1, 6683; CHECK-NEXT:    mul a0, a0, a1684; CHECK-NEXT:    sub sp, sp, a0685; CHECK-NEXT:    addi a0, sp, 16686; CHECK-NEXT:    csrr a1, vlenb687; CHECK-NEXT:    slli a1, a1, 1688; CHECK-NEXT:    vsetvli a2, zero, e32, m2, ta, ma689; CHECK-NEXT:    vsseg3e32.v v8, (a0)690; CHECK-NEXT:    vl2re32.v v8, (a0)691; CHECK-NEXT:    add a0, a0, a1692; CHECK-NEXT:    vl2re32.v v10, (a0)693; CHECK-NEXT:    add a0, a0, a1694; CHECK-NEXT:    vl2re32.v v12, (a0)695; CHECK-NEXT:    csrr a0, vlenb696; CHECK-NEXT:    li a1, 6697; CHECK-NEXT:    mul a0, a0, a1698; CHECK-NEXT:    add sp, sp, a0699; CHECK-NEXT:    addi sp, sp, 16700; CHECK-NEXT:    ret701;702; ZVBB-LABEL: vector_interleave_nxv12i32_nxv4i32:703; ZVBB:       # %bb.0:704; ZVBB-NEXT:    addi sp, sp, -16705; ZVBB-NEXT:    csrr a0, vlenb706; ZVBB-NEXT:    li a1, 6707; ZVBB-NEXT:    mul a0, a0, a1708; ZVBB-NEXT:    sub sp, sp, a0709; ZVBB-NEXT:    addi a0, sp, 16710; ZVBB-NEXT:    csrr a1, vlenb711; ZVBB-NEXT:    slli a1, a1, 1712; ZVBB-NEXT:    vsetvli a2, zero, e32, m2, ta, ma713; ZVBB-NEXT:    vsseg3e32.v v8, (a0)714; ZVBB-NEXT:    vl2re32.v v8, (a0)715; ZVBB-NEXT:    add a0, a0, a1716; ZVBB-NEXT:    vl2re32.v v10, (a0)717; ZVBB-NEXT:    add a0, a0, a1718; ZVBB-NEXT:    vl2re32.v v12, (a0)719; ZVBB-NEXT:    csrr a0, vlenb720; ZVBB-NEXT:    li a1, 6721; ZVBB-NEXT:    mul a0, a0, a1722; ZVBB-NEXT:    add sp, sp, a0723; ZVBB-NEXT:    addi sp, sp, 16724; ZVBB-NEXT:    ret725  %res = call <vscale x 12 x i32> @llvm.vector.interleave3.nxv12i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c)726  ret <vscale x 12 x i32> %res727}728 729 730define <vscale x 6 x i64> @vector_interleave_nxv6i64_nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c) nounwind {731; CHECK-LABEL: vector_interleave_nxv6i64_nxv2i64:732; CHECK:       # %bb.0:733; CHECK-NEXT:    addi sp, sp, -16734; CHECK-NEXT:    csrr a0, vlenb735; CHECK-NEXT:    li a1, 6736; CHECK-NEXT:    mul a0, a0, a1737; CHECK-NEXT:    sub sp, sp, a0738; CHECK-NEXT:    addi a0, sp, 16739; CHECK-NEXT:    csrr a1, vlenb740; CHECK-NEXT:    slli a1, a1, 1741; CHECK-NEXT:    vsetvli a2, zero, e64, m2, ta, ma742; CHECK-NEXT:    vsseg3e64.v v8, (a0)743; CHECK-NEXT:    vl2re64.v v8, (a0)744; CHECK-NEXT:    add a0, a0, a1745; CHECK-NEXT:    vl2re64.v v10, (a0)746; CHECK-NEXT:    add a0, a0, a1747; CHECK-NEXT:    vl2re64.v v12, (a0)748; CHECK-NEXT:    csrr a0, vlenb749; CHECK-NEXT:    li a1, 6750; CHECK-NEXT:    mul a0, a0, a1751; CHECK-NEXT:    add sp, sp, a0752; CHECK-NEXT:    addi sp, sp, 16753; CHECK-NEXT:    ret754;755; ZVBB-LABEL: vector_interleave_nxv6i64_nxv2i64:756; ZVBB:       # %bb.0:757; ZVBB-NEXT:    addi sp, sp, -16758; ZVBB-NEXT:    csrr a0, vlenb759; ZVBB-NEXT:    li a1, 6760; ZVBB-NEXT:    mul a0, a0, a1761; ZVBB-NEXT:    sub sp, sp, a0762; ZVBB-NEXT:    addi a0, sp, 16763; ZVBB-NEXT:    csrr a1, vlenb764; ZVBB-NEXT:    slli a1, a1, 1765; ZVBB-NEXT:    vsetvli a2, zero, e64, m2, ta, ma766; ZVBB-NEXT:    vsseg3e64.v v8, (a0)767; ZVBB-NEXT:    vl2re64.v v8, (a0)768; ZVBB-NEXT:    add a0, a0, a1769; ZVBB-NEXT:    vl2re64.v v10, (a0)770; ZVBB-NEXT:    add a0, a0, a1771; ZVBB-NEXT:    vl2re64.v v12, (a0)772; ZVBB-NEXT:    csrr a0, vlenb773; ZVBB-NEXT:    li a1, 6774; ZVBB-NEXT:    mul a0, a0, a1775; ZVBB-NEXT:    add sp, sp, a0776; ZVBB-NEXT:    addi sp, sp, 16777; ZVBB-NEXT:    ret778  %res = call <vscale x 6 x i64> @llvm.vector.interleave3.nxv6i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c)779  ret <vscale x 6 x i64> %res780}781 782define <vscale x 64 x i1> @vector_interleave_nxv64i1_nxv16i1(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b, <vscale x 16 x i1> %c, <vscale x 16 x i1> %d) nounwind {783; CHECK-LABEL: vector_interleave_nxv64i1_nxv16i1:784; CHECK:       # %bb.0:785; CHECK-NEXT:    addi sp, sp, -16786; CHECK-NEXT:    csrr a0, vlenb787; CHECK-NEXT:    slli a0, a0, 3788; CHECK-NEXT:    sub sp, sp, a0789; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, ma790; CHECK-NEXT:    vmv1r.v v11, v0791; CHECK-NEXT:    vmv1r.v v0, v8792; CHECK-NEXT:    vmv.v.i v12, 0793; CHECK-NEXT:    addi a0, sp, 16794; CHECK-NEXT:    csrr a1, vlenb795; CHECK-NEXT:    vmerge.vim v16, v12, 1, v0796; CHECK-NEXT:    slli a2, a1, 1797; CHECK-NEXT:    vmv1r.v v0, v11798; CHECK-NEXT:    vmerge.vim v14, v12, 1, v0799; CHECK-NEXT:    add a3, a0, a2800; CHECK-NEXT:    vmv1r.v v0, v9801; CHECK-NEXT:    vmerge.vim v18, v12, 1, v0802; CHECK-NEXT:    add a4, a3, a2803; CHECK-NEXT:    vmv1r.v v0, v10804; CHECK-NEXT:    vmerge.vim v20, v12, 1, v0805; CHECK-NEXT:    add a2, a4, a2806; CHECK-NEXT:    vsseg4e8.v v14, (a0)807; CHECK-NEXT:    vl2r.v v8, (a2)808; CHECK-NEXT:    srli a2, a1, 1809; CHECK-NEXT:    srli a1, a1, 2810; CHECK-NEXT:    vl2r.v v10, (a4)811; CHECK-NEXT:    vl2r.v v12, (a3)812; CHECK-NEXT:    vl2r.v v14, (a0)813; CHECK-NEXT:    vmsne.vi v16, v8, 0814; CHECK-NEXT:    vmsne.vi v8, v10, 0815; CHECK-NEXT:    vmsne.vi v9, v12, 0816; CHECK-NEXT:    vmsne.vi v0, v14, 0817; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma818; CHECK-NEXT:    vslideup.vx v8, v16, a1819; CHECK-NEXT:    vslideup.vx v0, v9, a1820; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma821; CHECK-NEXT:    vslideup.vx v0, v8, a2822; CHECK-NEXT:    csrr a0, vlenb823; CHECK-NEXT:    slli a0, a0, 3824; CHECK-NEXT:    add sp, sp, a0825; CHECK-NEXT:    addi sp, sp, 16826; CHECK-NEXT:    ret827;828; ZVBB-LABEL: vector_interleave_nxv64i1_nxv16i1:829; ZVBB:       # %bb.0:830; ZVBB-NEXT:    addi sp, sp, -16831; ZVBB-NEXT:    csrr a0, vlenb832; ZVBB-NEXT:    slli a0, a0, 3833; ZVBB-NEXT:    sub sp, sp, a0834; ZVBB-NEXT:    vsetvli a0, zero, e8, m2, ta, ma835; ZVBB-NEXT:    vmv1r.v v11, v0836; ZVBB-NEXT:    vmv1r.v v0, v8837; ZVBB-NEXT:    vmv.v.i v12, 0838; ZVBB-NEXT:    addi a0, sp, 16839; ZVBB-NEXT:    csrr a1, vlenb840; ZVBB-NEXT:    vmerge.vim v16, v12, 1, v0841; ZVBB-NEXT:    slli a2, a1, 1842; ZVBB-NEXT:    vmv1r.v v0, v11843; ZVBB-NEXT:    vmerge.vim v14, v12, 1, v0844; ZVBB-NEXT:    add a3, a0, a2845; ZVBB-NEXT:    vmv1r.v v0, v9846; ZVBB-NEXT:    vmerge.vim v18, v12, 1, v0847; ZVBB-NEXT:    add a4, a3, a2848; ZVBB-NEXT:    vmv1r.v v0, v10849; ZVBB-NEXT:    vmerge.vim v20, v12, 1, v0850; ZVBB-NEXT:    add a2, a4, a2851; ZVBB-NEXT:    vsseg4e8.v v14, (a0)852; ZVBB-NEXT:    vl2r.v v8, (a2)853; ZVBB-NEXT:    srli a2, a1, 1854; ZVBB-NEXT:    srli a1, a1, 2855; ZVBB-NEXT:    vl2r.v v10, (a4)856; ZVBB-NEXT:    vl2r.v v12, (a3)857; ZVBB-NEXT:    vl2r.v v14, (a0)858; ZVBB-NEXT:    vmsne.vi v16, v8, 0859; ZVBB-NEXT:    vmsne.vi v8, v10, 0860; ZVBB-NEXT:    vmsne.vi v9, v12, 0861; ZVBB-NEXT:    vmsne.vi v0, v14, 0862; ZVBB-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma863; ZVBB-NEXT:    vslideup.vx v8, v16, a1864; ZVBB-NEXT:    vslideup.vx v0, v9, a1865; ZVBB-NEXT:    vsetvli a0, zero, e8, m1, ta, ma866; ZVBB-NEXT:    vslideup.vx v0, v8, a2867; ZVBB-NEXT:    csrr a0, vlenb868; ZVBB-NEXT:    slli a0, a0, 3869; ZVBB-NEXT:    add sp, sp, a0870; ZVBB-NEXT:    addi sp, sp, 16871; ZVBB-NEXT:    ret872  %res = call <vscale x 64 x i1> @llvm.vector.interleave4.nxv64i1(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b, <vscale x 16 x i1> %c, <vscale x 16 x i1> %d)873  ret <vscale x 64 x i1> %res874}875 876define <vscale x 64 x i8> @vector_interleave_nxv64i8_nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c, <vscale x 16 x i8> %d) nounwind {877;878; CHECK-LABEL: vector_interleave_nxv64i8_nxv16i8:879; CHECK:       # %bb.0:880; CHECK-NEXT:    addi sp, sp, -16881; CHECK-NEXT:    csrr a0, vlenb882; CHECK-NEXT:    slli a0, a0, 3883; CHECK-NEXT:    sub sp, sp, a0884; CHECK-NEXT:    addi a0, sp, 16885; CHECK-NEXT:    csrr a1, vlenb886; CHECK-NEXT:    slli a1, a1, 1887; CHECK-NEXT:    add a2, a0, a1888; CHECK-NEXT:    vsetvli a3, zero, e8, m2, ta, ma889; CHECK-NEXT:    vsseg4e8.v v8, (a0)890; CHECK-NEXT:    add a3, a2, a1891; CHECK-NEXT:    vl2r.v v12, (a3)892; CHECK-NEXT:    add a1, a3, a1893; CHECK-NEXT:    vl2r.v v14, (a1)894; CHECK-NEXT:    vl2r.v v8, (a0)895; CHECK-NEXT:    vl2r.v v10, (a2)896; CHECK-NEXT:    csrr a0, vlenb897; CHECK-NEXT:    slli a0, a0, 3898; CHECK-NEXT:    add sp, sp, a0899; CHECK-NEXT:    addi sp, sp, 16900; CHECK-NEXT:    ret901;902; ZVBB-LABEL: vector_interleave_nxv64i8_nxv16i8:903; ZVBB:       # %bb.0:904; ZVBB-NEXT:    addi sp, sp, -16905; ZVBB-NEXT:    csrr a0, vlenb906; ZVBB-NEXT:    slli a0, a0, 3907; ZVBB-NEXT:    sub sp, sp, a0908; ZVBB-NEXT:    addi a0, sp, 16909; ZVBB-NEXT:    csrr a1, vlenb910; ZVBB-NEXT:    slli a1, a1, 1911; ZVBB-NEXT:    add a2, a0, a1912; ZVBB-NEXT:    vsetvli a3, zero, e8, m2, ta, ma913; ZVBB-NEXT:    vsseg4e8.v v8, (a0)914; ZVBB-NEXT:    add a3, a2, a1915; ZVBB-NEXT:    vl2r.v v12, (a3)916; ZVBB-NEXT:    add a1, a3, a1917; ZVBB-NEXT:    vl2r.v v14, (a1)918; ZVBB-NEXT:    vl2r.v v8, (a0)919; ZVBB-NEXT:    vl2r.v v10, (a2)920; ZVBB-NEXT:    csrr a0, vlenb921; ZVBB-NEXT:    slli a0, a0, 3922; ZVBB-NEXT:    add sp, sp, a0923; ZVBB-NEXT:    addi sp, sp, 16924; ZVBB-NEXT:    ret925  %res = call <vscale x 64 x i8> @llvm.vector.interleave4.nxv64i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c, <vscale x 16 x i8> %d)926  ret <vscale x 64 x i8> %res927}928 929define <vscale x 32 x i8> @vector_interleave_nxv32i8_nxv8i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b, <vscale x 8 x i8> %c, <vscale x 8 x i8> %d) nounwind {930; CHECK-LABEL: vector_interleave_nxv32i8_nxv8i8:931; CHECK:       # %bb.0:932; CHECK-NEXT:    addi sp, sp, -16933; CHECK-NEXT:    csrr a0, vlenb934; CHECK-NEXT:    slli a0, a0, 2935; CHECK-NEXT:    sub sp, sp, a0936; CHECK-NEXT:    addi a0, sp, 16937; CHECK-NEXT:    csrr a1, vlenb938; CHECK-NEXT:    add a2, a0, a1939; CHECK-NEXT:    add a3, a2, a1940; CHECK-NEXT:    vsetvli a4, zero, e8, m1, ta, ma941; CHECK-NEXT:    vsseg4e8.v v8, (a0)942; CHECK-NEXT:    vl1r.v v10, (a3)943; CHECK-NEXT:    add a1, a3, a1944; CHECK-NEXT:    vl1r.v v11, (a1)945; CHECK-NEXT:    vl1r.v v8, (a0)946; CHECK-NEXT:    vl1r.v v9, (a2)947; CHECK-NEXT:    csrr a0, vlenb948; CHECK-NEXT:    slli a0, a0, 2949; CHECK-NEXT:    add sp, sp, a0950; CHECK-NEXT:    addi sp, sp, 16951; CHECK-NEXT:    ret952;953; ZVBB-LABEL: vector_interleave_nxv32i8_nxv8i8:954; ZVBB:       # %bb.0:955; ZVBB-NEXT:    addi sp, sp, -16956; ZVBB-NEXT:    csrr a0, vlenb957; ZVBB-NEXT:    slli a0, a0, 2958; ZVBB-NEXT:    sub sp, sp, a0959; ZVBB-NEXT:    addi a0, sp, 16960; ZVBB-NEXT:    csrr a1, vlenb961; ZVBB-NEXT:    add a2, a0, a1962; ZVBB-NEXT:    add a3, a2, a1963; ZVBB-NEXT:    vsetvli a4, zero, e8, m1, ta, ma964; ZVBB-NEXT:    vsseg4e8.v v8, (a0)965; ZVBB-NEXT:    vl1r.v v10, (a3)966; ZVBB-NEXT:    add a1, a3, a1967; ZVBB-NEXT:    vl1r.v v11, (a1)968; ZVBB-NEXT:    vl1r.v v8, (a0)969; ZVBB-NEXT:    vl1r.v v9, (a2)970; ZVBB-NEXT:    csrr a0, vlenb971; ZVBB-NEXT:    slli a0, a0, 2972; ZVBB-NEXT:    add sp, sp, a0973; ZVBB-NEXT:    addi sp, sp, 16974; ZVBB-NEXT:    ret975  %res = call <vscale x 32 x i8> @llvm.vector.interleave4.nxv32i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b, <vscale x 8 x i8> %c, <vscale x 8 x i8> %d)976  ret <vscale x 32 x i8> %res977}978 979define <vscale x 16 x i32> @vector_interleave_nxv16i32_nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c, <vscale x 4 x i32> %d) nounwind {980;981; CHECK-LABEL: vector_interleave_nxv16i32_nxv4i32:982; CHECK:       # %bb.0:983; CHECK-NEXT:    addi sp, sp, -16984; CHECK-NEXT:    csrr a0, vlenb985; CHECK-NEXT:    slli a0, a0, 3986; CHECK-NEXT:    sub sp, sp, a0987; CHECK-NEXT:    addi a0, sp, 16988; CHECK-NEXT:    csrr a1, vlenb989; CHECK-NEXT:    slli a1, a1, 1990; CHECK-NEXT:    add a2, a0, a1991; CHECK-NEXT:    vsetvli a3, zero, e32, m2, ta, ma992; CHECK-NEXT:    vsseg4e32.v v8, (a0)993; CHECK-NEXT:    add a3, a2, a1994; CHECK-NEXT:    vl2re32.v v12, (a3)995; CHECK-NEXT:    add a1, a3, a1996; CHECK-NEXT:    vl2re32.v v14, (a1)997; CHECK-NEXT:    vl2re32.v v8, (a0)998; CHECK-NEXT:    vl2re32.v v10, (a2)999; CHECK-NEXT:    csrr a0, vlenb1000; CHECK-NEXT:    slli a0, a0, 31001; CHECK-NEXT:    add sp, sp, a01002; CHECK-NEXT:    addi sp, sp, 161003; CHECK-NEXT:    ret1004;1005; ZVBB-LABEL: vector_interleave_nxv16i32_nxv4i32:1006; ZVBB:       # %bb.0:1007; ZVBB-NEXT:    addi sp, sp, -161008; ZVBB-NEXT:    csrr a0, vlenb1009; ZVBB-NEXT:    slli a0, a0, 31010; ZVBB-NEXT:    sub sp, sp, a01011; ZVBB-NEXT:    addi a0, sp, 161012; ZVBB-NEXT:    csrr a1, vlenb1013; ZVBB-NEXT:    slli a1, a1, 11014; ZVBB-NEXT:    add a2, a0, a11015; ZVBB-NEXT:    vsetvli a3, zero, e32, m2, ta, ma1016; ZVBB-NEXT:    vsseg4e32.v v8, (a0)1017; ZVBB-NEXT:    add a3, a2, a11018; ZVBB-NEXT:    vl2re32.v v12, (a3)1019; ZVBB-NEXT:    add a1, a3, a11020; ZVBB-NEXT:    vl2re32.v v14, (a1)1021; ZVBB-NEXT:    vl2re32.v v8, (a0)1022; ZVBB-NEXT:    vl2re32.v v10, (a2)1023; ZVBB-NEXT:    csrr a0, vlenb1024; ZVBB-NEXT:    slli a0, a0, 31025; ZVBB-NEXT:    add sp, sp, a01026; ZVBB-NEXT:    addi sp, sp, 161027; ZVBB-NEXT:    ret1028  %res = call <vscale x 16 x i32> @llvm.vector.interleave4.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c, <vscale x 4 x i32> %d)1029  ret <vscale x 16 x i32> %res1030}1031 1032define <vscale x 8 x i64> @vector_interleave_nxv8i64_nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c, <vscale x 2 x i64> %d) nounwind {1033;1034; CHECK-LABEL: vector_interleave_nxv8i64_nxv2i64:1035; CHECK:       # %bb.0:1036; CHECK-NEXT:    addi sp, sp, -161037; CHECK-NEXT:    csrr a0, vlenb1038; CHECK-NEXT:    slli a0, a0, 31039; CHECK-NEXT:    sub sp, sp, a01040; CHECK-NEXT:    addi a0, sp, 161041; CHECK-NEXT:    csrr a1, vlenb1042; CHECK-NEXT:    slli a1, a1, 11043; CHECK-NEXT:    add a2, a0, a11044; CHECK-NEXT:    vsetvli a3, zero, e64, m2, ta, ma1045; CHECK-NEXT:    vsseg4e64.v v8, (a0)1046; CHECK-NEXT:    add a3, a2, a11047; CHECK-NEXT:    vl2re64.v v12, (a3)1048; CHECK-NEXT:    add a1, a3, a11049; CHECK-NEXT:    vl2re64.v v14, (a1)1050; CHECK-NEXT:    vl2re64.v v8, (a0)1051; CHECK-NEXT:    vl2re64.v v10, (a2)1052; CHECK-NEXT:    csrr a0, vlenb1053; CHECK-NEXT:    slli a0, a0, 31054; CHECK-NEXT:    add sp, sp, a01055; CHECK-NEXT:    addi sp, sp, 161056; CHECK-NEXT:    ret1057;1058; ZVBB-LABEL: vector_interleave_nxv8i64_nxv2i64:1059; ZVBB:       # %bb.0:1060; ZVBB-NEXT:    addi sp, sp, -161061; ZVBB-NEXT:    csrr a0, vlenb1062; ZVBB-NEXT:    slli a0, a0, 31063; ZVBB-NEXT:    sub sp, sp, a01064; ZVBB-NEXT:    addi a0, sp, 161065; ZVBB-NEXT:    csrr a1, vlenb1066; ZVBB-NEXT:    slli a1, a1, 11067; ZVBB-NEXT:    add a2, a0, a11068; ZVBB-NEXT:    vsetvli a3, zero, e64, m2, ta, ma1069; ZVBB-NEXT:    vsseg4e64.v v8, (a0)1070; ZVBB-NEXT:    add a3, a2, a11071; ZVBB-NEXT:    vl2re64.v v12, (a3)1072; ZVBB-NEXT:    add a1, a3, a11073; ZVBB-NEXT:    vl2re64.v v14, (a1)1074; ZVBB-NEXT:    vl2re64.v v8, (a0)1075; ZVBB-NEXT:    vl2re64.v v10, (a2)1076; ZVBB-NEXT:    csrr a0, vlenb1077; ZVBB-NEXT:    slli a0, a0, 31078; ZVBB-NEXT:    add sp, sp, a01079; ZVBB-NEXT:    addi sp, sp, 161080; ZVBB-NEXT:    ret1081  %res = call <vscale x 8 x i64> @llvm.vector.interleave4.nxv8i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c, <vscale x 2 x i64> %d)1082  ret <vscale x 8 x i64> %res1083}1084 1085define <vscale x 80 x i1> @vector_interleave_nxv80i1_nxv16i1(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b, <vscale x 16 x i1> %c, <vscale x 16 x i1> %d, <vscale x 16 x i1> %e) nounwind {1086; CHECK-LABEL: vector_interleave_nxv80i1_nxv16i1:1087; CHECK:       # %bb.0:1088; CHECK-NEXT:    addi sp, sp, -161089; CHECK-NEXT:    csrr a0, vlenb1090; CHECK-NEXT:    li a1, 101091; CHECK-NEXT:    mul a0, a0, a11092; CHECK-NEXT:    sub sp, sp, a01093; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, ma1094; CHECK-NEXT:    vmv.v.i v12, 01095; CHECK-NEXT:    addi a4, sp, 161096; CHECK-NEXT:    csrr a0, vlenb1097; CHECK-NEXT:    slli a1, a0, 21098; CHECK-NEXT:    add a0, a1, a01099; CHECK-NEXT:    add a0, sp, a01100; CHECK-NEXT:    addi a0, a0, 161101; CHECK-NEXT:    csrr a1, vlenb1102; CHECK-NEXT:    vmerge.vim v14, v12, 1, v01103; CHECK-NEXT:    vmv1r.v v0, v81104; CHECK-NEXT:    vmerge.vim v18, v12, 1, v01105; CHECK-NEXT:    add a2, a4, a11106; CHECK-NEXT:    srli a3, a1, 11107; CHECK-NEXT:    vmv2r.v v20, v141108; CHECK-NEXT:    vmv1r.v v0, v91109; CHECK-NEXT:    vmerge.vim v16, v12, 1, v01110; CHECK-NEXT:    vmv1r.v v21, v181111; CHECK-NEXT:    vmv1r.v v0, v101112; CHECK-NEXT:    vmerge.vim v8, v12, 1, v01113; CHECK-NEXT:    vmv1r.v v22, v161114; CHECK-NEXT:    vmv1r.v v16, v191115; CHECK-NEXT:    add a5, a2, a11116; CHECK-NEXT:    vmv1r.v v23, v81117; CHECK-NEXT:    vmv1r.v v18, v91118; CHECK-NEXT:    vmv1r.v v0, v111119; CHECK-NEXT:    vmerge.vim v24, v12, 1, v01120; CHECK-NEXT:    vsetvli a6, zero, e8, m1, ta, ma1121; CHECK-NEXT:    vsseg5e8.v v20, (a4)1122; CHECK-NEXT:    vmv1r.v v19, v251123; CHECK-NEXT:    vsseg5e8.v v15, (a0)1124; CHECK-NEXT:    vl1r.v v8, (a5)1125; CHECK-NEXT:    add a5, a5, a11126; CHECK-NEXT:    vl1r.v v10, (a4)1127; CHECK-NEXT:    add a4, a5, a11128; CHECK-NEXT:    vl1r.v v12, (a4)1129; CHECK-NEXT:    add a4, a0, a11130; CHECK-NEXT:    vl1r.v v14, (a4)1131; CHECK-NEXT:    add a4, a4, a11132; CHECK-NEXT:    vl1r.v v9, (a5)1133; CHECK-NEXT:    add a5, a4, a11134; CHECK-NEXT:    vl1r.v v16, (a5)1135; CHECK-NEXT:    add a5, a5, a11136; CHECK-NEXT:    srli a1, a1, 21137; CHECK-NEXT:    vl1r.v v11, (a2)1138; CHECK-NEXT:    vl1r.v v15, (a4)1139; CHECK-NEXT:    vl1r.v v13, (a0)1140; CHECK-NEXT:    vl1r.v v17, (a5)1141; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, ma1142; CHECK-NEXT:    vmsne.vi v18, v8, 01143; CHECK-NEXT:    vmsne.vi v0, v10, 01144; CHECK-NEXT:    vmsne.vi v8, v14, 01145; CHECK-NEXT:    vmsne.vi v9, v12, 01146; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma1147; CHECK-NEXT:    vslideup.vx v0, v18, a11148; CHECK-NEXT:    vslideup.vx v9, v8, a11149; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma1150; CHECK-NEXT:    vslideup.vx v0, v9, a31151; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, ma1152; CHECK-NEXT:    vmsne.vi v8, v16, 01153; CHECK-NEXT:    csrr a0, vlenb1154; CHECK-NEXT:    li a1, 101155; CHECK-NEXT:    mul a0, a0, a11156; CHECK-NEXT:    add sp, sp, a01157; CHECK-NEXT:    addi sp, sp, 161158; CHECK-NEXT:    ret1159;1160; ZVBB-LABEL: vector_interleave_nxv80i1_nxv16i1:1161; ZVBB:       # %bb.0:1162; ZVBB-NEXT:    addi sp, sp, -161163; ZVBB-NEXT:    csrr a0, vlenb1164; ZVBB-NEXT:    li a1, 101165; ZVBB-NEXT:    mul a0, a0, a11166; ZVBB-NEXT:    sub sp, sp, a01167; ZVBB-NEXT:    vsetvli a0, zero, e8, m2, ta, ma1168; ZVBB-NEXT:    vmv.v.i v12, 01169; ZVBB-NEXT:    addi a4, sp, 161170; ZVBB-NEXT:    csrr a0, vlenb1171; ZVBB-NEXT:    slli a1, a0, 21172; ZVBB-NEXT:    add a0, a1, a01173; ZVBB-NEXT:    add a0, sp, a01174; ZVBB-NEXT:    addi a0, a0, 161175; ZVBB-NEXT:    csrr a1, vlenb1176; ZVBB-NEXT:    vmerge.vim v14, v12, 1, v01177; ZVBB-NEXT:    vmv1r.v v0, v81178; ZVBB-NEXT:    vmerge.vim v18, v12, 1, v01179; ZVBB-NEXT:    add a2, a4, a11180; ZVBB-NEXT:    srli a3, a1, 11181; ZVBB-NEXT:    vmv2r.v v20, v141182; ZVBB-NEXT:    vmv1r.v v0, v91183; ZVBB-NEXT:    vmerge.vim v16, v12, 1, v01184; ZVBB-NEXT:    vmv1r.v v21, v181185; ZVBB-NEXT:    vmv1r.v v0, v101186; ZVBB-NEXT:    vmerge.vim v8, v12, 1, v01187; ZVBB-NEXT:    vmv1r.v v22, v161188; ZVBB-NEXT:    vmv1r.v v16, v191189; ZVBB-NEXT:    add a5, a2, a11190; ZVBB-NEXT:    vmv1r.v v23, v81191; ZVBB-NEXT:    vmv1r.v v18, v91192; ZVBB-NEXT:    vmv1r.v v0, v111193; ZVBB-NEXT:    vmerge.vim v24, v12, 1, v01194; ZVBB-NEXT:    vsetvli a6, zero, e8, m1, ta, ma1195; ZVBB-NEXT:    vsseg5e8.v v20, (a4)1196; ZVBB-NEXT:    vmv1r.v v19, v251197; ZVBB-NEXT:    vsseg5e8.v v15, (a0)1198; ZVBB-NEXT:    vl1r.v v8, (a5)1199; ZVBB-NEXT:    add a5, a5, a11200; ZVBB-NEXT:    vl1r.v v10, (a4)1201; ZVBB-NEXT:    add a4, a5, a11202; ZVBB-NEXT:    vl1r.v v12, (a4)1203; ZVBB-NEXT:    add a4, a0, a11204; ZVBB-NEXT:    vl1r.v v14, (a4)1205; ZVBB-NEXT:    add a4, a4, a11206; ZVBB-NEXT:    vl1r.v v9, (a5)1207; ZVBB-NEXT:    add a5, a4, a11208; ZVBB-NEXT:    vl1r.v v16, (a5)1209; ZVBB-NEXT:    add a5, a5, a11210; ZVBB-NEXT:    srli a1, a1, 21211; ZVBB-NEXT:    vl1r.v v11, (a2)1212; ZVBB-NEXT:    vl1r.v v15, (a4)1213; ZVBB-NEXT:    vl1r.v v13, (a0)1214; ZVBB-NEXT:    vl1r.v v17, (a5)1215; ZVBB-NEXT:    vsetvli a0, zero, e8, m2, ta, ma1216; ZVBB-NEXT:    vmsne.vi v18, v8, 01217; ZVBB-NEXT:    vmsne.vi v0, v10, 01218; ZVBB-NEXT:    vmsne.vi v8, v14, 01219; ZVBB-NEXT:    vmsne.vi v9, v12, 01220; ZVBB-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma1221; ZVBB-NEXT:    vslideup.vx v0, v18, a11222; ZVBB-NEXT:    vslideup.vx v9, v8, a11223; ZVBB-NEXT:    vsetvli a0, zero, e8, m1, ta, ma1224; ZVBB-NEXT:    vslideup.vx v0, v9, a31225; ZVBB-NEXT:    vsetvli a0, zero, e8, m2, ta, ma1226; ZVBB-NEXT:    vmsne.vi v8, v16, 01227; ZVBB-NEXT:    csrr a0, vlenb1228; ZVBB-NEXT:    li a1, 101229; ZVBB-NEXT:    mul a0, a0, a11230; ZVBB-NEXT:    add sp, sp, a01231; ZVBB-NEXT:    addi sp, sp, 161232; ZVBB-NEXT:    ret1233  %res = call <vscale x 80 x i1> @llvm.vector.interleave5.nxv80i1(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b, <vscale x 16 x i1> %c, <vscale x 16 x i1> %d, <vscale x 16 x i1> %e)1234  ret <vscale x 80 x i1> %res1235}1236 1237 1238define <vscale x 80 x i8> @vector_interleave_nxv80i8_nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c, <vscale x 16 x i8> %d, <vscale x 16 x i8> %e) nounwind {1239;1240; RV32-LABEL: vector_interleave_nxv80i8_nxv16i8:1241; RV32:       # %bb.0:1242; RV32-NEXT:    addi sp, sp, -801243; RV32-NEXT:    sw ra, 76(sp) # 4-byte Folded Spill1244; RV32-NEXT:    sw s0, 72(sp) # 4-byte Folded Spill1245; RV32-NEXT:    addi s0, sp, 801246; RV32-NEXT:    csrr a0, vlenb1247; RV32-NEXT:    li a1, 281248; RV32-NEXT:    mul a0, a0, a11249; RV32-NEXT:    sub sp, sp, a01250; RV32-NEXT:    andi sp, sp, -641251; RV32-NEXT:    vsetvli a0, zero, e8, m1, ta, ma1252; RV32-NEXT:    vmv2r.v v20, v161253; RV32-NEXT:    addi a0, sp, 641254; RV32-NEXT:    vmv2r.v v18, v121255; RV32-NEXT:    csrr a1, vlenb1256; RV32-NEXT:    slli a2, a1, 21257; RV32-NEXT:    add a1, a2, a11258; RV32-NEXT:    add a1, sp, a11259; RV32-NEXT:    addi a1, a1, 641260; RV32-NEXT:    csrr a2, vlenb1261; RV32-NEXT:    vmv2r.v v16, v81262; RV32-NEXT:    vmv2r.v v22, v161263; RV32-NEXT:    vmv2r.v v24, v181264; RV32-NEXT:    vmv1r.v v26, v201265; RV32-NEXT:    add a3, a0, a21266; RV32-NEXT:    vmv1r.v v23, v101267; RV32-NEXT:    add a4, a1, a21268; RV32-NEXT:    add a5, a4, a21269; RV32-NEXT:    vmv1r.v v25, v141270; RV32-NEXT:    add a6, a5, a21271; RV32-NEXT:    vmv1r.v v18, v111272; RV32-NEXT:    vsseg5e8.v v22, (a0)1273; RV32-NEXT:    vmv1r.v v20, v151274; RV32-NEXT:    vsseg5e8.v v17, (a1)1275; RV32-NEXT:    vl1r.v v16, (a6)1276; RV32-NEXT:    add a6, a6, a21277; RV32-NEXT:    vl1r.v v17, (a6)1278; RV32-NEXT:    add a6, a3, a21279; RV32-NEXT:    vl1r.v v10, (a6)1280; RV32-NEXT:    add a6, a6, a21281; RV32-NEXT:    vl1r.v v11, (a6)1282; RV32-NEXT:    vl1r.v v8, (a0)1283; RV32-NEXT:    vl1r.v v9, (a3)1284; RV32-NEXT:    vl1r.v v14, (a4)1285; RV32-NEXT:    csrr a0, vlenb1286; RV32-NEXT:    li a3, 101287; RV32-NEXT:    mul a0, a0, a31288; RV32-NEXT:    add a0, sp, a01289; RV32-NEXT:    addi a0, a0, 641290; RV32-NEXT:    add a6, a6, a21291; RV32-NEXT:    vl1r.v v15, (a5)1292; RV32-NEXT:    vl1r.v v12, (a6)1293; RV32-NEXT:    vl1r.v v13, (a1)1294; RV32-NEXT:    slli a2, a2, 31295; RV32-NEXT:    add a2, a0, a21296; RV32-NEXT:    vs2r.v v16, (a2)1297; RV32-NEXT:    vs8r.v v8, (a0)1298; RV32-NEXT:    vl8r.v v16, (a2)1299; RV32-NEXT:    vl8r.v v8, (a0)1300; RV32-NEXT:    addi sp, s0, -801301; RV32-NEXT:    lw ra, 76(sp) # 4-byte Folded Reload1302; RV32-NEXT:    lw s0, 72(sp) # 4-byte Folded Reload1303; RV32-NEXT:    addi sp, sp, 801304; RV32-NEXT:    ret1305;1306; RV64-LABEL: vector_interleave_nxv80i8_nxv16i8:1307; RV64:       # %bb.0:1308; RV64-NEXT:    addi sp, sp, -801309; RV64-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill1310; RV64-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill1311; RV64-NEXT:    addi s0, sp, 801312; RV64-NEXT:    csrr a0, vlenb1313; RV64-NEXT:    li a1, 281314; RV64-NEXT:    mul a0, a0, a11315; RV64-NEXT:    sub sp, sp, a01316; RV64-NEXT:    andi sp, sp, -641317; RV64-NEXT:    vsetvli a0, zero, e8, m1, ta, ma1318; RV64-NEXT:    vmv2r.v v20, v161319; RV64-NEXT:    addi a0, sp, 641320; RV64-NEXT:    vmv2r.v v18, v121321; RV64-NEXT:    csrr a1, vlenb1322; RV64-NEXT:    slli a2, a1, 21323; RV64-NEXT:    add a1, a2, a11324; RV64-NEXT:    add a1, sp, a11325; RV64-NEXT:    addi a1, a1, 641326; RV64-NEXT:    csrr a2, vlenb1327; RV64-NEXT:    vmv2r.v v16, v81328; RV64-NEXT:    vmv2r.v v22, v161329; RV64-NEXT:    vmv2r.v v24, v181330; RV64-NEXT:    vmv1r.v v26, v201331; RV64-NEXT:    add a3, a0, a21332; RV64-NEXT:    vmv1r.v v23, v101333; RV64-NEXT:    add a4, a1, a21334; RV64-NEXT:    add a5, a4, a21335; RV64-NEXT:    vmv1r.v v25, v141336; RV64-NEXT:    add a6, a5, a21337; RV64-NEXT:    vmv1r.v v18, v111338; RV64-NEXT:    vsseg5e8.v v22, (a0)1339; RV64-NEXT:    vmv1r.v v20, v151340; RV64-NEXT:    vsseg5e8.v v17, (a1)1341; RV64-NEXT:    vl1r.v v16, (a6)1342; RV64-NEXT:    add a6, a6, a21343; RV64-NEXT:    vl1r.v v17, (a6)1344; RV64-NEXT:    add a6, a3, a21345; RV64-NEXT:    vl1r.v v10, (a6)1346; RV64-NEXT:    add a6, a6, a21347; RV64-NEXT:    vl1r.v v11, (a6)1348; RV64-NEXT:    vl1r.v v8, (a0)1349; RV64-NEXT:    vl1r.v v9, (a3)1350; RV64-NEXT:    vl1r.v v14, (a4)1351; RV64-NEXT:    csrr a0, vlenb1352; RV64-NEXT:    li a3, 101353; RV64-NEXT:    mul a0, a0, a31354; RV64-NEXT:    add a0, sp, a01355; RV64-NEXT:    addi a0, a0, 641356; RV64-NEXT:    add a6, a6, a21357; RV64-NEXT:    vl1r.v v15, (a5)1358; RV64-NEXT:    vl1r.v v12, (a6)1359; RV64-NEXT:    vl1r.v v13, (a1)1360; RV64-NEXT:    slli a2, a2, 31361; RV64-NEXT:    add a2, a0, a21362; RV64-NEXT:    vs2r.v v16, (a2)1363; RV64-NEXT:    vs8r.v v8, (a0)1364; RV64-NEXT:    vl8r.v v16, (a2)1365; RV64-NEXT:    vl8r.v v8, (a0)1366; RV64-NEXT:    addi sp, s0, -801367; RV64-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload1368; RV64-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload1369; RV64-NEXT:    addi sp, sp, 801370; RV64-NEXT:    ret1371;1372; ZVBB-RV32-LABEL: vector_interleave_nxv80i8_nxv16i8:1373; ZVBB-RV32:       # %bb.0:1374; ZVBB-RV32-NEXT:    addi sp, sp, -801375; ZVBB-RV32-NEXT:    sw ra, 76(sp) # 4-byte Folded Spill1376; ZVBB-RV32-NEXT:    sw s0, 72(sp) # 4-byte Folded Spill1377; ZVBB-RV32-NEXT:    addi s0, sp, 801378; ZVBB-RV32-NEXT:    csrr a0, vlenb1379; ZVBB-RV32-NEXT:    li a1, 281380; ZVBB-RV32-NEXT:    mul a0, a0, a11381; ZVBB-RV32-NEXT:    sub sp, sp, a01382; ZVBB-RV32-NEXT:    andi sp, sp, -641383; ZVBB-RV32-NEXT:    vsetvli a0, zero, e8, m1, ta, ma1384; ZVBB-RV32-NEXT:    vmv2r.v v20, v161385; ZVBB-RV32-NEXT:    addi a0, sp, 641386; ZVBB-RV32-NEXT:    vmv2r.v v18, v121387; ZVBB-RV32-NEXT:    csrr a1, vlenb1388; ZVBB-RV32-NEXT:    slli a2, a1, 21389; ZVBB-RV32-NEXT:    add a1, a2, a11390; ZVBB-RV32-NEXT:    add a1, sp, a11391; ZVBB-RV32-NEXT:    addi a1, a1, 641392; ZVBB-RV32-NEXT:    csrr a2, vlenb1393; ZVBB-RV32-NEXT:    vmv2r.v v16, v81394; ZVBB-RV32-NEXT:    vmv2r.v v22, v161395; ZVBB-RV32-NEXT:    vmv2r.v v24, v181396; ZVBB-RV32-NEXT:    vmv1r.v v26, v201397; ZVBB-RV32-NEXT:    add a3, a0, a21398; ZVBB-RV32-NEXT:    vmv1r.v v23, v101399; ZVBB-RV32-NEXT:    add a4, a1, a21400; ZVBB-RV32-NEXT:    add a5, a4, a21401; ZVBB-RV32-NEXT:    vmv1r.v v25, v141402; ZVBB-RV32-NEXT:    add a6, a5, a21403; ZVBB-RV32-NEXT:    vmv1r.v v18, v111404; ZVBB-RV32-NEXT:    vsseg5e8.v v22, (a0)1405; ZVBB-RV32-NEXT:    vmv1r.v v20, v151406; ZVBB-RV32-NEXT:    vsseg5e8.v v17, (a1)1407; ZVBB-RV32-NEXT:    vl1r.v v16, (a6)1408; ZVBB-RV32-NEXT:    add a6, a6, a21409; ZVBB-RV32-NEXT:    vl1r.v v17, (a6)1410; ZVBB-RV32-NEXT:    add a6, a3, a21411; ZVBB-RV32-NEXT:    vl1r.v v10, (a6)1412; ZVBB-RV32-NEXT:    add a6, a6, a21413; ZVBB-RV32-NEXT:    vl1r.v v11, (a6)1414; ZVBB-RV32-NEXT:    vl1r.v v8, (a0)1415; ZVBB-RV32-NEXT:    vl1r.v v9, (a3)1416; ZVBB-RV32-NEXT:    vl1r.v v14, (a4)1417; ZVBB-RV32-NEXT:    csrr a0, vlenb1418; ZVBB-RV32-NEXT:    li a3, 101419; ZVBB-RV32-NEXT:    mul a0, a0, a31420; ZVBB-RV32-NEXT:    add a0, sp, a01421; ZVBB-RV32-NEXT:    addi a0, a0, 641422; ZVBB-RV32-NEXT:    add a6, a6, a21423; ZVBB-RV32-NEXT:    vl1r.v v15, (a5)1424; ZVBB-RV32-NEXT:    vl1r.v v12, (a6)1425; ZVBB-RV32-NEXT:    vl1r.v v13, (a1)1426; ZVBB-RV32-NEXT:    slli a2, a2, 31427; ZVBB-RV32-NEXT:    add a2, a0, a21428; ZVBB-RV32-NEXT:    vs2r.v v16, (a2)1429; ZVBB-RV32-NEXT:    vs8r.v v8, (a0)1430; ZVBB-RV32-NEXT:    vl8r.v v16, (a2)1431; ZVBB-RV32-NEXT:    vl8r.v v8, (a0)1432; ZVBB-RV32-NEXT:    addi sp, s0, -801433; ZVBB-RV32-NEXT:    lw ra, 76(sp) # 4-byte Folded Reload1434; ZVBB-RV32-NEXT:    lw s0, 72(sp) # 4-byte Folded Reload1435; ZVBB-RV32-NEXT:    addi sp, sp, 801436; ZVBB-RV32-NEXT:    ret1437;1438; ZVBB-RV64-LABEL: vector_interleave_nxv80i8_nxv16i8:1439; ZVBB-RV64:       # %bb.0:1440; ZVBB-RV64-NEXT:    addi sp, sp, -801441; ZVBB-RV64-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill1442; ZVBB-RV64-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill1443; ZVBB-RV64-NEXT:    addi s0, sp, 801444; ZVBB-RV64-NEXT:    csrr a0, vlenb1445; ZVBB-RV64-NEXT:    li a1, 281446; ZVBB-RV64-NEXT:    mul a0, a0, a11447; ZVBB-RV64-NEXT:    sub sp, sp, a01448; ZVBB-RV64-NEXT:    andi sp, sp, -641449; ZVBB-RV64-NEXT:    vsetvli a0, zero, e8, m1, ta, ma1450; ZVBB-RV64-NEXT:    vmv2r.v v20, v161451; ZVBB-RV64-NEXT:    addi a0, sp, 641452; ZVBB-RV64-NEXT:    vmv2r.v v18, v121453; ZVBB-RV64-NEXT:    csrr a1, vlenb1454; ZVBB-RV64-NEXT:    slli a2, a1, 21455; ZVBB-RV64-NEXT:    add a1, a2, a11456; ZVBB-RV64-NEXT:    add a1, sp, a11457; ZVBB-RV64-NEXT:    addi a1, a1, 641458; ZVBB-RV64-NEXT:    csrr a2, vlenb1459; ZVBB-RV64-NEXT:    vmv2r.v v16, v81460; ZVBB-RV64-NEXT:    vmv2r.v v22, v161461; ZVBB-RV64-NEXT:    vmv2r.v v24, v181462; ZVBB-RV64-NEXT:    vmv1r.v v26, v201463; ZVBB-RV64-NEXT:    add a3, a0, a21464; ZVBB-RV64-NEXT:    vmv1r.v v23, v101465; ZVBB-RV64-NEXT:    add a4, a1, a21466; ZVBB-RV64-NEXT:    add a5, a4, a21467; ZVBB-RV64-NEXT:    vmv1r.v v25, v141468; ZVBB-RV64-NEXT:    add a6, a5, a21469; ZVBB-RV64-NEXT:    vmv1r.v v18, v111470; ZVBB-RV64-NEXT:    vsseg5e8.v v22, (a0)1471; ZVBB-RV64-NEXT:    vmv1r.v v20, v151472; ZVBB-RV64-NEXT:    vsseg5e8.v v17, (a1)1473; ZVBB-RV64-NEXT:    vl1r.v v16, (a6)1474; ZVBB-RV64-NEXT:    add a6, a6, a21475; ZVBB-RV64-NEXT:    vl1r.v v17, (a6)1476; ZVBB-RV64-NEXT:    add a6, a3, a21477; ZVBB-RV64-NEXT:    vl1r.v v10, (a6)1478; ZVBB-RV64-NEXT:    add a6, a6, a21479; ZVBB-RV64-NEXT:    vl1r.v v11, (a6)1480; ZVBB-RV64-NEXT:    vl1r.v v8, (a0)1481; ZVBB-RV64-NEXT:    vl1r.v v9, (a3)1482; ZVBB-RV64-NEXT:    vl1r.v v14, (a4)1483; ZVBB-RV64-NEXT:    csrr a0, vlenb1484; ZVBB-RV64-NEXT:    li a3, 101485; ZVBB-RV64-NEXT:    mul a0, a0, a31486; ZVBB-RV64-NEXT:    add a0, sp, a01487; ZVBB-RV64-NEXT:    addi a0, a0, 641488; ZVBB-RV64-NEXT:    add a6, a6, a21489; ZVBB-RV64-NEXT:    vl1r.v v15, (a5)1490; ZVBB-RV64-NEXT:    vl1r.v v12, (a6)1491; ZVBB-RV64-NEXT:    vl1r.v v13, (a1)1492; ZVBB-RV64-NEXT:    slli a2, a2, 31493; ZVBB-RV64-NEXT:    add a2, a0, a21494; ZVBB-RV64-NEXT:    vs2r.v v16, (a2)1495; ZVBB-RV64-NEXT:    vs8r.v v8, (a0)1496; ZVBB-RV64-NEXT:    vl8r.v v16, (a2)1497; ZVBB-RV64-NEXT:    vl8r.v v8, (a0)1498; ZVBB-RV64-NEXT:    addi sp, s0, -801499; ZVBB-RV64-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload1500; ZVBB-RV64-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload1501; ZVBB-RV64-NEXT:    addi sp, sp, 801502; ZVBB-RV64-NEXT:    ret1503;1504; ZIP-LABEL: vector_interleave_nxv80i8_nxv16i8:1505; ZIP:       # %bb.0:1506; ZIP-NEXT:    addi sp, sp, -801507; ZIP-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill1508; ZIP-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill1509; ZIP-NEXT:    addi s0, sp, 801510; ZIP-NEXT:    csrr a0, vlenb1511; ZIP-NEXT:    li a1, 281512; ZIP-NEXT:    mul a0, a0, a11513; ZIP-NEXT:    sub sp, sp, a01514; ZIP-NEXT:    andi sp, sp, -641515; ZIP-NEXT:    vsetvli a0, zero, e8, m1, ta, ma1516; ZIP-NEXT:    vmv2r.v v20, v161517; ZIP-NEXT:    addi a0, sp, 641518; ZIP-NEXT:    vmv2r.v v18, v121519; ZIP-NEXT:    csrr a1, vlenb1520; ZIP-NEXT:    slli a2, a1, 21521; ZIP-NEXT:    add a1, a2, a11522; ZIP-NEXT:    add a1, sp, a11523; ZIP-NEXT:    addi a1, a1, 641524; ZIP-NEXT:    csrr a2, vlenb1525; ZIP-NEXT:    vmv2r.v v16, v81526; ZIP-NEXT:    vmv2r.v v22, v161527; ZIP-NEXT:    vmv2r.v v24, v181528; ZIP-NEXT:    vmv1r.v v26, v201529; ZIP-NEXT:    add a3, a0, a21530; ZIP-NEXT:    vmv1r.v v23, v101531; ZIP-NEXT:    add a4, a1, a21532; ZIP-NEXT:    add a5, a4, a21533; ZIP-NEXT:    vmv1r.v v25, v141534; ZIP-NEXT:    add a6, a5, a21535; ZIP-NEXT:    vmv1r.v v18, v111536; ZIP-NEXT:    vsseg5e8.v v22, (a0)1537; ZIP-NEXT:    vmv1r.v v20, v151538; ZIP-NEXT:    vsseg5e8.v v17, (a1)1539; ZIP-NEXT:    vl1r.v v16, (a6)1540; ZIP-NEXT:    add a6, a6, a21541; ZIP-NEXT:    vl1r.v v17, (a6)1542; ZIP-NEXT:    add a6, a3, a21543; ZIP-NEXT:    vl1r.v v10, (a6)1544; ZIP-NEXT:    add a6, a6, a21545; ZIP-NEXT:    vl1r.v v11, (a6)1546; ZIP-NEXT:    vl1r.v v8, (a0)1547; ZIP-NEXT:    vl1r.v v9, (a3)1548; ZIP-NEXT:    vl1r.v v14, (a4)1549; ZIP-NEXT:    csrr a0, vlenb1550; ZIP-NEXT:    li a3, 101551; ZIP-NEXT:    mul a0, a0, a31552; ZIP-NEXT:    add a0, sp, a01553; ZIP-NEXT:    addi a0, a0, 641554; ZIP-NEXT:    add a6, a6, a21555; ZIP-NEXT:    vl1r.v v15, (a5)1556; ZIP-NEXT:    vl1r.v v12, (a6)1557; ZIP-NEXT:    vl1r.v v13, (a1)1558; ZIP-NEXT:    slli a2, a2, 31559; ZIP-NEXT:    add a2, a0, a21560; ZIP-NEXT:    vs2r.v v16, (a2)1561; ZIP-NEXT:    vs8r.v v8, (a0)1562; ZIP-NEXT:    vl8r.v v16, (a2)1563; ZIP-NEXT:    vl8r.v v8, (a0)1564; ZIP-NEXT:    addi sp, s0, -801565; ZIP-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload1566; ZIP-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload1567; ZIP-NEXT:    addi sp, sp, 801568; ZIP-NEXT:    ret1569  %res = call <vscale x 80 x i8> @llvm.vector.interleave5.nxv80i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c, <vscale x 16 x i8> %d, <vscale x 16 x i8> %e)1570  ret <vscale x 80 x i8> %res1571}1572 1573 1574define <vscale x 40 x i8> @vector_interleave_nxv40i8_nxv8i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b, <vscale x 8 x i8> %c, <vscale x 8 x i8> %d, <vscale x 8 x i8> %e) nounwind {1575; CHECK-LABEL: vector_interleave_nxv40i8_nxv8i8:1576; CHECK:       # %bb.0:1577; CHECK-NEXT:    addi sp, sp, -161578; CHECK-NEXT:    csrr a0, vlenb1579; CHECK-NEXT:    slli a1, a0, 21580; CHECK-NEXT:    add a0, a1, a01581; CHECK-NEXT:    sub sp, sp, a01582; CHECK-NEXT:    addi a0, sp, 161583; CHECK-NEXT:    csrr a1, vlenb1584; CHECK-NEXT:    add a2, a0, a11585; CHECK-NEXT:    add a3, a2, a11586; CHECK-NEXT:    vsetvli a4, zero, e8, m1, ta, ma1587; CHECK-NEXT:    vsseg5e8.v v8, (a0)1588; CHECK-NEXT:    vl1r.v v10, (a3)1589; CHECK-NEXT:    add a3, a3, a11590; CHECK-NEXT:    vl1r.v v11, (a3)1591; CHECK-NEXT:    vl1r.v v8, (a0)1592; CHECK-NEXT:    vl1r.v v9, (a2)1593; CHECK-NEXT:    add a1, a3, a11594; CHECK-NEXT:    vl1r.v v12, (a1)1595; CHECK-NEXT:    csrr a0, vlenb1596; CHECK-NEXT:    slli a1, a0, 21597; CHECK-NEXT:    add a0, a1, a01598; CHECK-NEXT:    add sp, sp, a01599; CHECK-NEXT:    addi sp, sp, 161600; CHECK-NEXT:    ret1601;1602; ZVBB-LABEL: vector_interleave_nxv40i8_nxv8i8:1603; ZVBB:       # %bb.0:1604; ZVBB-NEXT:    addi sp, sp, -161605; ZVBB-NEXT:    csrr a0, vlenb1606; ZVBB-NEXT:    slli a1, a0, 21607; ZVBB-NEXT:    add a0, a1, a01608; ZVBB-NEXT:    sub sp, sp, a01609; ZVBB-NEXT:    addi a0, sp, 161610; ZVBB-NEXT:    csrr a1, vlenb1611; ZVBB-NEXT:    add a2, a0, a11612; ZVBB-NEXT:    add a3, a2, a11613; ZVBB-NEXT:    vsetvli a4, zero, e8, m1, ta, ma1614; ZVBB-NEXT:    vsseg5e8.v v8, (a0)1615; ZVBB-NEXT:    vl1r.v v10, (a3)1616; ZVBB-NEXT:    add a3, a3, a11617; ZVBB-NEXT:    vl1r.v v11, (a3)1618; ZVBB-NEXT:    vl1r.v v8, (a0)1619; ZVBB-NEXT:    vl1r.v v9, (a2)1620; ZVBB-NEXT:    add a1, a3, a11621; ZVBB-NEXT:    vl1r.v v12, (a1)1622; ZVBB-NEXT:    csrr a0, vlenb1623; ZVBB-NEXT:    slli a1, a0, 21624; ZVBB-NEXT:    add a0, a1, a01625; ZVBB-NEXT:    add sp, sp, a01626; ZVBB-NEXT:    addi sp, sp, 161627; ZVBB-NEXT:    ret1628  %res = call <vscale x 40 x i8> @llvm.vector.interleave5.nxv40i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b, <vscale x 8 x i8> %c, <vscale x 8 x i8> %d, <vscale x 8 x i8> %e)1629  ret <vscale x 40 x i8> %res1630}1631 1632 1633define <vscale x 20 x i32> @vector_interleave_nxv20i32_nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c, <vscale x 4 x i32> %d, <vscale x 4 x i32> %e) nounwind {1634;1635; RV32-LABEL: vector_interleave_nxv20i32_nxv4i32:1636; RV32:       # %bb.0:1637; RV32-NEXT:    addi sp, sp, -801638; RV32-NEXT:    sw ra, 76(sp) # 4-byte Folded Spill1639; RV32-NEXT:    sw s0, 72(sp) # 4-byte Folded Spill1640; RV32-NEXT:    addi s0, sp, 801641; RV32-NEXT:    csrr a0, vlenb1642; RV32-NEXT:    li a1, 281643; RV32-NEXT:    mul a0, a0, a11644; RV32-NEXT:    sub sp, sp, a01645; RV32-NEXT:    andi sp, sp, -641646; RV32-NEXT:    vsetvli a0, zero, e32, m1, ta, ma1647; RV32-NEXT:    vmv2r.v v20, v161648; RV32-NEXT:    addi a0, sp, 641649; RV32-NEXT:    vmv2r.v v18, v121650; RV32-NEXT:    csrr a1, vlenb1651; RV32-NEXT:    slli a2, a1, 21652; RV32-NEXT:    add a1, a2, a11653; RV32-NEXT:    add a1, sp, a11654; RV32-NEXT:    addi a1, a1, 641655; RV32-NEXT:    csrr a2, vlenb1656; RV32-NEXT:    vmv2r.v v16, v81657; RV32-NEXT:    vmv2r.v v22, v161658; RV32-NEXT:    vmv2r.v v24, v181659; RV32-NEXT:    vmv1r.v v26, v201660; RV32-NEXT:    add a3, a0, a21661; RV32-NEXT:    vmv1r.v v23, v101662; RV32-NEXT:    add a4, a1, a21663; RV32-NEXT:    add a5, a4, a21664; RV32-NEXT:    vmv1r.v v25, v141665; RV32-NEXT:    add a6, a5, a21666; RV32-NEXT:    vmv1r.v v18, v111667; RV32-NEXT:    vsseg5e32.v v22, (a0)1668; RV32-NEXT:    vmv1r.v v20, v151669; RV32-NEXT:    vsseg5e32.v v17, (a1)1670; RV32-NEXT:    vl1re32.v v16, (a6)1671; RV32-NEXT:    add a6, a6, a21672; RV32-NEXT:    vl1re32.v v17, (a6)1673; RV32-NEXT:    add a6, a3, a21674; RV32-NEXT:    vl1re32.v v10, (a6)1675; RV32-NEXT:    add a6, a6, a21676; RV32-NEXT:    vl1re32.v v11, (a6)1677; RV32-NEXT:    vl1re32.v v8, (a0)1678; RV32-NEXT:    vl1re32.v v9, (a3)1679; RV32-NEXT:    vl1re32.v v14, (a4)1680; RV32-NEXT:    csrr a0, vlenb1681; RV32-NEXT:    li a3, 101682; RV32-NEXT:    mul a0, a0, a31683; RV32-NEXT:    add a0, sp, a01684; RV32-NEXT:    addi a0, a0, 641685; RV32-NEXT:    add a6, a6, a21686; RV32-NEXT:    vl1re32.v v15, (a5)1687; RV32-NEXT:    vl1re32.v v12, (a6)1688; RV32-NEXT:    vl1re32.v v13, (a1)1689; RV32-NEXT:    slli a2, a2, 31690; RV32-NEXT:    add a2, a0, a21691; RV32-NEXT:    vs2r.v v16, (a2)1692; RV32-NEXT:    vs8r.v v8, (a0)1693; RV32-NEXT:    vl8re32.v v16, (a2)1694; RV32-NEXT:    vl8re32.v v8, (a0)1695; RV32-NEXT:    addi sp, s0, -801696; RV32-NEXT:    lw ra, 76(sp) # 4-byte Folded Reload1697; RV32-NEXT:    lw s0, 72(sp) # 4-byte Folded Reload1698; RV32-NEXT:    addi sp, sp, 801699; RV32-NEXT:    ret1700;1701; RV64-LABEL: vector_interleave_nxv20i32_nxv4i32:1702; RV64:       # %bb.0:1703; RV64-NEXT:    addi sp, sp, -801704; RV64-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill1705; RV64-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill1706; RV64-NEXT:    addi s0, sp, 801707; RV64-NEXT:    csrr a0, vlenb1708; RV64-NEXT:    li a1, 281709; RV64-NEXT:    mul a0, a0, a11710; RV64-NEXT:    sub sp, sp, a01711; RV64-NEXT:    andi sp, sp, -641712; RV64-NEXT:    vsetvli a0, zero, e32, m1, ta, ma1713; RV64-NEXT:    vmv2r.v v20, v161714; RV64-NEXT:    addi a0, sp, 641715; RV64-NEXT:    vmv2r.v v18, v121716; RV64-NEXT:    csrr a1, vlenb1717; RV64-NEXT:    slli a2, a1, 21718; RV64-NEXT:    add a1, a2, a11719; RV64-NEXT:    add a1, sp, a11720; RV64-NEXT:    addi a1, a1, 641721; RV64-NEXT:    csrr a2, vlenb1722; RV64-NEXT:    vmv2r.v v16, v81723; RV64-NEXT:    vmv2r.v v22, v161724; RV64-NEXT:    vmv2r.v v24, v181725; RV64-NEXT:    vmv1r.v v26, v201726; RV64-NEXT:    add a3, a0, a21727; RV64-NEXT:    vmv1r.v v23, v101728; RV64-NEXT:    add a4, a1, a21729; RV64-NEXT:    add a5, a4, a21730; RV64-NEXT:    vmv1r.v v25, v141731; RV64-NEXT:    add a6, a5, a21732; RV64-NEXT:    vmv1r.v v18, v111733; RV64-NEXT:    vsseg5e32.v v22, (a0)1734; RV64-NEXT:    vmv1r.v v20, v151735; RV64-NEXT:    vsseg5e32.v v17, (a1)1736; RV64-NEXT:    vl1re32.v v16, (a6)1737; RV64-NEXT:    add a6, a6, a21738; RV64-NEXT:    vl1re32.v v17, (a6)1739; RV64-NEXT:    add a6, a3, a21740; RV64-NEXT:    vl1re32.v v10, (a6)1741; RV64-NEXT:    add a6, a6, a21742; RV64-NEXT:    vl1re32.v v11, (a6)1743; RV64-NEXT:    vl1re32.v v8, (a0)1744; RV64-NEXT:    vl1re32.v v9, (a3)1745; RV64-NEXT:    vl1re32.v v14, (a4)1746; RV64-NEXT:    csrr a0, vlenb1747; RV64-NEXT:    li a3, 101748; RV64-NEXT:    mul a0, a0, a31749; RV64-NEXT:    add a0, sp, a01750; RV64-NEXT:    addi a0, a0, 641751; RV64-NEXT:    add a6, a6, a21752; RV64-NEXT:    vl1re32.v v15, (a5)1753; RV64-NEXT:    vl1re32.v v12, (a6)1754; RV64-NEXT:    vl1re32.v v13, (a1)1755; RV64-NEXT:    slli a2, a2, 31756; RV64-NEXT:    add a2, a0, a21757; RV64-NEXT:    vs2r.v v16, (a2)1758; RV64-NEXT:    vs8r.v v8, (a0)1759; RV64-NEXT:    vl8re32.v v16, (a2)1760; RV64-NEXT:    vl8re32.v v8, (a0)1761; RV64-NEXT:    addi sp, s0, -801762; RV64-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload1763; RV64-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload1764; RV64-NEXT:    addi sp, sp, 801765; RV64-NEXT:    ret1766;1767; ZVBB-RV32-LABEL: vector_interleave_nxv20i32_nxv4i32:1768; ZVBB-RV32:       # %bb.0:1769; ZVBB-RV32-NEXT:    addi sp, sp, -801770; ZVBB-RV32-NEXT:    sw ra, 76(sp) # 4-byte Folded Spill1771; ZVBB-RV32-NEXT:    sw s0, 72(sp) # 4-byte Folded Spill1772; ZVBB-RV32-NEXT:    addi s0, sp, 801773; ZVBB-RV32-NEXT:    csrr a0, vlenb1774; ZVBB-RV32-NEXT:    li a1, 281775; ZVBB-RV32-NEXT:    mul a0, a0, a11776; ZVBB-RV32-NEXT:    sub sp, sp, a01777; ZVBB-RV32-NEXT:    andi sp, sp, -641778; ZVBB-RV32-NEXT:    vsetvli a0, zero, e32, m1, ta, ma1779; ZVBB-RV32-NEXT:    vmv2r.v v20, v161780; ZVBB-RV32-NEXT:    addi a0, sp, 641781; ZVBB-RV32-NEXT:    vmv2r.v v18, v121782; ZVBB-RV32-NEXT:    csrr a1, vlenb1783; ZVBB-RV32-NEXT:    slli a2, a1, 21784; ZVBB-RV32-NEXT:    add a1, a2, a11785; ZVBB-RV32-NEXT:    add a1, sp, a11786; ZVBB-RV32-NEXT:    addi a1, a1, 641787; ZVBB-RV32-NEXT:    csrr a2, vlenb1788; ZVBB-RV32-NEXT:    vmv2r.v v16, v81789; ZVBB-RV32-NEXT:    vmv2r.v v22, v161790; ZVBB-RV32-NEXT:    vmv2r.v v24, v181791; ZVBB-RV32-NEXT:    vmv1r.v v26, v201792; ZVBB-RV32-NEXT:    add a3, a0, a21793; ZVBB-RV32-NEXT:    vmv1r.v v23, v101794; ZVBB-RV32-NEXT:    add a4, a1, a21795; ZVBB-RV32-NEXT:    add a5, a4, a21796; ZVBB-RV32-NEXT:    vmv1r.v v25, v141797; ZVBB-RV32-NEXT:    add a6, a5, a21798; ZVBB-RV32-NEXT:    vmv1r.v v18, v111799; ZVBB-RV32-NEXT:    vsseg5e32.v v22, (a0)1800; ZVBB-RV32-NEXT:    vmv1r.v v20, v151801; ZVBB-RV32-NEXT:    vsseg5e32.v v17, (a1)1802; ZVBB-RV32-NEXT:    vl1re32.v v16, (a6)1803; ZVBB-RV32-NEXT:    add a6, a6, a21804; ZVBB-RV32-NEXT:    vl1re32.v v17, (a6)1805; ZVBB-RV32-NEXT:    add a6, a3, a21806; ZVBB-RV32-NEXT:    vl1re32.v v10, (a6)1807; ZVBB-RV32-NEXT:    add a6, a6, a21808; ZVBB-RV32-NEXT:    vl1re32.v v11, (a6)1809; ZVBB-RV32-NEXT:    vl1re32.v v8, (a0)1810; ZVBB-RV32-NEXT:    vl1re32.v v9, (a3)1811; ZVBB-RV32-NEXT:    vl1re32.v v14, (a4)1812; ZVBB-RV32-NEXT:    csrr a0, vlenb1813; ZVBB-RV32-NEXT:    li a3, 101814; ZVBB-RV32-NEXT:    mul a0, a0, a31815; ZVBB-RV32-NEXT:    add a0, sp, a01816; ZVBB-RV32-NEXT:    addi a0, a0, 641817; ZVBB-RV32-NEXT:    add a6, a6, a21818; ZVBB-RV32-NEXT:    vl1re32.v v15, (a5)1819; ZVBB-RV32-NEXT:    vl1re32.v v12, (a6)1820; ZVBB-RV32-NEXT:    vl1re32.v v13, (a1)1821; ZVBB-RV32-NEXT:    slli a2, a2, 31822; ZVBB-RV32-NEXT:    add a2, a0, a21823; ZVBB-RV32-NEXT:    vs2r.v v16, (a2)1824; ZVBB-RV32-NEXT:    vs8r.v v8, (a0)1825; ZVBB-RV32-NEXT:    vl8re32.v v16, (a2)1826; ZVBB-RV32-NEXT:    vl8re32.v v8, (a0)1827; ZVBB-RV32-NEXT:    addi sp, s0, -801828; ZVBB-RV32-NEXT:    lw ra, 76(sp) # 4-byte Folded Reload1829; ZVBB-RV32-NEXT:    lw s0, 72(sp) # 4-byte Folded Reload1830; ZVBB-RV32-NEXT:    addi sp, sp, 801831; ZVBB-RV32-NEXT:    ret1832;1833; ZVBB-RV64-LABEL: vector_interleave_nxv20i32_nxv4i32:1834; ZVBB-RV64:       # %bb.0:1835; ZVBB-RV64-NEXT:    addi sp, sp, -801836; ZVBB-RV64-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill1837; ZVBB-RV64-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill1838; ZVBB-RV64-NEXT:    addi s0, sp, 801839; ZVBB-RV64-NEXT:    csrr a0, vlenb1840; ZVBB-RV64-NEXT:    li a1, 281841; ZVBB-RV64-NEXT:    mul a0, a0, a11842; ZVBB-RV64-NEXT:    sub sp, sp, a01843; ZVBB-RV64-NEXT:    andi sp, sp, -641844; ZVBB-RV64-NEXT:    vsetvli a0, zero, e32, m1, ta, ma1845; ZVBB-RV64-NEXT:    vmv2r.v v20, v161846; ZVBB-RV64-NEXT:    addi a0, sp, 641847; ZVBB-RV64-NEXT:    vmv2r.v v18, v121848; ZVBB-RV64-NEXT:    csrr a1, vlenb1849; ZVBB-RV64-NEXT:    slli a2, a1, 21850; ZVBB-RV64-NEXT:    add a1, a2, a11851; ZVBB-RV64-NEXT:    add a1, sp, a11852; ZVBB-RV64-NEXT:    addi a1, a1, 641853; ZVBB-RV64-NEXT:    csrr a2, vlenb1854; ZVBB-RV64-NEXT:    vmv2r.v v16, v81855; ZVBB-RV64-NEXT:    vmv2r.v v22, v161856; ZVBB-RV64-NEXT:    vmv2r.v v24, v181857; ZVBB-RV64-NEXT:    vmv1r.v v26, v201858; ZVBB-RV64-NEXT:    add a3, a0, a21859; ZVBB-RV64-NEXT:    vmv1r.v v23, v101860; ZVBB-RV64-NEXT:    add a4, a1, a21861; ZVBB-RV64-NEXT:    add a5, a4, a21862; ZVBB-RV64-NEXT:    vmv1r.v v25, v141863; ZVBB-RV64-NEXT:    add a6, a5, a21864; ZVBB-RV64-NEXT:    vmv1r.v v18, v111865; ZVBB-RV64-NEXT:    vsseg5e32.v v22, (a0)1866; ZVBB-RV64-NEXT:    vmv1r.v v20, v151867; ZVBB-RV64-NEXT:    vsseg5e32.v v17, (a1)1868; ZVBB-RV64-NEXT:    vl1re32.v v16, (a6)1869; ZVBB-RV64-NEXT:    add a6, a6, a21870; ZVBB-RV64-NEXT:    vl1re32.v v17, (a6)1871; ZVBB-RV64-NEXT:    add a6, a3, a21872; ZVBB-RV64-NEXT:    vl1re32.v v10, (a6)1873; ZVBB-RV64-NEXT:    add a6, a6, a21874; ZVBB-RV64-NEXT:    vl1re32.v v11, (a6)1875; ZVBB-RV64-NEXT:    vl1re32.v v8, (a0)1876; ZVBB-RV64-NEXT:    vl1re32.v v9, (a3)1877; ZVBB-RV64-NEXT:    vl1re32.v v14, (a4)1878; ZVBB-RV64-NEXT:    csrr a0, vlenb1879; ZVBB-RV64-NEXT:    li a3, 101880; ZVBB-RV64-NEXT:    mul a0, a0, a31881; ZVBB-RV64-NEXT:    add a0, sp, a01882; ZVBB-RV64-NEXT:    addi a0, a0, 641883; ZVBB-RV64-NEXT:    add a6, a6, a21884; ZVBB-RV64-NEXT:    vl1re32.v v15, (a5)1885; ZVBB-RV64-NEXT:    vl1re32.v v12, (a6)1886; ZVBB-RV64-NEXT:    vl1re32.v v13, (a1)1887; ZVBB-RV64-NEXT:    slli a2, a2, 31888; ZVBB-RV64-NEXT:    add a2, a0, a21889; ZVBB-RV64-NEXT:    vs2r.v v16, (a2)1890; ZVBB-RV64-NEXT:    vs8r.v v8, (a0)1891; ZVBB-RV64-NEXT:    vl8re32.v v16, (a2)1892; ZVBB-RV64-NEXT:    vl8re32.v v8, (a0)1893; ZVBB-RV64-NEXT:    addi sp, s0, -801894; ZVBB-RV64-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload1895; ZVBB-RV64-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload1896; ZVBB-RV64-NEXT:    addi sp, sp, 801897; ZVBB-RV64-NEXT:    ret1898;1899; ZIP-LABEL: vector_interleave_nxv20i32_nxv4i32:1900; ZIP:       # %bb.0:1901; ZIP-NEXT:    addi sp, sp, -801902; ZIP-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill1903; ZIP-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill1904; ZIP-NEXT:    addi s0, sp, 801905; ZIP-NEXT:    csrr a0, vlenb1906; ZIP-NEXT:    li a1, 281907; ZIP-NEXT:    mul a0, a0, a11908; ZIP-NEXT:    sub sp, sp, a01909; ZIP-NEXT:    andi sp, sp, -641910; ZIP-NEXT:    vsetvli a0, zero, e32, m1, ta, ma1911; ZIP-NEXT:    vmv2r.v v20, v161912; ZIP-NEXT:    addi a0, sp, 641913; ZIP-NEXT:    vmv2r.v v18, v121914; ZIP-NEXT:    csrr a1, vlenb1915; ZIP-NEXT:    slli a2, a1, 21916; ZIP-NEXT:    add a1, a2, a11917; ZIP-NEXT:    add a1, sp, a11918; ZIP-NEXT:    addi a1, a1, 641919; ZIP-NEXT:    csrr a2, vlenb1920; ZIP-NEXT:    vmv2r.v v16, v81921; ZIP-NEXT:    vmv2r.v v22, v161922; ZIP-NEXT:    vmv2r.v v24, v181923; ZIP-NEXT:    vmv1r.v v26, v201924; ZIP-NEXT:    add a3, a0, a21925; ZIP-NEXT:    vmv1r.v v23, v101926; ZIP-NEXT:    add a4, a1, a21927; ZIP-NEXT:    add a5, a4, a21928; ZIP-NEXT:    vmv1r.v v25, v141929; ZIP-NEXT:    add a6, a5, a21930; ZIP-NEXT:    vmv1r.v v18, v111931; ZIP-NEXT:    vsseg5e32.v v22, (a0)1932; ZIP-NEXT:    vmv1r.v v20, v151933; ZIP-NEXT:    vsseg5e32.v v17, (a1)1934; ZIP-NEXT:    vl1re32.v v16, (a6)1935; ZIP-NEXT:    add a6, a6, a21936; ZIP-NEXT:    vl1re32.v v17, (a6)1937; ZIP-NEXT:    add a6, a3, a21938; ZIP-NEXT:    vl1re32.v v10, (a6)1939; ZIP-NEXT:    add a6, a6, a21940; ZIP-NEXT:    vl1re32.v v11, (a6)1941; ZIP-NEXT:    vl1re32.v v8, (a0)1942; ZIP-NEXT:    vl1re32.v v9, (a3)1943; ZIP-NEXT:    vl1re32.v v14, (a4)1944; ZIP-NEXT:    csrr a0, vlenb1945; ZIP-NEXT:    li a3, 101946; ZIP-NEXT:    mul a0, a0, a31947; ZIP-NEXT:    add a0, sp, a01948; ZIP-NEXT:    addi a0, a0, 641949; ZIP-NEXT:    add a6, a6, a21950; ZIP-NEXT:    vl1re32.v v15, (a5)1951; ZIP-NEXT:    vl1re32.v v12, (a6)1952; ZIP-NEXT:    vl1re32.v v13, (a1)1953; ZIP-NEXT:    slli a2, a2, 31954; ZIP-NEXT:    add a2, a0, a21955; ZIP-NEXT:    vs2r.v v16, (a2)1956; ZIP-NEXT:    vs8r.v v8, (a0)1957; ZIP-NEXT:    vl8re32.v v16, (a2)1958; ZIP-NEXT:    vl8re32.v v8, (a0)1959; ZIP-NEXT:    addi sp, s0, -801960; ZIP-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload1961; ZIP-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload1962; ZIP-NEXT:    addi sp, sp, 801963; ZIP-NEXT:    ret1964  %res = call <vscale x 20 x i32> @llvm.vector.interleave5.nxv20i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c, <vscale x 4 x i32> %d, <vscale x 4 x i32> %e)1965  ret <vscale x 20 x i32> %res1966}1967 1968 1969define <vscale x 10 x i64> @vector_interleave_nxv10i64_nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c, <vscale x 2 x i64> %d, <vscale x 2 x i64> %e) nounwind {1970;1971; RV32-LABEL: vector_interleave_nxv10i64_nxv2i64:1972; RV32:       # %bb.0:1973; RV32-NEXT:    addi sp, sp, -801974; RV32-NEXT:    sw ra, 76(sp) # 4-byte Folded Spill1975; RV32-NEXT:    sw s0, 72(sp) # 4-byte Folded Spill1976; RV32-NEXT:    addi s0, sp, 801977; RV32-NEXT:    csrr a0, vlenb1978; RV32-NEXT:    li a1, 281979; RV32-NEXT:    mul a0, a0, a11980; RV32-NEXT:    sub sp, sp, a01981; RV32-NEXT:    andi sp, sp, -641982; RV32-NEXT:    vsetvli a0, zero, e64, m1, ta, ma1983; RV32-NEXT:    vmv2r.v v20, v161984; RV32-NEXT:    addi a0, sp, 641985; RV32-NEXT:    vmv2r.v v18, v121986; RV32-NEXT:    csrr a1, vlenb1987; RV32-NEXT:    slli a2, a1, 21988; RV32-NEXT:    add a1, a2, a11989; RV32-NEXT:    add a1, sp, a11990; RV32-NEXT:    addi a1, a1, 641991; RV32-NEXT:    csrr a2, vlenb1992; RV32-NEXT:    vmv2r.v v16, v81993; RV32-NEXT:    vmv2r.v v22, v161994; RV32-NEXT:    vmv2r.v v24, v181995; RV32-NEXT:    vmv1r.v v26, v201996; RV32-NEXT:    add a3, a0, a21997; RV32-NEXT:    vmv1r.v v23, v101998; RV32-NEXT:    add a4, a1, a21999; RV32-NEXT:    add a5, a4, a22000; RV32-NEXT:    vmv1r.v v25, v142001; RV32-NEXT:    add a6, a5, a22002; RV32-NEXT:    vmv1r.v v18, v112003; RV32-NEXT:    vsseg5e64.v v22, (a0)2004; RV32-NEXT:    vmv1r.v v20, v152005; RV32-NEXT:    vsseg5e64.v v17, (a1)2006; RV32-NEXT:    vl1re64.v v16, (a6)2007; RV32-NEXT:    add a6, a6, a22008; RV32-NEXT:    vl1re64.v v17, (a6)2009; RV32-NEXT:    add a6, a3, a22010; RV32-NEXT:    vl1re64.v v10, (a6)2011; RV32-NEXT:    add a6, a6, a22012; RV32-NEXT:    vl1re64.v v11, (a6)2013; RV32-NEXT:    vl1re64.v v8, (a0)2014; RV32-NEXT:    vl1re64.v v9, (a3)2015; RV32-NEXT:    vl1re64.v v14, (a4)2016; RV32-NEXT:    csrr a0, vlenb2017; RV32-NEXT:    li a3, 102018; RV32-NEXT:    mul a0, a0, a32019; RV32-NEXT:    add a0, sp, a02020; RV32-NEXT:    addi a0, a0, 642021; RV32-NEXT:    add a6, a6, a22022; RV32-NEXT:    vl1re64.v v15, (a5)2023; RV32-NEXT:    vl1re64.v v12, (a6)2024; RV32-NEXT:    vl1re64.v v13, (a1)2025; RV32-NEXT:    slli a2, a2, 32026; RV32-NEXT:    add a2, a0, a22027; RV32-NEXT:    vs2r.v v16, (a2)2028; RV32-NEXT:    vs8r.v v8, (a0)2029; RV32-NEXT:    vl8re64.v v16, (a2)2030; RV32-NEXT:    vl8re64.v v8, (a0)2031; RV32-NEXT:    addi sp, s0, -802032; RV32-NEXT:    lw ra, 76(sp) # 4-byte Folded Reload2033; RV32-NEXT:    lw s0, 72(sp) # 4-byte Folded Reload2034; RV32-NEXT:    addi sp, sp, 802035; RV32-NEXT:    ret2036;2037; RV64-LABEL: vector_interleave_nxv10i64_nxv2i64:2038; RV64:       # %bb.0:2039; RV64-NEXT:    addi sp, sp, -802040; RV64-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill2041; RV64-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill2042; RV64-NEXT:    addi s0, sp, 802043; RV64-NEXT:    csrr a0, vlenb2044; RV64-NEXT:    li a1, 282045; RV64-NEXT:    mul a0, a0, a12046; RV64-NEXT:    sub sp, sp, a02047; RV64-NEXT:    andi sp, sp, -642048; RV64-NEXT:    vsetvli a0, zero, e64, m1, ta, ma2049; RV64-NEXT:    vmv2r.v v20, v162050; RV64-NEXT:    addi a0, sp, 642051; RV64-NEXT:    vmv2r.v v18, v122052; RV64-NEXT:    csrr a1, vlenb2053; RV64-NEXT:    slli a2, a1, 22054; RV64-NEXT:    add a1, a2, a12055; RV64-NEXT:    add a1, sp, a12056; RV64-NEXT:    addi a1, a1, 642057; RV64-NEXT:    csrr a2, vlenb2058; RV64-NEXT:    vmv2r.v v16, v82059; RV64-NEXT:    vmv2r.v v22, v162060; RV64-NEXT:    vmv2r.v v24, v182061; RV64-NEXT:    vmv1r.v v26, v202062; RV64-NEXT:    add a3, a0, a22063; RV64-NEXT:    vmv1r.v v23, v102064; RV64-NEXT:    add a4, a1, a22065; RV64-NEXT:    add a5, a4, a22066; RV64-NEXT:    vmv1r.v v25, v142067; RV64-NEXT:    add a6, a5, a22068; RV64-NEXT:    vmv1r.v v18, v112069; RV64-NEXT:    vsseg5e64.v v22, (a0)2070; RV64-NEXT:    vmv1r.v v20, v152071; RV64-NEXT:    vsseg5e64.v v17, (a1)2072; RV64-NEXT:    vl1re64.v v16, (a6)2073; RV64-NEXT:    add a6, a6, a22074; RV64-NEXT:    vl1re64.v v17, (a6)2075; RV64-NEXT:    add a6, a3, a22076; RV64-NEXT:    vl1re64.v v10, (a6)2077; RV64-NEXT:    add a6, a6, a22078; RV64-NEXT:    vl1re64.v v11, (a6)2079; RV64-NEXT:    vl1re64.v v8, (a0)2080; RV64-NEXT:    vl1re64.v v9, (a3)2081; RV64-NEXT:    vl1re64.v v14, (a4)2082; RV64-NEXT:    csrr a0, vlenb2083; RV64-NEXT:    li a3, 102084; RV64-NEXT:    mul a0, a0, a32085; RV64-NEXT:    add a0, sp, a02086; RV64-NEXT:    addi a0, a0, 642087; RV64-NEXT:    add a6, a6, a22088; RV64-NEXT:    vl1re64.v v15, (a5)2089; RV64-NEXT:    vl1re64.v v12, (a6)2090; RV64-NEXT:    vl1re64.v v13, (a1)2091; RV64-NEXT:    slli a2, a2, 32092; RV64-NEXT:    add a2, a0, a22093; RV64-NEXT:    vs2r.v v16, (a2)2094; RV64-NEXT:    vs8r.v v8, (a0)2095; RV64-NEXT:    vl8re64.v v16, (a2)2096; RV64-NEXT:    vl8re64.v v8, (a0)2097; RV64-NEXT:    addi sp, s0, -802098; RV64-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload2099; RV64-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload2100; RV64-NEXT:    addi sp, sp, 802101; RV64-NEXT:    ret2102;2103; ZVBB-RV32-LABEL: vector_interleave_nxv10i64_nxv2i64:2104; ZVBB-RV32:       # %bb.0:2105; ZVBB-RV32-NEXT:    addi sp, sp, -802106; ZVBB-RV32-NEXT:    sw ra, 76(sp) # 4-byte Folded Spill2107; ZVBB-RV32-NEXT:    sw s0, 72(sp) # 4-byte Folded Spill2108; ZVBB-RV32-NEXT:    addi s0, sp, 802109; ZVBB-RV32-NEXT:    csrr a0, vlenb2110; ZVBB-RV32-NEXT:    li a1, 282111; ZVBB-RV32-NEXT:    mul a0, a0, a12112; ZVBB-RV32-NEXT:    sub sp, sp, a02113; ZVBB-RV32-NEXT:    andi sp, sp, -642114; ZVBB-RV32-NEXT:    vsetvli a0, zero, e64, m1, ta, ma2115; ZVBB-RV32-NEXT:    vmv2r.v v20, v162116; ZVBB-RV32-NEXT:    addi a0, sp, 642117; ZVBB-RV32-NEXT:    vmv2r.v v18, v122118; ZVBB-RV32-NEXT:    csrr a1, vlenb2119; ZVBB-RV32-NEXT:    slli a2, a1, 22120; ZVBB-RV32-NEXT:    add a1, a2, a12121; ZVBB-RV32-NEXT:    add a1, sp, a12122; ZVBB-RV32-NEXT:    addi a1, a1, 642123; ZVBB-RV32-NEXT:    csrr a2, vlenb2124; ZVBB-RV32-NEXT:    vmv2r.v v16, v82125; ZVBB-RV32-NEXT:    vmv2r.v v22, v162126; ZVBB-RV32-NEXT:    vmv2r.v v24, v182127; ZVBB-RV32-NEXT:    vmv1r.v v26, v202128; ZVBB-RV32-NEXT:    add a3, a0, a22129; ZVBB-RV32-NEXT:    vmv1r.v v23, v102130; ZVBB-RV32-NEXT:    add a4, a1, a22131; ZVBB-RV32-NEXT:    add a5, a4, a22132; ZVBB-RV32-NEXT:    vmv1r.v v25, v142133; ZVBB-RV32-NEXT:    add a6, a5, a22134; ZVBB-RV32-NEXT:    vmv1r.v v18, v112135; ZVBB-RV32-NEXT:    vsseg5e64.v v22, (a0)2136; ZVBB-RV32-NEXT:    vmv1r.v v20, v152137; ZVBB-RV32-NEXT:    vsseg5e64.v v17, (a1)2138; ZVBB-RV32-NEXT:    vl1re64.v v16, (a6)2139; ZVBB-RV32-NEXT:    add a6, a6, a22140; ZVBB-RV32-NEXT:    vl1re64.v v17, (a6)2141; ZVBB-RV32-NEXT:    add a6, a3, a22142; ZVBB-RV32-NEXT:    vl1re64.v v10, (a6)2143; ZVBB-RV32-NEXT:    add a6, a6, a22144; ZVBB-RV32-NEXT:    vl1re64.v v11, (a6)2145; ZVBB-RV32-NEXT:    vl1re64.v v8, (a0)2146; ZVBB-RV32-NEXT:    vl1re64.v v9, (a3)2147; ZVBB-RV32-NEXT:    vl1re64.v v14, (a4)2148; ZVBB-RV32-NEXT:    csrr a0, vlenb2149; ZVBB-RV32-NEXT:    li a3, 102150; ZVBB-RV32-NEXT:    mul a0, a0, a32151; ZVBB-RV32-NEXT:    add a0, sp, a02152; ZVBB-RV32-NEXT:    addi a0, a0, 642153; ZVBB-RV32-NEXT:    add a6, a6, a22154; ZVBB-RV32-NEXT:    vl1re64.v v15, (a5)2155; ZVBB-RV32-NEXT:    vl1re64.v v12, (a6)2156; ZVBB-RV32-NEXT:    vl1re64.v v13, (a1)2157; ZVBB-RV32-NEXT:    slli a2, a2, 32158; ZVBB-RV32-NEXT:    add a2, a0, a22159; ZVBB-RV32-NEXT:    vs2r.v v16, (a2)2160; ZVBB-RV32-NEXT:    vs8r.v v8, (a0)2161; ZVBB-RV32-NEXT:    vl8re64.v v16, (a2)2162; ZVBB-RV32-NEXT:    vl8re64.v v8, (a0)2163; ZVBB-RV32-NEXT:    addi sp, s0, -802164; ZVBB-RV32-NEXT:    lw ra, 76(sp) # 4-byte Folded Reload2165; ZVBB-RV32-NEXT:    lw s0, 72(sp) # 4-byte Folded Reload2166; ZVBB-RV32-NEXT:    addi sp, sp, 802167; ZVBB-RV32-NEXT:    ret2168;2169; ZVBB-RV64-LABEL: vector_interleave_nxv10i64_nxv2i64:2170; ZVBB-RV64:       # %bb.0:2171; ZVBB-RV64-NEXT:    addi sp, sp, -802172; ZVBB-RV64-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill2173; ZVBB-RV64-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill2174; ZVBB-RV64-NEXT:    addi s0, sp, 802175; ZVBB-RV64-NEXT:    csrr a0, vlenb2176; ZVBB-RV64-NEXT:    li a1, 282177; ZVBB-RV64-NEXT:    mul a0, a0, a12178; ZVBB-RV64-NEXT:    sub sp, sp, a02179; ZVBB-RV64-NEXT:    andi sp, sp, -642180; ZVBB-RV64-NEXT:    vsetvli a0, zero, e64, m1, ta, ma2181; ZVBB-RV64-NEXT:    vmv2r.v v20, v162182; ZVBB-RV64-NEXT:    addi a0, sp, 642183; ZVBB-RV64-NEXT:    vmv2r.v v18, v122184; ZVBB-RV64-NEXT:    csrr a1, vlenb2185; ZVBB-RV64-NEXT:    slli a2, a1, 22186; ZVBB-RV64-NEXT:    add a1, a2, a12187; ZVBB-RV64-NEXT:    add a1, sp, a12188; ZVBB-RV64-NEXT:    addi a1, a1, 642189; ZVBB-RV64-NEXT:    csrr a2, vlenb2190; ZVBB-RV64-NEXT:    vmv2r.v v16, v82191; ZVBB-RV64-NEXT:    vmv2r.v v22, v162192; ZVBB-RV64-NEXT:    vmv2r.v v24, v182193; ZVBB-RV64-NEXT:    vmv1r.v v26, v202194; ZVBB-RV64-NEXT:    add a3, a0, a22195; ZVBB-RV64-NEXT:    vmv1r.v v23, v102196; ZVBB-RV64-NEXT:    add a4, a1, a22197; ZVBB-RV64-NEXT:    add a5, a4, a22198; ZVBB-RV64-NEXT:    vmv1r.v v25, v142199; ZVBB-RV64-NEXT:    add a6, a5, a22200; ZVBB-RV64-NEXT:    vmv1r.v v18, v112201; ZVBB-RV64-NEXT:    vsseg5e64.v v22, (a0)2202; ZVBB-RV64-NEXT:    vmv1r.v v20, v152203; ZVBB-RV64-NEXT:    vsseg5e64.v v17, (a1)2204; ZVBB-RV64-NEXT:    vl1re64.v v16, (a6)2205; ZVBB-RV64-NEXT:    add a6, a6, a22206; ZVBB-RV64-NEXT:    vl1re64.v v17, (a6)2207; ZVBB-RV64-NEXT:    add a6, a3, a22208; ZVBB-RV64-NEXT:    vl1re64.v v10, (a6)2209; ZVBB-RV64-NEXT:    add a6, a6, a22210; ZVBB-RV64-NEXT:    vl1re64.v v11, (a6)2211; ZVBB-RV64-NEXT:    vl1re64.v v8, (a0)2212; ZVBB-RV64-NEXT:    vl1re64.v v9, (a3)2213; ZVBB-RV64-NEXT:    vl1re64.v v14, (a4)2214; ZVBB-RV64-NEXT:    csrr a0, vlenb2215; ZVBB-RV64-NEXT:    li a3, 102216; ZVBB-RV64-NEXT:    mul a0, a0, a32217; ZVBB-RV64-NEXT:    add a0, sp, a02218; ZVBB-RV64-NEXT:    addi a0, a0, 642219; ZVBB-RV64-NEXT:    add a6, a6, a22220; ZVBB-RV64-NEXT:    vl1re64.v v15, (a5)2221; ZVBB-RV64-NEXT:    vl1re64.v v12, (a6)2222; ZVBB-RV64-NEXT:    vl1re64.v v13, (a1)2223; ZVBB-RV64-NEXT:    slli a2, a2, 32224; ZVBB-RV64-NEXT:    add a2, a0, a22225; ZVBB-RV64-NEXT:    vs2r.v v16, (a2)2226; ZVBB-RV64-NEXT:    vs8r.v v8, (a0)2227; ZVBB-RV64-NEXT:    vl8re64.v v16, (a2)2228; ZVBB-RV64-NEXT:    vl8re64.v v8, (a0)2229; ZVBB-RV64-NEXT:    addi sp, s0, -802230; ZVBB-RV64-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload2231; ZVBB-RV64-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload2232; ZVBB-RV64-NEXT:    addi sp, sp, 802233; ZVBB-RV64-NEXT:    ret2234;2235; ZIP-LABEL: vector_interleave_nxv10i64_nxv2i64:2236; ZIP:       # %bb.0:2237; ZIP-NEXT:    addi sp, sp, -802238; ZIP-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill2239; ZIP-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill2240; ZIP-NEXT:    addi s0, sp, 802241; ZIP-NEXT:    csrr a0, vlenb2242; ZIP-NEXT:    li a1, 282243; ZIP-NEXT:    mul a0, a0, a12244; ZIP-NEXT:    sub sp, sp, a02245; ZIP-NEXT:    andi sp, sp, -642246; ZIP-NEXT:    vsetvli a0, zero, e64, m1, ta, ma2247; ZIP-NEXT:    vmv2r.v v20, v162248; ZIP-NEXT:    addi a0, sp, 642249; ZIP-NEXT:    vmv2r.v v18, v122250; ZIP-NEXT:    csrr a1, vlenb2251; ZIP-NEXT:    slli a2, a1, 22252; ZIP-NEXT:    add a1, a2, a12253; ZIP-NEXT:    add a1, sp, a12254; ZIP-NEXT:    addi a1, a1, 642255; ZIP-NEXT:    csrr a2, vlenb2256; ZIP-NEXT:    vmv2r.v v16, v82257; ZIP-NEXT:    vmv2r.v v22, v162258; ZIP-NEXT:    vmv2r.v v24, v182259; ZIP-NEXT:    vmv1r.v v26, v202260; ZIP-NEXT:    add a3, a0, a22261; ZIP-NEXT:    vmv1r.v v23, v102262; ZIP-NEXT:    add a4, a1, a22263; ZIP-NEXT:    add a5, a4, a22264; ZIP-NEXT:    vmv1r.v v25, v142265; ZIP-NEXT:    add a6, a5, a22266; ZIP-NEXT:    vmv1r.v v18, v112267; ZIP-NEXT:    vsseg5e64.v v22, (a0)2268; ZIP-NEXT:    vmv1r.v v20, v152269; ZIP-NEXT:    vsseg5e64.v v17, (a1)2270; ZIP-NEXT:    vl1re64.v v16, (a6)2271; ZIP-NEXT:    add a6, a6, a22272; ZIP-NEXT:    vl1re64.v v17, (a6)2273; ZIP-NEXT:    add a6, a3, a22274; ZIP-NEXT:    vl1re64.v v10, (a6)2275; ZIP-NEXT:    add a6, a6, a22276; ZIP-NEXT:    vl1re64.v v11, (a6)2277; ZIP-NEXT:    vl1re64.v v8, (a0)2278; ZIP-NEXT:    vl1re64.v v9, (a3)2279; ZIP-NEXT:    vl1re64.v v14, (a4)2280; ZIP-NEXT:    csrr a0, vlenb2281; ZIP-NEXT:    li a3, 102282; ZIP-NEXT:    mul a0, a0, a32283; ZIP-NEXT:    add a0, sp, a02284; ZIP-NEXT:    addi a0, a0, 642285; ZIP-NEXT:    add a6, a6, a22286; ZIP-NEXT:    vl1re64.v v15, (a5)2287; ZIP-NEXT:    vl1re64.v v12, (a6)2288; ZIP-NEXT:    vl1re64.v v13, (a1)2289; ZIP-NEXT:    slli a2, a2, 32290; ZIP-NEXT:    add a2, a0, a22291; ZIP-NEXT:    vs2r.v v16, (a2)2292; ZIP-NEXT:    vs8r.v v8, (a0)2293; ZIP-NEXT:    vl8re64.v v16, (a2)2294; ZIP-NEXT:    vl8re64.v v8, (a0)2295; ZIP-NEXT:    addi sp, s0, -802296; ZIP-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload2297; ZIP-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload2298; ZIP-NEXT:    addi sp, sp, 802299; ZIP-NEXT:    ret2300  %res = call <vscale x 10 x i64> @llvm.vector.interleave5.nxv10i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c, <vscale x 2 x i64> %d, <vscale x 2 x i64> %e)2301  ret <vscale x 10 x i64> %res2302}2303 2304define <vscale x 96 x i1> @vector_interleave_nxv96i1_nxv16i1(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b, <vscale x 16 x i1> %c, <vscale x 16 x i1> %d, <vscale x 16 x i1> %e, <vscale x 16 x i1> %f) nounwind {2305; CHECK-LABEL: vector_interleave_nxv96i1_nxv16i1:2306; CHECK:       # %bb.0:2307; CHECK-NEXT:    addi sp, sp, -162308; CHECK-NEXT:    csrr a0, vlenb2309; CHECK-NEXT:    li a1, 122310; CHECK-NEXT:    mul a0, a0, a12311; CHECK-NEXT:    sub sp, sp, a02312; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, ma2313; CHECK-NEXT:    vmv.v.i v20, 02314; CHECK-NEXT:    vmerge.vim v14, v20, 1, v02315; CHECK-NEXT:    vmv1r.v v0, v82316; CHECK-NEXT:    vmerge.vim v22, v20, 1, v02317; CHECK-NEXT:    vmv1r.v v0, v92318; CHECK-NEXT:    vmv1r.v v16, v232319; CHECK-NEXT:    vmerge.vim v8, v20, 1, v02320; CHECK-NEXT:    csrr a0, vlenb2321; CHECK-NEXT:    li a1, 62322; CHECK-NEXT:    mul a0, a0, a12323; CHECK-NEXT:    add a0, sp, a02324; CHECK-NEXT:    addi a0, a0, 162325; CHECK-NEXT:    vmv1r.v v17, v92326; CHECK-NEXT:    vmv1r.v v0, v102327; CHECK-NEXT:    vmerge.vim v24, v20, 1, v02328; CHECK-NEXT:    addi a4, sp, 162329; CHECK-NEXT:    vmv1r.v v18, v252330; CHECK-NEXT:    vmv1r.v v0, v112331; CHECK-NEXT:    vmerge.vim v26, v20, 1, v02332; CHECK-NEXT:    csrr a1, vlenb2333; CHECK-NEXT:    vmv1r.v v19, v272334; CHECK-NEXT:    vmv1r.v v0, v122335; CHECK-NEXT:    vmerge.vim v10, v20, 1, v02336; CHECK-NEXT:    add a2, a0, a12337; CHECK-NEXT:    vmv1r.v v20, v112338; CHECK-NEXT:    vsetvli a3, zero, e8, m1, ta, ma2339; CHECK-NEXT:    vsseg6e8.v v15, (a0)2340; CHECK-NEXT:    vmv1r.v v15, v222341; CHECK-NEXT:    add a5, a4, a12342; CHECK-NEXT:    vmv1r.v v16, v82343; CHECK-NEXT:    srli a3, a1, 12344; CHECK-NEXT:    vmv1r.v v17, v242345; CHECK-NEXT:    add a6, a5, a12346; CHECK-NEXT:    vmv1r.v v18, v262347; CHECK-NEXT:    add a7, a2, a12348; CHECK-NEXT:    vmv1r.v v19, v102349; CHECK-NEXT:    vsseg6e8.v v14, (a4)2350; CHECK-NEXT:    vl1r.v v8, (a0)2351; CHECK-NEXT:    add a0, a6, a12352; CHECK-NEXT:    vl1r.v v10, (a6)2353; CHECK-NEXT:    add a6, a7, a12354; CHECK-NEXT:    vl1r.v v12, (a4)2355; CHECK-NEXT:    add a4, a0, a12356; CHECK-NEXT:    vl1r.v v14, (a7)2357; CHECK-NEXT:    add a7, a6, a12358; CHECK-NEXT:    vl1r.v v16, (a4)2359; CHECK-NEXT:    add a4, a4, a12360; CHECK-NEXT:    vl1r.v v18, (a7)2361; CHECK-NEXT:    add a7, a7, a12362; CHECK-NEXT:    srli a1, a1, 22363; CHECK-NEXT:    vl1r.v v9, (a2)2364; CHECK-NEXT:    vl1r.v v17, (a4)2365; CHECK-NEXT:    vl1r.v v11, (a0)2366; CHECK-NEXT:    vl1r.v v13, (a5)2367; CHECK-NEXT:    vl1r.v v19, (a7)2368; CHECK-NEXT:    vl1r.v v15, (a6)2369; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, ma2370; CHECK-NEXT:    vmsne.vi v20, v8, 02371; CHECK-NEXT:    vmsne.vi v9, v16, 02372; CHECK-NEXT:    vmsne.vi v16, v10, 02373; CHECK-NEXT:    vmsne.vi v0, v12, 02374; CHECK-NEXT:    vmsne.vi v10, v18, 02375; CHECK-NEXT:    vmsne.vi v8, v14, 02376; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma2377; CHECK-NEXT:    vslideup.vx v9, v20, a12378; CHECK-NEXT:    vslideup.vx v0, v16, a12379; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma2380; CHECK-NEXT:    vslideup.vx v0, v9, a32381; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma2382; CHECK-NEXT:    vslideup.vx v8, v10, a12383; CHECK-NEXT:    csrr a0, vlenb2384; CHECK-NEXT:    li a1, 122385; CHECK-NEXT:    mul a0, a0, a12386; CHECK-NEXT:    add sp, sp, a02387; CHECK-NEXT:    addi sp, sp, 162388; CHECK-NEXT:    ret2389;2390; ZVBB-LABEL: vector_interleave_nxv96i1_nxv16i1:2391; ZVBB:       # %bb.0:2392; ZVBB-NEXT:    addi sp, sp, -162393; ZVBB-NEXT:    csrr a0, vlenb2394; ZVBB-NEXT:    li a1, 122395; ZVBB-NEXT:    mul a0, a0, a12396; ZVBB-NEXT:    sub sp, sp, a02397; ZVBB-NEXT:    vsetvli a0, zero, e8, m2, ta, ma2398; ZVBB-NEXT:    vmv.v.i v20, 02399; ZVBB-NEXT:    vmerge.vim v14, v20, 1, v02400; ZVBB-NEXT:    vmv1r.v v0, v82401; ZVBB-NEXT:    vmerge.vim v22, v20, 1, v02402; ZVBB-NEXT:    vmv1r.v v0, v92403; ZVBB-NEXT:    vmv1r.v v16, v232404; ZVBB-NEXT:    vmerge.vim v8, v20, 1, v02405; ZVBB-NEXT:    csrr a0, vlenb2406; ZVBB-NEXT:    li a1, 62407; ZVBB-NEXT:    mul a0, a0, a12408; ZVBB-NEXT:    add a0, sp, a02409; ZVBB-NEXT:    addi a0, a0, 162410; ZVBB-NEXT:    vmv1r.v v17, v92411; ZVBB-NEXT:    vmv1r.v v0, v102412; ZVBB-NEXT:    vmerge.vim v24, v20, 1, v02413; ZVBB-NEXT:    addi a4, sp, 162414; ZVBB-NEXT:    vmv1r.v v18, v252415; ZVBB-NEXT:    vmv1r.v v0, v112416; ZVBB-NEXT:    vmerge.vim v26, v20, 1, v02417; ZVBB-NEXT:    csrr a1, vlenb2418; ZVBB-NEXT:    vmv1r.v v19, v272419; ZVBB-NEXT:    vmv1r.v v0, v122420; ZVBB-NEXT:    vmerge.vim v10, v20, 1, v02421; ZVBB-NEXT:    add a2, a0, a12422; ZVBB-NEXT:    vmv1r.v v20, v112423; ZVBB-NEXT:    vsetvli a3, zero, e8, m1, ta, ma2424; ZVBB-NEXT:    vsseg6e8.v v15, (a0)2425; ZVBB-NEXT:    vmv1r.v v15, v222426; ZVBB-NEXT:    add a5, a4, a12427; ZVBB-NEXT:    vmv1r.v v16, v82428; ZVBB-NEXT:    srli a3, a1, 12429; ZVBB-NEXT:    vmv1r.v v17, v242430; ZVBB-NEXT:    add a6, a5, a12431; ZVBB-NEXT:    vmv1r.v v18, v262432; ZVBB-NEXT:    add a7, a2, a12433; ZVBB-NEXT:    vmv1r.v v19, v102434; ZVBB-NEXT:    vsseg6e8.v v14, (a4)2435; ZVBB-NEXT:    vl1r.v v8, (a0)2436; ZVBB-NEXT:    add a0, a6, a12437; ZVBB-NEXT:    vl1r.v v10, (a6)2438; ZVBB-NEXT:    add a6, a7, a12439; ZVBB-NEXT:    vl1r.v v12, (a4)2440; ZVBB-NEXT:    add a4, a0, a12441; ZVBB-NEXT:    vl1r.v v14, (a7)2442; ZVBB-NEXT:    add a7, a6, a12443; ZVBB-NEXT:    vl1r.v v16, (a4)2444; ZVBB-NEXT:    add a4, a4, a12445; ZVBB-NEXT:    vl1r.v v18, (a7)2446; ZVBB-NEXT:    add a7, a7, a12447; ZVBB-NEXT:    srli a1, a1, 22448; ZVBB-NEXT:    vl1r.v v9, (a2)2449; ZVBB-NEXT:    vl1r.v v17, (a4)2450; ZVBB-NEXT:    vl1r.v v11, (a0)2451; ZVBB-NEXT:    vl1r.v v13, (a5)2452; ZVBB-NEXT:    vl1r.v v19, (a7)2453; ZVBB-NEXT:    vl1r.v v15, (a6)2454; ZVBB-NEXT:    vsetvli a0, zero, e8, m2, ta, ma2455; ZVBB-NEXT:    vmsne.vi v20, v8, 02456; ZVBB-NEXT:    vmsne.vi v9, v16, 02457; ZVBB-NEXT:    vmsne.vi v16, v10, 02458; ZVBB-NEXT:    vmsne.vi v0, v12, 02459; ZVBB-NEXT:    vmsne.vi v10, v18, 02460; ZVBB-NEXT:    vmsne.vi v8, v14, 02461; ZVBB-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma2462; ZVBB-NEXT:    vslideup.vx v9, v20, a12463; ZVBB-NEXT:    vslideup.vx v0, v16, a12464; ZVBB-NEXT:    vsetvli a0, zero, e8, m1, ta, ma2465; ZVBB-NEXT:    vslideup.vx v0, v9, a32466; ZVBB-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma2467; ZVBB-NEXT:    vslideup.vx v8, v10, a12468; ZVBB-NEXT:    csrr a0, vlenb2469; ZVBB-NEXT:    li a1, 122470; ZVBB-NEXT:    mul a0, a0, a12471; ZVBB-NEXT:    add sp, sp, a02472; ZVBB-NEXT:    addi sp, sp, 162473; ZVBB-NEXT:    ret2474  %res = call <vscale x 96 x i1> @llvm.vector.interleave6.nxv96i1(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b, <vscale x 16 x i1> %c, <vscale x 16 x i1> %d, <vscale x 16 x i1> %e, <vscale x 16 x i1> %f)2475  ret <vscale x 96 x i1> %res2476}2477 2478define <vscale x 96 x i8> @vector_interleave_nxv96i8_nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c, <vscale x 16 x i8> %d, <vscale x 16 x i8> %e, <vscale x 16 x i8> %f) nounwind {2479;2480; RV32-LABEL: vector_interleave_nxv96i8_nxv16i8:2481; RV32:       # %bb.0:2482; RV32-NEXT:    addi sp, sp, -802483; RV32-NEXT:    sw ra, 76(sp) # 4-byte Folded Spill2484; RV32-NEXT:    sw s0, 72(sp) # 4-byte Folded Spill2485; RV32-NEXT:    addi s0, sp, 802486; RV32-NEXT:    csrr a0, vlenb2487; RV32-NEXT:    li a1, 282488; RV32-NEXT:    mul a0, a0, a12489; RV32-NEXT:    sub sp, sp, a02490; RV32-NEXT:    andi sp, sp, -642491; RV32-NEXT:    vsetvli a0, zero, e8, m1, ta, ma2492; RV32-NEXT:    vmv2r.v v20, v142493; RV32-NEXT:    vmv2r.v v22, v122494; RV32-NEXT:    vmv2r.v v24, v102495; RV32-NEXT:    csrr a1, vlenb2496; RV32-NEXT:    li a0, 62497; RV32-NEXT:    mul a1, a1, a02498; RV32-NEXT:    add a1, sp, a12499; RV32-NEXT:    addi a1, a1, 642500; RV32-NEXT:    vmv1r.v v10, v252501; RV32-NEXT:    vmv1r.v v11, v232502; RV32-NEXT:    vmv1r.v v12, v212503; RV32-NEXT:    addi a0, sp, 642504; RV32-NEXT:    vmv1r.v v13, v172505; RV32-NEXT:    csrr a2, vlenb2506; RV32-NEXT:    vmv1r.v v14, v192507; RV32-NEXT:    vsseg6e8.v v9, (a1)2508; RV32-NEXT:    vmv1r.v v9, v242509; RV32-NEXT:    add a5, a1, a22510; RV32-NEXT:    vmv1r.v v10, v222511; RV32-NEXT:    add a3, a0, a22512; RV32-NEXT:    vmv1r.v v11, v202513; RV32-NEXT:    add a4, a3, a22514; RV32-NEXT:    vmv1r.v v12, v162515; RV32-NEXT:    add a6, a5, a22516; RV32-NEXT:    vmv1r.v v13, v182517; RV32-NEXT:    vsseg6e8.v v8, (a0)2518; RV32-NEXT:    vl1r.v v14, (a1)2519; RV32-NEXT:    add a1, a6, a22520; RV32-NEXT:    vl1r.v v15, (a5)2521; RV32-NEXT:    add a5, a1, a22522; RV32-NEXT:    vl1r.v v18, (a5)2523; RV32-NEXT:    add a5, a5, a22524; RV32-NEXT:    vl1r.v v19, (a5)2525; RV32-NEXT:    add a5, a4, a22526; RV32-NEXT:    vl1r.v v16, (a6)2527; RV32-NEXT:    add a6, a5, a22528; RV32-NEXT:    vl1r.v v12, (a6)2529; RV32-NEXT:    add a6, a6, a22530; RV32-NEXT:    vl1r.v v13, (a6)2531; RV32-NEXT:    csrr a6, vlenb2532; RV32-NEXT:    li a7, 122533; RV32-NEXT:    mul a6, a6, a72534; RV32-NEXT:    add a6, sp, a62535; RV32-NEXT:    addi a6, a6, 642536; RV32-NEXT:    vl1r.v v17, (a1)2537; RV32-NEXT:    vl1r.v v10, (a4)2538; RV32-NEXT:    vl1r.v v11, (a5)2539; RV32-NEXT:    vl1r.v v8, (a0)2540; RV32-NEXT:    vl1r.v v9, (a3)2541; RV32-NEXT:    slli a2, a2, 32542; RV32-NEXT:    add a2, a6, a22543; RV32-NEXT:    vs4r.v v16, (a2)2544; RV32-NEXT:    vs8r.v v8, (a6)2545; RV32-NEXT:    vl8r.v v16, (a2)2546; RV32-NEXT:    vl8r.v v8, (a6)2547; RV32-NEXT:    addi sp, s0, -802548; RV32-NEXT:    lw ra, 76(sp) # 4-byte Folded Reload2549; RV32-NEXT:    lw s0, 72(sp) # 4-byte Folded Reload2550; RV32-NEXT:    addi sp, sp, 802551; RV32-NEXT:    ret2552;2553; RV64-LABEL: vector_interleave_nxv96i8_nxv16i8:2554; RV64:       # %bb.0:2555; RV64-NEXT:    addi sp, sp, -802556; RV64-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill2557; RV64-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill2558; RV64-NEXT:    addi s0, sp, 802559; RV64-NEXT:    csrr a0, vlenb2560; RV64-NEXT:    li a1, 282561; RV64-NEXT:    mul a0, a0, a12562; RV64-NEXT:    sub sp, sp, a02563; RV64-NEXT:    andi sp, sp, -642564; RV64-NEXT:    vsetvli a0, zero, e8, m1, ta, ma2565; RV64-NEXT:    vmv2r.v v20, v142566; RV64-NEXT:    vmv2r.v v22, v122567; RV64-NEXT:    vmv2r.v v24, v102568; RV64-NEXT:    csrr a1, vlenb2569; RV64-NEXT:    li a0, 62570; RV64-NEXT:    mul a1, a1, a02571; RV64-NEXT:    add a1, sp, a12572; RV64-NEXT:    addi a1, a1, 642573; RV64-NEXT:    vmv1r.v v10, v252574; RV64-NEXT:    vmv1r.v v11, v232575; RV64-NEXT:    vmv1r.v v12, v212576; RV64-NEXT:    addi a0, sp, 642577; RV64-NEXT:    vmv1r.v v13, v172578; RV64-NEXT:    csrr a2, vlenb2579; RV64-NEXT:    vmv1r.v v14, v192580; RV64-NEXT:    vsseg6e8.v v9, (a1)2581; RV64-NEXT:    vmv1r.v v9, v242582; RV64-NEXT:    add a5, a1, a22583; RV64-NEXT:    vmv1r.v v10, v222584; RV64-NEXT:    add a3, a0, a22585; RV64-NEXT:    vmv1r.v v11, v202586; RV64-NEXT:    add a4, a3, a22587; RV64-NEXT:    vmv1r.v v12, v162588; RV64-NEXT:    add a6, a5, a22589; RV64-NEXT:    vmv1r.v v13, v182590; RV64-NEXT:    vsseg6e8.v v8, (a0)2591; RV64-NEXT:    vl1r.v v14, (a1)2592; RV64-NEXT:    add a1, a6, a22593; RV64-NEXT:    vl1r.v v15, (a5)2594; RV64-NEXT:    add a5, a1, a22595; RV64-NEXT:    vl1r.v v18, (a5)2596; RV64-NEXT:    add a5, a5, a22597; RV64-NEXT:    vl1r.v v19, (a5)2598; RV64-NEXT:    add a5, a4, a22599; RV64-NEXT:    vl1r.v v16, (a6)2600; RV64-NEXT:    add a6, a5, a22601; RV64-NEXT:    vl1r.v v12, (a6)2602; RV64-NEXT:    add a6, a6, a22603; RV64-NEXT:    vl1r.v v13, (a6)2604; RV64-NEXT:    csrr a6, vlenb2605; RV64-NEXT:    li a7, 122606; RV64-NEXT:    mul a6, a6, a72607; RV64-NEXT:    add a6, sp, a62608; RV64-NEXT:    addi a6, a6, 642609; RV64-NEXT:    vl1r.v v17, (a1)2610; RV64-NEXT:    vl1r.v v10, (a4)2611; RV64-NEXT:    vl1r.v v11, (a5)2612; RV64-NEXT:    vl1r.v v8, (a0)2613; RV64-NEXT:    vl1r.v v9, (a3)2614; RV64-NEXT:    slli a2, a2, 32615; RV64-NEXT:    add a2, a6, a22616; RV64-NEXT:    vs4r.v v16, (a2)2617; RV64-NEXT:    vs8r.v v8, (a6)2618; RV64-NEXT:    vl8r.v v16, (a2)2619; RV64-NEXT:    vl8r.v v8, (a6)2620; RV64-NEXT:    addi sp, s0, -802621; RV64-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload2622; RV64-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload2623; RV64-NEXT:    addi sp, sp, 802624; RV64-NEXT:    ret2625;2626; ZVBB-RV32-LABEL: vector_interleave_nxv96i8_nxv16i8:2627; ZVBB-RV32:       # %bb.0:2628; ZVBB-RV32-NEXT:    addi sp, sp, -802629; ZVBB-RV32-NEXT:    sw ra, 76(sp) # 4-byte Folded Spill2630; ZVBB-RV32-NEXT:    sw s0, 72(sp) # 4-byte Folded Spill2631; ZVBB-RV32-NEXT:    addi s0, sp, 802632; ZVBB-RV32-NEXT:    csrr a0, vlenb2633; ZVBB-RV32-NEXT:    li a1, 282634; ZVBB-RV32-NEXT:    mul a0, a0, a12635; ZVBB-RV32-NEXT:    sub sp, sp, a02636; ZVBB-RV32-NEXT:    andi sp, sp, -642637; ZVBB-RV32-NEXT:    vsetvli a0, zero, e8, m1, ta, ma2638; ZVBB-RV32-NEXT:    vmv2r.v v20, v142639; ZVBB-RV32-NEXT:    vmv2r.v v22, v122640; ZVBB-RV32-NEXT:    vmv2r.v v24, v102641; ZVBB-RV32-NEXT:    csrr a1, vlenb2642; ZVBB-RV32-NEXT:    li a0, 62643; ZVBB-RV32-NEXT:    mul a1, a1, a02644; ZVBB-RV32-NEXT:    add a1, sp, a12645; ZVBB-RV32-NEXT:    addi a1, a1, 642646; ZVBB-RV32-NEXT:    vmv1r.v v10, v252647; ZVBB-RV32-NEXT:    vmv1r.v v11, v232648; ZVBB-RV32-NEXT:    vmv1r.v v12, v212649; ZVBB-RV32-NEXT:    addi a0, sp, 642650; ZVBB-RV32-NEXT:    vmv1r.v v13, v172651; ZVBB-RV32-NEXT:    csrr a2, vlenb2652; ZVBB-RV32-NEXT:    vmv1r.v v14, v192653; ZVBB-RV32-NEXT:    vsseg6e8.v v9, (a1)2654; ZVBB-RV32-NEXT:    vmv1r.v v9, v242655; ZVBB-RV32-NEXT:    add a5, a1, a22656; ZVBB-RV32-NEXT:    vmv1r.v v10, v222657; ZVBB-RV32-NEXT:    add a3, a0, a22658; ZVBB-RV32-NEXT:    vmv1r.v v11, v202659; ZVBB-RV32-NEXT:    add a4, a3, a22660; ZVBB-RV32-NEXT:    vmv1r.v v12, v162661; ZVBB-RV32-NEXT:    add a6, a5, a22662; ZVBB-RV32-NEXT:    vmv1r.v v13, v182663; ZVBB-RV32-NEXT:    vsseg6e8.v v8, (a0)2664; ZVBB-RV32-NEXT:    vl1r.v v14, (a1)2665; ZVBB-RV32-NEXT:    add a1, a6, a22666; ZVBB-RV32-NEXT:    vl1r.v v15, (a5)2667; ZVBB-RV32-NEXT:    add a5, a1, a22668; ZVBB-RV32-NEXT:    vl1r.v v18, (a5)2669; ZVBB-RV32-NEXT:    add a5, a5, a22670; ZVBB-RV32-NEXT:    vl1r.v v19, (a5)2671; ZVBB-RV32-NEXT:    add a5, a4, a22672; ZVBB-RV32-NEXT:    vl1r.v v16, (a6)2673; ZVBB-RV32-NEXT:    add a6, a5, a22674; ZVBB-RV32-NEXT:    vl1r.v v12, (a6)2675; ZVBB-RV32-NEXT:    add a6, a6, a22676; ZVBB-RV32-NEXT:    vl1r.v v13, (a6)2677; ZVBB-RV32-NEXT:    csrr a6, vlenb2678; ZVBB-RV32-NEXT:    li a7, 122679; ZVBB-RV32-NEXT:    mul a6, a6, a72680; ZVBB-RV32-NEXT:    add a6, sp, a62681; ZVBB-RV32-NEXT:    addi a6, a6, 642682; ZVBB-RV32-NEXT:    vl1r.v v17, (a1)2683; ZVBB-RV32-NEXT:    vl1r.v v10, (a4)2684; ZVBB-RV32-NEXT:    vl1r.v v11, (a5)2685; ZVBB-RV32-NEXT:    vl1r.v v8, (a0)2686; ZVBB-RV32-NEXT:    vl1r.v v9, (a3)2687; ZVBB-RV32-NEXT:    slli a2, a2, 32688; ZVBB-RV32-NEXT:    add a2, a6, a22689; ZVBB-RV32-NEXT:    vs4r.v v16, (a2)2690; ZVBB-RV32-NEXT:    vs8r.v v8, (a6)2691; ZVBB-RV32-NEXT:    vl8r.v v16, (a2)2692; ZVBB-RV32-NEXT:    vl8r.v v8, (a6)2693; ZVBB-RV32-NEXT:    addi sp, s0, -802694; ZVBB-RV32-NEXT:    lw ra, 76(sp) # 4-byte Folded Reload2695; ZVBB-RV32-NEXT:    lw s0, 72(sp) # 4-byte Folded Reload2696; ZVBB-RV32-NEXT:    addi sp, sp, 802697; ZVBB-RV32-NEXT:    ret2698;2699; ZVBB-RV64-LABEL: vector_interleave_nxv96i8_nxv16i8:2700; ZVBB-RV64:       # %bb.0:2701; ZVBB-RV64-NEXT:    addi sp, sp, -802702; ZVBB-RV64-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill2703; ZVBB-RV64-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill2704; ZVBB-RV64-NEXT:    addi s0, sp, 802705; ZVBB-RV64-NEXT:    csrr a0, vlenb2706; ZVBB-RV64-NEXT:    li a1, 282707; ZVBB-RV64-NEXT:    mul a0, a0, a12708; ZVBB-RV64-NEXT:    sub sp, sp, a02709; ZVBB-RV64-NEXT:    andi sp, sp, -642710; ZVBB-RV64-NEXT:    vsetvli a0, zero, e8, m1, ta, ma2711; ZVBB-RV64-NEXT:    vmv2r.v v20, v142712; ZVBB-RV64-NEXT:    vmv2r.v v22, v122713; ZVBB-RV64-NEXT:    vmv2r.v v24, v102714; ZVBB-RV64-NEXT:    csrr a1, vlenb2715; ZVBB-RV64-NEXT:    li a0, 62716; ZVBB-RV64-NEXT:    mul a1, a1, a02717; ZVBB-RV64-NEXT:    add a1, sp, a12718; ZVBB-RV64-NEXT:    addi a1, a1, 642719; ZVBB-RV64-NEXT:    vmv1r.v v10, v252720; ZVBB-RV64-NEXT:    vmv1r.v v11, v232721; ZVBB-RV64-NEXT:    vmv1r.v v12, v212722; ZVBB-RV64-NEXT:    addi a0, sp, 642723; ZVBB-RV64-NEXT:    vmv1r.v v13, v172724; ZVBB-RV64-NEXT:    csrr a2, vlenb2725; ZVBB-RV64-NEXT:    vmv1r.v v14, v192726; ZVBB-RV64-NEXT:    vsseg6e8.v v9, (a1)2727; ZVBB-RV64-NEXT:    vmv1r.v v9, v242728; ZVBB-RV64-NEXT:    add a5, a1, a22729; ZVBB-RV64-NEXT:    vmv1r.v v10, v222730; ZVBB-RV64-NEXT:    add a3, a0, a22731; ZVBB-RV64-NEXT:    vmv1r.v v11, v202732; ZVBB-RV64-NEXT:    add a4, a3, a22733; ZVBB-RV64-NEXT:    vmv1r.v v12, v162734; ZVBB-RV64-NEXT:    add a6, a5, a22735; ZVBB-RV64-NEXT:    vmv1r.v v13, v182736; ZVBB-RV64-NEXT:    vsseg6e8.v v8, (a0)2737; ZVBB-RV64-NEXT:    vl1r.v v14, (a1)2738; ZVBB-RV64-NEXT:    add a1, a6, a22739; ZVBB-RV64-NEXT:    vl1r.v v15, (a5)2740; ZVBB-RV64-NEXT:    add a5, a1, a22741; ZVBB-RV64-NEXT:    vl1r.v v18, (a5)2742; ZVBB-RV64-NEXT:    add a5, a5, a22743; ZVBB-RV64-NEXT:    vl1r.v v19, (a5)2744; ZVBB-RV64-NEXT:    add a5, a4, a22745; ZVBB-RV64-NEXT:    vl1r.v v16, (a6)2746; ZVBB-RV64-NEXT:    add a6, a5, a22747; ZVBB-RV64-NEXT:    vl1r.v v12, (a6)2748; ZVBB-RV64-NEXT:    add a6, a6, a22749; ZVBB-RV64-NEXT:    vl1r.v v13, (a6)2750; ZVBB-RV64-NEXT:    csrr a6, vlenb2751; ZVBB-RV64-NEXT:    li a7, 122752; ZVBB-RV64-NEXT:    mul a6, a6, a72753; ZVBB-RV64-NEXT:    add a6, sp, a62754; ZVBB-RV64-NEXT:    addi a6, a6, 642755; ZVBB-RV64-NEXT:    vl1r.v v17, (a1)2756; ZVBB-RV64-NEXT:    vl1r.v v10, (a4)2757; ZVBB-RV64-NEXT:    vl1r.v v11, (a5)2758; ZVBB-RV64-NEXT:    vl1r.v v8, (a0)2759; ZVBB-RV64-NEXT:    vl1r.v v9, (a3)2760; ZVBB-RV64-NEXT:    slli a2, a2, 32761; ZVBB-RV64-NEXT:    add a2, a6, a22762; ZVBB-RV64-NEXT:    vs4r.v v16, (a2)2763; ZVBB-RV64-NEXT:    vs8r.v v8, (a6)2764; ZVBB-RV64-NEXT:    vl8r.v v16, (a2)2765; ZVBB-RV64-NEXT:    vl8r.v v8, (a6)2766; ZVBB-RV64-NEXT:    addi sp, s0, -802767; ZVBB-RV64-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload2768; ZVBB-RV64-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload2769; ZVBB-RV64-NEXT:    addi sp, sp, 802770; ZVBB-RV64-NEXT:    ret2771;2772; ZIP-LABEL: vector_interleave_nxv96i8_nxv16i8:2773; ZIP:       # %bb.0:2774; ZIP-NEXT:    addi sp, sp, -802775; ZIP-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill2776; ZIP-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill2777; ZIP-NEXT:    addi s0, sp, 802778; ZIP-NEXT:    csrr a0, vlenb2779; ZIP-NEXT:    li a1, 282780; ZIP-NEXT:    mul a0, a0, a12781; ZIP-NEXT:    sub sp, sp, a02782; ZIP-NEXT:    andi sp, sp, -642783; ZIP-NEXT:    vsetvli a0, zero, e8, m1, ta, ma2784; ZIP-NEXT:    vmv2r.v v20, v142785; ZIP-NEXT:    vmv2r.v v22, v122786; ZIP-NEXT:    vmv2r.v v24, v102787; ZIP-NEXT:    csrr a1, vlenb2788; ZIP-NEXT:    li a0, 62789; ZIP-NEXT:    mul a1, a1, a02790; ZIP-NEXT:    add a1, sp, a12791; ZIP-NEXT:    addi a1, a1, 642792; ZIP-NEXT:    vmv1r.v v10, v252793; ZIP-NEXT:    vmv1r.v v11, v232794; ZIP-NEXT:    vmv1r.v v12, v212795; ZIP-NEXT:    addi a0, sp, 642796; ZIP-NEXT:    vmv1r.v v13, v172797; ZIP-NEXT:    csrr a2, vlenb2798; ZIP-NEXT:    vmv1r.v v14, v192799; ZIP-NEXT:    vsseg6e8.v v9, (a1)2800; ZIP-NEXT:    vmv1r.v v9, v242801; ZIP-NEXT:    add a5, a1, a22802; ZIP-NEXT:    vmv1r.v v10, v222803; ZIP-NEXT:    add a3, a0, a22804; ZIP-NEXT:    vmv1r.v v11, v202805; ZIP-NEXT:    add a4, a3, a22806; ZIP-NEXT:    vmv1r.v v12, v162807; ZIP-NEXT:    add a6, a5, a22808; ZIP-NEXT:    vmv1r.v v13, v182809; ZIP-NEXT:    vsseg6e8.v v8, (a0)2810; ZIP-NEXT:    vl1r.v v14, (a1)2811; ZIP-NEXT:    add a1, a6, a22812; ZIP-NEXT:    vl1r.v v15, (a5)2813; ZIP-NEXT:    add a5, a1, a22814; ZIP-NEXT:    vl1r.v v18, (a5)2815; ZIP-NEXT:    add a5, a5, a22816; ZIP-NEXT:    vl1r.v v19, (a5)2817; ZIP-NEXT:    add a5, a4, a22818; ZIP-NEXT:    vl1r.v v16, (a6)2819; ZIP-NEXT:    add a6, a5, a22820; ZIP-NEXT:    vl1r.v v12, (a6)2821; ZIP-NEXT:    add a6, a6, a22822; ZIP-NEXT:    vl1r.v v13, (a6)2823; ZIP-NEXT:    csrr a6, vlenb2824; ZIP-NEXT:    li a7, 122825; ZIP-NEXT:    mul a6, a6, a72826; ZIP-NEXT:    add a6, sp, a62827; ZIP-NEXT:    addi a6, a6, 642828; ZIP-NEXT:    vl1r.v v17, (a1)2829; ZIP-NEXT:    vl1r.v v10, (a4)2830; ZIP-NEXT:    vl1r.v v11, (a5)2831; ZIP-NEXT:    vl1r.v v8, (a0)2832; ZIP-NEXT:    vl1r.v v9, (a3)2833; ZIP-NEXT:    slli a2, a2, 32834; ZIP-NEXT:    add a2, a6, a22835; ZIP-NEXT:    vs4r.v v16, (a2)2836; ZIP-NEXT:    vs8r.v v8, (a6)2837; ZIP-NEXT:    vl8r.v v16, (a2)2838; ZIP-NEXT:    vl8r.v v8, (a6)2839; ZIP-NEXT:    addi sp, s0, -802840; ZIP-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload2841; ZIP-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload2842; ZIP-NEXT:    addi sp, sp, 802843; ZIP-NEXT:    ret2844  %res = call <vscale x 96 x i8> @llvm.vector.interleave6.nxv96i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c, <vscale x 16 x i8> %d, <vscale x 16 x i8> %e, <vscale x 16 x i8> %f)2845  ret <vscale x 96 x i8> %res2846}2847 2848define <vscale x 48 x i8> @vector_interleave_nxv48i8_nxv8i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b, <vscale x 8 x i8> %c, <vscale x 8 x i8> %d, <vscale x 8 x i8> %e, <vscale x 8 x i8> %f) nounwind {2849; CHECK-LABEL: vector_interleave_nxv48i8_nxv8i8:2850; CHECK:       # %bb.0:2851; CHECK-NEXT:    addi sp, sp, -162852; CHECK-NEXT:    csrr a0, vlenb2853; CHECK-NEXT:    li a1, 62854; CHECK-NEXT:    mul a0, a0, a12855; CHECK-NEXT:    sub sp, sp, a02856; CHECK-NEXT:    addi a0, sp, 162857; CHECK-NEXT:    csrr a1, vlenb2858; CHECK-NEXT:    add a2, a0, a12859; CHECK-NEXT:    add a3, a2, a12860; CHECK-NEXT:    vsetvli a4, zero, e8, m1, ta, ma2861; CHECK-NEXT:    vsseg6e8.v v8, (a0)2862; CHECK-NEXT:    vl1r.v v10, (a3)2863; CHECK-NEXT:    add a3, a3, a12864; CHECK-NEXT:    vl1r.v v11, (a3)2865; CHECK-NEXT:    add a3, a3, a12866; CHECK-NEXT:    vl1r.v v8, (a0)2867; CHECK-NEXT:    vl1r.v v9, (a2)2868; CHECK-NEXT:    vl1r.v v12, (a3)2869; CHECK-NEXT:    add a1, a3, a12870; CHECK-NEXT:    vl1r.v v13, (a1)2871; CHECK-NEXT:    csrr a0, vlenb2872; CHECK-NEXT:    li a1, 62873; CHECK-NEXT:    mul a0, a0, a12874; CHECK-NEXT:    add sp, sp, a02875; CHECK-NEXT:    addi sp, sp, 162876; CHECK-NEXT:    ret2877;2878; ZVBB-LABEL: vector_interleave_nxv48i8_nxv8i8:2879; ZVBB:       # %bb.0:2880; ZVBB-NEXT:    addi sp, sp, -162881; ZVBB-NEXT:    csrr a0, vlenb2882; ZVBB-NEXT:    li a1, 62883; ZVBB-NEXT:    mul a0, a0, a12884; ZVBB-NEXT:    sub sp, sp, a02885; ZVBB-NEXT:    addi a0, sp, 162886; ZVBB-NEXT:    csrr a1, vlenb2887; ZVBB-NEXT:    add a2, a0, a12888; ZVBB-NEXT:    add a3, a2, a12889; ZVBB-NEXT:    vsetvli a4, zero, e8, m1, ta, ma2890; ZVBB-NEXT:    vsseg6e8.v v8, (a0)2891; ZVBB-NEXT:    vl1r.v v10, (a3)2892; ZVBB-NEXT:    add a3, a3, a12893; ZVBB-NEXT:    vl1r.v v11, (a3)2894; ZVBB-NEXT:    add a3, a3, a12895; ZVBB-NEXT:    vl1r.v v8, (a0)2896; ZVBB-NEXT:    vl1r.v v9, (a2)2897; ZVBB-NEXT:    vl1r.v v12, (a3)2898; ZVBB-NEXT:    add a1, a3, a12899; ZVBB-NEXT:    vl1r.v v13, (a1)2900; ZVBB-NEXT:    csrr a0, vlenb2901; ZVBB-NEXT:    li a1, 62902; ZVBB-NEXT:    mul a0, a0, a12903; ZVBB-NEXT:    add sp, sp, a02904; ZVBB-NEXT:    addi sp, sp, 162905; ZVBB-NEXT:    ret2906  %res = call <vscale x 48 x i8> @llvm.vector.interleave6.nxv48i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b, <vscale x 8 x i8> %c, <vscale x 8 x i8> %d, <vscale x 8 x i8> %e, <vscale x 8 x i8> %f)2907  ret <vscale x 48 x i8> %res2908}2909 2910define <vscale x 24 x i32> @vector_interleave_nxv24i32_nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c, <vscale x 4 x i32> %d, <vscale x 4 x i32> %e, <vscale x 4 x i32> %f) nounwind {2911;2912; RV32-LABEL: vector_interleave_nxv24i32_nxv4i32:2913; RV32:       # %bb.0:2914; RV32-NEXT:    addi sp, sp, -802915; RV32-NEXT:    sw ra, 76(sp) # 4-byte Folded Spill2916; RV32-NEXT:    sw s0, 72(sp) # 4-byte Folded Spill2917; RV32-NEXT:    addi s0, sp, 802918; RV32-NEXT:    csrr a0, vlenb2919; RV32-NEXT:    li a1, 282920; RV32-NEXT:    mul a0, a0, a12921; RV32-NEXT:    sub sp, sp, a02922; RV32-NEXT:    andi sp, sp, -642923; RV32-NEXT:    vsetvli a0, zero, e32, m1, ta, ma2924; RV32-NEXT:    vmv2r.v v20, v142925; RV32-NEXT:    vmv2r.v v22, v122926; RV32-NEXT:    vmv2r.v v24, v102927; RV32-NEXT:    csrr a1, vlenb2928; RV32-NEXT:    li a0, 62929; RV32-NEXT:    mul a1, a1, a02930; RV32-NEXT:    add a1, sp, a12931; RV32-NEXT:    addi a1, a1, 642932; RV32-NEXT:    vmv1r.v v10, v252933; RV32-NEXT:    vmv1r.v v11, v232934; RV32-NEXT:    vmv1r.v v12, v212935; RV32-NEXT:    addi a0, sp, 642936; RV32-NEXT:    vmv1r.v v13, v172937; RV32-NEXT:    csrr a2, vlenb2938; RV32-NEXT:    vmv1r.v v14, v192939; RV32-NEXT:    vsseg6e32.v v9, (a1)2940; RV32-NEXT:    vmv1r.v v9, v242941; RV32-NEXT:    add a5, a1, a22942; RV32-NEXT:    vmv1r.v v10, v222943; RV32-NEXT:    add a3, a0, a22944; RV32-NEXT:    vmv1r.v v11, v202945; RV32-NEXT:    add a4, a3, a22946; RV32-NEXT:    vmv1r.v v12, v162947; RV32-NEXT:    add a6, a5, a22948; RV32-NEXT:    vmv1r.v v13, v182949; RV32-NEXT:    vsseg6e32.v v8, (a0)2950; RV32-NEXT:    vl1re32.v v14, (a1)2951; RV32-NEXT:    add a1, a6, a22952; RV32-NEXT:    vl1re32.v v15, (a5)2953; RV32-NEXT:    add a5, a1, a22954; RV32-NEXT:    vl1re32.v v18, (a5)2955; RV32-NEXT:    add a5, a5, a22956; RV32-NEXT:    vl1re32.v v19, (a5)2957; RV32-NEXT:    add a5, a4, a22958; RV32-NEXT:    vl1re32.v v16, (a6)2959; RV32-NEXT:    add a6, a5, a22960; RV32-NEXT:    vl1re32.v v12, (a6)2961; RV32-NEXT:    add a6, a6, a22962; RV32-NEXT:    vl1re32.v v13, (a6)2963; RV32-NEXT:    csrr a6, vlenb2964; RV32-NEXT:    li a7, 122965; RV32-NEXT:    mul a6, a6, a72966; RV32-NEXT:    add a6, sp, a62967; RV32-NEXT:    addi a6, a6, 642968; RV32-NEXT:    vl1re32.v v17, (a1)2969; RV32-NEXT:    vl1re32.v v10, (a4)2970; RV32-NEXT:    vl1re32.v v11, (a5)2971; RV32-NEXT:    vl1re32.v v8, (a0)2972; RV32-NEXT:    vl1re32.v v9, (a3)2973; RV32-NEXT:    slli a2, a2, 32974; RV32-NEXT:    add a2, a6, a22975; RV32-NEXT:    vs4r.v v16, (a2)2976; RV32-NEXT:    vs8r.v v8, (a6)2977; RV32-NEXT:    vl8re32.v v16, (a2)2978; RV32-NEXT:    vl8re32.v v8, (a6)2979; RV32-NEXT:    addi sp, s0, -802980; RV32-NEXT:    lw ra, 76(sp) # 4-byte Folded Reload2981; RV32-NEXT:    lw s0, 72(sp) # 4-byte Folded Reload2982; RV32-NEXT:    addi sp, sp, 802983; RV32-NEXT:    ret2984;2985; RV64-LABEL: vector_interleave_nxv24i32_nxv4i32:2986; RV64:       # %bb.0:2987; RV64-NEXT:    addi sp, sp, -802988; RV64-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill2989; RV64-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill2990; RV64-NEXT:    addi s0, sp, 802991; RV64-NEXT:    csrr a0, vlenb2992; RV64-NEXT:    li a1, 282993; RV64-NEXT:    mul a0, a0, a12994; RV64-NEXT:    sub sp, sp, a02995; RV64-NEXT:    andi sp, sp, -642996; RV64-NEXT:    vsetvli a0, zero, e32, m1, ta, ma2997; RV64-NEXT:    vmv2r.v v20, v142998; RV64-NEXT:    vmv2r.v v22, v122999; RV64-NEXT:    vmv2r.v v24, v103000; RV64-NEXT:    csrr a1, vlenb3001; RV64-NEXT:    li a0, 63002; RV64-NEXT:    mul a1, a1, a03003; RV64-NEXT:    add a1, sp, a13004; RV64-NEXT:    addi a1, a1, 643005; RV64-NEXT:    vmv1r.v v10, v253006; RV64-NEXT:    vmv1r.v v11, v233007; RV64-NEXT:    vmv1r.v v12, v213008; RV64-NEXT:    addi a0, sp, 643009; RV64-NEXT:    vmv1r.v v13, v173010; RV64-NEXT:    csrr a2, vlenb3011; RV64-NEXT:    vmv1r.v v14, v193012; RV64-NEXT:    vsseg6e32.v v9, (a1)3013; RV64-NEXT:    vmv1r.v v9, v243014; RV64-NEXT:    add a5, a1, a23015; RV64-NEXT:    vmv1r.v v10, v223016; RV64-NEXT:    add a3, a0, a23017; RV64-NEXT:    vmv1r.v v11, v203018; RV64-NEXT:    add a4, a3, a23019; RV64-NEXT:    vmv1r.v v12, v163020; RV64-NEXT:    add a6, a5, a23021; RV64-NEXT:    vmv1r.v v13, v183022; RV64-NEXT:    vsseg6e32.v v8, (a0)3023; RV64-NEXT:    vl1re32.v v14, (a1)3024; RV64-NEXT:    add a1, a6, a23025; RV64-NEXT:    vl1re32.v v15, (a5)3026; RV64-NEXT:    add a5, a1, a23027; RV64-NEXT:    vl1re32.v v18, (a5)3028; RV64-NEXT:    add a5, a5, a23029; RV64-NEXT:    vl1re32.v v19, (a5)3030; RV64-NEXT:    add a5, a4, a23031; RV64-NEXT:    vl1re32.v v16, (a6)3032; RV64-NEXT:    add a6, a5, a23033; RV64-NEXT:    vl1re32.v v12, (a6)3034; RV64-NEXT:    add a6, a6, a23035; RV64-NEXT:    vl1re32.v v13, (a6)3036; RV64-NEXT:    csrr a6, vlenb3037; RV64-NEXT:    li a7, 123038; RV64-NEXT:    mul a6, a6, a73039; RV64-NEXT:    add a6, sp, a63040; RV64-NEXT:    addi a6, a6, 643041; RV64-NEXT:    vl1re32.v v17, (a1)3042; RV64-NEXT:    vl1re32.v v10, (a4)3043; RV64-NEXT:    vl1re32.v v11, (a5)3044; RV64-NEXT:    vl1re32.v v8, (a0)3045; RV64-NEXT:    vl1re32.v v9, (a3)3046; RV64-NEXT:    slli a2, a2, 33047; RV64-NEXT:    add a2, a6, a23048; RV64-NEXT:    vs4r.v v16, (a2)3049; RV64-NEXT:    vs8r.v v8, (a6)3050; RV64-NEXT:    vl8re32.v v16, (a2)3051; RV64-NEXT:    vl8re32.v v8, (a6)3052; RV64-NEXT:    addi sp, s0, -803053; RV64-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload3054; RV64-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload3055; RV64-NEXT:    addi sp, sp, 803056; RV64-NEXT:    ret3057;3058; ZVBB-RV32-LABEL: vector_interleave_nxv24i32_nxv4i32:3059; ZVBB-RV32:       # %bb.0:3060; ZVBB-RV32-NEXT:    addi sp, sp, -803061; ZVBB-RV32-NEXT:    sw ra, 76(sp) # 4-byte Folded Spill3062; ZVBB-RV32-NEXT:    sw s0, 72(sp) # 4-byte Folded Spill3063; ZVBB-RV32-NEXT:    addi s0, sp, 803064; ZVBB-RV32-NEXT:    csrr a0, vlenb3065; ZVBB-RV32-NEXT:    li a1, 283066; ZVBB-RV32-NEXT:    mul a0, a0, a13067; ZVBB-RV32-NEXT:    sub sp, sp, a03068; ZVBB-RV32-NEXT:    andi sp, sp, -643069; ZVBB-RV32-NEXT:    vsetvli a0, zero, e32, m1, ta, ma3070; ZVBB-RV32-NEXT:    vmv2r.v v20, v143071; ZVBB-RV32-NEXT:    vmv2r.v v22, v123072; ZVBB-RV32-NEXT:    vmv2r.v v24, v103073; ZVBB-RV32-NEXT:    csrr a1, vlenb3074; ZVBB-RV32-NEXT:    li a0, 63075; ZVBB-RV32-NEXT:    mul a1, a1, a03076; ZVBB-RV32-NEXT:    add a1, sp, a13077; ZVBB-RV32-NEXT:    addi a1, a1, 643078; ZVBB-RV32-NEXT:    vmv1r.v v10, v253079; ZVBB-RV32-NEXT:    vmv1r.v v11, v233080; ZVBB-RV32-NEXT:    vmv1r.v v12, v213081; ZVBB-RV32-NEXT:    addi a0, sp, 643082; ZVBB-RV32-NEXT:    vmv1r.v v13, v173083; ZVBB-RV32-NEXT:    csrr a2, vlenb3084; ZVBB-RV32-NEXT:    vmv1r.v v14, v193085; ZVBB-RV32-NEXT:    vsseg6e32.v v9, (a1)3086; ZVBB-RV32-NEXT:    vmv1r.v v9, v243087; ZVBB-RV32-NEXT:    add a5, a1, a23088; ZVBB-RV32-NEXT:    vmv1r.v v10, v223089; ZVBB-RV32-NEXT:    add a3, a0, a23090; ZVBB-RV32-NEXT:    vmv1r.v v11, v203091; ZVBB-RV32-NEXT:    add a4, a3, a23092; ZVBB-RV32-NEXT:    vmv1r.v v12, v163093; ZVBB-RV32-NEXT:    add a6, a5, a23094; ZVBB-RV32-NEXT:    vmv1r.v v13, v183095; ZVBB-RV32-NEXT:    vsseg6e32.v v8, (a0)3096; ZVBB-RV32-NEXT:    vl1re32.v v14, (a1)3097; ZVBB-RV32-NEXT:    add a1, a6, a23098; ZVBB-RV32-NEXT:    vl1re32.v v15, (a5)3099; ZVBB-RV32-NEXT:    add a5, a1, a23100; ZVBB-RV32-NEXT:    vl1re32.v v18, (a5)3101; ZVBB-RV32-NEXT:    add a5, a5, a23102; ZVBB-RV32-NEXT:    vl1re32.v v19, (a5)3103; ZVBB-RV32-NEXT:    add a5, a4, a23104; ZVBB-RV32-NEXT:    vl1re32.v v16, (a6)3105; ZVBB-RV32-NEXT:    add a6, a5, a23106; ZVBB-RV32-NEXT:    vl1re32.v v12, (a6)3107; ZVBB-RV32-NEXT:    add a6, a6, a23108; ZVBB-RV32-NEXT:    vl1re32.v v13, (a6)3109; ZVBB-RV32-NEXT:    csrr a6, vlenb3110; ZVBB-RV32-NEXT:    li a7, 123111; ZVBB-RV32-NEXT:    mul a6, a6, a73112; ZVBB-RV32-NEXT:    add a6, sp, a63113; ZVBB-RV32-NEXT:    addi a6, a6, 643114; ZVBB-RV32-NEXT:    vl1re32.v v17, (a1)3115; ZVBB-RV32-NEXT:    vl1re32.v v10, (a4)3116; ZVBB-RV32-NEXT:    vl1re32.v v11, (a5)3117; ZVBB-RV32-NEXT:    vl1re32.v v8, (a0)3118; ZVBB-RV32-NEXT:    vl1re32.v v9, (a3)3119; ZVBB-RV32-NEXT:    slli a2, a2, 33120; ZVBB-RV32-NEXT:    add a2, a6, a23121; ZVBB-RV32-NEXT:    vs4r.v v16, (a2)3122; ZVBB-RV32-NEXT:    vs8r.v v8, (a6)3123; ZVBB-RV32-NEXT:    vl8re32.v v16, (a2)3124; ZVBB-RV32-NEXT:    vl8re32.v v8, (a6)3125; ZVBB-RV32-NEXT:    addi sp, s0, -803126; ZVBB-RV32-NEXT:    lw ra, 76(sp) # 4-byte Folded Reload3127; ZVBB-RV32-NEXT:    lw s0, 72(sp) # 4-byte Folded Reload3128; ZVBB-RV32-NEXT:    addi sp, sp, 803129; ZVBB-RV32-NEXT:    ret3130;3131; ZVBB-RV64-LABEL: vector_interleave_nxv24i32_nxv4i32:3132; ZVBB-RV64:       # %bb.0:3133; ZVBB-RV64-NEXT:    addi sp, sp, -803134; ZVBB-RV64-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill3135; ZVBB-RV64-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill3136; ZVBB-RV64-NEXT:    addi s0, sp, 803137; ZVBB-RV64-NEXT:    csrr a0, vlenb3138; ZVBB-RV64-NEXT:    li a1, 283139; ZVBB-RV64-NEXT:    mul a0, a0, a13140; ZVBB-RV64-NEXT:    sub sp, sp, a03141; ZVBB-RV64-NEXT:    andi sp, sp, -643142; ZVBB-RV64-NEXT:    vsetvli a0, zero, e32, m1, ta, ma3143; ZVBB-RV64-NEXT:    vmv2r.v v20, v143144; ZVBB-RV64-NEXT:    vmv2r.v v22, v123145; ZVBB-RV64-NEXT:    vmv2r.v v24, v103146; ZVBB-RV64-NEXT:    csrr a1, vlenb3147; ZVBB-RV64-NEXT:    li a0, 63148; ZVBB-RV64-NEXT:    mul a1, a1, a03149; ZVBB-RV64-NEXT:    add a1, sp, a13150; ZVBB-RV64-NEXT:    addi a1, a1, 643151; ZVBB-RV64-NEXT:    vmv1r.v v10, v253152; ZVBB-RV64-NEXT:    vmv1r.v v11, v233153; ZVBB-RV64-NEXT:    vmv1r.v v12, v213154; ZVBB-RV64-NEXT:    addi a0, sp, 643155; ZVBB-RV64-NEXT:    vmv1r.v v13, v173156; ZVBB-RV64-NEXT:    csrr a2, vlenb3157; ZVBB-RV64-NEXT:    vmv1r.v v14, v193158; ZVBB-RV64-NEXT:    vsseg6e32.v v9, (a1)3159; ZVBB-RV64-NEXT:    vmv1r.v v9, v243160; ZVBB-RV64-NEXT:    add a5, a1, a23161; ZVBB-RV64-NEXT:    vmv1r.v v10, v223162; ZVBB-RV64-NEXT:    add a3, a0, a23163; ZVBB-RV64-NEXT:    vmv1r.v v11, v203164; ZVBB-RV64-NEXT:    add a4, a3, a23165; ZVBB-RV64-NEXT:    vmv1r.v v12, v163166; ZVBB-RV64-NEXT:    add a6, a5, a23167; ZVBB-RV64-NEXT:    vmv1r.v v13, v183168; ZVBB-RV64-NEXT:    vsseg6e32.v v8, (a0)3169; ZVBB-RV64-NEXT:    vl1re32.v v14, (a1)3170; ZVBB-RV64-NEXT:    add a1, a6, a23171; ZVBB-RV64-NEXT:    vl1re32.v v15, (a5)3172; ZVBB-RV64-NEXT:    add a5, a1, a23173; ZVBB-RV64-NEXT:    vl1re32.v v18, (a5)3174; ZVBB-RV64-NEXT:    add a5, a5, a23175; ZVBB-RV64-NEXT:    vl1re32.v v19, (a5)3176; ZVBB-RV64-NEXT:    add a5, a4, a23177; ZVBB-RV64-NEXT:    vl1re32.v v16, (a6)3178; ZVBB-RV64-NEXT:    add a6, a5, a23179; ZVBB-RV64-NEXT:    vl1re32.v v12, (a6)3180; ZVBB-RV64-NEXT:    add a6, a6, a23181; ZVBB-RV64-NEXT:    vl1re32.v v13, (a6)3182; ZVBB-RV64-NEXT:    csrr a6, vlenb3183; ZVBB-RV64-NEXT:    li a7, 123184; ZVBB-RV64-NEXT:    mul a6, a6, a73185; ZVBB-RV64-NEXT:    add a6, sp, a63186; ZVBB-RV64-NEXT:    addi a6, a6, 643187; ZVBB-RV64-NEXT:    vl1re32.v v17, (a1)3188; ZVBB-RV64-NEXT:    vl1re32.v v10, (a4)3189; ZVBB-RV64-NEXT:    vl1re32.v v11, (a5)3190; ZVBB-RV64-NEXT:    vl1re32.v v8, (a0)3191; ZVBB-RV64-NEXT:    vl1re32.v v9, (a3)3192; ZVBB-RV64-NEXT:    slli a2, a2, 33193; ZVBB-RV64-NEXT:    add a2, a6, a23194; ZVBB-RV64-NEXT:    vs4r.v v16, (a2)3195; ZVBB-RV64-NEXT:    vs8r.v v8, (a6)3196; ZVBB-RV64-NEXT:    vl8re32.v v16, (a2)3197; ZVBB-RV64-NEXT:    vl8re32.v v8, (a6)3198; ZVBB-RV64-NEXT:    addi sp, s0, -803199; ZVBB-RV64-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload3200; ZVBB-RV64-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload3201; ZVBB-RV64-NEXT:    addi sp, sp, 803202; ZVBB-RV64-NEXT:    ret3203;3204; ZIP-LABEL: vector_interleave_nxv24i32_nxv4i32:3205; ZIP:       # %bb.0:3206; ZIP-NEXT:    addi sp, sp, -803207; ZIP-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill3208; ZIP-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill3209; ZIP-NEXT:    addi s0, sp, 803210; ZIP-NEXT:    csrr a0, vlenb3211; ZIP-NEXT:    li a1, 283212; ZIP-NEXT:    mul a0, a0, a13213; ZIP-NEXT:    sub sp, sp, a03214; ZIP-NEXT:    andi sp, sp, -643215; ZIP-NEXT:    vsetvli a0, zero, e32, m1, ta, ma3216; ZIP-NEXT:    vmv2r.v v20, v143217; ZIP-NEXT:    vmv2r.v v22, v123218; ZIP-NEXT:    vmv2r.v v24, v103219; ZIP-NEXT:    csrr a1, vlenb3220; ZIP-NEXT:    li a0, 63221; ZIP-NEXT:    mul a1, a1, a03222; ZIP-NEXT:    add a1, sp, a13223; ZIP-NEXT:    addi a1, a1, 643224; ZIP-NEXT:    vmv1r.v v10, v253225; ZIP-NEXT:    vmv1r.v v11, v233226; ZIP-NEXT:    vmv1r.v v12, v213227; ZIP-NEXT:    addi a0, sp, 643228; ZIP-NEXT:    vmv1r.v v13, v173229; ZIP-NEXT:    csrr a2, vlenb3230; ZIP-NEXT:    vmv1r.v v14, v193231; ZIP-NEXT:    vsseg6e32.v v9, (a1)3232; ZIP-NEXT:    vmv1r.v v9, v243233; ZIP-NEXT:    add a5, a1, a23234; ZIP-NEXT:    vmv1r.v v10, v223235; ZIP-NEXT:    add a3, a0, a23236; ZIP-NEXT:    vmv1r.v v11, v203237; ZIP-NEXT:    add a4, a3, a23238; ZIP-NEXT:    vmv1r.v v12, v163239; ZIP-NEXT:    add a6, a5, a23240; ZIP-NEXT:    vmv1r.v v13, v183241; ZIP-NEXT:    vsseg6e32.v v8, (a0)3242; ZIP-NEXT:    vl1re32.v v14, (a1)3243; ZIP-NEXT:    add a1, a6, a23244; ZIP-NEXT:    vl1re32.v v15, (a5)3245; ZIP-NEXT:    add a5, a1, a23246; ZIP-NEXT:    vl1re32.v v18, (a5)3247; ZIP-NEXT:    add a5, a5, a23248; ZIP-NEXT:    vl1re32.v v19, (a5)3249; ZIP-NEXT:    add a5, a4, a23250; ZIP-NEXT:    vl1re32.v v16, (a6)3251; ZIP-NEXT:    add a6, a5, a23252; ZIP-NEXT:    vl1re32.v v12, (a6)3253; ZIP-NEXT:    add a6, a6, a23254; ZIP-NEXT:    vl1re32.v v13, (a6)3255; ZIP-NEXT:    csrr a6, vlenb3256; ZIP-NEXT:    li a7, 123257; ZIP-NEXT:    mul a6, a6, a73258; ZIP-NEXT:    add a6, sp, a63259; ZIP-NEXT:    addi a6, a6, 643260; ZIP-NEXT:    vl1re32.v v17, (a1)3261; ZIP-NEXT:    vl1re32.v v10, (a4)3262; ZIP-NEXT:    vl1re32.v v11, (a5)3263; ZIP-NEXT:    vl1re32.v v8, (a0)3264; ZIP-NEXT:    vl1re32.v v9, (a3)3265; ZIP-NEXT:    slli a2, a2, 33266; ZIP-NEXT:    add a2, a6, a23267; ZIP-NEXT:    vs4r.v v16, (a2)3268; ZIP-NEXT:    vs8r.v v8, (a6)3269; ZIP-NEXT:    vl8re32.v v16, (a2)3270; ZIP-NEXT:    vl8re32.v v8, (a6)3271; ZIP-NEXT:    addi sp, s0, -803272; ZIP-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload3273; ZIP-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload3274; ZIP-NEXT:    addi sp, sp, 803275; ZIP-NEXT:    ret3276  %res = call <vscale x 24 x i32> @llvm.vector.interleave6.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c, <vscale x 4 x i32> %d, <vscale x 4 x i32> %e, <vscale x 4 x i32> %f)3277  ret <vscale x 24 x i32> %res3278}3279 3280define <vscale x 12 x i64> @vector_interleave_nxv12i64_nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c, <vscale x 2 x i64> %d, <vscale x 2 x i64> %e, <vscale x 2 x i64> %f) nounwind {3281;3282; RV32-LABEL: vector_interleave_nxv12i64_nxv2i64:3283; RV32:       # %bb.0:3284; RV32-NEXT:    addi sp, sp, -803285; RV32-NEXT:    sw ra, 76(sp) # 4-byte Folded Spill3286; RV32-NEXT:    sw s0, 72(sp) # 4-byte Folded Spill3287; RV32-NEXT:    addi s0, sp, 803288; RV32-NEXT:    csrr a0, vlenb3289; RV32-NEXT:    li a1, 283290; RV32-NEXT:    mul a0, a0, a13291; RV32-NEXT:    sub sp, sp, a03292; RV32-NEXT:    andi sp, sp, -643293; RV32-NEXT:    vsetvli a0, zero, e64, m1, ta, ma3294; RV32-NEXT:    vmv2r.v v20, v143295; RV32-NEXT:    vmv2r.v v22, v123296; RV32-NEXT:    vmv2r.v v24, v103297; RV32-NEXT:    csrr a1, vlenb3298; RV32-NEXT:    li a0, 63299; RV32-NEXT:    mul a1, a1, a03300; RV32-NEXT:    add a1, sp, a13301; RV32-NEXT:    addi a1, a1, 643302; RV32-NEXT:    vmv1r.v v10, v253303; RV32-NEXT:    vmv1r.v v11, v233304; RV32-NEXT:    vmv1r.v v12, v213305; RV32-NEXT:    addi a0, sp, 643306; RV32-NEXT:    vmv1r.v v13, v173307; RV32-NEXT:    csrr a2, vlenb3308; RV32-NEXT:    vmv1r.v v14, v193309; RV32-NEXT:    vsseg6e64.v v9, (a1)3310; RV32-NEXT:    vmv1r.v v9, v243311; RV32-NEXT:    add a5, a1, a23312; RV32-NEXT:    vmv1r.v v10, v223313; RV32-NEXT:    add a3, a0, a23314; RV32-NEXT:    vmv1r.v v11, v203315; RV32-NEXT:    add a4, a3, a23316; RV32-NEXT:    vmv1r.v v12, v163317; RV32-NEXT:    add a6, a5, a23318; RV32-NEXT:    vmv1r.v v13, v183319; RV32-NEXT:    vsseg6e64.v v8, (a0)3320; RV32-NEXT:    vl1re64.v v14, (a1)3321; RV32-NEXT:    add a1, a6, a23322; RV32-NEXT:    vl1re64.v v15, (a5)3323; RV32-NEXT:    add a5, a1, a23324; RV32-NEXT:    vl1re64.v v18, (a5)3325; RV32-NEXT:    add a5, a5, a23326; RV32-NEXT:    vl1re64.v v19, (a5)3327; RV32-NEXT:    add a5, a4, a23328; RV32-NEXT:    vl1re64.v v16, (a6)3329; RV32-NEXT:    add a6, a5, a23330; RV32-NEXT:    vl1re64.v v12, (a6)3331; RV32-NEXT:    add a6, a6, a23332; RV32-NEXT:    vl1re64.v v13, (a6)3333; RV32-NEXT:    csrr a6, vlenb3334; RV32-NEXT:    li a7, 123335; RV32-NEXT:    mul a6, a6, a73336; RV32-NEXT:    add a6, sp, a63337; RV32-NEXT:    addi a6, a6, 643338; RV32-NEXT:    vl1re64.v v17, (a1)3339; RV32-NEXT:    vl1re64.v v10, (a4)3340; RV32-NEXT:    vl1re64.v v11, (a5)3341; RV32-NEXT:    vl1re64.v v8, (a0)3342; RV32-NEXT:    vl1re64.v v9, (a3)3343; RV32-NEXT:    slli a2, a2, 33344; RV32-NEXT:    add a2, a6, a23345; RV32-NEXT:    vs4r.v v16, (a2)3346; RV32-NEXT:    vs8r.v v8, (a6)3347; RV32-NEXT:    vl8re64.v v16, (a2)3348; RV32-NEXT:    vl8re64.v v8, (a6)3349; RV32-NEXT:    addi sp, s0, -803350; RV32-NEXT:    lw ra, 76(sp) # 4-byte Folded Reload3351; RV32-NEXT:    lw s0, 72(sp) # 4-byte Folded Reload3352; RV32-NEXT:    addi sp, sp, 803353; RV32-NEXT:    ret3354;3355; RV64-LABEL: vector_interleave_nxv12i64_nxv2i64:3356; RV64:       # %bb.0:3357; RV64-NEXT:    addi sp, sp, -803358; RV64-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill3359; RV64-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill3360; RV64-NEXT:    addi s0, sp, 803361; RV64-NEXT:    csrr a0, vlenb3362; RV64-NEXT:    li a1, 283363; RV64-NEXT:    mul a0, a0, a13364; RV64-NEXT:    sub sp, sp, a03365; RV64-NEXT:    andi sp, sp, -643366; RV64-NEXT:    vsetvli a0, zero, e64, m1, ta, ma3367; RV64-NEXT:    vmv2r.v v20, v143368; RV64-NEXT:    vmv2r.v v22, v123369; RV64-NEXT:    vmv2r.v v24, v103370; RV64-NEXT:    csrr a1, vlenb3371; RV64-NEXT:    li a0, 63372; RV64-NEXT:    mul a1, a1, a03373; RV64-NEXT:    add a1, sp, a13374; RV64-NEXT:    addi a1, a1, 643375; RV64-NEXT:    vmv1r.v v10, v253376; RV64-NEXT:    vmv1r.v v11, v233377; RV64-NEXT:    vmv1r.v v12, v213378; RV64-NEXT:    addi a0, sp, 643379; RV64-NEXT:    vmv1r.v v13, v173380; RV64-NEXT:    csrr a2, vlenb3381; RV64-NEXT:    vmv1r.v v14, v193382; RV64-NEXT:    vsseg6e64.v v9, (a1)3383; RV64-NEXT:    vmv1r.v v9, v243384; RV64-NEXT:    add a5, a1, a23385; RV64-NEXT:    vmv1r.v v10, v223386; RV64-NEXT:    add a3, a0, a23387; RV64-NEXT:    vmv1r.v v11, v203388; RV64-NEXT:    add a4, a3, a23389; RV64-NEXT:    vmv1r.v v12, v163390; RV64-NEXT:    add a6, a5, a23391; RV64-NEXT:    vmv1r.v v13, v183392; RV64-NEXT:    vsseg6e64.v v8, (a0)3393; RV64-NEXT:    vl1re64.v v14, (a1)3394; RV64-NEXT:    add a1, a6, a23395; RV64-NEXT:    vl1re64.v v15, (a5)3396; RV64-NEXT:    add a5, a1, a23397; RV64-NEXT:    vl1re64.v v18, (a5)3398; RV64-NEXT:    add a5, a5, a23399; RV64-NEXT:    vl1re64.v v19, (a5)3400; RV64-NEXT:    add a5, a4, a23401; RV64-NEXT:    vl1re64.v v16, (a6)3402; RV64-NEXT:    add a6, a5, a23403; RV64-NEXT:    vl1re64.v v12, (a6)3404; RV64-NEXT:    add a6, a6, a23405; RV64-NEXT:    vl1re64.v v13, (a6)3406; RV64-NEXT:    csrr a6, vlenb3407; RV64-NEXT:    li a7, 123408; RV64-NEXT:    mul a6, a6, a73409; RV64-NEXT:    add a6, sp, a63410; RV64-NEXT:    addi a6, a6, 643411; RV64-NEXT:    vl1re64.v v17, (a1)3412; RV64-NEXT:    vl1re64.v v10, (a4)3413; RV64-NEXT:    vl1re64.v v11, (a5)3414; RV64-NEXT:    vl1re64.v v8, (a0)3415; RV64-NEXT:    vl1re64.v v9, (a3)3416; RV64-NEXT:    slli a2, a2, 33417; RV64-NEXT:    add a2, a6, a23418; RV64-NEXT:    vs4r.v v16, (a2)3419; RV64-NEXT:    vs8r.v v8, (a6)3420; RV64-NEXT:    vl8re64.v v16, (a2)3421; RV64-NEXT:    vl8re64.v v8, (a6)3422; RV64-NEXT:    addi sp, s0, -803423; RV64-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload3424; RV64-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload3425; RV64-NEXT:    addi sp, sp, 803426; RV64-NEXT:    ret3427;3428; ZVBB-RV32-LABEL: vector_interleave_nxv12i64_nxv2i64:3429; ZVBB-RV32:       # %bb.0:3430; ZVBB-RV32-NEXT:    addi sp, sp, -803431; ZVBB-RV32-NEXT:    sw ra, 76(sp) # 4-byte Folded Spill3432; ZVBB-RV32-NEXT:    sw s0, 72(sp) # 4-byte Folded Spill3433; ZVBB-RV32-NEXT:    addi s0, sp, 803434; ZVBB-RV32-NEXT:    csrr a0, vlenb3435; ZVBB-RV32-NEXT:    li a1, 283436; ZVBB-RV32-NEXT:    mul a0, a0, a13437; ZVBB-RV32-NEXT:    sub sp, sp, a03438; ZVBB-RV32-NEXT:    andi sp, sp, -643439; ZVBB-RV32-NEXT:    vsetvli a0, zero, e64, m1, ta, ma3440; ZVBB-RV32-NEXT:    vmv2r.v v20, v143441; ZVBB-RV32-NEXT:    vmv2r.v v22, v123442; ZVBB-RV32-NEXT:    vmv2r.v v24, v103443; ZVBB-RV32-NEXT:    csrr a1, vlenb3444; ZVBB-RV32-NEXT:    li a0, 63445; ZVBB-RV32-NEXT:    mul a1, a1, a03446; ZVBB-RV32-NEXT:    add a1, sp, a13447; ZVBB-RV32-NEXT:    addi a1, a1, 643448; ZVBB-RV32-NEXT:    vmv1r.v v10, v253449; ZVBB-RV32-NEXT:    vmv1r.v v11, v233450; ZVBB-RV32-NEXT:    vmv1r.v v12, v213451; ZVBB-RV32-NEXT:    addi a0, sp, 643452; ZVBB-RV32-NEXT:    vmv1r.v v13, v173453; ZVBB-RV32-NEXT:    csrr a2, vlenb3454; ZVBB-RV32-NEXT:    vmv1r.v v14, v193455; ZVBB-RV32-NEXT:    vsseg6e64.v v9, (a1)3456; ZVBB-RV32-NEXT:    vmv1r.v v9, v243457; ZVBB-RV32-NEXT:    add a5, a1, a23458; ZVBB-RV32-NEXT:    vmv1r.v v10, v223459; ZVBB-RV32-NEXT:    add a3, a0, a23460; ZVBB-RV32-NEXT:    vmv1r.v v11, v203461; ZVBB-RV32-NEXT:    add a4, a3, a23462; ZVBB-RV32-NEXT:    vmv1r.v v12, v163463; ZVBB-RV32-NEXT:    add a6, a5, a23464; ZVBB-RV32-NEXT:    vmv1r.v v13, v183465; ZVBB-RV32-NEXT:    vsseg6e64.v v8, (a0)3466; ZVBB-RV32-NEXT:    vl1re64.v v14, (a1)3467; ZVBB-RV32-NEXT:    add a1, a6, a23468; ZVBB-RV32-NEXT:    vl1re64.v v15, (a5)3469; ZVBB-RV32-NEXT:    add a5, a1, a23470; ZVBB-RV32-NEXT:    vl1re64.v v18, (a5)3471; ZVBB-RV32-NEXT:    add a5, a5, a23472; ZVBB-RV32-NEXT:    vl1re64.v v19, (a5)3473; ZVBB-RV32-NEXT:    add a5, a4, a23474; ZVBB-RV32-NEXT:    vl1re64.v v16, (a6)3475; ZVBB-RV32-NEXT:    add a6, a5, a23476; ZVBB-RV32-NEXT:    vl1re64.v v12, (a6)3477; ZVBB-RV32-NEXT:    add a6, a6, a23478; ZVBB-RV32-NEXT:    vl1re64.v v13, (a6)3479; ZVBB-RV32-NEXT:    csrr a6, vlenb3480; ZVBB-RV32-NEXT:    li a7, 123481; ZVBB-RV32-NEXT:    mul a6, a6, a73482; ZVBB-RV32-NEXT:    add a6, sp, a63483; ZVBB-RV32-NEXT:    addi a6, a6, 643484; ZVBB-RV32-NEXT:    vl1re64.v v17, (a1)3485; ZVBB-RV32-NEXT:    vl1re64.v v10, (a4)3486; ZVBB-RV32-NEXT:    vl1re64.v v11, (a5)3487; ZVBB-RV32-NEXT:    vl1re64.v v8, (a0)3488; ZVBB-RV32-NEXT:    vl1re64.v v9, (a3)3489; ZVBB-RV32-NEXT:    slli a2, a2, 33490; ZVBB-RV32-NEXT:    add a2, a6, a23491; ZVBB-RV32-NEXT:    vs4r.v v16, (a2)3492; ZVBB-RV32-NEXT:    vs8r.v v8, (a6)3493; ZVBB-RV32-NEXT:    vl8re64.v v16, (a2)3494; ZVBB-RV32-NEXT:    vl8re64.v v8, (a6)3495; ZVBB-RV32-NEXT:    addi sp, s0, -803496; ZVBB-RV32-NEXT:    lw ra, 76(sp) # 4-byte Folded Reload3497; ZVBB-RV32-NEXT:    lw s0, 72(sp) # 4-byte Folded Reload3498; ZVBB-RV32-NEXT:    addi sp, sp, 803499; ZVBB-RV32-NEXT:    ret3500;3501; ZVBB-RV64-LABEL: vector_interleave_nxv12i64_nxv2i64:3502; ZVBB-RV64:       # %bb.0:3503; ZVBB-RV64-NEXT:    addi sp, sp, -803504; ZVBB-RV64-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill3505; ZVBB-RV64-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill3506; ZVBB-RV64-NEXT:    addi s0, sp, 803507; ZVBB-RV64-NEXT:    csrr a0, vlenb3508; ZVBB-RV64-NEXT:    li a1, 283509; ZVBB-RV64-NEXT:    mul a0, a0, a13510; ZVBB-RV64-NEXT:    sub sp, sp, a03511; ZVBB-RV64-NEXT:    andi sp, sp, -643512; ZVBB-RV64-NEXT:    vsetvli a0, zero, e64, m1, ta, ma3513; ZVBB-RV64-NEXT:    vmv2r.v v20, v143514; ZVBB-RV64-NEXT:    vmv2r.v v22, v123515; ZVBB-RV64-NEXT:    vmv2r.v v24, v103516; ZVBB-RV64-NEXT:    csrr a1, vlenb3517; ZVBB-RV64-NEXT:    li a0, 63518; ZVBB-RV64-NEXT:    mul a1, a1, a03519; ZVBB-RV64-NEXT:    add a1, sp, a13520; ZVBB-RV64-NEXT:    addi a1, a1, 643521; ZVBB-RV64-NEXT:    vmv1r.v v10, v253522; ZVBB-RV64-NEXT:    vmv1r.v v11, v233523; ZVBB-RV64-NEXT:    vmv1r.v v12, v213524; ZVBB-RV64-NEXT:    addi a0, sp, 643525; ZVBB-RV64-NEXT:    vmv1r.v v13, v173526; ZVBB-RV64-NEXT:    csrr a2, vlenb3527; ZVBB-RV64-NEXT:    vmv1r.v v14, v193528; ZVBB-RV64-NEXT:    vsseg6e64.v v9, (a1)3529; ZVBB-RV64-NEXT:    vmv1r.v v9, v243530; ZVBB-RV64-NEXT:    add a5, a1, a23531; ZVBB-RV64-NEXT:    vmv1r.v v10, v223532; ZVBB-RV64-NEXT:    add a3, a0, a23533; ZVBB-RV64-NEXT:    vmv1r.v v11, v203534; ZVBB-RV64-NEXT:    add a4, a3, a23535; ZVBB-RV64-NEXT:    vmv1r.v v12, v163536; ZVBB-RV64-NEXT:    add a6, a5, a23537; ZVBB-RV64-NEXT:    vmv1r.v v13, v183538; ZVBB-RV64-NEXT:    vsseg6e64.v v8, (a0)3539; ZVBB-RV64-NEXT:    vl1re64.v v14, (a1)3540; ZVBB-RV64-NEXT:    add a1, a6, a23541; ZVBB-RV64-NEXT:    vl1re64.v v15, (a5)3542; ZVBB-RV64-NEXT:    add a5, a1, a23543; ZVBB-RV64-NEXT:    vl1re64.v v18, (a5)3544; ZVBB-RV64-NEXT:    add a5, a5, a23545; ZVBB-RV64-NEXT:    vl1re64.v v19, (a5)3546; ZVBB-RV64-NEXT:    add a5, a4, a23547; ZVBB-RV64-NEXT:    vl1re64.v v16, (a6)3548; ZVBB-RV64-NEXT:    add a6, a5, a23549; ZVBB-RV64-NEXT:    vl1re64.v v12, (a6)3550; ZVBB-RV64-NEXT:    add a6, a6, a23551; ZVBB-RV64-NEXT:    vl1re64.v v13, (a6)3552; ZVBB-RV64-NEXT:    csrr a6, vlenb3553; ZVBB-RV64-NEXT:    li a7, 123554; ZVBB-RV64-NEXT:    mul a6, a6, a73555; ZVBB-RV64-NEXT:    add a6, sp, a63556; ZVBB-RV64-NEXT:    addi a6, a6, 643557; ZVBB-RV64-NEXT:    vl1re64.v v17, (a1)3558; ZVBB-RV64-NEXT:    vl1re64.v v10, (a4)3559; ZVBB-RV64-NEXT:    vl1re64.v v11, (a5)3560; ZVBB-RV64-NEXT:    vl1re64.v v8, (a0)3561; ZVBB-RV64-NEXT:    vl1re64.v v9, (a3)3562; ZVBB-RV64-NEXT:    slli a2, a2, 33563; ZVBB-RV64-NEXT:    add a2, a6, a23564; ZVBB-RV64-NEXT:    vs4r.v v16, (a2)3565; ZVBB-RV64-NEXT:    vs8r.v v8, (a6)3566; ZVBB-RV64-NEXT:    vl8re64.v v16, (a2)3567; ZVBB-RV64-NEXT:    vl8re64.v v8, (a6)3568; ZVBB-RV64-NEXT:    addi sp, s0, -803569; ZVBB-RV64-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload3570; ZVBB-RV64-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload3571; ZVBB-RV64-NEXT:    addi sp, sp, 803572; ZVBB-RV64-NEXT:    ret3573;3574; ZIP-LABEL: vector_interleave_nxv12i64_nxv2i64:3575; ZIP:       # %bb.0:3576; ZIP-NEXT:    addi sp, sp, -803577; ZIP-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill3578; ZIP-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill3579; ZIP-NEXT:    addi s0, sp, 803580; ZIP-NEXT:    csrr a0, vlenb3581; ZIP-NEXT:    li a1, 283582; ZIP-NEXT:    mul a0, a0, a13583; ZIP-NEXT:    sub sp, sp, a03584; ZIP-NEXT:    andi sp, sp, -643585; ZIP-NEXT:    vsetvli a0, zero, e64, m1, ta, ma3586; ZIP-NEXT:    vmv2r.v v20, v143587; ZIP-NEXT:    vmv2r.v v22, v123588; ZIP-NEXT:    vmv2r.v v24, v103589; ZIP-NEXT:    csrr a1, vlenb3590; ZIP-NEXT:    li a0, 63591; ZIP-NEXT:    mul a1, a1, a03592; ZIP-NEXT:    add a1, sp, a13593; ZIP-NEXT:    addi a1, a1, 643594; ZIP-NEXT:    vmv1r.v v10, v253595; ZIP-NEXT:    vmv1r.v v11, v233596; ZIP-NEXT:    vmv1r.v v12, v213597; ZIP-NEXT:    addi a0, sp, 643598; ZIP-NEXT:    vmv1r.v v13, v173599; ZIP-NEXT:    csrr a2, vlenb3600; ZIP-NEXT:    vmv1r.v v14, v193601; ZIP-NEXT:    vsseg6e64.v v9, (a1)3602; ZIP-NEXT:    vmv1r.v v9, v243603; ZIP-NEXT:    add a5, a1, a23604; ZIP-NEXT:    vmv1r.v v10, v223605; ZIP-NEXT:    add a3, a0, a23606; ZIP-NEXT:    vmv1r.v v11, v203607; ZIP-NEXT:    add a4, a3, a23608; ZIP-NEXT:    vmv1r.v v12, v163609; ZIP-NEXT:    add a6, a5, a23610; ZIP-NEXT:    vmv1r.v v13, v183611; ZIP-NEXT:    vsseg6e64.v v8, (a0)3612; ZIP-NEXT:    vl1re64.v v14, (a1)3613; ZIP-NEXT:    add a1, a6, a23614; ZIP-NEXT:    vl1re64.v v15, (a5)3615; ZIP-NEXT:    add a5, a1, a23616; ZIP-NEXT:    vl1re64.v v18, (a5)3617; ZIP-NEXT:    add a5, a5, a23618; ZIP-NEXT:    vl1re64.v v19, (a5)3619; ZIP-NEXT:    add a5, a4, a23620; ZIP-NEXT:    vl1re64.v v16, (a6)3621; ZIP-NEXT:    add a6, a5, a23622; ZIP-NEXT:    vl1re64.v v12, (a6)3623; ZIP-NEXT:    add a6, a6, a23624; ZIP-NEXT:    vl1re64.v v13, (a6)3625; ZIP-NEXT:    csrr a6, vlenb3626; ZIP-NEXT:    li a7, 123627; ZIP-NEXT:    mul a6, a6, a73628; ZIP-NEXT:    add a6, sp, a63629; ZIP-NEXT:    addi a6, a6, 643630; ZIP-NEXT:    vl1re64.v v17, (a1)3631; ZIP-NEXT:    vl1re64.v v10, (a4)3632; ZIP-NEXT:    vl1re64.v v11, (a5)3633; ZIP-NEXT:    vl1re64.v v8, (a0)3634; ZIP-NEXT:    vl1re64.v v9, (a3)3635; ZIP-NEXT:    slli a2, a2, 33636; ZIP-NEXT:    add a2, a6, a23637; ZIP-NEXT:    vs4r.v v16, (a2)3638; ZIP-NEXT:    vs8r.v v8, (a6)3639; ZIP-NEXT:    vl8re64.v v16, (a2)3640; ZIP-NEXT:    vl8re64.v v8, (a6)3641; ZIP-NEXT:    addi sp, s0, -803642; ZIP-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload3643; ZIP-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload3644; ZIP-NEXT:    addi sp, sp, 803645; ZIP-NEXT:    ret3646  %res = call <vscale x 12 x i64> @llvm.vector.interleave6.nxv12i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c, <vscale x 2 x i64> %d, <vscale x 2 x i64> %e, <vscale x 2 x i64> %f)3647  ret <vscale x 12 x i64> %res3648}3649 3650define <vscale x 112 x i1> @vector_interleave_nxv112i1_nxv16i1(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b, <vscale x 16 x i1> %c, <vscale x 16 x i1> %d, <vscale x 16 x i1> %e, <vscale x 16 x i1> %f, <vscale x 16 x i1> %g) nounwind {3651; CHECK-LABEL: vector_interleave_nxv112i1_nxv16i1:3652; CHECK:       # %bb.0:3653; CHECK-NEXT:    addi sp, sp, -163654; CHECK-NEXT:    csrr a0, vlenb3655; CHECK-NEXT:    li a1, 143656; CHECK-NEXT:    mul a0, a0, a13657; CHECK-NEXT:    sub sp, sp, a03658; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, ma3659; CHECK-NEXT:    vmv.v.i v14, 03660; CHECK-NEXT:    addi a3, sp, 163661; CHECK-NEXT:    csrr a0, vlenb3662; CHECK-NEXT:    slli a1, a0, 33663; CHECK-NEXT:    sub a0, a1, a03664; CHECK-NEXT:    add a0, sp, a03665; CHECK-NEXT:    addi a0, a0, 163666; CHECK-NEXT:    csrr a1, vlenb3667; CHECK-NEXT:    vmerge.vim v16, v14, 1, v03668; CHECK-NEXT:    vmv1r.v v0, v83669; CHECK-NEXT:    vmerge.vim v22, v14, 1, v03670; CHECK-NEXT:    add a2, a3, a13671; CHECK-NEXT:    vmv4r.v v24, v163672; CHECK-NEXT:    vmv1r.v v0, v93673; CHECK-NEXT:    vmerge.vim v18, v14, 1, v03674; CHECK-NEXT:    add a4, a2, a13675; CHECK-NEXT:    vmv1r.v v25, v223676; CHECK-NEXT:    vmv1r.v v0, v103677; CHECK-NEXT:    vmerge.vim v8, v14, 1, v03678; CHECK-NEXT:    vmv1r.v v26, v183679; CHECK-NEXT:    vmv1r.v v0, v113680; CHECK-NEXT:    vmerge.vim v20, v14, 1, v03681; CHECK-NEXT:    vmv1r.v v27, v83682; CHECK-NEXT:    vmv1r.v v0, v123683; CHECK-NEXT:    vmerge.vim v10, v14, 1, v03684; CHECK-NEXT:    vmv1r.v v28, v203685; CHECK-NEXT:    vmv1r.v v18, v233686; CHECK-NEXT:    add a5, a4, a13687; CHECK-NEXT:    vmv1r.v v29, v103688; CHECK-NEXT:    vmv1r.v v20, v93689; CHECK-NEXT:    vmv1r.v v0, v133690; CHECK-NEXT:    vmerge.vim v30, v14, 1, v03691; CHECK-NEXT:    vmv1r.v v22, v113692; CHECK-NEXT:    vsetvli a6, zero, e8, m1, ta, ma3693; CHECK-NEXT:    vsseg7e8.v v24, (a3)3694; CHECK-NEXT:    vmv1r.v v23, v313695; CHECK-NEXT:    vsseg7e8.v v17, (a0)3696; CHECK-NEXT:    vl1r.v v8, (a4)3697; CHECK-NEXT:    add a4, a5, a13698; CHECK-NEXT:    vl1r.v v10, (a3)3699; CHECK-NEXT:    add a6, a4, a13700; CHECK-NEXT:    vl1r.v v12, (a4)3701; CHECK-NEXT:    add a3, a6, a13702; CHECK-NEXT:    vl1r.v v14, (a3)3703; CHECK-NEXT:    srli a3, a1, 13704; CHECK-NEXT:    vl1r.v v9, (a5)3705; CHECK-NEXT:    add a4, a0, a13706; CHECK-NEXT:    vl1r.v v16, (a4)3707; CHECK-NEXT:    add a4, a4, a13708; CHECK-NEXT:    vl1r.v v11, (a2)3709; CHECK-NEXT:    add a2, a4, a13710; CHECK-NEXT:    vl1r.v v18, (a2)3711; CHECK-NEXT:    add a2, a2, a13712; CHECK-NEXT:    vl1r.v v13, (a6)3713; CHECK-NEXT:    add a5, a2, a13714; CHECK-NEXT:    vl1r.v v20, (a5)3715; CHECK-NEXT:    add a5, a5, a13716; CHECK-NEXT:    srli a1, a1, 23717; CHECK-NEXT:    vl1r.v v15, (a0)3718; CHECK-NEXT:    vl1r.v v19, (a2)3719; CHECK-NEXT:    vl1r.v v17, (a4)3720; CHECK-NEXT:    vl1r.v v21, (a5)3721; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, ma3722; CHECK-NEXT:    vmsne.vi v22, v8, 03723; CHECK-NEXT:    vmsne.vi v0, v10, 03724; CHECK-NEXT:    vmsne.vi v9, v12, 03725; CHECK-NEXT:    vmsne.vi v10, v14, 03726; CHECK-NEXT:    vmsne.vi v11, v18, 03727; CHECK-NEXT:    vmsne.vi v8, v16, 03728; CHECK-NEXT:    vmsne.vi v12, v20, 03729; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma3730; CHECK-NEXT:    vslideup.vx v0, v22, a13731; CHECK-NEXT:    vslideup.vx v9, v10, a13732; CHECK-NEXT:    vslideup.vx v8, v11, a13733; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma3734; CHECK-NEXT:    vslideup.vx v0, v9, a33735; CHECK-NEXT:    vslideup.vx v8, v12, a33736; CHECK-NEXT:    csrr a0, vlenb3737; CHECK-NEXT:    li a1, 143738; CHECK-NEXT:    mul a0, a0, a13739; CHECK-NEXT:    add sp, sp, a03740; CHECK-NEXT:    addi sp, sp, 163741; CHECK-NEXT:    ret3742;3743; ZVBB-LABEL: vector_interleave_nxv112i1_nxv16i1:3744; ZVBB:       # %bb.0:3745; ZVBB-NEXT:    addi sp, sp, -163746; ZVBB-NEXT:    csrr a0, vlenb3747; ZVBB-NEXT:    li a1, 143748; ZVBB-NEXT:    mul a0, a0, a13749; ZVBB-NEXT:    sub sp, sp, a03750; ZVBB-NEXT:    vsetvli a0, zero, e8, m2, ta, ma3751; ZVBB-NEXT:    vmv.v.i v14, 03752; ZVBB-NEXT:    addi a3, sp, 163753; ZVBB-NEXT:    csrr a0, vlenb3754; ZVBB-NEXT:    slli a1, a0, 33755; ZVBB-NEXT:    sub a0, a1, a03756; ZVBB-NEXT:    add a0, sp, a03757; ZVBB-NEXT:    addi a0, a0, 163758; ZVBB-NEXT:    csrr a1, vlenb3759; ZVBB-NEXT:    vmerge.vim v16, v14, 1, v03760; ZVBB-NEXT:    vmv1r.v v0, v83761; ZVBB-NEXT:    vmerge.vim v22, v14, 1, v03762; ZVBB-NEXT:    add a2, a3, a13763; ZVBB-NEXT:    vmv4r.v v24, v163764; ZVBB-NEXT:    vmv1r.v v0, v93765; ZVBB-NEXT:    vmerge.vim v18, v14, 1, v03766; ZVBB-NEXT:    add a4, a2, a13767; ZVBB-NEXT:    vmv1r.v v25, v223768; ZVBB-NEXT:    vmv1r.v v0, v103769; ZVBB-NEXT:    vmerge.vim v8, v14, 1, v03770; ZVBB-NEXT:    vmv1r.v v26, v183771; ZVBB-NEXT:    vmv1r.v v0, v113772; ZVBB-NEXT:    vmerge.vim v20, v14, 1, v03773; ZVBB-NEXT:    vmv1r.v v27, v83774; ZVBB-NEXT:    vmv1r.v v0, v123775; ZVBB-NEXT:    vmerge.vim v10, v14, 1, v03776; ZVBB-NEXT:    vmv1r.v v28, v203777; ZVBB-NEXT:    vmv1r.v v18, v233778; ZVBB-NEXT:    add a5, a4, a13779; ZVBB-NEXT:    vmv1r.v v29, v103780; ZVBB-NEXT:    vmv1r.v v20, v93781; ZVBB-NEXT:    vmv1r.v v0, v133782; ZVBB-NEXT:    vmerge.vim v30, v14, 1, v03783; ZVBB-NEXT:    vmv1r.v v22, v113784; ZVBB-NEXT:    vsetvli a6, zero, e8, m1, ta, ma3785; ZVBB-NEXT:    vsseg7e8.v v24, (a3)3786; ZVBB-NEXT:    vmv1r.v v23, v313787; ZVBB-NEXT:    vsseg7e8.v v17, (a0)3788; ZVBB-NEXT:    vl1r.v v8, (a4)3789; ZVBB-NEXT:    add a4, a5, a13790; ZVBB-NEXT:    vl1r.v v10, (a3)3791; ZVBB-NEXT:    add a6, a4, a13792; ZVBB-NEXT:    vl1r.v v12, (a4)3793; ZVBB-NEXT:    add a3, a6, a13794; ZVBB-NEXT:    vl1r.v v14, (a3)3795; ZVBB-NEXT:    srli a3, a1, 13796; ZVBB-NEXT:    vl1r.v v9, (a5)3797; ZVBB-NEXT:    add a4, a0, a13798; ZVBB-NEXT:    vl1r.v v16, (a4)3799; ZVBB-NEXT:    add a4, a4, a13800; ZVBB-NEXT:    vl1r.v v11, (a2)3801; ZVBB-NEXT:    add a2, a4, a13802; ZVBB-NEXT:    vl1r.v v18, (a2)3803; ZVBB-NEXT:    add a2, a2, a13804; ZVBB-NEXT:    vl1r.v v13, (a6)3805; ZVBB-NEXT:    add a5, a2, a13806; ZVBB-NEXT:    vl1r.v v20, (a5)3807; ZVBB-NEXT:    add a5, a5, a13808; ZVBB-NEXT:    srli a1, a1, 23809; ZVBB-NEXT:    vl1r.v v15, (a0)3810; ZVBB-NEXT:    vl1r.v v19, (a2)3811; ZVBB-NEXT:    vl1r.v v17, (a4)3812; ZVBB-NEXT:    vl1r.v v21, (a5)3813; ZVBB-NEXT:    vsetvli a0, zero, e8, m2, ta, ma3814; ZVBB-NEXT:    vmsne.vi v22, v8, 03815; ZVBB-NEXT:    vmsne.vi v0, v10, 03816; ZVBB-NEXT:    vmsne.vi v9, v12, 03817; ZVBB-NEXT:    vmsne.vi v10, v14, 03818; ZVBB-NEXT:    vmsne.vi v11, v18, 03819; ZVBB-NEXT:    vmsne.vi v8, v16, 03820; ZVBB-NEXT:    vmsne.vi v12, v20, 03821; ZVBB-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma3822; ZVBB-NEXT:    vslideup.vx v0, v22, a13823; ZVBB-NEXT:    vslideup.vx v9, v10, a13824; ZVBB-NEXT:    vslideup.vx v8, v11, a13825; ZVBB-NEXT:    vsetvli a0, zero, e8, m1, ta, ma3826; ZVBB-NEXT:    vslideup.vx v0, v9, a33827; ZVBB-NEXT:    vslideup.vx v8, v12, a33828; ZVBB-NEXT:    csrr a0, vlenb3829; ZVBB-NEXT:    li a1, 143830; ZVBB-NEXT:    mul a0, a0, a13831; ZVBB-NEXT:    add sp, sp, a03832; ZVBB-NEXT:    addi sp, sp, 163833; ZVBB-NEXT:    ret3834  %res = call <vscale x 112 x i1> @llvm.vector.interleave7.nxv112i1(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b, <vscale x 16 x i1> %c, <vscale x 16 x i1> %d, <vscale x 16 x i1> %e, <vscale x 16 x i1> %f, <vscale x 16 x i1> %g)3835  ret <vscale x 112 x i1> %res3836}3837 3838 3839define <vscale x 112 x i8> @vector_interleave_nxv112i8_nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c, <vscale x 16 x i8> %d, <vscale x 16 x i8> %e, <vscale x 16 x i8> %f, <vscale x 16 x i8> %g) nounwind {3840;3841; RV32-LABEL: vector_interleave_nxv112i8_nxv16i8:3842; RV32:       # %bb.0:3843; RV32-NEXT:    addi sp, sp, -803844; RV32-NEXT:    sw ra, 76(sp) # 4-byte Folded Spill3845; RV32-NEXT:    sw s0, 72(sp) # 4-byte Folded Spill3846; RV32-NEXT:    addi s0, sp, 803847; RV32-NEXT:    csrr a0, vlenb3848; RV32-NEXT:    slli a0, a0, 53849; RV32-NEXT:    sub sp, sp, a03850; RV32-NEXT:    andi sp, sp, -643851; RV32-NEXT:    vsetvli a0, zero, e8, m1, ta, ma3852; RV32-NEXT:    vmv2r.v v26, v203853; RV32-NEXT:    addi a0, sp, 643854; RV32-NEXT:    vmv2r.v v24, v163855; RV32-NEXT:    vmv2r.v v22, v123856; RV32-NEXT:    vmv2r.v v20, v83857; RV32-NEXT:    vmv1r.v v1, v203858; RV32-NEXT:    vmv1r.v v3, v223859; RV32-NEXT:    vmv1r.v v5, v243860; RV32-NEXT:    vmv1r.v v7, v263861; RV32-NEXT:    vmv1r.v v2, v103862; RV32-NEXT:    csrr a1, vlenb3863; RV32-NEXT:    slli a2, a1, 33864; RV32-NEXT:    sub a1, a2, a13865; RV32-NEXT:    add a1, sp, a13866; RV32-NEXT:    addi a1, a1, 643867; RV32-NEXT:    csrr a2, vlenb3868; RV32-NEXT:    vmv1r.v v4, v143869; RV32-NEXT:    add a3, a0, a23870; RV32-NEXT:    add a4, a1, a23871; RV32-NEXT:    vmv1r.v v6, v183872; RV32-NEXT:    add a5, a4, a23873; RV32-NEXT:    vmv1r.v v22, v113874; RV32-NEXT:    add a6, a5, a23875; RV32-NEXT:    vmv1r.v v24, v153876; RV32-NEXT:    vsseg7e8.v v1, (a0)3877; RV32-NEXT:    vmv1r.v v26, v193878; RV32-NEXT:    vsseg7e8.v v21, (a1)3879; RV32-NEXT:    vl1r.v v18, (a6)3880; RV32-NEXT:    add a6, a6, a23881; RV32-NEXT:    vl1r.v v19, (a6)3882; RV32-NEXT:    add a6, a6, a23883; RV32-NEXT:    vl1r.v v20, (a6)3884; RV32-NEXT:    add a6, a6, a23885; RV32-NEXT:    vl1r.v v21, (a6)3886; RV32-NEXT:    add a6, a3, a23887; RV32-NEXT:    vl1r.v v10, (a6)3888; RV32-NEXT:    add a6, a6, a23889; RV32-NEXT:    vl1r.v v11, (a6)3890; RV32-NEXT:    vl1r.v v8, (a0)3891; RV32-NEXT:    vl1r.v v16, (a4)3892; RV32-NEXT:    vl1r.v v9, (a3)3893; RV32-NEXT:    csrr a0, vlenb3894; RV32-NEXT:    li a3, 143895; RV32-NEXT:    mul a0, a0, a33896; RV32-NEXT:    add a0, sp, a03897; RV32-NEXT:    addi a0, a0, 643898; RV32-NEXT:    vl1r.v v17, (a5)3899; RV32-NEXT:    slli a3, a2, 23900; RV32-NEXT:    add a6, a6, a23901; RV32-NEXT:    vl1r.v v12, (a6)3902; RV32-NEXT:    add a6, a6, a23903; RV32-NEXT:    vl1r.v v13, (a6)3904; RV32-NEXT:    add a6, a6, a23905; RV32-NEXT:    slli a2, a2, 33906; RV32-NEXT:    add a3, a2, a33907; RV32-NEXT:    add a2, a0, a23908; RV32-NEXT:    vl1r.v v14, (a6)3909; RV32-NEXT:    vl1r.v v15, (a1)3910; RV32-NEXT:    add a3, a0, a33911; RV32-NEXT:    vs2r.v v20, (a3)3912; RV32-NEXT:    vs4r.v v16, (a2)3913; RV32-NEXT:    vs8r.v v8, (a0)3914; RV32-NEXT:    vl8r.v v16, (a2)3915; RV32-NEXT:    vl8r.v v8, (a0)3916; RV32-NEXT:    addi sp, s0, -803917; RV32-NEXT:    lw ra, 76(sp) # 4-byte Folded Reload3918; RV32-NEXT:    lw s0, 72(sp) # 4-byte Folded Reload3919; RV32-NEXT:    addi sp, sp, 803920; RV32-NEXT:    ret3921;3922; RV64-LABEL: vector_interleave_nxv112i8_nxv16i8:3923; RV64:       # %bb.0:3924; RV64-NEXT:    addi sp, sp, -803925; RV64-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill3926; RV64-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill3927; RV64-NEXT:    addi s0, sp, 803928; RV64-NEXT:    csrr a0, vlenb3929; RV64-NEXT:    slli a0, a0, 53930; RV64-NEXT:    sub sp, sp, a03931; RV64-NEXT:    andi sp, sp, -643932; RV64-NEXT:    vsetvli a0, zero, e8, m1, ta, ma3933; RV64-NEXT:    vmv2r.v v26, v203934; RV64-NEXT:    addi a0, sp, 643935; RV64-NEXT:    vmv2r.v v24, v163936; RV64-NEXT:    vmv2r.v v22, v123937; RV64-NEXT:    vmv2r.v v20, v83938; RV64-NEXT:    vmv1r.v v1, v203939; RV64-NEXT:    vmv1r.v v3, v223940; RV64-NEXT:    vmv1r.v v5, v243941; RV64-NEXT:    vmv1r.v v7, v263942; RV64-NEXT:    vmv1r.v v2, v103943; RV64-NEXT:    csrr a1, vlenb3944; RV64-NEXT:    slli a2, a1, 33945; RV64-NEXT:    sub a1, a2, a13946; RV64-NEXT:    add a1, sp, a13947; RV64-NEXT:    addi a1, a1, 643948; RV64-NEXT:    csrr a2, vlenb3949; RV64-NEXT:    vmv1r.v v4, v143950; RV64-NEXT:    add a3, a0, a23951; RV64-NEXT:    add a4, a1, a23952; RV64-NEXT:    vmv1r.v v6, v183953; RV64-NEXT:    add a5, a4, a23954; RV64-NEXT:    vmv1r.v v22, v113955; RV64-NEXT:    add a6, a5, a23956; RV64-NEXT:    vmv1r.v v24, v153957; RV64-NEXT:    vsseg7e8.v v1, (a0)3958; RV64-NEXT:    vmv1r.v v26, v193959; RV64-NEXT:    vsseg7e8.v v21, (a1)3960; RV64-NEXT:    vl1r.v v18, (a6)3961; RV64-NEXT:    add a6, a6, a23962; RV64-NEXT:    vl1r.v v19, (a6)3963; RV64-NEXT:    add a6, a6, a23964; RV64-NEXT:    vl1r.v v20, (a6)3965; RV64-NEXT:    add a6, a6, a23966; RV64-NEXT:    vl1r.v v21, (a6)3967; RV64-NEXT:    add a6, a3, a23968; RV64-NEXT:    vl1r.v v10, (a6)3969; RV64-NEXT:    add a6, a6, a23970; RV64-NEXT:    vl1r.v v11, (a6)3971; RV64-NEXT:    vl1r.v v8, (a0)3972; RV64-NEXT:    vl1r.v v16, (a4)3973; RV64-NEXT:    vl1r.v v9, (a3)3974; RV64-NEXT:    csrr a0, vlenb3975; RV64-NEXT:    li a3, 143976; RV64-NEXT:    mul a0, a0, a33977; RV64-NEXT:    add a0, sp, a03978; RV64-NEXT:    addi a0, a0, 643979; RV64-NEXT:    vl1r.v v17, (a5)3980; RV64-NEXT:    slli a3, a2, 23981; RV64-NEXT:    add a6, a6, a23982; RV64-NEXT:    vl1r.v v12, (a6)3983; RV64-NEXT:    add a6, a6, a23984; RV64-NEXT:    vl1r.v v13, (a6)3985; RV64-NEXT:    add a6, a6, a23986; RV64-NEXT:    slli a2, a2, 33987; RV64-NEXT:    add a3, a2, a33988; RV64-NEXT:    add a2, a0, a23989; RV64-NEXT:    vl1r.v v14, (a6)3990; RV64-NEXT:    vl1r.v v15, (a1)3991; RV64-NEXT:    add a3, a0, a33992; RV64-NEXT:    vs2r.v v20, (a3)3993; RV64-NEXT:    vs4r.v v16, (a2)3994; RV64-NEXT:    vs8r.v v8, (a0)3995; RV64-NEXT:    vl8r.v v16, (a2)3996; RV64-NEXT:    vl8r.v v8, (a0)3997; RV64-NEXT:    addi sp, s0, -803998; RV64-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload3999; RV64-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload4000; RV64-NEXT:    addi sp, sp, 804001; RV64-NEXT:    ret4002;4003; ZVBB-RV32-LABEL: vector_interleave_nxv112i8_nxv16i8:4004; ZVBB-RV32:       # %bb.0:4005; ZVBB-RV32-NEXT:    addi sp, sp, -804006; ZVBB-RV32-NEXT:    sw ra, 76(sp) # 4-byte Folded Spill4007; ZVBB-RV32-NEXT:    sw s0, 72(sp) # 4-byte Folded Spill4008; ZVBB-RV32-NEXT:    addi s0, sp, 804009; ZVBB-RV32-NEXT:    csrr a0, vlenb4010; ZVBB-RV32-NEXT:    slli a0, a0, 54011; ZVBB-RV32-NEXT:    sub sp, sp, a04012; ZVBB-RV32-NEXT:    andi sp, sp, -644013; ZVBB-RV32-NEXT:    vsetvli a0, zero, e8, m1, ta, ma4014; ZVBB-RV32-NEXT:    vmv2r.v v26, v204015; ZVBB-RV32-NEXT:    addi a0, sp, 644016; ZVBB-RV32-NEXT:    vmv2r.v v24, v164017; ZVBB-RV32-NEXT:    vmv2r.v v22, v124018; ZVBB-RV32-NEXT:    vmv2r.v v20, v84019; ZVBB-RV32-NEXT:    vmv1r.v v1, v204020; ZVBB-RV32-NEXT:    vmv1r.v v3, v224021; ZVBB-RV32-NEXT:    vmv1r.v v5, v244022; ZVBB-RV32-NEXT:    vmv1r.v v7, v264023; ZVBB-RV32-NEXT:    vmv1r.v v2, v104024; ZVBB-RV32-NEXT:    csrr a1, vlenb4025; ZVBB-RV32-NEXT:    slli a2, a1, 34026; ZVBB-RV32-NEXT:    sub a1, a2, a14027; ZVBB-RV32-NEXT:    add a1, sp, a14028; ZVBB-RV32-NEXT:    addi a1, a1, 644029; ZVBB-RV32-NEXT:    csrr a2, vlenb4030; ZVBB-RV32-NEXT:    vmv1r.v v4, v144031; ZVBB-RV32-NEXT:    add a3, a0, a24032; ZVBB-RV32-NEXT:    add a4, a1, a24033; ZVBB-RV32-NEXT:    vmv1r.v v6, v184034; ZVBB-RV32-NEXT:    add a5, a4, a24035; ZVBB-RV32-NEXT:    vmv1r.v v22, v114036; ZVBB-RV32-NEXT:    add a6, a5, a24037; ZVBB-RV32-NEXT:    vmv1r.v v24, v154038; ZVBB-RV32-NEXT:    vsseg7e8.v v1, (a0)4039; ZVBB-RV32-NEXT:    vmv1r.v v26, v194040; ZVBB-RV32-NEXT:    vsseg7e8.v v21, (a1)4041; ZVBB-RV32-NEXT:    vl1r.v v18, (a6)4042; ZVBB-RV32-NEXT:    add a6, a6, a24043; ZVBB-RV32-NEXT:    vl1r.v v19, (a6)4044; ZVBB-RV32-NEXT:    add a6, a6, a24045; ZVBB-RV32-NEXT:    vl1r.v v20, (a6)4046; ZVBB-RV32-NEXT:    add a6, a6, a24047; ZVBB-RV32-NEXT:    vl1r.v v21, (a6)4048; ZVBB-RV32-NEXT:    add a6, a3, a24049; ZVBB-RV32-NEXT:    vl1r.v v10, (a6)4050; ZVBB-RV32-NEXT:    add a6, a6, a24051; ZVBB-RV32-NEXT:    vl1r.v v11, (a6)4052; ZVBB-RV32-NEXT:    vl1r.v v8, (a0)4053; ZVBB-RV32-NEXT:    vl1r.v v16, (a4)4054; ZVBB-RV32-NEXT:    vl1r.v v9, (a3)4055; ZVBB-RV32-NEXT:    csrr a0, vlenb4056; ZVBB-RV32-NEXT:    li a3, 144057; ZVBB-RV32-NEXT:    mul a0, a0, a34058; ZVBB-RV32-NEXT:    add a0, sp, a04059; ZVBB-RV32-NEXT:    addi a0, a0, 644060; ZVBB-RV32-NEXT:    vl1r.v v17, (a5)4061; ZVBB-RV32-NEXT:    slli a3, a2, 24062; ZVBB-RV32-NEXT:    add a6, a6, a24063; ZVBB-RV32-NEXT:    vl1r.v v12, (a6)4064; ZVBB-RV32-NEXT:    add a6, a6, a24065; ZVBB-RV32-NEXT:    vl1r.v v13, (a6)4066; ZVBB-RV32-NEXT:    add a6, a6, a24067; ZVBB-RV32-NEXT:    slli a2, a2, 34068; ZVBB-RV32-NEXT:    add a3, a2, a34069; ZVBB-RV32-NEXT:    add a2, a0, a24070; ZVBB-RV32-NEXT:    vl1r.v v14, (a6)4071; ZVBB-RV32-NEXT:    vl1r.v v15, (a1)4072; ZVBB-RV32-NEXT:    add a3, a0, a34073; ZVBB-RV32-NEXT:    vs2r.v v20, (a3)4074; ZVBB-RV32-NEXT:    vs4r.v v16, (a2)4075; ZVBB-RV32-NEXT:    vs8r.v v8, (a0)4076; ZVBB-RV32-NEXT:    vl8r.v v16, (a2)4077; ZVBB-RV32-NEXT:    vl8r.v v8, (a0)4078; ZVBB-RV32-NEXT:    addi sp, s0, -804079; ZVBB-RV32-NEXT:    lw ra, 76(sp) # 4-byte Folded Reload4080; ZVBB-RV32-NEXT:    lw s0, 72(sp) # 4-byte Folded Reload4081; ZVBB-RV32-NEXT:    addi sp, sp, 804082; ZVBB-RV32-NEXT:    ret4083;4084; ZVBB-RV64-LABEL: vector_interleave_nxv112i8_nxv16i8:4085; ZVBB-RV64:       # %bb.0:4086; ZVBB-RV64-NEXT:    addi sp, sp, -804087; ZVBB-RV64-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill4088; ZVBB-RV64-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill4089; ZVBB-RV64-NEXT:    addi s0, sp, 804090; ZVBB-RV64-NEXT:    csrr a0, vlenb4091; ZVBB-RV64-NEXT:    slli a0, a0, 54092; ZVBB-RV64-NEXT:    sub sp, sp, a04093; ZVBB-RV64-NEXT:    andi sp, sp, -644094; ZVBB-RV64-NEXT:    vsetvli a0, zero, e8, m1, ta, ma4095; ZVBB-RV64-NEXT:    vmv2r.v v26, v204096; ZVBB-RV64-NEXT:    addi a0, sp, 644097; ZVBB-RV64-NEXT:    vmv2r.v v24, v164098; ZVBB-RV64-NEXT:    vmv2r.v v22, v124099; ZVBB-RV64-NEXT:    vmv2r.v v20, v84100; ZVBB-RV64-NEXT:    vmv1r.v v1, v204101; ZVBB-RV64-NEXT:    vmv1r.v v3, v224102; ZVBB-RV64-NEXT:    vmv1r.v v5, v244103; ZVBB-RV64-NEXT:    vmv1r.v v7, v264104; ZVBB-RV64-NEXT:    vmv1r.v v2, v104105; ZVBB-RV64-NEXT:    csrr a1, vlenb4106; ZVBB-RV64-NEXT:    slli a2, a1, 34107; ZVBB-RV64-NEXT:    sub a1, a2, a14108; ZVBB-RV64-NEXT:    add a1, sp, a14109; ZVBB-RV64-NEXT:    addi a1, a1, 644110; ZVBB-RV64-NEXT:    csrr a2, vlenb4111; ZVBB-RV64-NEXT:    vmv1r.v v4, v144112; ZVBB-RV64-NEXT:    add a3, a0, a24113; ZVBB-RV64-NEXT:    add a4, a1, a24114; ZVBB-RV64-NEXT:    vmv1r.v v6, v184115; ZVBB-RV64-NEXT:    add a5, a4, a24116; ZVBB-RV64-NEXT:    vmv1r.v v22, v114117; ZVBB-RV64-NEXT:    add a6, a5, a24118; ZVBB-RV64-NEXT:    vmv1r.v v24, v154119; ZVBB-RV64-NEXT:    vsseg7e8.v v1, (a0)4120; ZVBB-RV64-NEXT:    vmv1r.v v26, v194121; ZVBB-RV64-NEXT:    vsseg7e8.v v21, (a1)4122; ZVBB-RV64-NEXT:    vl1r.v v18, (a6)4123; ZVBB-RV64-NEXT:    add a6, a6, a24124; ZVBB-RV64-NEXT:    vl1r.v v19, (a6)4125; ZVBB-RV64-NEXT:    add a6, a6, a24126; ZVBB-RV64-NEXT:    vl1r.v v20, (a6)4127; ZVBB-RV64-NEXT:    add a6, a6, a24128; ZVBB-RV64-NEXT:    vl1r.v v21, (a6)4129; ZVBB-RV64-NEXT:    add a6, a3, a24130; ZVBB-RV64-NEXT:    vl1r.v v10, (a6)4131; ZVBB-RV64-NEXT:    add a6, a6, a24132; ZVBB-RV64-NEXT:    vl1r.v v11, (a6)4133; ZVBB-RV64-NEXT:    vl1r.v v8, (a0)4134; ZVBB-RV64-NEXT:    vl1r.v v16, (a4)4135; ZVBB-RV64-NEXT:    vl1r.v v9, (a3)4136; ZVBB-RV64-NEXT:    csrr a0, vlenb4137; ZVBB-RV64-NEXT:    li a3, 144138; ZVBB-RV64-NEXT:    mul a0, a0, a34139; ZVBB-RV64-NEXT:    add a0, sp, a04140; ZVBB-RV64-NEXT:    addi a0, a0, 644141; ZVBB-RV64-NEXT:    vl1r.v v17, (a5)4142; ZVBB-RV64-NEXT:    slli a3, a2, 24143; ZVBB-RV64-NEXT:    add a6, a6, a24144; ZVBB-RV64-NEXT:    vl1r.v v12, (a6)4145; ZVBB-RV64-NEXT:    add a6, a6, a24146; ZVBB-RV64-NEXT:    vl1r.v v13, (a6)4147; ZVBB-RV64-NEXT:    add a6, a6, a24148; ZVBB-RV64-NEXT:    slli a2, a2, 34149; ZVBB-RV64-NEXT:    add a3, a2, a34150; ZVBB-RV64-NEXT:    add a2, a0, a24151; ZVBB-RV64-NEXT:    vl1r.v v14, (a6)4152; ZVBB-RV64-NEXT:    vl1r.v v15, (a1)4153; ZVBB-RV64-NEXT:    add a3, a0, a34154; ZVBB-RV64-NEXT:    vs2r.v v20, (a3)4155; ZVBB-RV64-NEXT:    vs4r.v v16, (a2)4156; ZVBB-RV64-NEXT:    vs8r.v v8, (a0)4157; ZVBB-RV64-NEXT:    vl8r.v v16, (a2)4158; ZVBB-RV64-NEXT:    vl8r.v v8, (a0)4159; ZVBB-RV64-NEXT:    addi sp, s0, -804160; ZVBB-RV64-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload4161; ZVBB-RV64-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload4162; ZVBB-RV64-NEXT:    addi sp, sp, 804163; ZVBB-RV64-NEXT:    ret4164;4165; ZIP-LABEL: vector_interleave_nxv112i8_nxv16i8:4166; ZIP:       # %bb.0:4167; ZIP-NEXT:    addi sp, sp, -804168; ZIP-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill4169; ZIP-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill4170; ZIP-NEXT:    addi s0, sp, 804171; ZIP-NEXT:    csrr a0, vlenb4172; ZIP-NEXT:    slli a0, a0, 54173; ZIP-NEXT:    sub sp, sp, a04174; ZIP-NEXT:    andi sp, sp, -644175; ZIP-NEXT:    vsetvli a0, zero, e8, m1, ta, ma4176; ZIP-NEXT:    vmv2r.v v26, v204177; ZIP-NEXT:    addi a0, sp, 644178; ZIP-NEXT:    vmv2r.v v24, v164179; ZIP-NEXT:    vmv2r.v v22, v124180; ZIP-NEXT:    vmv2r.v v20, v84181; ZIP-NEXT:    vmv1r.v v1, v204182; ZIP-NEXT:    vmv1r.v v3, v224183; ZIP-NEXT:    vmv1r.v v5, v244184; ZIP-NEXT:    vmv1r.v v7, v264185; ZIP-NEXT:    vmv1r.v v2, v104186; ZIP-NEXT:    csrr a1, vlenb4187; ZIP-NEXT:    slli a2, a1, 34188; ZIP-NEXT:    sub a1, a2, a14189; ZIP-NEXT:    add a1, sp, a14190; ZIP-NEXT:    addi a1, a1, 644191; ZIP-NEXT:    csrr a2, vlenb4192; ZIP-NEXT:    vmv1r.v v4, v144193; ZIP-NEXT:    add a3, a0, a24194; ZIP-NEXT:    add a4, a1, a24195; ZIP-NEXT:    vmv1r.v v6, v184196; ZIP-NEXT:    add a5, a4, a24197; ZIP-NEXT:    vmv1r.v v22, v114198; ZIP-NEXT:    add a6, a5, a24199; ZIP-NEXT:    vmv1r.v v24, v154200; ZIP-NEXT:    vsseg7e8.v v1, (a0)4201; ZIP-NEXT:    vmv1r.v v26, v194202; ZIP-NEXT:    vsseg7e8.v v21, (a1)4203; ZIP-NEXT:    vl1r.v v18, (a6)4204; ZIP-NEXT:    add a6, a6, a24205; ZIP-NEXT:    vl1r.v v19, (a6)4206; ZIP-NEXT:    add a6, a6, a24207; ZIP-NEXT:    vl1r.v v20, (a6)4208; ZIP-NEXT:    add a6, a6, a24209; ZIP-NEXT:    vl1r.v v21, (a6)4210; ZIP-NEXT:    add a6, a3, a24211; ZIP-NEXT:    vl1r.v v10, (a6)4212; ZIP-NEXT:    add a6, a6, a24213; ZIP-NEXT:    vl1r.v v11, (a6)4214; ZIP-NEXT:    vl1r.v v8, (a0)4215; ZIP-NEXT:    vl1r.v v16, (a4)4216; ZIP-NEXT:    vl1r.v v9, (a3)4217; ZIP-NEXT:    csrr a0, vlenb4218; ZIP-NEXT:    li a3, 144219; ZIP-NEXT:    mul a0, a0, a34220; ZIP-NEXT:    add a0, sp, a04221; ZIP-NEXT:    addi a0, a0, 644222; ZIP-NEXT:    vl1r.v v17, (a5)4223; ZIP-NEXT:    slli a3, a2, 24224; ZIP-NEXT:    add a6, a6, a24225; ZIP-NEXT:    vl1r.v v12, (a6)4226; ZIP-NEXT:    add a6, a6, a24227; ZIP-NEXT:    vl1r.v v13, (a6)4228; ZIP-NEXT:    add a6, a6, a24229; ZIP-NEXT:    slli a2, a2, 34230; ZIP-NEXT:    add a3, a2, a34231; ZIP-NEXT:    add a2, a0, a24232; ZIP-NEXT:    vl1r.v v14, (a6)4233; ZIP-NEXT:    vl1r.v v15, (a1)4234; ZIP-NEXT:    add a3, a0, a34235; ZIP-NEXT:    vs2r.v v20, (a3)4236; ZIP-NEXT:    vs4r.v v16, (a2)4237; ZIP-NEXT:    vs8r.v v8, (a0)4238; ZIP-NEXT:    vl8r.v v16, (a2)4239; ZIP-NEXT:    vl8r.v v8, (a0)4240; ZIP-NEXT:    addi sp, s0, -804241; ZIP-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload4242; ZIP-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload4243; ZIP-NEXT:    addi sp, sp, 804244; ZIP-NEXT:    ret4245  %res = call <vscale x 112 x i8> @llvm.vector.interleave7.nxv112i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c, <vscale x 16 x i8> %d, <vscale x 16 x i8> %e, <vscale x 16 x i8> %f, <vscale x 16 x i8> %g)4246  ret <vscale x 112 x i8> %res4247}4248 4249 4250define <vscale x 56 x i16> @vector_interleave_nxv56i16_nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c, <vscale x 8 x i16> %d, <vscale x 8 x i16> %e, <vscale x 8 x i16> %f, <vscale x 8 x i16> %g) nounwind {4251;4252; RV32-LABEL: vector_interleave_nxv56i16_nxv8i16:4253; RV32:       # %bb.0:4254; RV32-NEXT:    addi sp, sp, -804255; RV32-NEXT:    sw ra, 76(sp) # 4-byte Folded Spill4256; RV32-NEXT:    sw s0, 72(sp) # 4-byte Folded Spill4257; RV32-NEXT:    addi s0, sp, 804258; RV32-NEXT:    csrr a0, vlenb4259; RV32-NEXT:    slli a0, a0, 54260; RV32-NEXT:    sub sp, sp, a04261; RV32-NEXT:    andi sp, sp, -644262; RV32-NEXT:    vsetvli a0, zero, e16, m1, ta, ma4263; RV32-NEXT:    vmv2r.v v26, v204264; RV32-NEXT:    addi a0, sp, 644265; RV32-NEXT:    vmv2r.v v24, v164266; RV32-NEXT:    vmv2r.v v22, v124267; RV32-NEXT:    vmv2r.v v20, v84268; RV32-NEXT:    vmv1r.v v1, v204269; RV32-NEXT:    vmv1r.v v3, v224270; RV32-NEXT:    vmv1r.v v5, v244271; RV32-NEXT:    vmv1r.v v7, v264272; RV32-NEXT:    vmv1r.v v2, v104273; RV32-NEXT:    csrr a1, vlenb4274; RV32-NEXT:    slli a2, a1, 34275; RV32-NEXT:    sub a1, a2, a14276; RV32-NEXT:    add a1, sp, a14277; RV32-NEXT:    addi a1, a1, 644278; RV32-NEXT:    csrr a2, vlenb4279; RV32-NEXT:    vmv1r.v v4, v144280; RV32-NEXT:    add a3, a0, a24281; RV32-NEXT:    add a4, a1, a24282; RV32-NEXT:    vmv1r.v v6, v184283; RV32-NEXT:    add a5, a4, a24284; RV32-NEXT:    vmv1r.v v22, v114285; RV32-NEXT:    add a6, a5, a24286; RV32-NEXT:    vmv1r.v v24, v154287; RV32-NEXT:    vsseg7e16.v v1, (a0)4288; RV32-NEXT:    vmv1r.v v26, v194289; RV32-NEXT:    vsseg7e16.v v21, (a1)4290; RV32-NEXT:    vl1re16.v v18, (a6)4291; RV32-NEXT:    add a6, a6, a24292; RV32-NEXT:    vl1re16.v v19, (a6)4293; RV32-NEXT:    add a6, a6, a24294; RV32-NEXT:    vl1re16.v v20, (a6)4295; RV32-NEXT:    add a6, a6, a24296; RV32-NEXT:    vl1re16.v v21, (a6)4297; RV32-NEXT:    add a6, a3, a24298; RV32-NEXT:    vl1re16.v v10, (a6)4299; RV32-NEXT:    add a6, a6, a24300; RV32-NEXT:    vl1re16.v v11, (a6)4301; RV32-NEXT:    vl1re16.v v8, (a0)4302; RV32-NEXT:    vl1re16.v v16, (a4)4303; RV32-NEXT:    vl1re16.v v9, (a3)4304; RV32-NEXT:    csrr a0, vlenb4305; RV32-NEXT:    li a3, 144306; RV32-NEXT:    mul a0, a0, a34307; RV32-NEXT:    add a0, sp, a04308; RV32-NEXT:    addi a0, a0, 644309; RV32-NEXT:    vl1re16.v v17, (a5)4310; RV32-NEXT:    slli a3, a2, 24311; RV32-NEXT:    add a6, a6, a24312; RV32-NEXT:    vl1re16.v v12, (a6)4313; RV32-NEXT:    add a6, a6, a24314; RV32-NEXT:    vl1re16.v v13, (a6)4315; RV32-NEXT:    add a6, a6, a24316; RV32-NEXT:    slli a2, a2, 34317; RV32-NEXT:    add a3, a2, a34318; RV32-NEXT:    add a2, a0, a24319; RV32-NEXT:    vl1re16.v v14, (a6)4320; RV32-NEXT:    vl1re16.v v15, (a1)4321; RV32-NEXT:    add a3, a0, a34322; RV32-NEXT:    vs2r.v v20, (a3)4323; RV32-NEXT:    vs4r.v v16, (a2)4324; RV32-NEXT:    vs8r.v v8, (a0)4325; RV32-NEXT:    vl8re16.v v16, (a2)4326; RV32-NEXT:    vl8re16.v v8, (a0)4327; RV32-NEXT:    addi sp, s0, -804328; RV32-NEXT:    lw ra, 76(sp) # 4-byte Folded Reload4329; RV32-NEXT:    lw s0, 72(sp) # 4-byte Folded Reload4330; RV32-NEXT:    addi sp, sp, 804331; RV32-NEXT:    ret4332;4333; RV64-LABEL: vector_interleave_nxv56i16_nxv8i16:4334; RV64:       # %bb.0:4335; RV64-NEXT:    addi sp, sp, -804336; RV64-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill4337; RV64-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill4338; RV64-NEXT:    addi s0, sp, 804339; RV64-NEXT:    csrr a0, vlenb4340; RV64-NEXT:    slli a0, a0, 54341; RV64-NEXT:    sub sp, sp, a04342; RV64-NEXT:    andi sp, sp, -644343; RV64-NEXT:    vsetvli a0, zero, e16, m1, ta, ma4344; RV64-NEXT:    vmv2r.v v26, v204345; RV64-NEXT:    addi a0, sp, 644346; RV64-NEXT:    vmv2r.v v24, v164347; RV64-NEXT:    vmv2r.v v22, v124348; RV64-NEXT:    vmv2r.v v20, v84349; RV64-NEXT:    vmv1r.v v1, v204350; RV64-NEXT:    vmv1r.v v3, v224351; RV64-NEXT:    vmv1r.v v5, v244352; RV64-NEXT:    vmv1r.v v7, v264353; RV64-NEXT:    vmv1r.v v2, v104354; RV64-NEXT:    csrr a1, vlenb4355; RV64-NEXT:    slli a2, a1, 34356; RV64-NEXT:    sub a1, a2, a14357; RV64-NEXT:    add a1, sp, a14358; RV64-NEXT:    addi a1, a1, 644359; RV64-NEXT:    csrr a2, vlenb4360; RV64-NEXT:    vmv1r.v v4, v144361; RV64-NEXT:    add a3, a0, a24362; RV64-NEXT:    add a4, a1, a24363; RV64-NEXT:    vmv1r.v v6, v184364; RV64-NEXT:    add a5, a4, a24365; RV64-NEXT:    vmv1r.v v22, v114366; RV64-NEXT:    add a6, a5, a24367; RV64-NEXT:    vmv1r.v v24, v154368; RV64-NEXT:    vsseg7e16.v v1, (a0)4369; RV64-NEXT:    vmv1r.v v26, v194370; RV64-NEXT:    vsseg7e16.v v21, (a1)4371; RV64-NEXT:    vl1re16.v v18, (a6)4372; RV64-NEXT:    add a6, a6, a24373; RV64-NEXT:    vl1re16.v v19, (a6)4374; RV64-NEXT:    add a6, a6, a24375; RV64-NEXT:    vl1re16.v v20, (a6)4376; RV64-NEXT:    add a6, a6, a24377; RV64-NEXT:    vl1re16.v v21, (a6)4378; RV64-NEXT:    add a6, a3, a24379; RV64-NEXT:    vl1re16.v v10, (a6)4380; RV64-NEXT:    add a6, a6, a24381; RV64-NEXT:    vl1re16.v v11, (a6)4382; RV64-NEXT:    vl1re16.v v8, (a0)4383; RV64-NEXT:    vl1re16.v v16, (a4)4384; RV64-NEXT:    vl1re16.v v9, (a3)4385; RV64-NEXT:    csrr a0, vlenb4386; RV64-NEXT:    li a3, 144387; RV64-NEXT:    mul a0, a0, a34388; RV64-NEXT:    add a0, sp, a04389; RV64-NEXT:    addi a0, a0, 644390; RV64-NEXT:    vl1re16.v v17, (a5)4391; RV64-NEXT:    slli a3, a2, 24392; RV64-NEXT:    add a6, a6, a24393; RV64-NEXT:    vl1re16.v v12, (a6)4394; RV64-NEXT:    add a6, a6, a24395; RV64-NEXT:    vl1re16.v v13, (a6)4396; RV64-NEXT:    add a6, a6, a24397; RV64-NEXT:    slli a2, a2, 34398; RV64-NEXT:    add a3, a2, a34399; RV64-NEXT:    add a2, a0, a24400; RV64-NEXT:    vl1re16.v v14, (a6)4401; RV64-NEXT:    vl1re16.v v15, (a1)4402; RV64-NEXT:    add a3, a0, a34403; RV64-NEXT:    vs2r.v v20, (a3)4404; RV64-NEXT:    vs4r.v v16, (a2)4405; RV64-NEXT:    vs8r.v v8, (a0)4406; RV64-NEXT:    vl8re16.v v16, (a2)4407; RV64-NEXT:    vl8re16.v v8, (a0)4408; RV64-NEXT:    addi sp, s0, -804409; RV64-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload4410; RV64-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload4411; RV64-NEXT:    addi sp, sp, 804412; RV64-NEXT:    ret4413;4414; ZVBB-RV32-LABEL: vector_interleave_nxv56i16_nxv8i16:4415; ZVBB-RV32:       # %bb.0:4416; ZVBB-RV32-NEXT:    addi sp, sp, -804417; ZVBB-RV32-NEXT:    sw ra, 76(sp) # 4-byte Folded Spill4418; ZVBB-RV32-NEXT:    sw s0, 72(sp) # 4-byte Folded Spill4419; ZVBB-RV32-NEXT:    addi s0, sp, 804420; ZVBB-RV32-NEXT:    csrr a0, vlenb4421; ZVBB-RV32-NEXT:    slli a0, a0, 54422; ZVBB-RV32-NEXT:    sub sp, sp, a04423; ZVBB-RV32-NEXT:    andi sp, sp, -644424; ZVBB-RV32-NEXT:    vsetvli a0, zero, e16, m1, ta, ma4425; ZVBB-RV32-NEXT:    vmv2r.v v26, v204426; ZVBB-RV32-NEXT:    addi a0, sp, 644427; ZVBB-RV32-NEXT:    vmv2r.v v24, v164428; ZVBB-RV32-NEXT:    vmv2r.v v22, v124429; ZVBB-RV32-NEXT:    vmv2r.v v20, v84430; ZVBB-RV32-NEXT:    vmv1r.v v1, v204431; ZVBB-RV32-NEXT:    vmv1r.v v3, v224432; ZVBB-RV32-NEXT:    vmv1r.v v5, v244433; ZVBB-RV32-NEXT:    vmv1r.v v7, v264434; ZVBB-RV32-NEXT:    vmv1r.v v2, v104435; ZVBB-RV32-NEXT:    csrr a1, vlenb4436; ZVBB-RV32-NEXT:    slli a2, a1, 34437; ZVBB-RV32-NEXT:    sub a1, a2, a14438; ZVBB-RV32-NEXT:    add a1, sp, a14439; ZVBB-RV32-NEXT:    addi a1, a1, 644440; ZVBB-RV32-NEXT:    csrr a2, vlenb4441; ZVBB-RV32-NEXT:    vmv1r.v v4, v144442; ZVBB-RV32-NEXT:    add a3, a0, a24443; ZVBB-RV32-NEXT:    add a4, a1, a24444; ZVBB-RV32-NEXT:    vmv1r.v v6, v184445; ZVBB-RV32-NEXT:    add a5, a4, a24446; ZVBB-RV32-NEXT:    vmv1r.v v22, v114447; ZVBB-RV32-NEXT:    add a6, a5, a24448; ZVBB-RV32-NEXT:    vmv1r.v v24, v154449; ZVBB-RV32-NEXT:    vsseg7e16.v v1, (a0)4450; ZVBB-RV32-NEXT:    vmv1r.v v26, v194451; ZVBB-RV32-NEXT:    vsseg7e16.v v21, (a1)4452; ZVBB-RV32-NEXT:    vl1re16.v v18, (a6)4453; ZVBB-RV32-NEXT:    add a6, a6, a24454; ZVBB-RV32-NEXT:    vl1re16.v v19, (a6)4455; ZVBB-RV32-NEXT:    add a6, a6, a24456; ZVBB-RV32-NEXT:    vl1re16.v v20, (a6)4457; ZVBB-RV32-NEXT:    add a6, a6, a24458; ZVBB-RV32-NEXT:    vl1re16.v v21, (a6)4459; ZVBB-RV32-NEXT:    add a6, a3, a24460; ZVBB-RV32-NEXT:    vl1re16.v v10, (a6)4461; ZVBB-RV32-NEXT:    add a6, a6, a24462; ZVBB-RV32-NEXT:    vl1re16.v v11, (a6)4463; ZVBB-RV32-NEXT:    vl1re16.v v8, (a0)4464; ZVBB-RV32-NEXT:    vl1re16.v v16, (a4)4465; ZVBB-RV32-NEXT:    vl1re16.v v9, (a3)4466; ZVBB-RV32-NEXT:    csrr a0, vlenb4467; ZVBB-RV32-NEXT:    li a3, 144468; ZVBB-RV32-NEXT:    mul a0, a0, a34469; ZVBB-RV32-NEXT:    add a0, sp, a04470; ZVBB-RV32-NEXT:    addi a0, a0, 644471; ZVBB-RV32-NEXT:    vl1re16.v v17, (a5)4472; ZVBB-RV32-NEXT:    slli a3, a2, 24473; ZVBB-RV32-NEXT:    add a6, a6, a24474; ZVBB-RV32-NEXT:    vl1re16.v v12, (a6)4475; ZVBB-RV32-NEXT:    add a6, a6, a24476; ZVBB-RV32-NEXT:    vl1re16.v v13, (a6)4477; ZVBB-RV32-NEXT:    add a6, a6, a24478; ZVBB-RV32-NEXT:    slli a2, a2, 34479; ZVBB-RV32-NEXT:    add a3, a2, a34480; ZVBB-RV32-NEXT:    add a2, a0, a24481; ZVBB-RV32-NEXT:    vl1re16.v v14, (a6)4482; ZVBB-RV32-NEXT:    vl1re16.v v15, (a1)4483; ZVBB-RV32-NEXT:    add a3, a0, a34484; ZVBB-RV32-NEXT:    vs2r.v v20, (a3)4485; ZVBB-RV32-NEXT:    vs4r.v v16, (a2)4486; ZVBB-RV32-NEXT:    vs8r.v v8, (a0)4487; ZVBB-RV32-NEXT:    vl8re16.v v16, (a2)4488; ZVBB-RV32-NEXT:    vl8re16.v v8, (a0)4489; ZVBB-RV32-NEXT:    addi sp, s0, -804490; ZVBB-RV32-NEXT:    lw ra, 76(sp) # 4-byte Folded Reload4491; ZVBB-RV32-NEXT:    lw s0, 72(sp) # 4-byte Folded Reload4492; ZVBB-RV32-NEXT:    addi sp, sp, 804493; ZVBB-RV32-NEXT:    ret4494;4495; ZVBB-RV64-LABEL: vector_interleave_nxv56i16_nxv8i16:4496; ZVBB-RV64:       # %bb.0:4497; ZVBB-RV64-NEXT:    addi sp, sp, -804498; ZVBB-RV64-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill4499; ZVBB-RV64-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill4500; ZVBB-RV64-NEXT:    addi s0, sp, 804501; ZVBB-RV64-NEXT:    csrr a0, vlenb4502; ZVBB-RV64-NEXT:    slli a0, a0, 54503; ZVBB-RV64-NEXT:    sub sp, sp, a04504; ZVBB-RV64-NEXT:    andi sp, sp, -644505; ZVBB-RV64-NEXT:    vsetvli a0, zero, e16, m1, ta, ma4506; ZVBB-RV64-NEXT:    vmv2r.v v26, v204507; ZVBB-RV64-NEXT:    addi a0, sp, 644508; ZVBB-RV64-NEXT:    vmv2r.v v24, v164509; ZVBB-RV64-NEXT:    vmv2r.v v22, v124510; ZVBB-RV64-NEXT:    vmv2r.v v20, v84511; ZVBB-RV64-NEXT:    vmv1r.v v1, v204512; ZVBB-RV64-NEXT:    vmv1r.v v3, v224513; ZVBB-RV64-NEXT:    vmv1r.v v5, v244514; ZVBB-RV64-NEXT:    vmv1r.v v7, v264515; ZVBB-RV64-NEXT:    vmv1r.v v2, v104516; ZVBB-RV64-NEXT:    csrr a1, vlenb4517; ZVBB-RV64-NEXT:    slli a2, a1, 34518; ZVBB-RV64-NEXT:    sub a1, a2, a14519; ZVBB-RV64-NEXT:    add a1, sp, a14520; ZVBB-RV64-NEXT:    addi a1, a1, 644521; ZVBB-RV64-NEXT:    csrr a2, vlenb4522; ZVBB-RV64-NEXT:    vmv1r.v v4, v144523; ZVBB-RV64-NEXT:    add a3, a0, a24524; ZVBB-RV64-NEXT:    add a4, a1, a24525; ZVBB-RV64-NEXT:    vmv1r.v v6, v184526; ZVBB-RV64-NEXT:    add a5, a4, a24527; ZVBB-RV64-NEXT:    vmv1r.v v22, v114528; ZVBB-RV64-NEXT:    add a6, a5, a24529; ZVBB-RV64-NEXT:    vmv1r.v v24, v154530; ZVBB-RV64-NEXT:    vsseg7e16.v v1, (a0)4531; ZVBB-RV64-NEXT:    vmv1r.v v26, v194532; ZVBB-RV64-NEXT:    vsseg7e16.v v21, (a1)4533; ZVBB-RV64-NEXT:    vl1re16.v v18, (a6)4534; ZVBB-RV64-NEXT:    add a6, a6, a24535; ZVBB-RV64-NEXT:    vl1re16.v v19, (a6)4536; ZVBB-RV64-NEXT:    add a6, a6, a24537; ZVBB-RV64-NEXT:    vl1re16.v v20, (a6)4538; ZVBB-RV64-NEXT:    add a6, a6, a24539; ZVBB-RV64-NEXT:    vl1re16.v v21, (a6)4540; ZVBB-RV64-NEXT:    add a6, a3, a24541; ZVBB-RV64-NEXT:    vl1re16.v v10, (a6)4542; ZVBB-RV64-NEXT:    add a6, a6, a24543; ZVBB-RV64-NEXT:    vl1re16.v v11, (a6)4544; ZVBB-RV64-NEXT:    vl1re16.v v8, (a0)4545; ZVBB-RV64-NEXT:    vl1re16.v v16, (a4)4546; ZVBB-RV64-NEXT:    vl1re16.v v9, (a3)4547; ZVBB-RV64-NEXT:    csrr a0, vlenb4548; ZVBB-RV64-NEXT:    li a3, 144549; ZVBB-RV64-NEXT:    mul a0, a0, a34550; ZVBB-RV64-NEXT:    add a0, sp, a04551; ZVBB-RV64-NEXT:    addi a0, a0, 644552; ZVBB-RV64-NEXT:    vl1re16.v v17, (a5)4553; ZVBB-RV64-NEXT:    slli a3, a2, 24554; ZVBB-RV64-NEXT:    add a6, a6, a24555; ZVBB-RV64-NEXT:    vl1re16.v v12, (a6)4556; ZVBB-RV64-NEXT:    add a6, a6, a24557; ZVBB-RV64-NEXT:    vl1re16.v v13, (a6)4558; ZVBB-RV64-NEXT:    add a6, a6, a24559; ZVBB-RV64-NEXT:    slli a2, a2, 34560; ZVBB-RV64-NEXT:    add a3, a2, a34561; ZVBB-RV64-NEXT:    add a2, a0, a24562; ZVBB-RV64-NEXT:    vl1re16.v v14, (a6)4563; ZVBB-RV64-NEXT:    vl1re16.v v15, (a1)4564; ZVBB-RV64-NEXT:    add a3, a0, a34565; ZVBB-RV64-NEXT:    vs2r.v v20, (a3)4566; ZVBB-RV64-NEXT:    vs4r.v v16, (a2)4567; ZVBB-RV64-NEXT:    vs8r.v v8, (a0)4568; ZVBB-RV64-NEXT:    vl8re16.v v16, (a2)4569; ZVBB-RV64-NEXT:    vl8re16.v v8, (a0)4570; ZVBB-RV64-NEXT:    addi sp, s0, -804571; ZVBB-RV64-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload4572; ZVBB-RV64-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload4573; ZVBB-RV64-NEXT:    addi sp, sp, 804574; ZVBB-RV64-NEXT:    ret4575;4576; ZIP-LABEL: vector_interleave_nxv56i16_nxv8i16:4577; ZIP:       # %bb.0:4578; ZIP-NEXT:    addi sp, sp, -804579; ZIP-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill4580; ZIP-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill4581; ZIP-NEXT:    addi s0, sp, 804582; ZIP-NEXT:    csrr a0, vlenb4583; ZIP-NEXT:    slli a0, a0, 54584; ZIP-NEXT:    sub sp, sp, a04585; ZIP-NEXT:    andi sp, sp, -644586; ZIP-NEXT:    vsetvli a0, zero, e16, m1, ta, ma4587; ZIP-NEXT:    vmv2r.v v26, v204588; ZIP-NEXT:    addi a0, sp, 644589; ZIP-NEXT:    vmv2r.v v24, v164590; ZIP-NEXT:    vmv2r.v v22, v124591; ZIP-NEXT:    vmv2r.v v20, v84592; ZIP-NEXT:    vmv1r.v v1, v204593; ZIP-NEXT:    vmv1r.v v3, v224594; ZIP-NEXT:    vmv1r.v v5, v244595; ZIP-NEXT:    vmv1r.v v7, v264596; ZIP-NEXT:    vmv1r.v v2, v104597; ZIP-NEXT:    csrr a1, vlenb4598; ZIP-NEXT:    slli a2, a1, 34599; ZIP-NEXT:    sub a1, a2, a14600; ZIP-NEXT:    add a1, sp, a14601; ZIP-NEXT:    addi a1, a1, 644602; ZIP-NEXT:    csrr a2, vlenb4603; ZIP-NEXT:    vmv1r.v v4, v144604; ZIP-NEXT:    add a3, a0, a24605; ZIP-NEXT:    add a4, a1, a24606; ZIP-NEXT:    vmv1r.v v6, v184607; ZIP-NEXT:    add a5, a4, a24608; ZIP-NEXT:    vmv1r.v v22, v114609; ZIP-NEXT:    add a6, a5, a24610; ZIP-NEXT:    vmv1r.v v24, v154611; ZIP-NEXT:    vsseg7e16.v v1, (a0)4612; ZIP-NEXT:    vmv1r.v v26, v194613; ZIP-NEXT:    vsseg7e16.v v21, (a1)4614; ZIP-NEXT:    vl1re16.v v18, (a6)4615; ZIP-NEXT:    add a6, a6, a24616; ZIP-NEXT:    vl1re16.v v19, (a6)4617; ZIP-NEXT:    add a6, a6, a24618; ZIP-NEXT:    vl1re16.v v20, (a6)4619; ZIP-NEXT:    add a6, a6, a24620; ZIP-NEXT:    vl1re16.v v21, (a6)4621; ZIP-NEXT:    add a6, a3, a24622; ZIP-NEXT:    vl1re16.v v10, (a6)4623; ZIP-NEXT:    add a6, a6, a24624; ZIP-NEXT:    vl1re16.v v11, (a6)4625; ZIP-NEXT:    vl1re16.v v8, (a0)4626; ZIP-NEXT:    vl1re16.v v16, (a4)4627; ZIP-NEXT:    vl1re16.v v9, (a3)4628; ZIP-NEXT:    csrr a0, vlenb4629; ZIP-NEXT:    li a3, 144630; ZIP-NEXT:    mul a0, a0, a34631; ZIP-NEXT:    add a0, sp, a04632; ZIP-NEXT:    addi a0, a0, 644633; ZIP-NEXT:    vl1re16.v v17, (a5)4634; ZIP-NEXT:    slli a3, a2, 24635; ZIP-NEXT:    add a6, a6, a24636; ZIP-NEXT:    vl1re16.v v12, (a6)4637; ZIP-NEXT:    add a6, a6, a24638; ZIP-NEXT:    vl1re16.v v13, (a6)4639; ZIP-NEXT:    add a6, a6, a24640; ZIP-NEXT:    slli a2, a2, 34641; ZIP-NEXT:    add a3, a2, a34642; ZIP-NEXT:    add a2, a0, a24643; ZIP-NEXT:    vl1re16.v v14, (a6)4644; ZIP-NEXT:    vl1re16.v v15, (a1)4645; ZIP-NEXT:    add a3, a0, a34646; ZIP-NEXT:    vs2r.v v20, (a3)4647; ZIP-NEXT:    vs4r.v v16, (a2)4648; ZIP-NEXT:    vs8r.v v8, (a0)4649; ZIP-NEXT:    vl8re16.v v16, (a2)4650; ZIP-NEXT:    vl8re16.v v8, (a0)4651; ZIP-NEXT:    addi sp, s0, -804652; ZIP-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload4653; ZIP-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload4654; ZIP-NEXT:    addi sp, sp, 804655; ZIP-NEXT:    ret4656  %res = call <vscale x 56 x i16> @llvm.vector.interleave7.nxv56i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c, <vscale x 8 x i16> %d, <vscale x 8 x i16> %e, <vscale x 8 x i16> %f, <vscale x 8 x i16> %g)4657  ret <vscale x 56 x i16> %res4658}4659 4660 4661define <vscale x 28 x i32> @vector_interleave_nxv28i32_nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c, <vscale x 4 x i32> %d, <vscale x 4 x i32> %e, <vscale x 4 x i32> %f, <vscale x 4 x i32> %g) nounwind {4662;4663; RV32-LABEL: vector_interleave_nxv28i32_nxv4i32:4664; RV32:       # %bb.0:4665; RV32-NEXT:    addi sp, sp, -804666; RV32-NEXT:    sw ra, 76(sp) # 4-byte Folded Spill4667; RV32-NEXT:    sw s0, 72(sp) # 4-byte Folded Spill4668; RV32-NEXT:    addi s0, sp, 804669; RV32-NEXT:    csrr a0, vlenb4670; RV32-NEXT:    slli a0, a0, 54671; RV32-NEXT:    sub sp, sp, a04672; RV32-NEXT:    andi sp, sp, -644673; RV32-NEXT:    vsetvli a0, zero, e32, m1, ta, ma4674; RV32-NEXT:    vmv2r.v v26, v204675; RV32-NEXT:    addi a0, sp, 644676; RV32-NEXT:    vmv2r.v v24, v164677; RV32-NEXT:    vmv2r.v v22, v124678; RV32-NEXT:    vmv2r.v v20, v84679; RV32-NEXT:    vmv1r.v v1, v204680; RV32-NEXT:    vmv1r.v v3, v224681; RV32-NEXT:    vmv1r.v v5, v244682; RV32-NEXT:    vmv1r.v v7, v264683; RV32-NEXT:    vmv1r.v v2, v104684; RV32-NEXT:    csrr a1, vlenb4685; RV32-NEXT:    slli a2, a1, 34686; RV32-NEXT:    sub a1, a2, a14687; RV32-NEXT:    add a1, sp, a14688; RV32-NEXT:    addi a1, a1, 644689; RV32-NEXT:    csrr a2, vlenb4690; RV32-NEXT:    vmv1r.v v4, v144691; RV32-NEXT:    add a3, a0, a24692; RV32-NEXT:    add a4, a1, a24693; RV32-NEXT:    vmv1r.v v6, v184694; RV32-NEXT:    add a5, a4, a24695; RV32-NEXT:    vmv1r.v v22, v114696; RV32-NEXT:    add a6, a5, a24697; RV32-NEXT:    vmv1r.v v24, v154698; RV32-NEXT:    vsseg7e32.v v1, (a0)4699; RV32-NEXT:    vmv1r.v v26, v194700; RV32-NEXT:    vsseg7e32.v v21, (a1)4701; RV32-NEXT:    vl1re32.v v18, (a6)4702; RV32-NEXT:    add a6, a6, a24703; RV32-NEXT:    vl1re32.v v19, (a6)4704; RV32-NEXT:    add a6, a6, a24705; RV32-NEXT:    vl1re32.v v20, (a6)4706; RV32-NEXT:    add a6, a6, a24707; RV32-NEXT:    vl1re32.v v21, (a6)4708; RV32-NEXT:    add a6, a3, a24709; RV32-NEXT:    vl1re32.v v10, (a6)4710; RV32-NEXT:    add a6, a6, a24711; RV32-NEXT:    vl1re32.v v11, (a6)4712; RV32-NEXT:    vl1re32.v v8, (a0)4713; RV32-NEXT:    vl1re32.v v16, (a4)4714; RV32-NEXT:    vl1re32.v v9, (a3)4715; RV32-NEXT:    csrr a0, vlenb4716; RV32-NEXT:    li a3, 144717; RV32-NEXT:    mul a0, a0, a34718; RV32-NEXT:    add a0, sp, a04719; RV32-NEXT:    addi a0, a0, 644720; RV32-NEXT:    vl1re32.v v17, (a5)4721; RV32-NEXT:    slli a3, a2, 24722; RV32-NEXT:    add a6, a6, a24723; RV32-NEXT:    vl1re32.v v12, (a6)4724; RV32-NEXT:    add a6, a6, a24725; RV32-NEXT:    vl1re32.v v13, (a6)4726; RV32-NEXT:    add a6, a6, a24727; RV32-NEXT:    slli a2, a2, 34728; RV32-NEXT:    add a3, a2, a34729; RV32-NEXT:    add a2, a0, a24730; RV32-NEXT:    vl1re32.v v14, (a6)4731; RV32-NEXT:    vl1re32.v v15, (a1)4732; RV32-NEXT:    add a3, a0, a34733; RV32-NEXT:    vs2r.v v20, (a3)4734; RV32-NEXT:    vs4r.v v16, (a2)4735; RV32-NEXT:    vs8r.v v8, (a0)4736; RV32-NEXT:    vl8re32.v v16, (a2)4737; RV32-NEXT:    vl8re32.v v8, (a0)4738; RV32-NEXT:    addi sp, s0, -804739; RV32-NEXT:    lw ra, 76(sp) # 4-byte Folded Reload4740; RV32-NEXT:    lw s0, 72(sp) # 4-byte Folded Reload4741; RV32-NEXT:    addi sp, sp, 804742; RV32-NEXT:    ret4743;4744; RV64-LABEL: vector_interleave_nxv28i32_nxv4i32:4745; RV64:       # %bb.0:4746; RV64-NEXT:    addi sp, sp, -804747; RV64-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill4748; RV64-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill4749; RV64-NEXT:    addi s0, sp, 804750; RV64-NEXT:    csrr a0, vlenb4751; RV64-NEXT:    slli a0, a0, 54752; RV64-NEXT:    sub sp, sp, a04753; RV64-NEXT:    andi sp, sp, -644754; RV64-NEXT:    vsetvli a0, zero, e32, m1, ta, ma4755; RV64-NEXT:    vmv2r.v v26, v204756; RV64-NEXT:    addi a0, sp, 644757; RV64-NEXT:    vmv2r.v v24, v164758; RV64-NEXT:    vmv2r.v v22, v124759; RV64-NEXT:    vmv2r.v v20, v84760; RV64-NEXT:    vmv1r.v v1, v204761; RV64-NEXT:    vmv1r.v v3, v224762; RV64-NEXT:    vmv1r.v v5, v244763; RV64-NEXT:    vmv1r.v v7, v264764; RV64-NEXT:    vmv1r.v v2, v104765; RV64-NEXT:    csrr a1, vlenb4766; RV64-NEXT:    slli a2, a1, 34767; RV64-NEXT:    sub a1, a2, a14768; RV64-NEXT:    add a1, sp, a14769; RV64-NEXT:    addi a1, a1, 644770; RV64-NEXT:    csrr a2, vlenb4771; RV64-NEXT:    vmv1r.v v4, v144772; RV64-NEXT:    add a3, a0, a24773; RV64-NEXT:    add a4, a1, a24774; RV64-NEXT:    vmv1r.v v6, v184775; RV64-NEXT:    add a5, a4, a24776; RV64-NEXT:    vmv1r.v v22, v114777; RV64-NEXT:    add a6, a5, a24778; RV64-NEXT:    vmv1r.v v24, v154779; RV64-NEXT:    vsseg7e32.v v1, (a0)4780; RV64-NEXT:    vmv1r.v v26, v194781; RV64-NEXT:    vsseg7e32.v v21, (a1)4782; RV64-NEXT:    vl1re32.v v18, (a6)4783; RV64-NEXT:    add a6, a6, a24784; RV64-NEXT:    vl1re32.v v19, (a6)4785; RV64-NEXT:    add a6, a6, a24786; RV64-NEXT:    vl1re32.v v20, (a6)4787; RV64-NEXT:    add a6, a6, a24788; RV64-NEXT:    vl1re32.v v21, (a6)4789; RV64-NEXT:    add a6, a3, a24790; RV64-NEXT:    vl1re32.v v10, (a6)4791; RV64-NEXT:    add a6, a6, a24792; RV64-NEXT:    vl1re32.v v11, (a6)4793; RV64-NEXT:    vl1re32.v v8, (a0)4794; RV64-NEXT:    vl1re32.v v16, (a4)4795; RV64-NEXT:    vl1re32.v v9, (a3)4796; RV64-NEXT:    csrr a0, vlenb4797; RV64-NEXT:    li a3, 144798; RV64-NEXT:    mul a0, a0, a34799; RV64-NEXT:    add a0, sp, a04800; RV64-NEXT:    addi a0, a0, 644801; RV64-NEXT:    vl1re32.v v17, (a5)4802; RV64-NEXT:    slli a3, a2, 24803; RV64-NEXT:    add a6, a6, a24804; RV64-NEXT:    vl1re32.v v12, (a6)4805; RV64-NEXT:    add a6, a6, a24806; RV64-NEXT:    vl1re32.v v13, (a6)4807; RV64-NEXT:    add a6, a6, a24808; RV64-NEXT:    slli a2, a2, 34809; RV64-NEXT:    add a3, a2, a34810; RV64-NEXT:    add a2, a0, a24811; RV64-NEXT:    vl1re32.v v14, (a6)4812; RV64-NEXT:    vl1re32.v v15, (a1)4813; RV64-NEXT:    add a3, a0, a34814; RV64-NEXT:    vs2r.v v20, (a3)4815; RV64-NEXT:    vs4r.v v16, (a2)4816; RV64-NEXT:    vs8r.v v8, (a0)4817; RV64-NEXT:    vl8re32.v v16, (a2)4818; RV64-NEXT:    vl8re32.v v8, (a0)4819; RV64-NEXT:    addi sp, s0, -804820; RV64-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload4821; RV64-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload4822; RV64-NEXT:    addi sp, sp, 804823; RV64-NEXT:    ret4824;4825; ZVBB-RV32-LABEL: vector_interleave_nxv28i32_nxv4i32:4826; ZVBB-RV32:       # %bb.0:4827; ZVBB-RV32-NEXT:    addi sp, sp, -804828; ZVBB-RV32-NEXT:    sw ra, 76(sp) # 4-byte Folded Spill4829; ZVBB-RV32-NEXT:    sw s0, 72(sp) # 4-byte Folded Spill4830; ZVBB-RV32-NEXT:    addi s0, sp, 804831; ZVBB-RV32-NEXT:    csrr a0, vlenb4832; ZVBB-RV32-NEXT:    slli a0, a0, 54833; ZVBB-RV32-NEXT:    sub sp, sp, a04834; ZVBB-RV32-NEXT:    andi sp, sp, -644835; ZVBB-RV32-NEXT:    vsetvli a0, zero, e32, m1, ta, ma4836; ZVBB-RV32-NEXT:    vmv2r.v v26, v204837; ZVBB-RV32-NEXT:    addi a0, sp, 644838; ZVBB-RV32-NEXT:    vmv2r.v v24, v164839; ZVBB-RV32-NEXT:    vmv2r.v v22, v124840; ZVBB-RV32-NEXT:    vmv2r.v v20, v84841; ZVBB-RV32-NEXT:    vmv1r.v v1, v204842; ZVBB-RV32-NEXT:    vmv1r.v v3, v224843; ZVBB-RV32-NEXT:    vmv1r.v v5, v244844; ZVBB-RV32-NEXT:    vmv1r.v v7, v264845; ZVBB-RV32-NEXT:    vmv1r.v v2, v104846; ZVBB-RV32-NEXT:    csrr a1, vlenb4847; ZVBB-RV32-NEXT:    slli a2, a1, 34848; ZVBB-RV32-NEXT:    sub a1, a2, a14849; ZVBB-RV32-NEXT:    add a1, sp, a14850; ZVBB-RV32-NEXT:    addi a1, a1, 644851; ZVBB-RV32-NEXT:    csrr a2, vlenb4852; ZVBB-RV32-NEXT:    vmv1r.v v4, v144853; ZVBB-RV32-NEXT:    add a3, a0, a24854; ZVBB-RV32-NEXT:    add a4, a1, a24855; ZVBB-RV32-NEXT:    vmv1r.v v6, v184856; ZVBB-RV32-NEXT:    add a5, a4, a24857; ZVBB-RV32-NEXT:    vmv1r.v v22, v114858; ZVBB-RV32-NEXT:    add a6, a5, a24859; ZVBB-RV32-NEXT:    vmv1r.v v24, v154860; ZVBB-RV32-NEXT:    vsseg7e32.v v1, (a0)4861; ZVBB-RV32-NEXT:    vmv1r.v v26, v194862; ZVBB-RV32-NEXT:    vsseg7e32.v v21, (a1)4863; ZVBB-RV32-NEXT:    vl1re32.v v18, (a6)4864; ZVBB-RV32-NEXT:    add a6, a6, a24865; ZVBB-RV32-NEXT:    vl1re32.v v19, (a6)4866; ZVBB-RV32-NEXT:    add a6, a6, a24867; ZVBB-RV32-NEXT:    vl1re32.v v20, (a6)4868; ZVBB-RV32-NEXT:    add a6, a6, a24869; ZVBB-RV32-NEXT:    vl1re32.v v21, (a6)4870; ZVBB-RV32-NEXT:    add a6, a3, a24871; ZVBB-RV32-NEXT:    vl1re32.v v10, (a6)4872; ZVBB-RV32-NEXT:    add a6, a6, a24873; ZVBB-RV32-NEXT:    vl1re32.v v11, (a6)4874; ZVBB-RV32-NEXT:    vl1re32.v v8, (a0)4875; ZVBB-RV32-NEXT:    vl1re32.v v16, (a4)4876; ZVBB-RV32-NEXT:    vl1re32.v v9, (a3)4877; ZVBB-RV32-NEXT:    csrr a0, vlenb4878; ZVBB-RV32-NEXT:    li a3, 144879; ZVBB-RV32-NEXT:    mul a0, a0, a34880; ZVBB-RV32-NEXT:    add a0, sp, a04881; ZVBB-RV32-NEXT:    addi a0, a0, 644882; ZVBB-RV32-NEXT:    vl1re32.v v17, (a5)4883; ZVBB-RV32-NEXT:    slli a3, a2, 24884; ZVBB-RV32-NEXT:    add a6, a6, a24885; ZVBB-RV32-NEXT:    vl1re32.v v12, (a6)4886; ZVBB-RV32-NEXT:    add a6, a6, a24887; ZVBB-RV32-NEXT:    vl1re32.v v13, (a6)4888; ZVBB-RV32-NEXT:    add a6, a6, a24889; ZVBB-RV32-NEXT:    slli a2, a2, 34890; ZVBB-RV32-NEXT:    add a3, a2, a34891; ZVBB-RV32-NEXT:    add a2, a0, a24892; ZVBB-RV32-NEXT:    vl1re32.v v14, (a6)4893; ZVBB-RV32-NEXT:    vl1re32.v v15, (a1)4894; ZVBB-RV32-NEXT:    add a3, a0, a34895; ZVBB-RV32-NEXT:    vs2r.v v20, (a3)4896; ZVBB-RV32-NEXT:    vs4r.v v16, (a2)4897; ZVBB-RV32-NEXT:    vs8r.v v8, (a0)4898; ZVBB-RV32-NEXT:    vl8re32.v v16, (a2)4899; ZVBB-RV32-NEXT:    vl8re32.v v8, (a0)4900; ZVBB-RV32-NEXT:    addi sp, s0, -804901; ZVBB-RV32-NEXT:    lw ra, 76(sp) # 4-byte Folded Reload4902; ZVBB-RV32-NEXT:    lw s0, 72(sp) # 4-byte Folded Reload4903; ZVBB-RV32-NEXT:    addi sp, sp, 804904; ZVBB-RV32-NEXT:    ret4905;4906; ZVBB-RV64-LABEL: vector_interleave_nxv28i32_nxv4i32:4907; ZVBB-RV64:       # %bb.0:4908; ZVBB-RV64-NEXT:    addi sp, sp, -804909; ZVBB-RV64-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill4910; ZVBB-RV64-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill4911; ZVBB-RV64-NEXT:    addi s0, sp, 804912; ZVBB-RV64-NEXT:    csrr a0, vlenb4913; ZVBB-RV64-NEXT:    slli a0, a0, 54914; ZVBB-RV64-NEXT:    sub sp, sp, a04915; ZVBB-RV64-NEXT:    andi sp, sp, -644916; ZVBB-RV64-NEXT:    vsetvli a0, zero, e32, m1, ta, ma4917; ZVBB-RV64-NEXT:    vmv2r.v v26, v204918; ZVBB-RV64-NEXT:    addi a0, sp, 644919; ZVBB-RV64-NEXT:    vmv2r.v v24, v164920; ZVBB-RV64-NEXT:    vmv2r.v v22, v124921; ZVBB-RV64-NEXT:    vmv2r.v v20, v84922; ZVBB-RV64-NEXT:    vmv1r.v v1, v204923; ZVBB-RV64-NEXT:    vmv1r.v v3, v224924; ZVBB-RV64-NEXT:    vmv1r.v v5, v244925; ZVBB-RV64-NEXT:    vmv1r.v v7, v264926; ZVBB-RV64-NEXT:    vmv1r.v v2, v104927; ZVBB-RV64-NEXT:    csrr a1, vlenb4928; ZVBB-RV64-NEXT:    slli a2, a1, 34929; ZVBB-RV64-NEXT:    sub a1, a2, a14930; ZVBB-RV64-NEXT:    add a1, sp, a14931; ZVBB-RV64-NEXT:    addi a1, a1, 644932; ZVBB-RV64-NEXT:    csrr a2, vlenb4933; ZVBB-RV64-NEXT:    vmv1r.v v4, v144934; ZVBB-RV64-NEXT:    add a3, a0, a24935; ZVBB-RV64-NEXT:    add a4, a1, a24936; ZVBB-RV64-NEXT:    vmv1r.v v6, v184937; ZVBB-RV64-NEXT:    add a5, a4, a24938; ZVBB-RV64-NEXT:    vmv1r.v v22, v114939; ZVBB-RV64-NEXT:    add a6, a5, a24940; ZVBB-RV64-NEXT:    vmv1r.v v24, v154941; ZVBB-RV64-NEXT:    vsseg7e32.v v1, (a0)4942; ZVBB-RV64-NEXT:    vmv1r.v v26, v194943; ZVBB-RV64-NEXT:    vsseg7e32.v v21, (a1)4944; ZVBB-RV64-NEXT:    vl1re32.v v18, (a6)4945; ZVBB-RV64-NEXT:    add a6, a6, a24946; ZVBB-RV64-NEXT:    vl1re32.v v19, (a6)4947; ZVBB-RV64-NEXT:    add a6, a6, a24948; ZVBB-RV64-NEXT:    vl1re32.v v20, (a6)4949; ZVBB-RV64-NEXT:    add a6, a6, a24950; ZVBB-RV64-NEXT:    vl1re32.v v21, (a6)4951; ZVBB-RV64-NEXT:    add a6, a3, a24952; ZVBB-RV64-NEXT:    vl1re32.v v10, (a6)4953; ZVBB-RV64-NEXT:    add a6, a6, a24954; ZVBB-RV64-NEXT:    vl1re32.v v11, (a6)4955; ZVBB-RV64-NEXT:    vl1re32.v v8, (a0)4956; ZVBB-RV64-NEXT:    vl1re32.v v16, (a4)4957; ZVBB-RV64-NEXT:    vl1re32.v v9, (a3)4958; ZVBB-RV64-NEXT:    csrr a0, vlenb4959; ZVBB-RV64-NEXT:    li a3, 144960; ZVBB-RV64-NEXT:    mul a0, a0, a34961; ZVBB-RV64-NEXT:    add a0, sp, a04962; ZVBB-RV64-NEXT:    addi a0, a0, 644963; ZVBB-RV64-NEXT:    vl1re32.v v17, (a5)4964; ZVBB-RV64-NEXT:    slli a3, a2, 24965; ZVBB-RV64-NEXT:    add a6, a6, a24966; ZVBB-RV64-NEXT:    vl1re32.v v12, (a6)4967; ZVBB-RV64-NEXT:    add a6, a6, a24968; ZVBB-RV64-NEXT:    vl1re32.v v13, (a6)4969; ZVBB-RV64-NEXT:    add a6, a6, a24970; ZVBB-RV64-NEXT:    slli a2, a2, 34971; ZVBB-RV64-NEXT:    add a3, a2, a34972; ZVBB-RV64-NEXT:    add a2, a0, a24973; ZVBB-RV64-NEXT:    vl1re32.v v14, (a6)4974; ZVBB-RV64-NEXT:    vl1re32.v v15, (a1)4975; ZVBB-RV64-NEXT:    add a3, a0, a34976; ZVBB-RV64-NEXT:    vs2r.v v20, (a3)4977; ZVBB-RV64-NEXT:    vs4r.v v16, (a2)4978; ZVBB-RV64-NEXT:    vs8r.v v8, (a0)4979; ZVBB-RV64-NEXT:    vl8re32.v v16, (a2)4980; ZVBB-RV64-NEXT:    vl8re32.v v8, (a0)4981; ZVBB-RV64-NEXT:    addi sp, s0, -804982; ZVBB-RV64-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload4983; ZVBB-RV64-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload4984; ZVBB-RV64-NEXT:    addi sp, sp, 804985; ZVBB-RV64-NEXT:    ret4986;4987; ZIP-LABEL: vector_interleave_nxv28i32_nxv4i32:4988; ZIP:       # %bb.0:4989; ZIP-NEXT:    addi sp, sp, -804990; ZIP-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill4991; ZIP-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill4992; ZIP-NEXT:    addi s0, sp, 804993; ZIP-NEXT:    csrr a0, vlenb4994; ZIP-NEXT:    slli a0, a0, 54995; ZIP-NEXT:    sub sp, sp, a04996; ZIP-NEXT:    andi sp, sp, -644997; ZIP-NEXT:    vsetvli a0, zero, e32, m1, ta, ma4998; ZIP-NEXT:    vmv2r.v v26, v204999; ZIP-NEXT:    addi a0, sp, 645000; ZIP-NEXT:    vmv2r.v v24, v165001; ZIP-NEXT:    vmv2r.v v22, v125002; ZIP-NEXT:    vmv2r.v v20, v85003; ZIP-NEXT:    vmv1r.v v1, v205004; ZIP-NEXT:    vmv1r.v v3, v225005; ZIP-NEXT:    vmv1r.v v5, v245006; ZIP-NEXT:    vmv1r.v v7, v265007; ZIP-NEXT:    vmv1r.v v2, v105008; ZIP-NEXT:    csrr a1, vlenb5009; ZIP-NEXT:    slli a2, a1, 35010; ZIP-NEXT:    sub a1, a2, a15011; ZIP-NEXT:    add a1, sp, a15012; ZIP-NEXT:    addi a1, a1, 645013; ZIP-NEXT:    csrr a2, vlenb5014; ZIP-NEXT:    vmv1r.v v4, v145015; ZIP-NEXT:    add a3, a0, a25016; ZIP-NEXT:    add a4, a1, a25017; ZIP-NEXT:    vmv1r.v v6, v185018; ZIP-NEXT:    add a5, a4, a25019; ZIP-NEXT:    vmv1r.v v22, v115020; ZIP-NEXT:    add a6, a5, a25021; ZIP-NEXT:    vmv1r.v v24, v155022; ZIP-NEXT:    vsseg7e32.v v1, (a0)5023; ZIP-NEXT:    vmv1r.v v26, v195024; ZIP-NEXT:    vsseg7e32.v v21, (a1)5025; ZIP-NEXT:    vl1re32.v v18, (a6)5026; ZIP-NEXT:    add a6, a6, a25027; ZIP-NEXT:    vl1re32.v v19, (a6)5028; ZIP-NEXT:    add a6, a6, a25029; ZIP-NEXT:    vl1re32.v v20, (a6)5030; ZIP-NEXT:    add a6, a6, a25031; ZIP-NEXT:    vl1re32.v v21, (a6)5032; ZIP-NEXT:    add a6, a3, a25033; ZIP-NEXT:    vl1re32.v v10, (a6)5034; ZIP-NEXT:    add a6, a6, a25035; ZIP-NEXT:    vl1re32.v v11, (a6)5036; ZIP-NEXT:    vl1re32.v v8, (a0)5037; ZIP-NEXT:    vl1re32.v v16, (a4)5038; ZIP-NEXT:    vl1re32.v v9, (a3)5039; ZIP-NEXT:    csrr a0, vlenb5040; ZIP-NEXT:    li a3, 145041; ZIP-NEXT:    mul a0, a0, a35042; ZIP-NEXT:    add a0, sp, a05043; ZIP-NEXT:    addi a0, a0, 645044; ZIP-NEXT:    vl1re32.v v17, (a5)5045; ZIP-NEXT:    slli a3, a2, 25046; ZIP-NEXT:    add a6, a6, a25047; ZIP-NEXT:    vl1re32.v v12, (a6)5048; ZIP-NEXT:    add a6, a6, a25049; ZIP-NEXT:    vl1re32.v v13, (a6)5050; ZIP-NEXT:    add a6, a6, a25051; ZIP-NEXT:    slli a2, a2, 35052; ZIP-NEXT:    add a3, a2, a35053; ZIP-NEXT:    add a2, a0, a25054; ZIP-NEXT:    vl1re32.v v14, (a6)5055; ZIP-NEXT:    vl1re32.v v15, (a1)5056; ZIP-NEXT:    add a3, a0, a35057; ZIP-NEXT:    vs2r.v v20, (a3)5058; ZIP-NEXT:    vs4r.v v16, (a2)5059; ZIP-NEXT:    vs8r.v v8, (a0)5060; ZIP-NEXT:    vl8re32.v v16, (a2)5061; ZIP-NEXT:    vl8re32.v v8, (a0)5062; ZIP-NEXT:    addi sp, s0, -805063; ZIP-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload5064; ZIP-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload5065; ZIP-NEXT:    addi sp, sp, 805066; ZIP-NEXT:    ret5067  %res = call <vscale x 28 x i32> @llvm.vector.interleave7.nxv28i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c, <vscale x 4 x i32> %d, <vscale x 4 x i32> %e, <vscale x 4 x i32> %f, <vscale x 4 x i32> %g)5068  ret <vscale x 28 x i32> %res5069}5070 5071define <vscale x 14 x i64> @vector_interleave_nxv14i64_nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c, <vscale x 2 x i64> %d, <vscale x 2 x i64> %e, <vscale x 2 x i64> %f, <vscale x 2 x i64> %g) nounwind {5072;5073; RV32-LABEL: vector_interleave_nxv14i64_nxv2i64:5074; RV32:       # %bb.0:5075; RV32-NEXT:    addi sp, sp, -805076; RV32-NEXT:    sw ra, 76(sp) # 4-byte Folded Spill5077; RV32-NEXT:    sw s0, 72(sp) # 4-byte Folded Spill5078; RV32-NEXT:    addi s0, sp, 805079; RV32-NEXT:    csrr a0, vlenb5080; RV32-NEXT:    slli a0, a0, 55081; RV32-NEXT:    sub sp, sp, a05082; RV32-NEXT:    andi sp, sp, -645083; RV32-NEXT:    vsetvli a0, zero, e64, m1, ta, ma5084; RV32-NEXT:    vmv2r.v v26, v205085; RV32-NEXT:    addi a0, sp, 645086; RV32-NEXT:    vmv2r.v v24, v165087; RV32-NEXT:    vmv2r.v v22, v125088; RV32-NEXT:    vmv2r.v v20, v85089; RV32-NEXT:    vmv1r.v v1, v205090; RV32-NEXT:    vmv1r.v v3, v225091; RV32-NEXT:    vmv1r.v v5, v245092; RV32-NEXT:    vmv1r.v v7, v265093; RV32-NEXT:    vmv1r.v v2, v105094; RV32-NEXT:    csrr a1, vlenb5095; RV32-NEXT:    slli a2, a1, 35096; RV32-NEXT:    sub a1, a2, a15097; RV32-NEXT:    add a1, sp, a15098; RV32-NEXT:    addi a1, a1, 645099; RV32-NEXT:    csrr a2, vlenb5100; RV32-NEXT:    vmv1r.v v4, v145101; RV32-NEXT:    add a3, a0, a25102; RV32-NEXT:    add a4, a1, a25103; RV32-NEXT:    vmv1r.v v6, v185104; RV32-NEXT:    add a5, a4, a25105; RV32-NEXT:    vmv1r.v v22, v115106; RV32-NEXT:    add a6, a5, a25107; RV32-NEXT:    vmv1r.v v24, v155108; RV32-NEXT:    vsseg7e64.v v1, (a0)5109; RV32-NEXT:    vmv1r.v v26, v195110; RV32-NEXT:    vsseg7e64.v v21, (a1)5111; RV32-NEXT:    vl1re64.v v18, (a6)5112; RV32-NEXT:    add a6, a6, a25113; RV32-NEXT:    vl1re64.v v19, (a6)5114; RV32-NEXT:    add a6, a6, a25115; RV32-NEXT:    vl1re64.v v20, (a6)5116; RV32-NEXT:    add a6, a6, a25117; RV32-NEXT:    vl1re64.v v21, (a6)5118; RV32-NEXT:    add a6, a3, a25119; RV32-NEXT:    vl1re64.v v10, (a6)5120; RV32-NEXT:    add a6, a6, a25121; RV32-NEXT:    vl1re64.v v11, (a6)5122; RV32-NEXT:    vl1re64.v v8, (a0)5123; RV32-NEXT:    vl1re64.v v16, (a4)5124; RV32-NEXT:    vl1re64.v v9, (a3)5125; RV32-NEXT:    csrr a0, vlenb5126; RV32-NEXT:    li a3, 145127; RV32-NEXT:    mul a0, a0, a35128; RV32-NEXT:    add a0, sp, a05129; RV32-NEXT:    addi a0, a0, 645130; RV32-NEXT:    vl1re64.v v17, (a5)5131; RV32-NEXT:    slli a3, a2, 25132; RV32-NEXT:    add a6, a6, a25133; RV32-NEXT:    vl1re64.v v12, (a6)5134; RV32-NEXT:    add a6, a6, a25135; RV32-NEXT:    vl1re64.v v13, (a6)5136; RV32-NEXT:    add a6, a6, a25137; RV32-NEXT:    slli a2, a2, 35138; RV32-NEXT:    add a3, a2, a35139; RV32-NEXT:    add a2, a0, a25140; RV32-NEXT:    vl1re64.v v14, (a6)5141; RV32-NEXT:    vl1re64.v v15, (a1)5142; RV32-NEXT:    add a3, a0, a35143; RV32-NEXT:    vs2r.v v20, (a3)5144; RV32-NEXT:    vs4r.v v16, (a2)5145; RV32-NEXT:    vs8r.v v8, (a0)5146; RV32-NEXT:    vl8re64.v v16, (a2)5147; RV32-NEXT:    vl8re64.v v8, (a0)5148; RV32-NEXT:    addi sp, s0, -805149; RV32-NEXT:    lw ra, 76(sp) # 4-byte Folded Reload5150; RV32-NEXT:    lw s0, 72(sp) # 4-byte Folded Reload5151; RV32-NEXT:    addi sp, sp, 805152; RV32-NEXT:    ret5153;5154; RV64-LABEL: vector_interleave_nxv14i64_nxv2i64:5155; RV64:       # %bb.0:5156; RV64-NEXT:    addi sp, sp, -805157; RV64-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill5158; RV64-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill5159; RV64-NEXT:    addi s0, sp, 805160; RV64-NEXT:    csrr a0, vlenb5161; RV64-NEXT:    slli a0, a0, 55162; RV64-NEXT:    sub sp, sp, a05163; RV64-NEXT:    andi sp, sp, -645164; RV64-NEXT:    vsetvli a0, zero, e64, m1, ta, ma5165; RV64-NEXT:    vmv2r.v v26, v205166; RV64-NEXT:    addi a0, sp, 645167; RV64-NEXT:    vmv2r.v v24, v165168; RV64-NEXT:    vmv2r.v v22, v125169; RV64-NEXT:    vmv2r.v v20, v85170; RV64-NEXT:    vmv1r.v v1, v205171; RV64-NEXT:    vmv1r.v v3, v225172; RV64-NEXT:    vmv1r.v v5, v245173; RV64-NEXT:    vmv1r.v v7, v265174; RV64-NEXT:    vmv1r.v v2, v105175; RV64-NEXT:    csrr a1, vlenb5176; RV64-NEXT:    slli a2, a1, 35177; RV64-NEXT:    sub a1, a2, a15178; RV64-NEXT:    add a1, sp, a15179; RV64-NEXT:    addi a1, a1, 645180; RV64-NEXT:    csrr a2, vlenb5181; RV64-NEXT:    vmv1r.v v4, v145182; RV64-NEXT:    add a3, a0, a25183; RV64-NEXT:    add a4, a1, a25184; RV64-NEXT:    vmv1r.v v6, v185185; RV64-NEXT:    add a5, a4, a25186; RV64-NEXT:    vmv1r.v v22, v115187; RV64-NEXT:    add a6, a5, a25188; RV64-NEXT:    vmv1r.v v24, v155189; RV64-NEXT:    vsseg7e64.v v1, (a0)5190; RV64-NEXT:    vmv1r.v v26, v195191; RV64-NEXT:    vsseg7e64.v v21, (a1)5192; RV64-NEXT:    vl1re64.v v18, (a6)5193; RV64-NEXT:    add a6, a6, a25194; RV64-NEXT:    vl1re64.v v19, (a6)5195; RV64-NEXT:    add a6, a6, a25196; RV64-NEXT:    vl1re64.v v20, (a6)5197; RV64-NEXT:    add a6, a6, a25198; RV64-NEXT:    vl1re64.v v21, (a6)5199; RV64-NEXT:    add a6, a3, a25200; RV64-NEXT:    vl1re64.v v10, (a6)5201; RV64-NEXT:    add a6, a6, a25202; RV64-NEXT:    vl1re64.v v11, (a6)5203; RV64-NEXT:    vl1re64.v v8, (a0)5204; RV64-NEXT:    vl1re64.v v16, (a4)5205; RV64-NEXT:    vl1re64.v v9, (a3)5206; RV64-NEXT:    csrr a0, vlenb5207; RV64-NEXT:    li a3, 145208; RV64-NEXT:    mul a0, a0, a35209; RV64-NEXT:    add a0, sp, a05210; RV64-NEXT:    addi a0, a0, 645211; RV64-NEXT:    vl1re64.v v17, (a5)5212; RV64-NEXT:    slli a3, a2, 25213; RV64-NEXT:    add a6, a6, a25214; RV64-NEXT:    vl1re64.v v12, (a6)5215; RV64-NEXT:    add a6, a6, a25216; RV64-NEXT:    vl1re64.v v13, (a6)5217; RV64-NEXT:    add a6, a6, a25218; RV64-NEXT:    slli a2, a2, 35219; RV64-NEXT:    add a3, a2, a35220; RV64-NEXT:    add a2, a0, a25221; RV64-NEXT:    vl1re64.v v14, (a6)5222; RV64-NEXT:    vl1re64.v v15, (a1)5223; RV64-NEXT:    add a3, a0, a35224; RV64-NEXT:    vs2r.v v20, (a3)5225; RV64-NEXT:    vs4r.v v16, (a2)5226; RV64-NEXT:    vs8r.v v8, (a0)5227; RV64-NEXT:    vl8re64.v v16, (a2)5228; RV64-NEXT:    vl8re64.v v8, (a0)5229; RV64-NEXT:    addi sp, s0, -805230; RV64-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload5231; RV64-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload5232; RV64-NEXT:    addi sp, sp, 805233; RV64-NEXT:    ret5234;5235; ZVBB-RV32-LABEL: vector_interleave_nxv14i64_nxv2i64:5236; ZVBB-RV32:       # %bb.0:5237; ZVBB-RV32-NEXT:    addi sp, sp, -805238; ZVBB-RV32-NEXT:    sw ra, 76(sp) # 4-byte Folded Spill5239; ZVBB-RV32-NEXT:    sw s0, 72(sp) # 4-byte Folded Spill5240; ZVBB-RV32-NEXT:    addi s0, sp, 805241; ZVBB-RV32-NEXT:    csrr a0, vlenb5242; ZVBB-RV32-NEXT:    slli a0, a0, 55243; ZVBB-RV32-NEXT:    sub sp, sp, a05244; ZVBB-RV32-NEXT:    andi sp, sp, -645245; ZVBB-RV32-NEXT:    vsetvli a0, zero, e64, m1, ta, ma5246; ZVBB-RV32-NEXT:    vmv2r.v v26, v205247; ZVBB-RV32-NEXT:    addi a0, sp, 645248; ZVBB-RV32-NEXT:    vmv2r.v v24, v165249; ZVBB-RV32-NEXT:    vmv2r.v v22, v125250; ZVBB-RV32-NEXT:    vmv2r.v v20, v85251; ZVBB-RV32-NEXT:    vmv1r.v v1, v205252; ZVBB-RV32-NEXT:    vmv1r.v v3, v225253; ZVBB-RV32-NEXT:    vmv1r.v v5, v245254; ZVBB-RV32-NEXT:    vmv1r.v v7, v265255; ZVBB-RV32-NEXT:    vmv1r.v v2, v105256; ZVBB-RV32-NEXT:    csrr a1, vlenb5257; ZVBB-RV32-NEXT:    slli a2, a1, 35258; ZVBB-RV32-NEXT:    sub a1, a2, a15259; ZVBB-RV32-NEXT:    add a1, sp, a15260; ZVBB-RV32-NEXT:    addi a1, a1, 645261; ZVBB-RV32-NEXT:    csrr a2, vlenb5262; ZVBB-RV32-NEXT:    vmv1r.v v4, v145263; ZVBB-RV32-NEXT:    add a3, a0, a25264; ZVBB-RV32-NEXT:    add a4, a1, a25265; ZVBB-RV32-NEXT:    vmv1r.v v6, v185266; ZVBB-RV32-NEXT:    add a5, a4, a25267; ZVBB-RV32-NEXT:    vmv1r.v v22, v115268; ZVBB-RV32-NEXT:    add a6, a5, a25269; ZVBB-RV32-NEXT:    vmv1r.v v24, v155270; ZVBB-RV32-NEXT:    vsseg7e64.v v1, (a0)5271; ZVBB-RV32-NEXT:    vmv1r.v v26, v195272; ZVBB-RV32-NEXT:    vsseg7e64.v v21, (a1)5273; ZVBB-RV32-NEXT:    vl1re64.v v18, (a6)5274; ZVBB-RV32-NEXT:    add a6, a6, a25275; ZVBB-RV32-NEXT:    vl1re64.v v19, (a6)5276; ZVBB-RV32-NEXT:    add a6, a6, a25277; ZVBB-RV32-NEXT:    vl1re64.v v20, (a6)5278; ZVBB-RV32-NEXT:    add a6, a6, a25279; ZVBB-RV32-NEXT:    vl1re64.v v21, (a6)5280; ZVBB-RV32-NEXT:    add a6, a3, a25281; ZVBB-RV32-NEXT:    vl1re64.v v10, (a6)5282; ZVBB-RV32-NEXT:    add a6, a6, a25283; ZVBB-RV32-NEXT:    vl1re64.v v11, (a6)5284; ZVBB-RV32-NEXT:    vl1re64.v v8, (a0)5285; ZVBB-RV32-NEXT:    vl1re64.v v16, (a4)5286; ZVBB-RV32-NEXT:    vl1re64.v v9, (a3)5287; ZVBB-RV32-NEXT:    csrr a0, vlenb5288; ZVBB-RV32-NEXT:    li a3, 145289; ZVBB-RV32-NEXT:    mul a0, a0, a35290; ZVBB-RV32-NEXT:    add a0, sp, a05291; ZVBB-RV32-NEXT:    addi a0, a0, 645292; ZVBB-RV32-NEXT:    vl1re64.v v17, (a5)5293; ZVBB-RV32-NEXT:    slli a3, a2, 25294; ZVBB-RV32-NEXT:    add a6, a6, a25295; ZVBB-RV32-NEXT:    vl1re64.v v12, (a6)5296; ZVBB-RV32-NEXT:    add a6, a6, a25297; ZVBB-RV32-NEXT:    vl1re64.v v13, (a6)5298; ZVBB-RV32-NEXT:    add a6, a6, a25299; ZVBB-RV32-NEXT:    slli a2, a2, 35300; ZVBB-RV32-NEXT:    add a3, a2, a35301; ZVBB-RV32-NEXT:    add a2, a0, a25302; ZVBB-RV32-NEXT:    vl1re64.v v14, (a6)5303; ZVBB-RV32-NEXT:    vl1re64.v v15, (a1)5304; ZVBB-RV32-NEXT:    add a3, a0, a35305; ZVBB-RV32-NEXT:    vs2r.v v20, (a3)5306; ZVBB-RV32-NEXT:    vs4r.v v16, (a2)5307; ZVBB-RV32-NEXT:    vs8r.v v8, (a0)5308; ZVBB-RV32-NEXT:    vl8re64.v v16, (a2)5309; ZVBB-RV32-NEXT:    vl8re64.v v8, (a0)5310; ZVBB-RV32-NEXT:    addi sp, s0, -805311; ZVBB-RV32-NEXT:    lw ra, 76(sp) # 4-byte Folded Reload5312; ZVBB-RV32-NEXT:    lw s0, 72(sp) # 4-byte Folded Reload5313; ZVBB-RV32-NEXT:    addi sp, sp, 805314; ZVBB-RV32-NEXT:    ret5315;5316; ZVBB-RV64-LABEL: vector_interleave_nxv14i64_nxv2i64:5317; ZVBB-RV64:       # %bb.0:5318; ZVBB-RV64-NEXT:    addi sp, sp, -805319; ZVBB-RV64-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill5320; ZVBB-RV64-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill5321; ZVBB-RV64-NEXT:    addi s0, sp, 805322; ZVBB-RV64-NEXT:    csrr a0, vlenb5323; ZVBB-RV64-NEXT:    slli a0, a0, 55324; ZVBB-RV64-NEXT:    sub sp, sp, a05325; ZVBB-RV64-NEXT:    andi sp, sp, -645326; ZVBB-RV64-NEXT:    vsetvli a0, zero, e64, m1, ta, ma5327; ZVBB-RV64-NEXT:    vmv2r.v v26, v205328; ZVBB-RV64-NEXT:    addi a0, sp, 645329; ZVBB-RV64-NEXT:    vmv2r.v v24, v165330; ZVBB-RV64-NEXT:    vmv2r.v v22, v125331; ZVBB-RV64-NEXT:    vmv2r.v v20, v85332; ZVBB-RV64-NEXT:    vmv1r.v v1, v205333; ZVBB-RV64-NEXT:    vmv1r.v v3, v225334; ZVBB-RV64-NEXT:    vmv1r.v v5, v245335; ZVBB-RV64-NEXT:    vmv1r.v v7, v265336; ZVBB-RV64-NEXT:    vmv1r.v v2, v105337; ZVBB-RV64-NEXT:    csrr a1, vlenb5338; ZVBB-RV64-NEXT:    slli a2, a1, 35339; ZVBB-RV64-NEXT:    sub a1, a2, a15340; ZVBB-RV64-NEXT:    add a1, sp, a15341; ZVBB-RV64-NEXT:    addi a1, a1, 645342; ZVBB-RV64-NEXT:    csrr a2, vlenb5343; ZVBB-RV64-NEXT:    vmv1r.v v4, v145344; ZVBB-RV64-NEXT:    add a3, a0, a25345; ZVBB-RV64-NEXT:    add a4, a1, a25346; ZVBB-RV64-NEXT:    vmv1r.v v6, v185347; ZVBB-RV64-NEXT:    add a5, a4, a25348; ZVBB-RV64-NEXT:    vmv1r.v v22, v115349; ZVBB-RV64-NEXT:    add a6, a5, a25350; ZVBB-RV64-NEXT:    vmv1r.v v24, v155351; ZVBB-RV64-NEXT:    vsseg7e64.v v1, (a0)5352; ZVBB-RV64-NEXT:    vmv1r.v v26, v195353; ZVBB-RV64-NEXT:    vsseg7e64.v v21, (a1)5354; ZVBB-RV64-NEXT:    vl1re64.v v18, (a6)5355; ZVBB-RV64-NEXT:    add a6, a6, a25356; ZVBB-RV64-NEXT:    vl1re64.v v19, (a6)5357; ZVBB-RV64-NEXT:    add a6, a6, a25358; ZVBB-RV64-NEXT:    vl1re64.v v20, (a6)5359; ZVBB-RV64-NEXT:    add a6, a6, a25360; ZVBB-RV64-NEXT:    vl1re64.v v21, (a6)5361; ZVBB-RV64-NEXT:    add a6, a3, a25362; ZVBB-RV64-NEXT:    vl1re64.v v10, (a6)5363; ZVBB-RV64-NEXT:    add a6, a6, a25364; ZVBB-RV64-NEXT:    vl1re64.v v11, (a6)5365; ZVBB-RV64-NEXT:    vl1re64.v v8, (a0)5366; ZVBB-RV64-NEXT:    vl1re64.v v16, (a4)5367; ZVBB-RV64-NEXT:    vl1re64.v v9, (a3)5368; ZVBB-RV64-NEXT:    csrr a0, vlenb5369; ZVBB-RV64-NEXT:    li a3, 145370; ZVBB-RV64-NEXT:    mul a0, a0, a35371; ZVBB-RV64-NEXT:    add a0, sp, a05372; ZVBB-RV64-NEXT:    addi a0, a0, 645373; ZVBB-RV64-NEXT:    vl1re64.v v17, (a5)5374; ZVBB-RV64-NEXT:    slli a3, a2, 25375; ZVBB-RV64-NEXT:    add a6, a6, a25376; ZVBB-RV64-NEXT:    vl1re64.v v12, (a6)5377; ZVBB-RV64-NEXT:    add a6, a6, a25378; ZVBB-RV64-NEXT:    vl1re64.v v13, (a6)5379; ZVBB-RV64-NEXT:    add a6, a6, a25380; ZVBB-RV64-NEXT:    slli a2, a2, 35381; ZVBB-RV64-NEXT:    add a3, a2, a35382; ZVBB-RV64-NEXT:    add a2, a0, a25383; ZVBB-RV64-NEXT:    vl1re64.v v14, (a6)5384; ZVBB-RV64-NEXT:    vl1re64.v v15, (a1)5385; ZVBB-RV64-NEXT:    add a3, a0, a35386; ZVBB-RV64-NEXT:    vs2r.v v20, (a3)5387; ZVBB-RV64-NEXT:    vs4r.v v16, (a2)5388; ZVBB-RV64-NEXT:    vs8r.v v8, (a0)5389; ZVBB-RV64-NEXT:    vl8re64.v v16, (a2)5390; ZVBB-RV64-NEXT:    vl8re64.v v8, (a0)5391; ZVBB-RV64-NEXT:    addi sp, s0, -805392; ZVBB-RV64-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload5393; ZVBB-RV64-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload5394; ZVBB-RV64-NEXT:    addi sp, sp, 805395; ZVBB-RV64-NEXT:    ret5396;5397; ZIP-LABEL: vector_interleave_nxv14i64_nxv2i64:5398; ZIP:       # %bb.0:5399; ZIP-NEXT:    addi sp, sp, -805400; ZIP-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill5401; ZIP-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill5402; ZIP-NEXT:    addi s0, sp, 805403; ZIP-NEXT:    csrr a0, vlenb5404; ZIP-NEXT:    slli a0, a0, 55405; ZIP-NEXT:    sub sp, sp, a05406; ZIP-NEXT:    andi sp, sp, -645407; ZIP-NEXT:    vsetvli a0, zero, e64, m1, ta, ma5408; ZIP-NEXT:    vmv2r.v v26, v205409; ZIP-NEXT:    addi a0, sp, 645410; ZIP-NEXT:    vmv2r.v v24, v165411; ZIP-NEXT:    vmv2r.v v22, v125412; ZIP-NEXT:    vmv2r.v v20, v85413; ZIP-NEXT:    vmv1r.v v1, v205414; ZIP-NEXT:    vmv1r.v v3, v225415; ZIP-NEXT:    vmv1r.v v5, v245416; ZIP-NEXT:    vmv1r.v v7, v265417; ZIP-NEXT:    vmv1r.v v2, v105418; ZIP-NEXT:    csrr a1, vlenb5419; ZIP-NEXT:    slli a2, a1, 35420; ZIP-NEXT:    sub a1, a2, a15421; ZIP-NEXT:    add a1, sp, a15422; ZIP-NEXT:    addi a1, a1, 645423; ZIP-NEXT:    csrr a2, vlenb5424; ZIP-NEXT:    vmv1r.v v4, v145425; ZIP-NEXT:    add a3, a0, a25426; ZIP-NEXT:    add a4, a1, a25427; ZIP-NEXT:    vmv1r.v v6, v185428; ZIP-NEXT:    add a5, a4, a25429; ZIP-NEXT:    vmv1r.v v22, v115430; ZIP-NEXT:    add a6, a5, a25431; ZIP-NEXT:    vmv1r.v v24, v155432; ZIP-NEXT:    vsseg7e64.v v1, (a0)5433; ZIP-NEXT:    vmv1r.v v26, v195434; ZIP-NEXT:    vsseg7e64.v v21, (a1)5435; ZIP-NEXT:    vl1re64.v v18, (a6)5436; ZIP-NEXT:    add a6, a6, a25437; ZIP-NEXT:    vl1re64.v v19, (a6)5438; ZIP-NEXT:    add a6, a6, a25439; ZIP-NEXT:    vl1re64.v v20, (a6)5440; ZIP-NEXT:    add a6, a6, a25441; ZIP-NEXT:    vl1re64.v v21, (a6)5442; ZIP-NEXT:    add a6, a3, a25443; ZIP-NEXT:    vl1re64.v v10, (a6)5444; ZIP-NEXT:    add a6, a6, a25445; ZIP-NEXT:    vl1re64.v v11, (a6)5446; ZIP-NEXT:    vl1re64.v v8, (a0)5447; ZIP-NEXT:    vl1re64.v v16, (a4)5448; ZIP-NEXT:    vl1re64.v v9, (a3)5449; ZIP-NEXT:    csrr a0, vlenb5450; ZIP-NEXT:    li a3, 145451; ZIP-NEXT:    mul a0, a0, a35452; ZIP-NEXT:    add a0, sp, a05453; ZIP-NEXT:    addi a0, a0, 645454; ZIP-NEXT:    vl1re64.v v17, (a5)5455; ZIP-NEXT:    slli a3, a2, 25456; ZIP-NEXT:    add a6, a6, a25457; ZIP-NEXT:    vl1re64.v v12, (a6)5458; ZIP-NEXT:    add a6, a6, a25459; ZIP-NEXT:    vl1re64.v v13, (a6)5460; ZIP-NEXT:    add a6, a6, a25461; ZIP-NEXT:    slli a2, a2, 35462; ZIP-NEXT:    add a3, a2, a35463; ZIP-NEXT:    add a2, a0, a25464; ZIP-NEXT:    vl1re64.v v14, (a6)5465; ZIP-NEXT:    vl1re64.v v15, (a1)5466; ZIP-NEXT:    add a3, a0, a35467; ZIP-NEXT:    vs2r.v v20, (a3)5468; ZIP-NEXT:    vs4r.v v16, (a2)5469; ZIP-NEXT:    vs8r.v v8, (a0)5470; ZIP-NEXT:    vl8re64.v v16, (a2)5471; ZIP-NEXT:    vl8re64.v v8, (a0)5472; ZIP-NEXT:    addi sp, s0, -805473; ZIP-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload5474; ZIP-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload5475; ZIP-NEXT:    addi sp, sp, 805476; ZIP-NEXT:    ret5477  %res = call <vscale x 14 x i64> @llvm.vector.interleave7.nxv14i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c, <vscale x 2 x i64> %d, <vscale x 2 x i64> %e, <vscale x 2 x i64> %f, <vscale x 2 x i64> %g)5478  ret <vscale x 14 x i64> %res5479}5480 5481define <vscale x 128 x i1> @vector_interleave_nxv128i1_nxv16i1(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b, <vscale x 16 x i1> %c, <vscale x 16 x i1> %d, <vscale x 16 x i1> %e, <vscale x 16 x i1> %f, <vscale x 16 x i1> %g, <vscale x 16 x i1> %h) nounwind {5482; CHECK-LABEL: vector_interleave_nxv128i1_nxv16i1:5483; CHECK:       # %bb.0:5484; CHECK-NEXT:    addi sp, sp, -165485; CHECK-NEXT:    csrr a0, vlenb5486; CHECK-NEXT:    slli a0, a0, 45487; CHECK-NEXT:    sub sp, sp, a05488; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, ma5489; CHECK-NEXT:    vmv.v.i v22, 05490; CHECK-NEXT:    vmerge.vim v24, v22, 1, v05491; CHECK-NEXT:    vmv1r.v v0, v85492; CHECK-NEXT:    vmerge.vim v16, v22, 1, v05493; CHECK-NEXT:    vmv1r.v v1, v245494; CHECK-NEXT:    vmv1r.v v2, v165495; CHECK-NEXT:    vmv1r.v v0, v95496; CHECK-NEXT:    vmerge.vim v26, v22, 1, v05497; CHECK-NEXT:    vmv1r.v v0, v105498; CHECK-NEXT:    vmerge.vim v18, v22, 1, v05499; CHECK-NEXT:    vmv1r.v v3, v265500; CHECK-NEXT:    vmv1r.v v4, v185501; CHECK-NEXT:    vmv1r.v v0, v115502; CHECK-NEXT:    vmerge.vim v8, v22, 1, v05503; CHECK-NEXT:    vmv1r.v v0, v125504; CHECK-NEXT:    vmerge.vim v20, v22, 1, v05505; CHECK-NEXT:    vmv1r.v v5, v85506; CHECK-NEXT:    vmv1r.v v6, v205507; CHECK-NEXT:    vmv1r.v v0, v135508; CHECK-NEXT:    vmerge.vim v10, v22, 1, v05509; CHECK-NEXT:    vmv1r.v v0, v145510; CHECK-NEXT:    vmerge.vim v22, v22, 1, v05511; CHECK-NEXT:    vmv1r.v v7, v105512; CHECK-NEXT:    vmv1r.v v8, v225513; CHECK-NEXT:    vmv1r.v v16, v255514; CHECK-NEXT:    addi a2, sp, 165515; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma5516; CHECK-NEXT:    vsseg8e8.v v1, (a2)5517; CHECK-NEXT:    vmv1r.v v18, v275518; CHECK-NEXT:    csrr a1, vlenb5519; CHECK-NEXT:    slli a1, a1, 35520; CHECK-NEXT:    add a1, sp, a15521; CHECK-NEXT:    addi a1, a1, 165522; CHECK-NEXT:    csrr a0, vlenb5523; CHECK-NEXT:    add a3, a2, a05524; CHECK-NEXT:    add a4, a1, a05525; CHECK-NEXT:    add a5, a3, a05526; CHECK-NEXT:    add a6, a4, a05527; CHECK-NEXT:    add a7, a5, a05528; CHECK-NEXT:    add t0, a6, a05529; CHECK-NEXT:    vmv1r.v v20, v95530; CHECK-NEXT:    add t1, a7, a05531; CHECK-NEXT:    vmv1r.v v22, v115532; CHECK-NEXT:    vsseg8e8.v v16, (a1)5533; CHECK-NEXT:    vl1r.v v8, (a5)5534; CHECK-NEXT:    add a5, t0, a05535; CHECK-NEXT:    vl1r.v v12, (t1)5536; CHECK-NEXT:    add t1, t1, a05537; CHECK-NEXT:    vl1r.v v14, (a2)5538; CHECK-NEXT:    add a2, a5, a05539; CHECK-NEXT:    vl1r.v v10, (a5)5540; CHECK-NEXT:    add a5, t1, a05541; CHECK-NEXT:    vl1r.v v16, (a5)5542; CHECK-NEXT:    add a5, a5, a05543; CHECK-NEXT:    vl1r.v v17, (a5)5544; CHECK-NEXT:    add a5, a2, a05545; CHECK-NEXT:    vl1r.v v18, (a5)5546; CHECK-NEXT:    add a5, a5, a05547; CHECK-NEXT:    vl1r.v v13, (t1)5548; CHECK-NEXT:    vl1r.v v9, (a7)5549; CHECK-NEXT:    vl1r.v v15, (a3)5550; CHECK-NEXT:    vsetvli a3, zero, e8, m2, ta, ma5551; CHECK-NEXT:    vmsne.vi v20, v16, 05552; CHECK-NEXT:    vmsne.vi v16, v12, 05553; CHECK-NEXT:    vl1r.v v12, (a6)5554; CHECK-NEXT:    vmsne.vi v17, v8, 05555; CHECK-NEXT:    vmsne.vi v0, v14, 05556; CHECK-NEXT:    vl1r.v v14, (a1)5557; CHECK-NEXT:    vl1r.v v19, (a5)5558; CHECK-NEXT:    vl1r.v v11, (a2)5559; CHECK-NEXT:    vl1r.v v13, (t0)5560; CHECK-NEXT:    vl1r.v v15, (a4)5561; CHECK-NEXT:    vmsne.vi v9, v18, 05562; CHECK-NEXT:    vmsne.vi v18, v10, 05563; CHECK-NEXT:    vmsne.vi v10, v12, 05564; CHECK-NEXT:    vmsne.vi v8, v14, 05565; CHECK-NEXT:    srli a1, a0, 25566; CHECK-NEXT:    vsetvli a2, zero, e8, mf2, ta, ma5567; CHECK-NEXT:    vslideup.vx v16, v20, a15568; CHECK-NEXT:    vslideup.vx v0, v17, a15569; CHECK-NEXT:    vslideup.vx v18, v9, a15570; CHECK-NEXT:    vslideup.vx v8, v10, a15571; CHECK-NEXT:    srli a0, a0, 15572; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma5573; CHECK-NEXT:    vslideup.vx v0, v16, a05574; CHECK-NEXT:    vslideup.vx v8, v18, a05575; CHECK-NEXT:    csrr a0, vlenb5576; CHECK-NEXT:    slli a0, a0, 45577; CHECK-NEXT:    add sp, sp, a05578; CHECK-NEXT:    addi sp, sp, 165579; CHECK-NEXT:    ret5580;5581; ZVBB-LABEL: vector_interleave_nxv128i1_nxv16i1:5582; ZVBB:       # %bb.0:5583; ZVBB-NEXT:    addi sp, sp, -165584; ZVBB-NEXT:    csrr a0, vlenb5585; ZVBB-NEXT:    slli a0, a0, 45586; ZVBB-NEXT:    sub sp, sp, a05587; ZVBB-NEXT:    vsetvli a0, zero, e8, m2, ta, ma5588; ZVBB-NEXT:    vmv.v.i v22, 05589; ZVBB-NEXT:    vmerge.vim v24, v22, 1, v05590; ZVBB-NEXT:    vmv1r.v v0, v85591; ZVBB-NEXT:    vmerge.vim v16, v22, 1, v05592; ZVBB-NEXT:    vmv1r.v v1, v245593; ZVBB-NEXT:    vmv1r.v v2, v165594; ZVBB-NEXT:    vmv1r.v v0, v95595; ZVBB-NEXT:    vmerge.vim v26, v22, 1, v05596; ZVBB-NEXT:    vmv1r.v v0, v105597; ZVBB-NEXT:    vmerge.vim v18, v22, 1, v05598; ZVBB-NEXT:    vmv1r.v v3, v265599; ZVBB-NEXT:    vmv1r.v v4, v185600; ZVBB-NEXT:    vmv1r.v v0, v115601; ZVBB-NEXT:    vmerge.vim v8, v22, 1, v05602; ZVBB-NEXT:    vmv1r.v v0, v125603; ZVBB-NEXT:    vmerge.vim v20, v22, 1, v05604; ZVBB-NEXT:    vmv1r.v v5, v85605; ZVBB-NEXT:    vmv1r.v v6, v205606; ZVBB-NEXT:    vmv1r.v v0, v135607; ZVBB-NEXT:    vmerge.vim v10, v22, 1, v05608; ZVBB-NEXT:    vmv1r.v v0, v145609; ZVBB-NEXT:    vmerge.vim v22, v22, 1, v05610; ZVBB-NEXT:    vmv1r.v v7, v105611; ZVBB-NEXT:    vmv1r.v v8, v225612; ZVBB-NEXT:    vmv1r.v v16, v255613; ZVBB-NEXT:    addi a2, sp, 165614; ZVBB-NEXT:    vsetvli a0, zero, e8, m1, ta, ma5615; ZVBB-NEXT:    vsseg8e8.v v1, (a2)5616; ZVBB-NEXT:    vmv1r.v v18, v275617; ZVBB-NEXT:    csrr a1, vlenb5618; ZVBB-NEXT:    slli a1, a1, 35619; ZVBB-NEXT:    add a1, sp, a15620; ZVBB-NEXT:    addi a1, a1, 165621; ZVBB-NEXT:    csrr a0, vlenb5622; ZVBB-NEXT:    add a3, a2, a05623; ZVBB-NEXT:    add a4, a1, a05624; ZVBB-NEXT:    add a5, a3, a05625; ZVBB-NEXT:    add a6, a4, a05626; ZVBB-NEXT:    add a7, a5, a05627; ZVBB-NEXT:    add t0, a6, a05628; ZVBB-NEXT:    vmv1r.v v20, v95629; ZVBB-NEXT:    add t1, a7, a05630; ZVBB-NEXT:    vmv1r.v v22, v115631; ZVBB-NEXT:    vsseg8e8.v v16, (a1)5632; ZVBB-NEXT:    vl1r.v v8, (a5)5633; ZVBB-NEXT:    add a5, t0, a05634; ZVBB-NEXT:    vl1r.v v12, (t1)5635; ZVBB-NEXT:    add t1, t1, a05636; ZVBB-NEXT:    vl1r.v v14, (a2)5637; ZVBB-NEXT:    add a2, a5, a05638; ZVBB-NEXT:    vl1r.v v10, (a5)5639; ZVBB-NEXT:    add a5, t1, a05640; ZVBB-NEXT:    vl1r.v v16, (a5)5641; ZVBB-NEXT:    add a5, a5, a05642; ZVBB-NEXT:    vl1r.v v17, (a5)5643; ZVBB-NEXT:    add a5, a2, a05644; ZVBB-NEXT:    vl1r.v v18, (a5)5645; ZVBB-NEXT:    add a5, a5, a05646; ZVBB-NEXT:    vl1r.v v13, (t1)5647; ZVBB-NEXT:    vl1r.v v9, (a7)5648; ZVBB-NEXT:    vl1r.v v15, (a3)5649; ZVBB-NEXT:    vsetvli a3, zero, e8, m2, ta, ma5650; ZVBB-NEXT:    vmsne.vi v20, v16, 05651; ZVBB-NEXT:    vmsne.vi v16, v12, 05652; ZVBB-NEXT:    vl1r.v v12, (a6)5653; ZVBB-NEXT:    vmsne.vi v17, v8, 05654; ZVBB-NEXT:    vmsne.vi v0, v14, 05655; ZVBB-NEXT:    vl1r.v v14, (a1)5656; ZVBB-NEXT:    vl1r.v v19, (a5)5657; ZVBB-NEXT:    vl1r.v v11, (a2)5658; ZVBB-NEXT:    vl1r.v v13, (t0)5659; ZVBB-NEXT:    vl1r.v v15, (a4)5660; ZVBB-NEXT:    vmsne.vi v9, v18, 05661; ZVBB-NEXT:    vmsne.vi v18, v10, 05662; ZVBB-NEXT:    vmsne.vi v10, v12, 05663; ZVBB-NEXT:    vmsne.vi v8, v14, 05664; ZVBB-NEXT:    srli a1, a0, 25665; ZVBB-NEXT:    vsetvli a2, zero, e8, mf2, ta, ma5666; ZVBB-NEXT:    vslideup.vx v16, v20, a15667; ZVBB-NEXT:    vslideup.vx v0, v17, a15668; ZVBB-NEXT:    vslideup.vx v18, v9, a15669; ZVBB-NEXT:    vslideup.vx v8, v10, a15670; ZVBB-NEXT:    srli a0, a0, 15671; ZVBB-NEXT:    vsetvli a1, zero, e8, m1, ta, ma5672; ZVBB-NEXT:    vslideup.vx v0, v16, a05673; ZVBB-NEXT:    vslideup.vx v8, v18, a05674; ZVBB-NEXT:    csrr a0, vlenb5675; ZVBB-NEXT:    slli a0, a0, 45676; ZVBB-NEXT:    add sp, sp, a05677; ZVBB-NEXT:    addi sp, sp, 165678; ZVBB-NEXT:    ret5679  %res = call <vscale x 128 x i1> @llvm.vector.interleave8.nxv128i1(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b, <vscale x 16 x i1> %c, <vscale x 16 x i1> %d, <vscale x 16 x i1> %e, <vscale x 16 x i1> %f, <vscale x 16 x i1> %g, <vscale x 16 x i1> %h)5680  ret <vscale x 128 x i1> %res5681}5682 5683 5684define <vscale x 128 x i8> @vector_interleave_nxv128i8_nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c, <vscale x 16 x i8> %d, <vscale x 16 x i8> %e, <vscale x 16 x i8> %f, <vscale x 16 x i8> %g, <vscale x 16 x i8> %h) nounwind {5685;5686; CHECK-LABEL: vector_interleave_nxv128i8_nxv16i8:5687; CHECK:       # %bb.0:5688; CHECK-NEXT:    addi sp, sp, -165689; CHECK-NEXT:    csrr a0, vlenb5690; CHECK-NEXT:    slli a0, a0, 45691; CHECK-NEXT:    sub sp, sp, a05692; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma5693; CHECK-NEXT:    vmv2r.v v28, v225694; CHECK-NEXT:    addi a0, sp, 165695; CHECK-NEXT:    vmv2r.v v26, v185696; CHECK-NEXT:    csrr a1, vlenb5697; CHECK-NEXT:    slli a1, a1, 35698; CHECK-NEXT:    add a1, sp, a15699; CHECK-NEXT:    addi a1, a1, 165700; CHECK-NEXT:    csrr a3, vlenb5701; CHECK-NEXT:    add a2, a0, a35702; CHECK-NEXT:    add a4, a1, a35703; CHECK-NEXT:    add a5, a2, a35704; CHECK-NEXT:    vmv1r.v v1, v85705; CHECK-NEXT:    vmv2r.v v24, v145706; CHECK-NEXT:    add a6, a4, a35707; CHECK-NEXT:    vmv2r.v v22, v105708; CHECK-NEXT:    vmv1r.v v2, v225709; CHECK-NEXT:    add a7, a5, a35710; CHECK-NEXT:    vmv1r.v v3, v125711; CHECK-NEXT:    add t0, a6, a35712; CHECK-NEXT:    vmv1r.v v4, v245713; CHECK-NEXT:    add t1, a7, a35714; CHECK-NEXT:    vmv1r.v v5, v165715; CHECK-NEXT:    add t2, t0, a35716; CHECK-NEXT:    vmv1r.v v6, v265717; CHECK-NEXT:    add t3, t1, a35718; CHECK-NEXT:    vmv1r.v v7, v205719; CHECK-NEXT:    add t4, t2, a35720; CHECK-NEXT:    vmv1r.v v8, v285721; CHECK-NEXT:    vmv1r.v v22, v95722; CHECK-NEXT:    add t5, t3, a35723; CHECK-NEXT:    vmv1r.v v24, v135724; CHECK-NEXT:    add t6, t4, a35725; CHECK-NEXT:    vmv1r.v v26, v175726; CHECK-NEXT:    vsseg8e8.v v1, (a0)5727; CHECK-NEXT:    vmv1r.v v28, v215728; CHECK-NEXT:    vsseg8e8.v v22, (a1)5729; CHECK-NEXT:    vl1r.v v14, (t5)5730; CHECK-NEXT:    add t5, t5, a35731; CHECK-NEXT:    add a3, t6, a35732; CHECK-NEXT:    vl1r.v v22, (t6)5733; CHECK-NEXT:    vl1r.v v15, (t5)5734; CHECK-NEXT:    vl1r.v v23, (a3)5735; CHECK-NEXT:    vl1r.v v12, (t1)5736; CHECK-NEXT:    vl1r.v v20, (t2)5737; CHECK-NEXT:    vl1r.v v13, (t3)5738; CHECK-NEXT:    vl1r.v v21, (t4)5739; CHECK-NEXT:    vl1r.v v10, (a5)5740; CHECK-NEXT:    vl1r.v v18, (a6)5741; CHECK-NEXT:    vl1r.v v11, (a7)5742; CHECK-NEXT:    vl1r.v v19, (t0)5743; CHECK-NEXT:    vl1r.v v8, (a0)5744; CHECK-NEXT:    vl1r.v v16, (a1)5745; CHECK-NEXT:    vl1r.v v9, (a2)5746; CHECK-NEXT:    vl1r.v v17, (a4)5747; CHECK-NEXT:    csrr a0, vlenb5748; CHECK-NEXT:    slli a0, a0, 45749; CHECK-NEXT:    add sp, sp, a05750; CHECK-NEXT:    addi sp, sp, 165751; CHECK-NEXT:    ret5752;5753; ZVBB-LABEL: vector_interleave_nxv128i8_nxv16i8:5754; ZVBB:       # %bb.0:5755; ZVBB-NEXT:    addi sp, sp, -165756; ZVBB-NEXT:    csrr a0, vlenb5757; ZVBB-NEXT:    slli a0, a0, 45758; ZVBB-NEXT:    sub sp, sp, a05759; ZVBB-NEXT:    vsetvli a0, zero, e8, m1, ta, ma5760; ZVBB-NEXT:    vmv2r.v v28, v225761; ZVBB-NEXT:    addi a0, sp, 165762; ZVBB-NEXT:    vmv2r.v v26, v185763; ZVBB-NEXT:    csrr a1, vlenb5764; ZVBB-NEXT:    slli a1, a1, 35765; ZVBB-NEXT:    add a1, sp, a15766; ZVBB-NEXT:    addi a1, a1, 165767; ZVBB-NEXT:    csrr a3, vlenb5768; ZVBB-NEXT:    add a2, a0, a35769; ZVBB-NEXT:    add a4, a1, a35770; ZVBB-NEXT:    add a5, a2, a35771; ZVBB-NEXT:    vmv1r.v v1, v85772; ZVBB-NEXT:    vmv2r.v v24, v145773; ZVBB-NEXT:    add a6, a4, a35774; ZVBB-NEXT:    vmv2r.v v22, v105775; ZVBB-NEXT:    vmv1r.v v2, v225776; ZVBB-NEXT:    add a7, a5, a35777; ZVBB-NEXT:    vmv1r.v v3, v125778; ZVBB-NEXT:    add t0, a6, a35779; ZVBB-NEXT:    vmv1r.v v4, v245780; ZVBB-NEXT:    add t1, a7, a35781; ZVBB-NEXT:    vmv1r.v v5, v165782; ZVBB-NEXT:    add t2, t0, a35783; ZVBB-NEXT:    vmv1r.v v6, v265784; ZVBB-NEXT:    add t3, t1, a35785; ZVBB-NEXT:    vmv1r.v v7, v205786; ZVBB-NEXT:    add t4, t2, a35787; ZVBB-NEXT:    vmv1r.v v8, v285788; ZVBB-NEXT:    vmv1r.v v22, v95789; ZVBB-NEXT:    add t5, t3, a35790; ZVBB-NEXT:    vmv1r.v v24, v135791; ZVBB-NEXT:    add t6, t4, a35792; ZVBB-NEXT:    vmv1r.v v26, v175793; ZVBB-NEXT:    vsseg8e8.v v1, (a0)5794; ZVBB-NEXT:    vmv1r.v v28, v215795; ZVBB-NEXT:    vsseg8e8.v v22, (a1)5796; ZVBB-NEXT:    vl1r.v v14, (t5)5797; ZVBB-NEXT:    add t5, t5, a35798; ZVBB-NEXT:    add a3, t6, a35799; ZVBB-NEXT:    vl1r.v v22, (t6)5800; ZVBB-NEXT:    vl1r.v v15, (t5)5801; ZVBB-NEXT:    vl1r.v v23, (a3)5802; ZVBB-NEXT:    vl1r.v v12, (t1)5803; ZVBB-NEXT:    vl1r.v v20, (t2)5804; ZVBB-NEXT:    vl1r.v v13, (t3)5805; ZVBB-NEXT:    vl1r.v v21, (t4)5806; ZVBB-NEXT:    vl1r.v v10, (a5)5807; ZVBB-NEXT:    vl1r.v v18, (a6)5808; ZVBB-NEXT:    vl1r.v v11, (a7)5809; ZVBB-NEXT:    vl1r.v v19, (t0)5810; ZVBB-NEXT:    vl1r.v v8, (a0)5811; ZVBB-NEXT:    vl1r.v v16, (a1)5812; ZVBB-NEXT:    vl1r.v v9, (a2)5813; ZVBB-NEXT:    vl1r.v v17, (a4)5814; ZVBB-NEXT:    csrr a0, vlenb5815; ZVBB-NEXT:    slli a0, a0, 45816; ZVBB-NEXT:    add sp, sp, a05817; ZVBB-NEXT:    addi sp, sp, 165818; ZVBB-NEXT:    ret5819  %res = call <vscale x 128 x i8> @llvm.vector.interleave8.nxv128i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c, <vscale x 16 x i8> %d, <vscale x 16 x i8> %e, <vscale x 16 x i8> %f, <vscale x 16 x i8> %g, <vscale x 16 x i8> %h)5820  ret <vscale x 128 x i8> %res5821}5822 5823 5824define <vscale x 64 x i16> @vector_interleave_nxv64i16_nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c, <vscale x 8 x i16> %d, <vscale x 8 x i16> %e, <vscale x 8 x i16> %f, <vscale x 8 x i16> %g, <vscale x 8 x i16> %h) nounwind {5825;5826; CHECK-LABEL: vector_interleave_nxv64i16_nxv8i16:5827; CHECK:       # %bb.0:5828; CHECK-NEXT:    addi sp, sp, -165829; CHECK-NEXT:    csrr a0, vlenb5830; CHECK-NEXT:    slli a0, a0, 45831; CHECK-NEXT:    sub sp, sp, a05832; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma5833; CHECK-NEXT:    vmv2r.v v28, v225834; CHECK-NEXT:    addi a0, sp, 165835; CHECK-NEXT:    vmv2r.v v26, v185836; CHECK-NEXT:    csrr a1, vlenb5837; CHECK-NEXT:    slli a1, a1, 35838; CHECK-NEXT:    add a1, sp, a15839; CHECK-NEXT:    addi a1, a1, 165840; CHECK-NEXT:    csrr a3, vlenb5841; CHECK-NEXT:    add a2, a0, a35842; CHECK-NEXT:    add a4, a1, a35843; CHECK-NEXT:    add a5, a2, a35844; CHECK-NEXT:    vmv1r.v v1, v85845; CHECK-NEXT:    vmv2r.v v24, v145846; CHECK-NEXT:    add a6, a4, a35847; CHECK-NEXT:    vmv2r.v v22, v105848; CHECK-NEXT:    vmv1r.v v2, v225849; CHECK-NEXT:    add a7, a5, a35850; CHECK-NEXT:    vmv1r.v v3, v125851; CHECK-NEXT:    add t0, a6, a35852; CHECK-NEXT:    vmv1r.v v4, v245853; CHECK-NEXT:    add t1, a7, a35854; CHECK-NEXT:    vmv1r.v v5, v165855; CHECK-NEXT:    add t2, t0, a35856; CHECK-NEXT:    vmv1r.v v6, v265857; CHECK-NEXT:    add t3, t1, a35858; CHECK-NEXT:    vmv1r.v v7, v205859; CHECK-NEXT:    add t4, t2, a35860; CHECK-NEXT:    vmv1r.v v8, v285861; CHECK-NEXT:    vmv1r.v v22, v95862; CHECK-NEXT:    add t5, t3, a35863; CHECK-NEXT:    vmv1r.v v24, v135864; CHECK-NEXT:    add t6, t4, a35865; CHECK-NEXT:    vmv1r.v v26, v175866; CHECK-NEXT:    vsseg8e16.v v1, (a0)5867; CHECK-NEXT:    vmv1r.v v28, v215868; CHECK-NEXT:    vsseg8e16.v v22, (a1)5869; CHECK-NEXT:    vl1re16.v v14, (t5)5870; CHECK-NEXT:    add t5, t5, a35871; CHECK-NEXT:    add a3, t6, a35872; CHECK-NEXT:    vl1re16.v v22, (t6)5873; CHECK-NEXT:    vl1re16.v v15, (t5)5874; CHECK-NEXT:    vl1re16.v v23, (a3)5875; CHECK-NEXT:    vl1re16.v v12, (t1)5876; CHECK-NEXT:    vl1re16.v v20, (t2)5877; CHECK-NEXT:    vl1re16.v v13, (t3)5878; CHECK-NEXT:    vl1re16.v v21, (t4)5879; CHECK-NEXT:    vl1re16.v v10, (a5)5880; CHECK-NEXT:    vl1re16.v v18, (a6)5881; CHECK-NEXT:    vl1re16.v v11, (a7)5882; CHECK-NEXT:    vl1re16.v v19, (t0)5883; CHECK-NEXT:    vl1re16.v v8, (a0)5884; CHECK-NEXT:    vl1re16.v v16, (a1)5885; CHECK-NEXT:    vl1re16.v v9, (a2)5886; CHECK-NEXT:    vl1re16.v v17, (a4)5887; CHECK-NEXT:    csrr a0, vlenb5888; CHECK-NEXT:    slli a0, a0, 45889; CHECK-NEXT:    add sp, sp, a05890; CHECK-NEXT:    addi sp, sp, 165891; CHECK-NEXT:    ret5892;5893; ZVBB-LABEL: vector_interleave_nxv64i16_nxv8i16:5894; ZVBB:       # %bb.0:5895; ZVBB-NEXT:    addi sp, sp, -165896; ZVBB-NEXT:    csrr a0, vlenb5897; ZVBB-NEXT:    slli a0, a0, 45898; ZVBB-NEXT:    sub sp, sp, a05899; ZVBB-NEXT:    vsetvli a0, zero, e16, m1, ta, ma5900; ZVBB-NEXT:    vmv2r.v v28, v225901; ZVBB-NEXT:    addi a0, sp, 165902; ZVBB-NEXT:    vmv2r.v v26, v185903; ZVBB-NEXT:    csrr a1, vlenb5904; ZVBB-NEXT:    slli a1, a1, 35905; ZVBB-NEXT:    add a1, sp, a15906; ZVBB-NEXT:    addi a1, a1, 165907; ZVBB-NEXT:    csrr a3, vlenb5908; ZVBB-NEXT:    add a2, a0, a35909; ZVBB-NEXT:    add a4, a1, a35910; ZVBB-NEXT:    add a5, a2, a35911; ZVBB-NEXT:    vmv1r.v v1, v85912; ZVBB-NEXT:    vmv2r.v v24, v145913; ZVBB-NEXT:    add a6, a4, a35914; ZVBB-NEXT:    vmv2r.v v22, v105915; ZVBB-NEXT:    vmv1r.v v2, v225916; ZVBB-NEXT:    add a7, a5, a35917; ZVBB-NEXT:    vmv1r.v v3, v125918; ZVBB-NEXT:    add t0, a6, a35919; ZVBB-NEXT:    vmv1r.v v4, v245920; ZVBB-NEXT:    add t1, a7, a35921; ZVBB-NEXT:    vmv1r.v v5, v165922; ZVBB-NEXT:    add t2, t0, a35923; ZVBB-NEXT:    vmv1r.v v6, v265924; ZVBB-NEXT:    add t3, t1, a35925; ZVBB-NEXT:    vmv1r.v v7, v205926; ZVBB-NEXT:    add t4, t2, a35927; ZVBB-NEXT:    vmv1r.v v8, v285928; ZVBB-NEXT:    vmv1r.v v22, v95929; ZVBB-NEXT:    add t5, t3, a35930; ZVBB-NEXT:    vmv1r.v v24, v135931; ZVBB-NEXT:    add t6, t4, a35932; ZVBB-NEXT:    vmv1r.v v26, v175933; ZVBB-NEXT:    vsseg8e16.v v1, (a0)5934; ZVBB-NEXT:    vmv1r.v v28, v215935; ZVBB-NEXT:    vsseg8e16.v v22, (a1)5936; ZVBB-NEXT:    vl1re16.v v14, (t5)5937; ZVBB-NEXT:    add t5, t5, a35938; ZVBB-NEXT:    add a3, t6, a35939; ZVBB-NEXT:    vl1re16.v v22, (t6)5940; ZVBB-NEXT:    vl1re16.v v15, (t5)5941; ZVBB-NEXT:    vl1re16.v v23, (a3)5942; ZVBB-NEXT:    vl1re16.v v12, (t1)5943; ZVBB-NEXT:    vl1re16.v v20, (t2)5944; ZVBB-NEXT:    vl1re16.v v13, (t3)5945; ZVBB-NEXT:    vl1re16.v v21, (t4)5946; ZVBB-NEXT:    vl1re16.v v10, (a5)5947; ZVBB-NEXT:    vl1re16.v v18, (a6)5948; ZVBB-NEXT:    vl1re16.v v11, (a7)5949; ZVBB-NEXT:    vl1re16.v v19, (t0)5950; ZVBB-NEXT:    vl1re16.v v8, (a0)5951; ZVBB-NEXT:    vl1re16.v v16, (a1)5952; ZVBB-NEXT:    vl1re16.v v9, (a2)5953; ZVBB-NEXT:    vl1re16.v v17, (a4)5954; ZVBB-NEXT:    csrr a0, vlenb5955; ZVBB-NEXT:    slli a0, a0, 45956; ZVBB-NEXT:    add sp, sp, a05957; ZVBB-NEXT:    addi sp, sp, 165958; ZVBB-NEXT:    ret5959  %res = call <vscale x 64 x i16> @llvm.vector.interleave8.nxv64i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c, <vscale x 8 x i16> %d, <vscale x 8 x i16> %e, <vscale x 8 x i16> %f, <vscale x 8 x i16> %g, <vscale x 8 x i16> %h)5960  ret <vscale x 64 x i16> %res5961}5962 5963 5964define <vscale x 32 x i32> @vector_interleave_nxv32i32_nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c, <vscale x 4 x i32> %d, <vscale x 4 x i32> %e, <vscale x 4 x i32> %f, <vscale x 4 x i32> %g, <vscale x 4 x i32> %h) nounwind {5965;5966; CHECK-LABEL: vector_interleave_nxv32i32_nxv4i32:5967; CHECK:       # %bb.0:5968; CHECK-NEXT:    addi sp, sp, -165969; CHECK-NEXT:    csrr a0, vlenb5970; CHECK-NEXT:    slli a0, a0, 45971; CHECK-NEXT:    sub sp, sp, a05972; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma5973; CHECK-NEXT:    vmv2r.v v28, v225974; CHECK-NEXT:    addi a0, sp, 165975; CHECK-NEXT:    vmv2r.v v26, v185976; CHECK-NEXT:    csrr a1, vlenb5977; CHECK-NEXT:    slli a1, a1, 35978; CHECK-NEXT:    add a1, sp, a15979; CHECK-NEXT:    addi a1, a1, 165980; CHECK-NEXT:    csrr a3, vlenb5981; CHECK-NEXT:    add a2, a0, a35982; CHECK-NEXT:    add a4, a1, a35983; CHECK-NEXT:    add a5, a2, a35984; CHECK-NEXT:    vmv1r.v v1, v85985; CHECK-NEXT:    vmv2r.v v24, v145986; CHECK-NEXT:    add a6, a4, a35987; CHECK-NEXT:    vmv2r.v v22, v105988; CHECK-NEXT:    vmv1r.v v2, v225989; CHECK-NEXT:    add a7, a5, a35990; CHECK-NEXT:    vmv1r.v v3, v125991; CHECK-NEXT:    add t0, a6, a35992; CHECK-NEXT:    vmv1r.v v4, v245993; CHECK-NEXT:    add t1, a7, a35994; CHECK-NEXT:    vmv1r.v v5, v165995; CHECK-NEXT:    add t2, t0, a35996; CHECK-NEXT:    vmv1r.v v6, v265997; CHECK-NEXT:    add t3, t1, a35998; CHECK-NEXT:    vmv1r.v v7, v205999; CHECK-NEXT:    add t4, t2, a36000; CHECK-NEXT:    vmv1r.v v8, v286001; CHECK-NEXT:    vmv1r.v v22, v96002; CHECK-NEXT:    add t5, t3, a36003; CHECK-NEXT:    vmv1r.v v24, v136004; CHECK-NEXT:    add t6, t4, a36005; CHECK-NEXT:    vmv1r.v v26, v176006; CHECK-NEXT:    vsseg8e32.v v1, (a0)6007; CHECK-NEXT:    vmv1r.v v28, v216008; CHECK-NEXT:    vsseg8e32.v v22, (a1)6009; CHECK-NEXT:    vl1re32.v v14, (t5)6010; CHECK-NEXT:    add t5, t5, a36011; CHECK-NEXT:    add a3, t6, a36012; CHECK-NEXT:    vl1re32.v v22, (t6)6013; CHECK-NEXT:    vl1re32.v v15, (t5)6014; CHECK-NEXT:    vl1re32.v v23, (a3)6015; CHECK-NEXT:    vl1re32.v v12, (t1)6016; CHECK-NEXT:    vl1re32.v v20, (t2)6017; CHECK-NEXT:    vl1re32.v v13, (t3)6018; CHECK-NEXT:    vl1re32.v v21, (t4)6019; CHECK-NEXT:    vl1re32.v v10, (a5)6020; CHECK-NEXT:    vl1re32.v v18, (a6)6021; CHECK-NEXT:    vl1re32.v v11, (a7)6022; CHECK-NEXT:    vl1re32.v v19, (t0)6023; CHECK-NEXT:    vl1re32.v v8, (a0)6024; CHECK-NEXT:    vl1re32.v v16, (a1)6025; CHECK-NEXT:    vl1re32.v v9, (a2)6026; CHECK-NEXT:    vl1re32.v v17, (a4)6027; CHECK-NEXT:    csrr a0, vlenb6028; CHECK-NEXT:    slli a0, a0, 46029; CHECK-NEXT:    add sp, sp, a06030; CHECK-NEXT:    addi sp, sp, 166031; CHECK-NEXT:    ret6032;6033; ZVBB-LABEL: vector_interleave_nxv32i32_nxv4i32:6034; ZVBB:       # %bb.0:6035; ZVBB-NEXT:    addi sp, sp, -166036; ZVBB-NEXT:    csrr a0, vlenb6037; ZVBB-NEXT:    slli a0, a0, 46038; ZVBB-NEXT:    sub sp, sp, a06039; ZVBB-NEXT:    vsetvli a0, zero, e32, m1, ta, ma6040; ZVBB-NEXT:    vmv2r.v v28, v226041; ZVBB-NEXT:    addi a0, sp, 166042; ZVBB-NEXT:    vmv2r.v v26, v186043; ZVBB-NEXT:    csrr a1, vlenb6044; ZVBB-NEXT:    slli a1, a1, 36045; ZVBB-NEXT:    add a1, sp, a16046; ZVBB-NEXT:    addi a1, a1, 166047; ZVBB-NEXT:    csrr a3, vlenb6048; ZVBB-NEXT:    add a2, a0, a36049; ZVBB-NEXT:    add a4, a1, a36050; ZVBB-NEXT:    add a5, a2, a36051; ZVBB-NEXT:    vmv1r.v v1, v86052; ZVBB-NEXT:    vmv2r.v v24, v146053; ZVBB-NEXT:    add a6, a4, a36054; ZVBB-NEXT:    vmv2r.v v22, v106055; ZVBB-NEXT:    vmv1r.v v2, v226056; ZVBB-NEXT:    add a7, a5, a36057; ZVBB-NEXT:    vmv1r.v v3, v126058; ZVBB-NEXT:    add t0, a6, a36059; ZVBB-NEXT:    vmv1r.v v4, v246060; ZVBB-NEXT:    add t1, a7, a36061; ZVBB-NEXT:    vmv1r.v v5, v166062; ZVBB-NEXT:    add t2, t0, a36063; ZVBB-NEXT:    vmv1r.v v6, v266064; ZVBB-NEXT:    add t3, t1, a36065; ZVBB-NEXT:    vmv1r.v v7, v206066; ZVBB-NEXT:    add t4, t2, a36067; ZVBB-NEXT:    vmv1r.v v8, v286068; ZVBB-NEXT:    vmv1r.v v22, v96069; ZVBB-NEXT:    add t5, t3, a36070; ZVBB-NEXT:    vmv1r.v v24, v136071; ZVBB-NEXT:    add t6, t4, a36072; ZVBB-NEXT:    vmv1r.v v26, v176073; ZVBB-NEXT:    vsseg8e32.v v1, (a0)6074; ZVBB-NEXT:    vmv1r.v v28, v216075; ZVBB-NEXT:    vsseg8e32.v v22, (a1)6076; ZVBB-NEXT:    vl1re32.v v14, (t5)6077; ZVBB-NEXT:    add t5, t5, a36078; ZVBB-NEXT:    add a3, t6, a36079; ZVBB-NEXT:    vl1re32.v v22, (t6)6080; ZVBB-NEXT:    vl1re32.v v15, (t5)6081; ZVBB-NEXT:    vl1re32.v v23, (a3)6082; ZVBB-NEXT:    vl1re32.v v12, (t1)6083; ZVBB-NEXT:    vl1re32.v v20, (t2)6084; ZVBB-NEXT:    vl1re32.v v13, (t3)6085; ZVBB-NEXT:    vl1re32.v v21, (t4)6086; ZVBB-NEXT:    vl1re32.v v10, (a5)6087; ZVBB-NEXT:    vl1re32.v v18, (a6)6088; ZVBB-NEXT:    vl1re32.v v11, (a7)6089; ZVBB-NEXT:    vl1re32.v v19, (t0)6090; ZVBB-NEXT:    vl1re32.v v8, (a0)6091; ZVBB-NEXT:    vl1re32.v v16, (a1)6092; ZVBB-NEXT:    vl1re32.v v9, (a2)6093; ZVBB-NEXT:    vl1re32.v v17, (a4)6094; ZVBB-NEXT:    csrr a0, vlenb6095; ZVBB-NEXT:    slli a0, a0, 46096; ZVBB-NEXT:    add sp, sp, a06097; ZVBB-NEXT:    addi sp, sp, 166098; ZVBB-NEXT:    ret6099  %res = call <vscale x 32 x i32> @llvm.vector.interleave8.nxv32i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c, <vscale x 4 x i32> %d, <vscale x 4 x i32> %e, <vscale x 4 x i32> %f, <vscale x 4 x i32> %g, <vscale x 4 x i32> %h)6100  ret <vscale x 32 x i32> %res6101}6102 6103define <vscale x 16 x i64> @vector_interleave_nxv16i64_nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c, <vscale x 2 x i64> %d, <vscale x 2 x i64> %e, <vscale x 2 x i64> %f, <vscale x 2 x i64> %g, <vscale x 2 x i64> %h) nounwind {6104;6105; CHECK-LABEL: vector_interleave_nxv16i64_nxv2i64:6106; CHECK:       # %bb.0:6107; CHECK-NEXT:    addi sp, sp, -166108; CHECK-NEXT:    csrr a0, vlenb6109; CHECK-NEXT:    slli a0, a0, 46110; CHECK-NEXT:    sub sp, sp, a06111; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, ma6112; CHECK-NEXT:    vmv2r.v v28, v226113; CHECK-NEXT:    addi a0, sp, 166114; CHECK-NEXT:    vmv2r.v v26, v186115; CHECK-NEXT:    csrr a1, vlenb6116; CHECK-NEXT:    slli a1, a1, 36117; CHECK-NEXT:    add a1, sp, a16118; CHECK-NEXT:    addi a1, a1, 166119; CHECK-NEXT:    csrr a3, vlenb6120; CHECK-NEXT:    add a2, a0, a36121; CHECK-NEXT:    add a4, a1, a36122; CHECK-NEXT:    add a5, a2, a36123; CHECK-NEXT:    vmv1r.v v1, v86124; CHECK-NEXT:    vmv2r.v v24, v146125; CHECK-NEXT:    add a6, a4, a36126; CHECK-NEXT:    vmv2r.v v22, v106127; CHECK-NEXT:    vmv1r.v v2, v226128; CHECK-NEXT:    add a7, a5, a36129; CHECK-NEXT:    vmv1r.v v3, v126130; CHECK-NEXT:    add t0, a6, a36131; CHECK-NEXT:    vmv1r.v v4, v246132; CHECK-NEXT:    add t1, a7, a36133; CHECK-NEXT:    vmv1r.v v5, v166134; CHECK-NEXT:    add t2, t0, a36135; CHECK-NEXT:    vmv1r.v v6, v266136; CHECK-NEXT:    add t3, t1, a36137; CHECK-NEXT:    vmv1r.v v7, v206138; CHECK-NEXT:    add t4, t2, a36139; CHECK-NEXT:    vmv1r.v v8, v286140; CHECK-NEXT:    vmv1r.v v22, v96141; CHECK-NEXT:    add t5, t3, a36142; CHECK-NEXT:    vmv1r.v v24, v136143; CHECK-NEXT:    add t6, t4, a36144; CHECK-NEXT:    vmv1r.v v26, v176145; CHECK-NEXT:    vsseg8e64.v v1, (a0)6146; CHECK-NEXT:    vmv1r.v v28, v216147; CHECK-NEXT:    vsseg8e64.v v22, (a1)6148; CHECK-NEXT:    vl1re64.v v14, (t5)6149; CHECK-NEXT:    add t5, t5, a36150; CHECK-NEXT:    add a3, t6, a36151; CHECK-NEXT:    vl1re64.v v22, (t6)6152; CHECK-NEXT:    vl1re64.v v15, (t5)6153; CHECK-NEXT:    vl1re64.v v23, (a3)6154; CHECK-NEXT:    vl1re64.v v12, (t1)6155; CHECK-NEXT:    vl1re64.v v20, (t2)6156; CHECK-NEXT:    vl1re64.v v13, (t3)6157; CHECK-NEXT:    vl1re64.v v21, (t4)6158; CHECK-NEXT:    vl1re64.v v10, (a5)6159; CHECK-NEXT:    vl1re64.v v18, (a6)6160; CHECK-NEXT:    vl1re64.v v11, (a7)6161; CHECK-NEXT:    vl1re64.v v19, (t0)6162; CHECK-NEXT:    vl1re64.v v8, (a0)6163; CHECK-NEXT:    vl1re64.v v16, (a1)6164; CHECK-NEXT:    vl1re64.v v9, (a2)6165; CHECK-NEXT:    vl1re64.v v17, (a4)6166; CHECK-NEXT:    csrr a0, vlenb6167; CHECK-NEXT:    slli a0, a0, 46168; CHECK-NEXT:    add sp, sp, a06169; CHECK-NEXT:    addi sp, sp, 166170; CHECK-NEXT:    ret6171;6172; ZVBB-LABEL: vector_interleave_nxv16i64_nxv2i64:6173; ZVBB:       # %bb.0:6174; ZVBB-NEXT:    addi sp, sp, -166175; ZVBB-NEXT:    csrr a0, vlenb6176; ZVBB-NEXT:    slli a0, a0, 46177; ZVBB-NEXT:    sub sp, sp, a06178; ZVBB-NEXT:    vsetvli a0, zero, e64, m1, ta, ma6179; ZVBB-NEXT:    vmv2r.v v28, v226180; ZVBB-NEXT:    addi a0, sp, 166181; ZVBB-NEXT:    vmv2r.v v26, v186182; ZVBB-NEXT:    csrr a1, vlenb6183; ZVBB-NEXT:    slli a1, a1, 36184; ZVBB-NEXT:    add a1, sp, a16185; ZVBB-NEXT:    addi a1, a1, 166186; ZVBB-NEXT:    csrr a3, vlenb6187; ZVBB-NEXT:    add a2, a0, a36188; ZVBB-NEXT:    add a4, a1, a36189; ZVBB-NEXT:    add a5, a2, a36190; ZVBB-NEXT:    vmv1r.v v1, v86191; ZVBB-NEXT:    vmv2r.v v24, v146192; ZVBB-NEXT:    add a6, a4, a36193; ZVBB-NEXT:    vmv2r.v v22, v106194; ZVBB-NEXT:    vmv1r.v v2, v226195; ZVBB-NEXT:    add a7, a5, a36196; ZVBB-NEXT:    vmv1r.v v3, v126197; ZVBB-NEXT:    add t0, a6, a36198; ZVBB-NEXT:    vmv1r.v v4, v246199; ZVBB-NEXT:    add t1, a7, a36200; ZVBB-NEXT:    vmv1r.v v5, v166201; ZVBB-NEXT:    add t2, t0, a36202; ZVBB-NEXT:    vmv1r.v v6, v266203; ZVBB-NEXT:    add t3, t1, a36204; ZVBB-NEXT:    vmv1r.v v7, v206205; ZVBB-NEXT:    add t4, t2, a36206; ZVBB-NEXT:    vmv1r.v v8, v286207; ZVBB-NEXT:    vmv1r.v v22, v96208; ZVBB-NEXT:    add t5, t3, a36209; ZVBB-NEXT:    vmv1r.v v24, v136210; ZVBB-NEXT:    add t6, t4, a36211; ZVBB-NEXT:    vmv1r.v v26, v176212; ZVBB-NEXT:    vsseg8e64.v v1, (a0)6213; ZVBB-NEXT:    vmv1r.v v28, v216214; ZVBB-NEXT:    vsseg8e64.v v22, (a1)6215; ZVBB-NEXT:    vl1re64.v v14, (t5)6216; ZVBB-NEXT:    add t5, t5, a36217; ZVBB-NEXT:    add a3, t6, a36218; ZVBB-NEXT:    vl1re64.v v22, (t6)6219; ZVBB-NEXT:    vl1re64.v v15, (t5)6220; ZVBB-NEXT:    vl1re64.v v23, (a3)6221; ZVBB-NEXT:    vl1re64.v v12, (t1)6222; ZVBB-NEXT:    vl1re64.v v20, (t2)6223; ZVBB-NEXT:    vl1re64.v v13, (t3)6224; ZVBB-NEXT:    vl1re64.v v21, (t4)6225; ZVBB-NEXT:    vl1re64.v v10, (a5)6226; ZVBB-NEXT:    vl1re64.v v18, (a6)6227; ZVBB-NEXT:    vl1re64.v v11, (a7)6228; ZVBB-NEXT:    vl1re64.v v19, (t0)6229; ZVBB-NEXT:    vl1re64.v v8, (a0)6230; ZVBB-NEXT:    vl1re64.v v16, (a1)6231; ZVBB-NEXT:    vl1re64.v v9, (a2)6232; ZVBB-NEXT:    vl1re64.v v17, (a4)6233; ZVBB-NEXT:    csrr a0, vlenb6234; ZVBB-NEXT:    slli a0, a0, 46235; ZVBB-NEXT:    add sp, sp, a06236; ZVBB-NEXT:    addi sp, sp, 166237; ZVBB-NEXT:    ret6238  %res = call <vscale x 16 x i64> @llvm.vector.interleave8.nxv16i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c, <vscale x 2 x i64> %d, <vscale x 2 x i64> %e, <vscale x 2 x i64> %f, <vscale x 2 x i64> %g, <vscale x 2 x i64> %h)6239  ret <vscale x 16 x i64> %res6240}6241 6242; Floats6243 6244define <vscale x 4 x bfloat> @vector_interleave_nxv4bf16_nxv2bf16(<vscale x 2 x bfloat> %a, <vscale x 2 x bfloat> %b) {6245; V-LABEL: vector_interleave_nxv4bf16_nxv2bf16:6246; V:       # %bb.0:6247; V-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma6248; V-NEXT:    vwaddu.vv v10, v8, v96249; V-NEXT:    li a0, -16250; V-NEXT:    vwmaccu.vx v10, a0, v96251; V-NEXT:    csrr a0, vlenb6252; V-NEXT:    srli a0, a0, 26253; V-NEXT:    vsetvli a1, zero, e16, m1, ta, ma6254; V-NEXT:    vslidedown.vx v8, v10, a06255; V-NEXT:    vslideup.vx v10, v8, a06256; V-NEXT:    vmv.v.v v8, v106257; V-NEXT:    ret6258;6259; ZVBB-LABEL: vector_interleave_nxv4bf16_nxv2bf16:6260; ZVBB:       # %bb.0:6261; ZVBB-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma6262; ZVBB-NEXT:    vwsll.vi v10, v9, 166263; ZVBB-NEXT:    csrr a0, vlenb6264; ZVBB-NEXT:    vwaddu.wv v10, v10, v86265; ZVBB-NEXT:    srli a0, a0, 26266; ZVBB-NEXT:    vsetvli a1, zero, e16, m1, ta, ma6267; ZVBB-NEXT:    vslidedown.vx v8, v10, a06268; ZVBB-NEXT:    vslideup.vx v10, v8, a06269; ZVBB-NEXT:    vmv.v.v v8, v106270; ZVBB-NEXT:    ret6271;6272; ZIP-LABEL: vector_interleave_nxv4bf16_nxv2bf16:6273; ZIP:       # %bb.0:6274; ZIP-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma6275; ZIP-NEXT:    ri.vzip2b.vv v11, v8, v96276; ZIP-NEXT:    ri.vzip2a.vv v10, v8, v96277; ZIP-NEXT:    csrr a0, vlenb6278; ZIP-NEXT:    srli a0, a0, 26279; ZIP-NEXT:    vsetvli a1, zero, e16, m1, ta, ma6280; ZIP-NEXT:    vslideup.vx v10, v11, a06281; ZIP-NEXT:    vmv.v.v v8, v106282; ZIP-NEXT:    ret6283  %res = call <vscale x 4 x bfloat> @llvm.vector.interleave2.nxv4bf16(<vscale x 2 x bfloat> %a, <vscale x 2 x bfloat> %b)6284  ret <vscale x 4 x bfloat> %res6285}6286 6287define <vscale x 8 x bfloat> @vector_interleave_nxv8bf16_nxv4bf16(<vscale x 4 x bfloat> %a, <vscale x 4 x bfloat> %b) {6288; V-LABEL: vector_interleave_nxv8bf16_nxv4bf16:6289; V:       # %bb.0:6290; V-NEXT:    vsetvli a0, zero, e16, m1, ta, ma6291; V-NEXT:    vmv1r.v v10, v96292; V-NEXT:    vmv1r.v v11, v86293; V-NEXT:    vwaddu.vv v8, v11, v106294; V-NEXT:    li a0, -16295; V-NEXT:    vwmaccu.vx v8, a0, v106296; V-NEXT:    ret6297;6298; ZVBB-LABEL: vector_interleave_nxv8bf16_nxv4bf16:6299; ZVBB:       # %bb.0:6300; ZVBB-NEXT:    vsetvli a0, zero, e16, m1, ta, ma6301; ZVBB-NEXT:    vmv1r.v v10, v96302; ZVBB-NEXT:    vmv1r.v v11, v86303; ZVBB-NEXT:    vwsll.vi v8, v10, 166304; ZVBB-NEXT:    vwaddu.wv v8, v8, v116305; ZVBB-NEXT:    ret6306;6307; ZIP-LABEL: vector_interleave_nxv8bf16_nxv4bf16:6308; ZIP:       # %bb.0:6309; ZIP-NEXT:    vsetvli a0, zero, e16, m1, ta, ma6310; ZIP-NEXT:    vmv1r.v v10, v96311; ZIP-NEXT:    vmv1r.v v11, v86312; ZIP-NEXT:    ri.vzip2b.vv v9, v8, v106313; ZIP-NEXT:    ri.vzip2a.vv v8, v11, v106314; ZIP-NEXT:    ret6315  %res = call <vscale x 8 x bfloat> @llvm.vector.interleave2.nxv8bf16(<vscale x 4 x bfloat> %a, <vscale x 4 x bfloat> %b)6316  ret <vscale x 8 x bfloat> %res6317}6318 6319define <vscale x 4 x half> @vector_interleave_nxv4f16_nxv2f16(<vscale x 2 x half> %a, <vscale x 2 x half> %b) {6320; V-LABEL: vector_interleave_nxv4f16_nxv2f16:6321; V:       # %bb.0:6322; V-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma6323; V-NEXT:    vwaddu.vv v10, v8, v96324; V-NEXT:    li a0, -16325; V-NEXT:    vwmaccu.vx v10, a0, v96326; V-NEXT:    csrr a0, vlenb6327; V-NEXT:    srli a0, a0, 26328; V-NEXT:    vsetvli a1, zero, e16, m1, ta, ma6329; V-NEXT:    vslidedown.vx v8, v10, a06330; V-NEXT:    vslideup.vx v10, v8, a06331; V-NEXT:    vmv.v.v v8, v106332; V-NEXT:    ret6333;6334; ZVBB-LABEL: vector_interleave_nxv4f16_nxv2f16:6335; ZVBB:       # %bb.0:6336; ZVBB-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma6337; ZVBB-NEXT:    vwsll.vi v10, v9, 166338; ZVBB-NEXT:    csrr a0, vlenb6339; ZVBB-NEXT:    vwaddu.wv v10, v10, v86340; ZVBB-NEXT:    srli a0, a0, 26341; ZVBB-NEXT:    vsetvli a1, zero, e16, m1, ta, ma6342; ZVBB-NEXT:    vslidedown.vx v8, v10, a06343; ZVBB-NEXT:    vslideup.vx v10, v8, a06344; ZVBB-NEXT:    vmv.v.v v8, v106345; ZVBB-NEXT:    ret6346;6347; ZIP-LABEL: vector_interleave_nxv4f16_nxv2f16:6348; ZIP:       # %bb.0:6349; ZIP-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma6350; ZIP-NEXT:    ri.vzip2b.vv v11, v8, v96351; ZIP-NEXT:    ri.vzip2a.vv v10, v8, v96352; ZIP-NEXT:    csrr a0, vlenb6353; ZIP-NEXT:    srli a0, a0, 26354; ZIP-NEXT:    vsetvli a1, zero, e16, m1, ta, ma6355; ZIP-NEXT:    vslideup.vx v10, v11, a06356; ZIP-NEXT:    vmv.v.v v8, v106357; ZIP-NEXT:    ret6358  %res = call <vscale x 4 x half> @llvm.vector.interleave2.nxv4f16(<vscale x 2 x half> %a, <vscale x 2 x half> %b)6359  ret <vscale x 4 x half> %res6360}6361 6362define <vscale x 8 x half> @vector_interleave_nxv8f16_nxv4f16(<vscale x 4 x half> %a, <vscale x 4 x half> %b) {6363; V-LABEL: vector_interleave_nxv8f16_nxv4f16:6364; V:       # %bb.0:6365; V-NEXT:    vsetvli a0, zero, e16, m1, ta, ma6366; V-NEXT:    vmv1r.v v10, v96367; V-NEXT:    vmv1r.v v11, v86368; V-NEXT:    vwaddu.vv v8, v11, v106369; V-NEXT:    li a0, -16370; V-NEXT:    vwmaccu.vx v8, a0, v106371; V-NEXT:    ret6372;6373; ZVBB-LABEL: vector_interleave_nxv8f16_nxv4f16:6374; ZVBB:       # %bb.0:6375; ZVBB-NEXT:    vsetvli a0, zero, e16, m1, ta, ma6376; ZVBB-NEXT:    vmv1r.v v10, v96377; ZVBB-NEXT:    vmv1r.v v11, v86378; ZVBB-NEXT:    vwsll.vi v8, v10, 166379; ZVBB-NEXT:    vwaddu.wv v8, v8, v116380; ZVBB-NEXT:    ret6381;6382; ZIP-LABEL: vector_interleave_nxv8f16_nxv4f16:6383; ZIP:       # %bb.0:6384; ZIP-NEXT:    vsetvli a0, zero, e16, m1, ta, ma6385; ZIP-NEXT:    vmv1r.v v10, v96386; ZIP-NEXT:    vmv1r.v v11, v86387; ZIP-NEXT:    ri.vzip2b.vv v9, v8, v106388; ZIP-NEXT:    ri.vzip2a.vv v8, v11, v106389; ZIP-NEXT:    ret6390  %res = call <vscale x 8 x half> @llvm.vector.interleave2.nxv8f16(<vscale x 4 x half> %a, <vscale x 4 x half> %b)6391  ret <vscale x 8 x half> %res6392}6393 6394define <vscale x 4 x float> @vector_interleave_nxv4f32_nxv2f32(<vscale x 2 x float> %a, <vscale x 2 x float> %b) {6395; V-LABEL: vector_interleave_nxv4f32_nxv2f32:6396; V:       # %bb.0:6397; V-NEXT:    vsetvli a0, zero, e32, m1, ta, ma6398; V-NEXT:    vmv1r.v v10, v96399; V-NEXT:    vmv1r.v v11, v86400; V-NEXT:    vwaddu.vv v8, v11, v106401; V-NEXT:    li a0, -16402; V-NEXT:    vwmaccu.vx v8, a0, v106403; V-NEXT:    ret6404;6405; ZVBB-LABEL: vector_interleave_nxv4f32_nxv2f32:6406; ZVBB:       # %bb.0:6407; ZVBB-NEXT:    vsetvli a0, zero, e32, m1, ta, ma6408; ZVBB-NEXT:    vmv1r.v v10, v96409; ZVBB-NEXT:    vmv1r.v v11, v86410; ZVBB-NEXT:    li a0, 326411; ZVBB-NEXT:    vwsll.vx v8, v10, a06412; ZVBB-NEXT:    vwaddu.wv v8, v8, v116413; ZVBB-NEXT:    ret6414;6415; ZIP-LABEL: vector_interleave_nxv4f32_nxv2f32:6416; ZIP:       # %bb.0:6417; ZIP-NEXT:    vsetvli a0, zero, e32, m1, ta, ma6418; ZIP-NEXT:    vmv1r.v v10, v96419; ZIP-NEXT:    vmv1r.v v11, v86420; ZIP-NEXT:    ri.vzip2b.vv v9, v8, v106421; ZIP-NEXT:    ri.vzip2a.vv v8, v11, v106422; ZIP-NEXT:    ret6423  %res = call <vscale x 4 x float> @llvm.vector.interleave2.nxv4f32(<vscale x 2 x float> %a, <vscale x 2 x float> %b)6424  ret <vscale x 4 x float> %res6425}6426 6427define <vscale x 16 x bfloat> @vector_interleave_nxv16bf16_nxv8bf16(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b) {6428; V-LABEL: vector_interleave_nxv16bf16_nxv8bf16:6429; V:       # %bb.0:6430; V-NEXT:    vsetvli a0, zero, e16, m2, ta, ma6431; V-NEXT:    vmv2r.v v12, v106432; V-NEXT:    vmv2r.v v14, v86433; V-NEXT:    vwaddu.vv v8, v14, v126434; V-NEXT:    li a0, -16435; V-NEXT:    vwmaccu.vx v8, a0, v126436; V-NEXT:    ret6437;6438; ZVBB-LABEL: vector_interleave_nxv16bf16_nxv8bf16:6439; ZVBB:       # %bb.0:6440; ZVBB-NEXT:    vsetvli a0, zero, e16, m2, ta, ma6441; ZVBB-NEXT:    vmv2r.v v12, v106442; ZVBB-NEXT:    vmv2r.v v14, v86443; ZVBB-NEXT:    vwsll.vi v8, v12, 166444; ZVBB-NEXT:    vwaddu.wv v8, v8, v146445; ZVBB-NEXT:    ret6446;6447; ZIP-LABEL: vector_interleave_nxv16bf16_nxv8bf16:6448; ZIP:       # %bb.0:6449; ZIP-NEXT:    vsetvli a0, zero, e16, m2, ta, ma6450; ZIP-NEXT:    vmv2r.v v12, v106451; ZIP-NEXT:    vmv2r.v v14, v86452; ZIP-NEXT:    ri.vzip2b.vv v10, v8, v126453; ZIP-NEXT:    ri.vzip2a.vv v8, v14, v126454; ZIP-NEXT:    ret6455  %res = call <vscale x 16 x bfloat> @llvm.vector.interleave2.nxv16bf16(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b)6456  ret <vscale x 16 x bfloat> %res6457}6458 6459define <vscale x 16 x half> @vector_interleave_nxv16f16_nxv8f16(<vscale x 8 x half> %a, <vscale x 8 x half> %b) {6460; V-LABEL: vector_interleave_nxv16f16_nxv8f16:6461; V:       # %bb.0:6462; V-NEXT:    vsetvli a0, zero, e16, m2, ta, ma6463; V-NEXT:    vmv2r.v v12, v106464; V-NEXT:    vmv2r.v v14, v86465; V-NEXT:    vwaddu.vv v8, v14, v126466; V-NEXT:    li a0, -16467; V-NEXT:    vwmaccu.vx v8, a0, v126468; V-NEXT:    ret6469;6470; ZVBB-LABEL: vector_interleave_nxv16f16_nxv8f16:6471; ZVBB:       # %bb.0:6472; ZVBB-NEXT:    vsetvli a0, zero, e16, m2, ta, ma6473; ZVBB-NEXT:    vmv2r.v v12, v106474; ZVBB-NEXT:    vmv2r.v v14, v86475; ZVBB-NEXT:    vwsll.vi v8, v12, 166476; ZVBB-NEXT:    vwaddu.wv v8, v8, v146477; ZVBB-NEXT:    ret6478;6479; ZIP-LABEL: vector_interleave_nxv16f16_nxv8f16:6480; ZIP:       # %bb.0:6481; ZIP-NEXT:    vsetvli a0, zero, e16, m2, ta, ma6482; ZIP-NEXT:    vmv2r.v v12, v106483; ZIP-NEXT:    vmv2r.v v14, v86484; ZIP-NEXT:    ri.vzip2b.vv v10, v8, v126485; ZIP-NEXT:    ri.vzip2a.vv v8, v14, v126486; ZIP-NEXT:    ret6487  %res = call <vscale x 16 x half> @llvm.vector.interleave2.nxv16f16(<vscale x 8 x half> %a, <vscale x 8 x half> %b)6488  ret <vscale x 16 x half> %res6489}6490 6491define <vscale x 8 x float> @vector_interleave_nxv8f32_nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x float> %b) {6492; V-LABEL: vector_interleave_nxv8f32_nxv4f32:6493; V:       # %bb.0:6494; V-NEXT:    vsetvli a0, zero, e32, m2, ta, ma6495; V-NEXT:    vmv2r.v v12, v106496; V-NEXT:    vmv2r.v v14, v86497; V-NEXT:    vwaddu.vv v8, v14, v126498; V-NEXT:    li a0, -16499; V-NEXT:    vwmaccu.vx v8, a0, v126500; V-NEXT:    ret6501;6502; ZVBB-LABEL: vector_interleave_nxv8f32_nxv4f32:6503; ZVBB:       # %bb.0:6504; ZVBB-NEXT:    vsetvli a0, zero, e32, m2, ta, ma6505; ZVBB-NEXT:    vmv2r.v v12, v106506; ZVBB-NEXT:    vmv2r.v v14, v86507; ZVBB-NEXT:    li a0, 326508; ZVBB-NEXT:    vwsll.vx v8, v12, a06509; ZVBB-NEXT:    vwaddu.wv v8, v8, v146510; ZVBB-NEXT:    ret6511;6512; ZIP-LABEL: vector_interleave_nxv8f32_nxv4f32:6513; ZIP:       # %bb.0:6514; ZIP-NEXT:    vsetvli a0, zero, e32, m2, ta, ma6515; ZIP-NEXT:    vmv2r.v v12, v106516; ZIP-NEXT:    vmv2r.v v14, v86517; ZIP-NEXT:    ri.vzip2b.vv v10, v8, v126518; ZIP-NEXT:    ri.vzip2a.vv v8, v14, v126519; ZIP-NEXT:    ret6520  %res = call <vscale x 8 x float> @llvm.vector.interleave2.nxv8f32(<vscale x 4 x float> %a, <vscale x 4 x float> %b)6521  ret <vscale x 8 x float> %res6522}6523 6524define <vscale x 4 x double> @vector_interleave_nxv4f64_nxv2f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b) {6525; V-LABEL: vector_interleave_nxv4f64_nxv2f64:6526; V:       # %bb.0:6527; V-NEXT:    csrr a0, vlenb6528; V-NEXT:    vsetvli a1, zero, e16, m1, ta, mu6529; V-NEXT:    vid.v v126530; V-NEXT:    srli a0, a0, 26531; V-NEXT:    vand.vi v13, v12, 16532; V-NEXT:    vmsne.vi v0, v13, 06533; V-NEXT:    vsrl.vi v16, v12, 16534; V-NEXT:    vadd.vx v16, v16, a0, v0.t6535; V-NEXT:    vsetvli zero, zero, e64, m4, ta, ma6536; V-NEXT:    vrgatherei16.vv v12, v8, v166537; V-NEXT:    vmv.v.v v8, v126538; V-NEXT:    ret6539;6540; ZVBB-LABEL: vector_interleave_nxv4f64_nxv2f64:6541; ZVBB:       # %bb.0:6542; ZVBB-NEXT:    csrr a0, vlenb6543; ZVBB-NEXT:    vsetvli a1, zero, e16, m1, ta, mu6544; ZVBB-NEXT:    vid.v v126545; ZVBB-NEXT:    srli a0, a0, 26546; ZVBB-NEXT:    vand.vi v13, v12, 16547; ZVBB-NEXT:    vmsne.vi v0, v13, 06548; ZVBB-NEXT:    vsrl.vi v16, v12, 16549; ZVBB-NEXT:    vadd.vx v16, v16, a0, v0.t6550; ZVBB-NEXT:    vsetvli zero, zero, e64, m4, ta, ma6551; ZVBB-NEXT:    vrgatherei16.vv v12, v8, v166552; ZVBB-NEXT:    vmv.v.v v8, v126553; ZVBB-NEXT:    ret6554;6555; ZIP-LABEL: vector_interleave_nxv4f64_nxv2f64:6556; ZIP:       # %bb.0:6557; ZIP-NEXT:    vsetvli a0, zero, e64, m2, ta, ma6558; ZIP-NEXT:    vmv2r.v v12, v106559; ZIP-NEXT:    vmv2r.v v14, v86560; ZIP-NEXT:    ri.vzip2b.vv v10, v8, v126561; ZIP-NEXT:    ri.vzip2a.vv v8, v14, v126562; ZIP-NEXT:    ret6563  %res = call <vscale x 4 x double> @llvm.vector.interleave2.nxv4f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b)6564  ret <vscale x 4 x double> %res6565}6566 6567 6568 6569define <vscale x 64 x bfloat> @vector_interleave_nxv64bf16_nxv32bf16(<vscale x 32 x bfloat> %a, <vscale x 32 x bfloat> %b) {6570; V-LABEL: vector_interleave_nxv64bf16_nxv32bf16:6571; V:       # %bb.0:6572; V-NEXT:    vsetvli a0, zero, e16, m4, ta, ma6573; V-NEXT:    vmv8r.v v24, v86574; V-NEXT:    vwaddu.vv v8, v24, v166575; V-NEXT:    li a0, -16576; V-NEXT:    vwaddu.vv v0, v28, v206577; V-NEXT:    vwmaccu.vx v8, a0, v166578; V-NEXT:    vwmaccu.vx v0, a0, v206579; V-NEXT:    vmv8r.v v16, v06580; V-NEXT:    ret6581;6582; ZVBB-LABEL: vector_interleave_nxv64bf16_nxv32bf16:6583; ZVBB:       # %bb.0:6584; ZVBB-NEXT:    vsetvli a0, zero, e16, m4, ta, ma6585; ZVBB-NEXT:    vwsll.vi v24, v16, 166586; ZVBB-NEXT:    vwsll.vi v0, v20, 166587; ZVBB-NEXT:    vwaddu.wv v24, v24, v86588; ZVBB-NEXT:    vwaddu.wv v0, v0, v126589; ZVBB-NEXT:    vmv8r.v v8, v246590; ZVBB-NEXT:    vmv8r.v v16, v06591; ZVBB-NEXT:    ret6592;6593; ZIP-LABEL: vector_interleave_nxv64bf16_nxv32bf16:6594; ZIP:       # %bb.0:6595; ZIP-NEXT:    vsetvli a0, zero, e16, m4, ta, ma6596; ZIP-NEXT:    ri.vzip2b.vv v28, v8, v166597; ZIP-NEXT:    ri.vzip2b.vv v4, v12, v206598; ZIP-NEXT:    ri.vzip2a.vv v24, v8, v166599; ZIP-NEXT:    ri.vzip2a.vv v0, v12, v206600; ZIP-NEXT:    vmv8r.v v8, v246601; ZIP-NEXT:    vmv8r.v v16, v06602; ZIP-NEXT:    ret6603  %res = call <vscale x 64 x bfloat> @llvm.vector.interleave2.nxv64bf16(<vscale x 32 x bfloat> %a, <vscale x 32 x bfloat> %b)6604  ret <vscale x 64 x bfloat> %res6605}6606 6607define <vscale x 64 x half> @vector_interleave_nxv64f16_nxv32f16(<vscale x 32 x half> %a, <vscale x 32 x half> %b) {6608; V-LABEL: vector_interleave_nxv64f16_nxv32f16:6609; V:       # %bb.0:6610; V-NEXT:    vsetvli a0, zero, e16, m4, ta, ma6611; V-NEXT:    vmv8r.v v24, v86612; V-NEXT:    vwaddu.vv v8, v24, v166613; V-NEXT:    li a0, -16614; V-NEXT:    vwaddu.vv v0, v28, v206615; V-NEXT:    vwmaccu.vx v8, a0, v166616; V-NEXT:    vwmaccu.vx v0, a0, v206617; V-NEXT:    vmv8r.v v16, v06618; V-NEXT:    ret6619;6620; ZVBB-LABEL: vector_interleave_nxv64f16_nxv32f16:6621; ZVBB:       # %bb.0:6622; ZVBB-NEXT:    vsetvli a0, zero, e16, m4, ta, ma6623; ZVBB-NEXT:    vwsll.vi v24, v16, 166624; ZVBB-NEXT:    vwsll.vi v0, v20, 166625; ZVBB-NEXT:    vwaddu.wv v24, v24, v86626; ZVBB-NEXT:    vwaddu.wv v0, v0, v126627; ZVBB-NEXT:    vmv8r.v v8, v246628; ZVBB-NEXT:    vmv8r.v v16, v06629; ZVBB-NEXT:    ret6630;6631; ZIP-LABEL: vector_interleave_nxv64f16_nxv32f16:6632; ZIP:       # %bb.0:6633; ZIP-NEXT:    vsetvli a0, zero, e16, m4, ta, ma6634; ZIP-NEXT:    ri.vzip2b.vv v28, v8, v166635; ZIP-NEXT:    ri.vzip2b.vv v4, v12, v206636; ZIP-NEXT:    ri.vzip2a.vv v24, v8, v166637; ZIP-NEXT:    ri.vzip2a.vv v0, v12, v206638; ZIP-NEXT:    vmv8r.v v8, v246639; ZIP-NEXT:    vmv8r.v v16, v06640; ZIP-NEXT:    ret6641  %res = call <vscale x 64 x half> @llvm.vector.interleave2.nxv64f16(<vscale x 32 x half> %a, <vscale x 32 x half> %b)6642  ret <vscale x 64 x half> %res6643}6644 6645define <vscale x 32 x float> @vector_interleave_nxv32f32_nxv16f32(<vscale x 16 x float> %a, <vscale x 16 x float> %b) {6646; V-LABEL: vector_interleave_nxv32f32_nxv16f32:6647; V:       # %bb.0:6648; V-NEXT:    vsetvli a0, zero, e32, m4, ta, ma6649; V-NEXT:    vmv8r.v v24, v86650; V-NEXT:    vwaddu.vv v8, v24, v166651; V-NEXT:    li a0, -16652; V-NEXT:    vwaddu.vv v0, v28, v206653; V-NEXT:    vwmaccu.vx v8, a0, v166654; V-NEXT:    vwmaccu.vx v0, a0, v206655; V-NEXT:    vmv8r.v v16, v06656; V-NEXT:    ret6657;6658; ZVBB-LABEL: vector_interleave_nxv32f32_nxv16f32:6659; ZVBB:       # %bb.0:6660; ZVBB-NEXT:    li a0, 326661; ZVBB-NEXT:    vsetvli a1, zero, e32, m4, ta, ma6662; ZVBB-NEXT:    vwsll.vx v24, v16, a06663; ZVBB-NEXT:    vwsll.vx v0, v20, a06664; ZVBB-NEXT:    vwaddu.wv v24, v24, v86665; ZVBB-NEXT:    vwaddu.wv v0, v0, v126666; ZVBB-NEXT:    vmv8r.v v8, v246667; ZVBB-NEXT:    vmv8r.v v16, v06668; ZVBB-NEXT:    ret6669;6670; ZIP-LABEL: vector_interleave_nxv32f32_nxv16f32:6671; ZIP:       # %bb.0:6672; ZIP-NEXT:    vsetvli a0, zero, e32, m4, ta, ma6673; ZIP-NEXT:    ri.vzip2b.vv v28, v8, v166674; ZIP-NEXT:    ri.vzip2b.vv v4, v12, v206675; ZIP-NEXT:    ri.vzip2a.vv v24, v8, v166676; ZIP-NEXT:    ri.vzip2a.vv v0, v12, v206677; ZIP-NEXT:    vmv8r.v v8, v246678; ZIP-NEXT:    vmv8r.v v16, v06679; ZIP-NEXT:    ret6680  %res = call <vscale x 32 x float> @llvm.vector.interleave2.nxv32f32(<vscale x 16 x float> %a, <vscale x 16 x float> %b)6681  ret <vscale x 32 x float> %res6682}6683 6684define <vscale x 16 x double> @vector_interleave_nxv16f64_nxv8f64(<vscale x 8 x double> %a, <vscale x 8 x double> %b) {6685; V-LABEL: vector_interleave_nxv16f64_nxv8f64:6686; V:       # %bb.0:6687; V-NEXT:    csrr a0, vlenb6688; V-NEXT:    vsetvli a1, zero, e16, m2, ta, mu6689; V-NEXT:    vid.v v66690; V-NEXT:    vmv8r.v v24, v86691; V-NEXT:    srli a0, a0, 16692; V-NEXT:    vmv4r.v v28, v166693; V-NEXT:    vmv4r.v v16, v126694; V-NEXT:    vand.vi v8, v6, 16695; V-NEXT:    vmsne.vi v0, v8, 06696; V-NEXT:    vsrl.vi v6, v6, 16697; V-NEXT:    vadd.vx v6, v6, a0, v0.t6698; V-NEXT:    vsetvli zero, zero, e64, m8, ta, ma6699; V-NEXT:    vrgatherei16.vv v8, v24, v66700; V-NEXT:    vrgatherei16.vv v24, v16, v66701; V-NEXT:    vmv.v.v v16, v246702; V-NEXT:    ret6703;6704; ZVBB-LABEL: vector_interleave_nxv16f64_nxv8f64:6705; ZVBB:       # %bb.0:6706; ZVBB-NEXT:    csrr a0, vlenb6707; ZVBB-NEXT:    vsetvli a1, zero, e16, m2, ta, mu6708; ZVBB-NEXT:    vid.v v66709; ZVBB-NEXT:    vmv8r.v v24, v86710; ZVBB-NEXT:    srli a0, a0, 16711; ZVBB-NEXT:    vmv4r.v v28, v166712; ZVBB-NEXT:    vmv4r.v v16, v126713; ZVBB-NEXT:    vand.vi v8, v6, 16714; ZVBB-NEXT:    vmsne.vi v0, v8, 06715; ZVBB-NEXT:    vsrl.vi v6, v6, 16716; ZVBB-NEXT:    vadd.vx v6, v6, a0, v0.t6717; ZVBB-NEXT:    vsetvli zero, zero, e64, m8, ta, ma6718; ZVBB-NEXT:    vrgatherei16.vv v8, v24, v66719; ZVBB-NEXT:    vrgatherei16.vv v24, v16, v66720; ZVBB-NEXT:    vmv.v.v v16, v246721; ZVBB-NEXT:    ret6722;6723; ZIP-LABEL: vector_interleave_nxv16f64_nxv8f64:6724; ZIP:       # %bb.0:6725; ZIP-NEXT:    vsetvli a0, zero, e64, m4, ta, ma6726; ZIP-NEXT:    ri.vzip2b.vv v28, v8, v166727; ZIP-NEXT:    ri.vzip2b.vv v4, v12, v206728; ZIP-NEXT:    ri.vzip2a.vv v24, v8, v166729; ZIP-NEXT:    ri.vzip2a.vv v0, v12, v206730; ZIP-NEXT:    vmv8r.v v8, v246731; ZIP-NEXT:    vmv8r.v v16, v06732; ZIP-NEXT:    ret6733  %res = call <vscale x 16 x double> @llvm.vector.interleave2.nxv16f64(<vscale x 8 x double> %a, <vscale x 8 x double> %b)6734  ret <vscale x 16 x double> %res6735}6736 6737define <vscale x 6 x half> @vector_interleave_nxv6f16_nxv2f16(<vscale x 2 x half> %v0, <vscale x 2 x half> %v1, <vscale x 2 x half> %v2) nounwind {6738; CHECK-LABEL: vector_interleave_nxv6f16_nxv2f16:6739; CHECK:       # %bb.0:6740; CHECK-NEXT:    addi sp, sp, -166741; CHECK-NEXT:    csrr a0, vlenb6742; CHECK-NEXT:    slli a0, a0, 16743; CHECK-NEXT:    sub sp, sp, a06744; CHECK-NEXT:    addi a0, sp, 166745; CHECK-NEXT:    csrr a1, vlenb6746; CHECK-NEXT:    srli a2, a1, 16747; CHECK-NEXT:    vsetvli a3, zero, e16, mf2, ta, ma6748; CHECK-NEXT:    vsseg3e16.v v8, (a0)6749; CHECK-NEXT:    add a3, a0, a26750; CHECK-NEXT:    vle16.v v9, (a3)6751; CHECK-NEXT:    vle16.v v8, (a0)6752; CHECK-NEXT:    srli a1, a1, 26753; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma6754; CHECK-NEXT:    vslideup.vx v8, v9, a16755; CHECK-NEXT:    add a2, a3, a26756; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma6757; CHECK-NEXT:    vle16.v v9, (a2)6758; CHECK-NEXT:    csrr a0, vlenb6759; CHECK-NEXT:    slli a0, a0, 16760; CHECK-NEXT:    add sp, sp, a06761; CHECK-NEXT:    addi sp, sp, 166762; CHECK-NEXT:    ret6763;6764; ZVBB-LABEL: vector_interleave_nxv6f16_nxv2f16:6765; ZVBB:       # %bb.0:6766; ZVBB-NEXT:    addi sp, sp, -166767; ZVBB-NEXT:    csrr a0, vlenb6768; ZVBB-NEXT:    slli a0, a0, 16769; ZVBB-NEXT:    sub sp, sp, a06770; ZVBB-NEXT:    addi a0, sp, 166771; ZVBB-NEXT:    csrr a1, vlenb6772; ZVBB-NEXT:    srli a2, a1, 16773; ZVBB-NEXT:    vsetvli a3, zero, e16, mf2, ta, ma6774; ZVBB-NEXT:    vsseg3e16.v v8, (a0)6775; ZVBB-NEXT:    add a3, a0, a26776; ZVBB-NEXT:    vle16.v v9, (a3)6777; ZVBB-NEXT:    vle16.v v8, (a0)6778; ZVBB-NEXT:    srli a1, a1, 26779; ZVBB-NEXT:    vsetvli a0, zero, e16, m1, ta, ma6780; ZVBB-NEXT:    vslideup.vx v8, v9, a16781; ZVBB-NEXT:    add a2, a3, a26782; ZVBB-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma6783; ZVBB-NEXT:    vle16.v v9, (a2)6784; ZVBB-NEXT:    csrr a0, vlenb6785; ZVBB-NEXT:    slli a0, a0, 16786; ZVBB-NEXT:    add sp, sp, a06787; ZVBB-NEXT:    addi sp, sp, 166788; ZVBB-NEXT:    ret6789  %res = call <vscale x 6 x half> @llvm.vector.interleave3.nxv6f16(<vscale x 2 x half> %v0, <vscale x 2 x half> %v1, <vscale x 2 x half> %v2)6790  ret <vscale x 6 x half> %res6791}6792 6793define <vscale x 12 x half> @vector_interleave_nxv12f16_nxv4f16(<vscale x 4 x half> %v0, <vscale x 4 x half> %v1, <vscale x 4 x half> %v2) nounwind {6794; CHECK-LABEL: vector_interleave_nxv12f16_nxv4f16:6795; CHECK:       # %bb.0:6796; CHECK-NEXT:    addi sp, sp, -166797; CHECK-NEXT:    csrr a0, vlenb6798; CHECK-NEXT:    slli a1, a0, 16799; CHECK-NEXT:    add a0, a1, a06800; CHECK-NEXT:    sub sp, sp, a06801; CHECK-NEXT:    addi a0, sp, 166802; CHECK-NEXT:    csrr a1, vlenb6803; CHECK-NEXT:    vsetvli a2, zero, e16, m1, ta, ma6804; CHECK-NEXT:    vsseg3e16.v v8, (a0)6805; CHECK-NEXT:    vl1re16.v v8, (a0)6806; CHECK-NEXT:    add a0, a0, a16807; CHECK-NEXT:    vl1re16.v v9, (a0)6808; CHECK-NEXT:    add a0, a0, a16809; CHECK-NEXT:    vl1re16.v v10, (a0)6810; CHECK-NEXT:    csrr a0, vlenb6811; CHECK-NEXT:    slli a1, a0, 16812; CHECK-NEXT:    add a0, a1, a06813; CHECK-NEXT:    add sp, sp, a06814; CHECK-NEXT:    addi sp, sp, 166815; CHECK-NEXT:    ret6816;6817; ZVBB-LABEL: vector_interleave_nxv12f16_nxv4f16:6818; ZVBB:       # %bb.0:6819; ZVBB-NEXT:    addi sp, sp, -166820; ZVBB-NEXT:    csrr a0, vlenb6821; ZVBB-NEXT:    slli a1, a0, 16822; ZVBB-NEXT:    add a0, a1, a06823; ZVBB-NEXT:    sub sp, sp, a06824; ZVBB-NEXT:    addi a0, sp, 166825; ZVBB-NEXT:    csrr a1, vlenb6826; ZVBB-NEXT:    vsetvli a2, zero, e16, m1, ta, ma6827; ZVBB-NEXT:    vsseg3e16.v v8, (a0)6828; ZVBB-NEXT:    vl1re16.v v8, (a0)6829; ZVBB-NEXT:    add a0, a0, a16830; ZVBB-NEXT:    vl1re16.v v9, (a0)6831; ZVBB-NEXT:    add a0, a0, a16832; ZVBB-NEXT:    vl1re16.v v10, (a0)6833; ZVBB-NEXT:    csrr a0, vlenb6834; ZVBB-NEXT:    slli a1, a0, 16835; ZVBB-NEXT:    add a0, a1, a06836; ZVBB-NEXT:    add sp, sp, a06837; ZVBB-NEXT:    addi sp, sp, 166838; ZVBB-NEXT:    ret6839  %res = call <vscale x 12 x half> @llvm.vector.interleave3.nxv12f16(<vscale x 4 x half> %v0, <vscale x 4 x half> %v1, <vscale x 4 x half> %v2)6840  ret <vscale x 12 x half> %res6841}6842 6843define <vscale x 24 x half> @vector_interleave_nxv24f16_nxv8f16(<vscale x 8 x half> %v0, <vscale x 8 x half> %v1, <vscale x 8 x half> %v2) nounwind {6844; CHECK-LABEL: vector_interleave_nxv24f16_nxv8f16:6845; CHECK:       # %bb.0:6846; CHECK-NEXT:    addi sp, sp, -166847; CHECK-NEXT:    csrr a0, vlenb6848; CHECK-NEXT:    li a1, 66849; CHECK-NEXT:    mul a0, a0, a16850; CHECK-NEXT:    sub sp, sp, a06851; CHECK-NEXT:    addi a0, sp, 166852; CHECK-NEXT:    csrr a1, vlenb6853; CHECK-NEXT:    slli a1, a1, 16854; CHECK-NEXT:    vsetvli a2, zero, e16, m2, ta, ma6855; CHECK-NEXT:    vsseg3e16.v v8, (a0)6856; CHECK-NEXT:    vl2re16.v v8, (a0)6857; CHECK-NEXT:    add a0, a0, a16858; CHECK-NEXT:    vl2re16.v v10, (a0)6859; CHECK-NEXT:    add a0, a0, a16860; CHECK-NEXT:    vl2re16.v v12, (a0)6861; CHECK-NEXT:    csrr a0, vlenb6862; CHECK-NEXT:    li a1, 66863; CHECK-NEXT:    mul a0, a0, a16864; CHECK-NEXT:    add sp, sp, a06865; CHECK-NEXT:    addi sp, sp, 166866; CHECK-NEXT:    ret6867;6868; ZVBB-LABEL: vector_interleave_nxv24f16_nxv8f16:6869; ZVBB:       # %bb.0:6870; ZVBB-NEXT:    addi sp, sp, -166871; ZVBB-NEXT:    csrr a0, vlenb6872; ZVBB-NEXT:    li a1, 66873; ZVBB-NEXT:    mul a0, a0, a16874; ZVBB-NEXT:    sub sp, sp, a06875; ZVBB-NEXT:    addi a0, sp, 166876; ZVBB-NEXT:    csrr a1, vlenb6877; ZVBB-NEXT:    slli a1, a1, 16878; ZVBB-NEXT:    vsetvli a2, zero, e16, m2, ta, ma6879; ZVBB-NEXT:    vsseg3e16.v v8, (a0)6880; ZVBB-NEXT:    vl2re16.v v8, (a0)6881; ZVBB-NEXT:    add a0, a0, a16882; ZVBB-NEXT:    vl2re16.v v10, (a0)6883; ZVBB-NEXT:    add a0, a0, a16884; ZVBB-NEXT:    vl2re16.v v12, (a0)6885; ZVBB-NEXT:    csrr a0, vlenb6886; ZVBB-NEXT:    li a1, 66887; ZVBB-NEXT:    mul a0, a0, a16888; ZVBB-NEXT:    add sp, sp, a06889; ZVBB-NEXT:    addi sp, sp, 166890; ZVBB-NEXT:    ret6891  %res = call <vscale x 24 x half> @llvm.vector.interleave3.nxv24f16(<vscale x 8 x half> %v0, <vscale x 8 x half> %v1, <vscale x 8 x half> %v2)6892  ret <vscale x 24 x half> %res6893}6894 6895define <vscale x 6 x bfloat> @vector_interleave_nxv6bf16_nxv2bf16(<vscale x 2 x bfloat> %v0, <vscale x 2 x bfloat> %v1, <vscale x 2 x bfloat> %v2) nounwind {6896; CHECK-LABEL: vector_interleave_nxv6bf16_nxv2bf16:6897; CHECK:       # %bb.0:6898; CHECK-NEXT:    addi sp, sp, -166899; CHECK-NEXT:    csrr a0, vlenb6900; CHECK-NEXT:    slli a0, a0, 16901; CHECK-NEXT:    sub sp, sp, a06902; CHECK-NEXT:    addi a0, sp, 166903; CHECK-NEXT:    csrr a1, vlenb6904; CHECK-NEXT:    srli a2, a1, 16905; CHECK-NEXT:    vsetvli a3, zero, e16, mf2, ta, ma6906; CHECK-NEXT:    vsseg3e16.v v8, (a0)6907; CHECK-NEXT:    add a3, a0, a26908; CHECK-NEXT:    vle16.v v9, (a3)6909; CHECK-NEXT:    vle16.v v8, (a0)6910; CHECK-NEXT:    srli a1, a1, 26911; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma6912; CHECK-NEXT:    vslideup.vx v8, v9, a16913; CHECK-NEXT:    add a2, a3, a26914; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma6915; CHECK-NEXT:    vle16.v v9, (a2)6916; CHECK-NEXT:    csrr a0, vlenb6917; CHECK-NEXT:    slli a0, a0, 16918; CHECK-NEXT:    add sp, sp, a06919; CHECK-NEXT:    addi sp, sp, 166920; CHECK-NEXT:    ret6921;6922; ZVBB-LABEL: vector_interleave_nxv6bf16_nxv2bf16:6923; ZVBB:       # %bb.0:6924; ZVBB-NEXT:    addi sp, sp, -166925; ZVBB-NEXT:    csrr a0, vlenb6926; ZVBB-NEXT:    slli a0, a0, 16927; ZVBB-NEXT:    sub sp, sp, a06928; ZVBB-NEXT:    addi a0, sp, 166929; ZVBB-NEXT:    csrr a1, vlenb6930; ZVBB-NEXT:    srli a2, a1, 16931; ZVBB-NEXT:    vsetvli a3, zero, e16, mf2, ta, ma6932; ZVBB-NEXT:    vsseg3e16.v v8, (a0)6933; ZVBB-NEXT:    add a3, a0, a26934; ZVBB-NEXT:    vle16.v v9, (a3)6935; ZVBB-NEXT:    vle16.v v8, (a0)6936; ZVBB-NEXT:    srli a1, a1, 26937; ZVBB-NEXT:    vsetvli a0, zero, e16, m1, ta, ma6938; ZVBB-NEXT:    vslideup.vx v8, v9, a16939; ZVBB-NEXT:    add a2, a3, a26940; ZVBB-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma6941; ZVBB-NEXT:    vle16.v v9, (a2)6942; ZVBB-NEXT:    csrr a0, vlenb6943; ZVBB-NEXT:    slli a0, a0, 16944; ZVBB-NEXT:    add sp, sp, a06945; ZVBB-NEXT:    addi sp, sp, 166946; ZVBB-NEXT:    ret6947  %res = call <vscale x 6 x bfloat> @llvm.vector.interleave3.nxv6bf16(<vscale x 2 x bfloat> %v0, <vscale x 2 x bfloat> %v1, <vscale x 2 x bfloat> %v2)6948  ret <vscale x 6 x bfloat> %res6949}6950 6951define <vscale x 12 x bfloat> @vector_interleave_nxv12bf16_nxv4bf16(<vscale x 4 x bfloat> %v0, <vscale x 4 x bfloat> %v1, <vscale x 4 x bfloat> %v2) nounwind {6952; CHECK-LABEL: vector_interleave_nxv12bf16_nxv4bf16:6953; CHECK:       # %bb.0:6954; CHECK-NEXT:    addi sp, sp, -166955; CHECK-NEXT:    csrr a0, vlenb6956; CHECK-NEXT:    slli a1, a0, 16957; CHECK-NEXT:    add a0, a1, a06958; CHECK-NEXT:    sub sp, sp, a06959; CHECK-NEXT:    addi a0, sp, 166960; CHECK-NEXT:    csrr a1, vlenb6961; CHECK-NEXT:    vsetvli a2, zero, e16, m1, ta, ma6962; CHECK-NEXT:    vsseg3e16.v v8, (a0)6963; CHECK-NEXT:    vl1re16.v v8, (a0)6964; CHECK-NEXT:    add a0, a0, a16965; CHECK-NEXT:    vl1re16.v v9, (a0)6966; CHECK-NEXT:    add a0, a0, a16967; CHECK-NEXT:    vl1re16.v v10, (a0)6968; CHECK-NEXT:    csrr a0, vlenb6969; CHECK-NEXT:    slli a1, a0, 16970; CHECK-NEXT:    add a0, a1, a06971; CHECK-NEXT:    add sp, sp, a06972; CHECK-NEXT:    addi sp, sp, 166973; CHECK-NEXT:    ret6974;6975; ZVBB-LABEL: vector_interleave_nxv12bf16_nxv4bf16:6976; ZVBB:       # %bb.0:6977; ZVBB-NEXT:    addi sp, sp, -166978; ZVBB-NEXT:    csrr a0, vlenb6979; ZVBB-NEXT:    slli a1, a0, 16980; ZVBB-NEXT:    add a0, a1, a06981; ZVBB-NEXT:    sub sp, sp, a06982; ZVBB-NEXT:    addi a0, sp, 166983; ZVBB-NEXT:    csrr a1, vlenb6984; ZVBB-NEXT:    vsetvli a2, zero, e16, m1, ta, ma6985; ZVBB-NEXT:    vsseg3e16.v v8, (a0)6986; ZVBB-NEXT:    vl1re16.v v8, (a0)6987; ZVBB-NEXT:    add a0, a0, a16988; ZVBB-NEXT:    vl1re16.v v9, (a0)6989; ZVBB-NEXT:    add a0, a0, a16990; ZVBB-NEXT:    vl1re16.v v10, (a0)6991; ZVBB-NEXT:    csrr a0, vlenb6992; ZVBB-NEXT:    slli a1, a0, 16993; ZVBB-NEXT:    add a0, a1, a06994; ZVBB-NEXT:    add sp, sp, a06995; ZVBB-NEXT:    addi sp, sp, 166996; ZVBB-NEXT:    ret6997  %res = call <vscale x 12 x bfloat> @llvm.vector.interleave3.nxv12bf16(<vscale x 4 x bfloat> %v0, <vscale x 4 x bfloat> %v1, <vscale x 4 x bfloat> %v2)6998  ret <vscale x 12 x bfloat> %res6999}7000 7001define <vscale x 24 x bfloat> @vector_interleave_nxv24bf16_nxv8bf16(<vscale x 8 x bfloat> %v0, <vscale x 8 x bfloat> %v1, <vscale x 8 x bfloat> %v2) nounwind {7002; CHECK-LABEL: vector_interleave_nxv24bf16_nxv8bf16:7003; CHECK:       # %bb.0:7004; CHECK-NEXT:    addi sp, sp, -167005; CHECK-NEXT:    csrr a0, vlenb7006; CHECK-NEXT:    li a1, 67007; CHECK-NEXT:    mul a0, a0, a17008; CHECK-NEXT:    sub sp, sp, a07009; CHECK-NEXT:    addi a0, sp, 167010; CHECK-NEXT:    csrr a1, vlenb7011; CHECK-NEXT:    slli a1, a1, 17012; CHECK-NEXT:    vsetvli a2, zero, e16, m2, ta, ma7013; CHECK-NEXT:    vsseg3e16.v v8, (a0)7014; CHECK-NEXT:    vl2re16.v v8, (a0)7015; CHECK-NEXT:    add a0, a0, a17016; CHECK-NEXT:    vl2re16.v v10, (a0)7017; CHECK-NEXT:    add a0, a0, a17018; CHECK-NEXT:    vl2re16.v v12, (a0)7019; CHECK-NEXT:    csrr a0, vlenb7020; CHECK-NEXT:    li a1, 67021; CHECK-NEXT:    mul a0, a0, a17022; CHECK-NEXT:    add sp, sp, a07023; CHECK-NEXT:    addi sp, sp, 167024; CHECK-NEXT:    ret7025;7026; ZVBB-LABEL: vector_interleave_nxv24bf16_nxv8bf16:7027; ZVBB:       # %bb.0:7028; ZVBB-NEXT:    addi sp, sp, -167029; ZVBB-NEXT:    csrr a0, vlenb7030; ZVBB-NEXT:    li a1, 67031; ZVBB-NEXT:    mul a0, a0, a17032; ZVBB-NEXT:    sub sp, sp, a07033; ZVBB-NEXT:    addi a0, sp, 167034; ZVBB-NEXT:    csrr a1, vlenb7035; ZVBB-NEXT:    slli a1, a1, 17036; ZVBB-NEXT:    vsetvli a2, zero, e16, m2, ta, ma7037; ZVBB-NEXT:    vsseg3e16.v v8, (a0)7038; ZVBB-NEXT:    vl2re16.v v8, (a0)7039; ZVBB-NEXT:    add a0, a0, a17040; ZVBB-NEXT:    vl2re16.v v10, (a0)7041; ZVBB-NEXT:    add a0, a0, a17042; ZVBB-NEXT:    vl2re16.v v12, (a0)7043; ZVBB-NEXT:    csrr a0, vlenb7044; ZVBB-NEXT:    li a1, 67045; ZVBB-NEXT:    mul a0, a0, a17046; ZVBB-NEXT:    add sp, sp, a07047; ZVBB-NEXT:    addi sp, sp, 167048; ZVBB-NEXT:    ret7049  %res = call <vscale x 24 x bfloat> @llvm.vector.interleave3.nxv24bf16(<vscale x 8 x bfloat> %v0, <vscale x 8 x bfloat> %v1, <vscale x 8 x bfloat> %v2)7050  ret <vscale x 24 x bfloat> %res7051}7052 7053define <vscale x 3 x float> @vector_interleave_nxv3f32_nxv1f32(<vscale x 1 x float> %v0, <vscale x 1 x float> %v1, <vscale x 1 x float> %v2) nounwind {7054; CHECK-LABEL: vector_interleave_nxv3f32_nxv1f32:7055; CHECK:       # %bb.0:7056; CHECK-NEXT:    addi sp, sp, -167057; CHECK-NEXT:    csrr a0, vlenb7058; CHECK-NEXT:    slli a0, a0, 17059; CHECK-NEXT:    sub sp, sp, a07060; CHECK-NEXT:    addi a0, sp, 167061; CHECK-NEXT:    csrr a1, vlenb7062; CHECK-NEXT:    srli a2, a1, 17063; CHECK-NEXT:    vsetvli a3, zero, e32, mf2, ta, ma7064; CHECK-NEXT:    vsseg3e32.v v8, (a0)7065; CHECK-NEXT:    add a3, a0, a27066; CHECK-NEXT:    vle32.v v9, (a3)7067; CHECK-NEXT:    vle32.v v8, (a0)7068; CHECK-NEXT:    srli a1, a1, 37069; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma7070; CHECK-NEXT:    vslideup.vx v8, v9, a17071; CHECK-NEXT:    add a2, a3, a27072; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma7073; CHECK-NEXT:    vle32.v v9, (a2)7074; CHECK-NEXT:    csrr a0, vlenb7075; CHECK-NEXT:    slli a0, a0, 17076; CHECK-NEXT:    add sp, sp, a07077; CHECK-NEXT:    addi sp, sp, 167078; CHECK-NEXT:    ret7079;7080; ZVBB-LABEL: vector_interleave_nxv3f32_nxv1f32:7081; ZVBB:       # %bb.0:7082; ZVBB-NEXT:    addi sp, sp, -167083; ZVBB-NEXT:    csrr a0, vlenb7084; ZVBB-NEXT:    slli a0, a0, 17085; ZVBB-NEXT:    sub sp, sp, a07086; ZVBB-NEXT:    addi a0, sp, 167087; ZVBB-NEXT:    csrr a1, vlenb7088; ZVBB-NEXT:    srli a2, a1, 17089; ZVBB-NEXT:    vsetvli a3, zero, e32, mf2, ta, ma7090; ZVBB-NEXT:    vsseg3e32.v v8, (a0)7091; ZVBB-NEXT:    add a3, a0, a27092; ZVBB-NEXT:    vle32.v v9, (a3)7093; ZVBB-NEXT:    vle32.v v8, (a0)7094; ZVBB-NEXT:    srli a1, a1, 37095; ZVBB-NEXT:    vsetvli a0, zero, e32, m1, ta, ma7096; ZVBB-NEXT:    vslideup.vx v8, v9, a17097; ZVBB-NEXT:    add a2, a3, a27098; ZVBB-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma7099; ZVBB-NEXT:    vle32.v v9, (a2)7100; ZVBB-NEXT:    csrr a0, vlenb7101; ZVBB-NEXT:    slli a0, a0, 17102; ZVBB-NEXT:    add sp, sp, a07103; ZVBB-NEXT:    addi sp, sp, 167104; ZVBB-NEXT:    ret7105  %res = call <vscale x 3 x float> @llvm.vector.interleave3.nxv3f32(<vscale x 1 x float> %v0, <vscale x 1 x float> %v1, <vscale x 1 x float> %v2)7106  ret <vscale x 3 x float> %res7107}7108 7109define <vscale x 6 x float> @vector_interleave_nxv6f32_nxv2f32(<vscale x 2 x float> %v0, <vscale x 2 x float> %v1, <vscale x 2 x float> %v2) nounwind {7110; CHECK-LABEL: vector_interleave_nxv6f32_nxv2f32:7111; CHECK:       # %bb.0:7112; CHECK-NEXT:    addi sp, sp, -167113; CHECK-NEXT:    csrr a0, vlenb7114; CHECK-NEXT:    slli a1, a0, 17115; CHECK-NEXT:    add a0, a1, a07116; CHECK-NEXT:    sub sp, sp, a07117; CHECK-NEXT:    addi a0, sp, 167118; CHECK-NEXT:    csrr a1, vlenb7119; CHECK-NEXT:    vsetvli a2, zero, e32, m1, ta, ma7120; CHECK-NEXT:    vsseg3e32.v v8, (a0)7121; CHECK-NEXT:    vl1re32.v v8, (a0)7122; CHECK-NEXT:    add a0, a0, a17123; CHECK-NEXT:    vl1re32.v v9, (a0)7124; CHECK-NEXT:    add a0, a0, a17125; CHECK-NEXT:    vl1re32.v v10, (a0)7126; CHECK-NEXT:    csrr a0, vlenb7127; CHECK-NEXT:    slli a1, a0, 17128; CHECK-NEXT:    add a0, a1, a07129; CHECK-NEXT:    add sp, sp, a07130; CHECK-NEXT:    addi sp, sp, 167131; CHECK-NEXT:    ret7132;7133; ZVBB-LABEL: vector_interleave_nxv6f32_nxv2f32:7134; ZVBB:       # %bb.0:7135; ZVBB-NEXT:    addi sp, sp, -167136; ZVBB-NEXT:    csrr a0, vlenb7137; ZVBB-NEXT:    slli a1, a0, 17138; ZVBB-NEXT:    add a0, a1, a07139; ZVBB-NEXT:    sub sp, sp, a07140; ZVBB-NEXT:    addi a0, sp, 167141; ZVBB-NEXT:    csrr a1, vlenb7142; ZVBB-NEXT:    vsetvli a2, zero, e32, m1, ta, ma7143; ZVBB-NEXT:    vsseg3e32.v v8, (a0)7144; ZVBB-NEXT:    vl1re32.v v8, (a0)7145; ZVBB-NEXT:    add a0, a0, a17146; ZVBB-NEXT:    vl1re32.v v9, (a0)7147; ZVBB-NEXT:    add a0, a0, a17148; ZVBB-NEXT:    vl1re32.v v10, (a0)7149; ZVBB-NEXT:    csrr a0, vlenb7150; ZVBB-NEXT:    slli a1, a0, 17151; ZVBB-NEXT:    add a0, a1, a07152; ZVBB-NEXT:    add sp, sp, a07153; ZVBB-NEXT:    addi sp, sp, 167154; ZVBB-NEXT:    ret7155  %res = call <vscale x 6 x float> @llvm.vector.interleave3.nxv6f32(<vscale x 2 x float> %v0, <vscale x 2 x float> %v1, <vscale x 2 x float> %v2)7156  ret <vscale x 6 x float> %res7157}7158 7159define <vscale x 12 x float> @vector_interleave_nxv12f32_nxv4f32(<vscale x 4 x float> %v0, <vscale x 4 x float> %v1, <vscale x 4 x float> %v2) nounwind {7160; CHECK-LABEL: vector_interleave_nxv12f32_nxv4f32:7161; CHECK:       # %bb.0:7162; CHECK-NEXT:    addi sp, sp, -167163; CHECK-NEXT:    csrr a0, vlenb7164; CHECK-NEXT:    li a1, 67165; CHECK-NEXT:    mul a0, a0, a17166; CHECK-NEXT:    sub sp, sp, a07167; CHECK-NEXT:    addi a0, sp, 167168; CHECK-NEXT:    csrr a1, vlenb7169; CHECK-NEXT:    slli a1, a1, 17170; CHECK-NEXT:    vsetvli a2, zero, e32, m2, ta, ma7171; CHECK-NEXT:    vsseg3e32.v v8, (a0)7172; CHECK-NEXT:    vl2re32.v v8, (a0)7173; CHECK-NEXT:    add a0, a0, a17174; CHECK-NEXT:    vl2re32.v v10, (a0)7175; CHECK-NEXT:    add a0, a0, a17176; CHECK-NEXT:    vl2re32.v v12, (a0)7177; CHECK-NEXT:    csrr a0, vlenb7178; CHECK-NEXT:    li a1, 67179; CHECK-NEXT:    mul a0, a0, a17180; CHECK-NEXT:    add sp, sp, a07181; CHECK-NEXT:    addi sp, sp, 167182; CHECK-NEXT:    ret7183;7184; ZVBB-LABEL: vector_interleave_nxv12f32_nxv4f32:7185; ZVBB:       # %bb.0:7186; ZVBB-NEXT:    addi sp, sp, -167187; ZVBB-NEXT:    csrr a0, vlenb7188; ZVBB-NEXT:    li a1, 67189; ZVBB-NEXT:    mul a0, a0, a17190; ZVBB-NEXT:    sub sp, sp, a07191; ZVBB-NEXT:    addi a0, sp, 167192; ZVBB-NEXT:    csrr a1, vlenb7193; ZVBB-NEXT:    slli a1, a1, 17194; ZVBB-NEXT:    vsetvli a2, zero, e32, m2, ta, ma7195; ZVBB-NEXT:    vsseg3e32.v v8, (a0)7196; ZVBB-NEXT:    vl2re32.v v8, (a0)7197; ZVBB-NEXT:    add a0, a0, a17198; ZVBB-NEXT:    vl2re32.v v10, (a0)7199; ZVBB-NEXT:    add a0, a0, a17200; ZVBB-NEXT:    vl2re32.v v12, (a0)7201; ZVBB-NEXT:    csrr a0, vlenb7202; ZVBB-NEXT:    li a1, 67203; ZVBB-NEXT:    mul a0, a0, a17204; ZVBB-NEXT:    add sp, sp, a07205; ZVBB-NEXT:    addi sp, sp, 167206; ZVBB-NEXT:    ret7207  %res = call <vscale x 12 x float> @llvm.vector.interleave3.nxv12f32(<vscale x 4 x float> %v0, <vscale x 4 x float> %v1, <vscale x 4 x float> %v2)7208  ret <vscale x 12 x float> %res7209}7210 7211define <vscale x 3 x double> @vector_interleave_nxv3f64_nxv1f64(<vscale x 1 x double> %v0, <vscale x 1 x double> %v1, <vscale x 1 x double> %v2) nounwind {7212; CHECK-LABEL: vector_interleave_nxv3f64_nxv1f64:7213; CHECK:       # %bb.0:7214; CHECK-NEXT:    addi sp, sp, -167215; CHECK-NEXT:    csrr a0, vlenb7216; CHECK-NEXT:    slli a1, a0, 17217; CHECK-NEXT:    add a0, a1, a07218; CHECK-NEXT:    sub sp, sp, a07219; CHECK-NEXT:    addi a0, sp, 167220; CHECK-NEXT:    csrr a1, vlenb7221; CHECK-NEXT:    vsetvli a2, zero, e64, m1, ta, ma7222; CHECK-NEXT:    vsseg3e64.v v8, (a0)7223; CHECK-NEXT:    vl1re64.v v8, (a0)7224; CHECK-NEXT:    add a0, a0, a17225; CHECK-NEXT:    vl1re64.v v9, (a0)7226; CHECK-NEXT:    add a0, a0, a17227; CHECK-NEXT:    vl1re64.v v10, (a0)7228; CHECK-NEXT:    csrr a0, vlenb7229; CHECK-NEXT:    slli a1, a0, 17230; CHECK-NEXT:    add a0, a1, a07231; CHECK-NEXT:    add sp, sp, a07232; CHECK-NEXT:    addi sp, sp, 167233; CHECK-NEXT:    ret7234;7235; ZVBB-LABEL: vector_interleave_nxv3f64_nxv1f64:7236; ZVBB:       # %bb.0:7237; ZVBB-NEXT:    addi sp, sp, -167238; ZVBB-NEXT:    csrr a0, vlenb7239; ZVBB-NEXT:    slli a1, a0, 17240; ZVBB-NEXT:    add a0, a1, a07241; ZVBB-NEXT:    sub sp, sp, a07242; ZVBB-NEXT:    addi a0, sp, 167243; ZVBB-NEXT:    csrr a1, vlenb7244; ZVBB-NEXT:    vsetvli a2, zero, e64, m1, ta, ma7245; ZVBB-NEXT:    vsseg3e64.v v8, (a0)7246; ZVBB-NEXT:    vl1re64.v v8, (a0)7247; ZVBB-NEXT:    add a0, a0, a17248; ZVBB-NEXT:    vl1re64.v v9, (a0)7249; ZVBB-NEXT:    add a0, a0, a17250; ZVBB-NEXT:    vl1re64.v v10, (a0)7251; ZVBB-NEXT:    csrr a0, vlenb7252; ZVBB-NEXT:    slli a1, a0, 17253; ZVBB-NEXT:    add a0, a1, a07254; ZVBB-NEXT:    add sp, sp, a07255; ZVBB-NEXT:    addi sp, sp, 167256; ZVBB-NEXT:    ret7257  %res = call <vscale x 3 x double> @llvm.vector.interleave3.nxv3f64(<vscale x 1 x double> %v0, <vscale x 1 x double> %v1, <vscale x 1 x double> %v2)7258  ret <vscale x 3 x double> %res7259}7260 7261define <vscale x 6 x double> @vector_interleave_nxv6f64_nxv2f64(<vscale x 2 x double> %v0, <vscale x 2 x double> %v1, <vscale x 2 x double> %v2) nounwind {7262; CHECK-LABEL: vector_interleave_nxv6f64_nxv2f64:7263; CHECK:       # %bb.0:7264; CHECK-NEXT:    addi sp, sp, -167265; CHECK-NEXT:    csrr a0, vlenb7266; CHECK-NEXT:    li a1, 67267; CHECK-NEXT:    mul a0, a0, a17268; CHECK-NEXT:    sub sp, sp, a07269; CHECK-NEXT:    addi a0, sp, 167270; CHECK-NEXT:    csrr a1, vlenb7271; CHECK-NEXT:    slli a1, a1, 17272; CHECK-NEXT:    vsetvli a2, zero, e64, m2, ta, ma7273; CHECK-NEXT:    vsseg3e64.v v8, (a0)7274; CHECK-NEXT:    vl2re64.v v8, (a0)7275; CHECK-NEXT:    add a0, a0, a17276; CHECK-NEXT:    vl2re64.v v10, (a0)7277; CHECK-NEXT:    add a0, a0, a17278; CHECK-NEXT:    vl2re64.v v12, (a0)7279; CHECK-NEXT:    csrr a0, vlenb7280; CHECK-NEXT:    li a1, 67281; CHECK-NEXT:    mul a0, a0, a17282; CHECK-NEXT:    add sp, sp, a07283; CHECK-NEXT:    addi sp, sp, 167284; CHECK-NEXT:    ret7285;7286; ZVBB-LABEL: vector_interleave_nxv6f64_nxv2f64:7287; ZVBB:       # %bb.0:7288; ZVBB-NEXT:    addi sp, sp, -167289; ZVBB-NEXT:    csrr a0, vlenb7290; ZVBB-NEXT:    li a1, 67291; ZVBB-NEXT:    mul a0, a0, a17292; ZVBB-NEXT:    sub sp, sp, a07293; ZVBB-NEXT:    addi a0, sp, 167294; ZVBB-NEXT:    csrr a1, vlenb7295; ZVBB-NEXT:    slli a1, a1, 17296; ZVBB-NEXT:    vsetvli a2, zero, e64, m2, ta, ma7297; ZVBB-NEXT:    vsseg3e64.v v8, (a0)7298; ZVBB-NEXT:    vl2re64.v v8, (a0)7299; ZVBB-NEXT:    add a0, a0, a17300; ZVBB-NEXT:    vl2re64.v v10, (a0)7301; ZVBB-NEXT:    add a0, a0, a17302; ZVBB-NEXT:    vl2re64.v v12, (a0)7303; ZVBB-NEXT:    csrr a0, vlenb7304; ZVBB-NEXT:    li a1, 67305; ZVBB-NEXT:    mul a0, a0, a17306; ZVBB-NEXT:    add sp, sp, a07307; ZVBB-NEXT:    addi sp, sp, 167308; ZVBB-NEXT:    ret7309  %res = call <vscale x 6 x double> @llvm.vector.interleave3.nxv6f64(<vscale x 2 x double> %v0, <vscale x 2 x double> %v1, <vscale x 2 x double> %v2)7310  ret <vscale x 6 x double> %res7311}7312 7313define <vscale x 8 x half> @vector_interleave_nxv8f16_nxv2f16(<vscale x 2 x half> %v0, <vscale x 2 x half> %v1, <vscale x 2 x half> %v2, <vscale x 2 x half> %v3) nounwind {7314; CHECK-LABEL: vector_interleave_nxv8f16_nxv2f16:7315; CHECK:       # %bb.0:7316; CHECK-NEXT:    addi sp, sp, -167317; CHECK-NEXT:    csrr a0, vlenb7318; CHECK-NEXT:    slli a0, a0, 17319; CHECK-NEXT:    sub sp, sp, a07320; CHECK-NEXT:    addi a0, sp, 167321; CHECK-NEXT:    csrr a1, vlenb7322; CHECK-NEXT:    srli a2, a1, 17323; CHECK-NEXT:    add a3, a0, a27324; CHECK-NEXT:    vsetvli a4, zero, e16, mf2, ta, ma7325; CHECK-NEXT:    vsseg4e16.v v8, (a0)7326; CHECK-NEXT:    add a4, a3, a27327; CHECK-NEXT:    add a2, a4, a27328; CHECK-NEXT:    vle16.v v9, (a4)7329; CHECK-NEXT:    vle16.v v8, (a2)7330; CHECK-NEXT:    srli a1, a1, 27331; CHECK-NEXT:    vsetvli a2, zero, e16, m1, ta, ma7332; CHECK-NEXT:    vslideup.vx v9, v8, a17333; CHECK-NEXT:    vsetvli a2, zero, e16, mf2, ta, ma7334; CHECK-NEXT:    vle16.v v10, (a3)7335; CHECK-NEXT:    vle16.v v8, (a0)7336; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma7337; CHECK-NEXT:    vslideup.vx v8, v10, a17338; CHECK-NEXT:    csrr a0, vlenb7339; CHECK-NEXT:    slli a0, a0, 17340; CHECK-NEXT:    add sp, sp, a07341; CHECK-NEXT:    addi sp, sp, 167342; CHECK-NEXT:    ret7343;7344; ZVBB-LABEL: vector_interleave_nxv8f16_nxv2f16:7345; ZVBB:       # %bb.0:7346; ZVBB-NEXT:    addi sp, sp, -167347; ZVBB-NEXT:    csrr a0, vlenb7348; ZVBB-NEXT:    slli a0, a0, 17349; ZVBB-NEXT:    sub sp, sp, a07350; ZVBB-NEXT:    addi a0, sp, 167351; ZVBB-NEXT:    csrr a1, vlenb7352; ZVBB-NEXT:    srli a2, a1, 17353; ZVBB-NEXT:    add a3, a0, a27354; ZVBB-NEXT:    vsetvli a4, zero, e16, mf2, ta, ma7355; ZVBB-NEXT:    vsseg4e16.v v8, (a0)7356; ZVBB-NEXT:    add a4, a3, a27357; ZVBB-NEXT:    add a2, a4, a27358; ZVBB-NEXT:    vle16.v v9, (a4)7359; ZVBB-NEXT:    vle16.v v8, (a2)7360; ZVBB-NEXT:    srli a1, a1, 27361; ZVBB-NEXT:    vsetvli a2, zero, e16, m1, ta, ma7362; ZVBB-NEXT:    vslideup.vx v9, v8, a17363; ZVBB-NEXT:    vsetvli a2, zero, e16, mf2, ta, ma7364; ZVBB-NEXT:    vle16.v v10, (a3)7365; ZVBB-NEXT:    vle16.v v8, (a0)7366; ZVBB-NEXT:    vsetvli a0, zero, e16, m1, ta, ma7367; ZVBB-NEXT:    vslideup.vx v8, v10, a17368; ZVBB-NEXT:    csrr a0, vlenb7369; ZVBB-NEXT:    slli a0, a0, 17370; ZVBB-NEXT:    add sp, sp, a07371; ZVBB-NEXT:    addi sp, sp, 167372; ZVBB-NEXT:    ret7373  %res = call <vscale x 8 x half> @llvm.vector.interleave4.nxv8f16(<vscale x 2 x half> %v0, <vscale x 2 x half> %v1, <vscale x 2 x half> %v2, <vscale x 2 x half> %v3)7374  ret <vscale x 8 x half> %res7375}7376 7377define <vscale x 16 x half> @vector_interleave_nxv16f16_nxv4f16(<vscale x 4 x half> %v0, <vscale x 4 x half> %v1, <vscale x 4 x half> %v2, <vscale x 4 x half> %v3) nounwind {7378; CHECK-LABEL: vector_interleave_nxv16f16_nxv4f16:7379; CHECK:       # %bb.0:7380; CHECK-NEXT:    addi sp, sp, -167381; CHECK-NEXT:    csrr a0, vlenb7382; CHECK-NEXT:    slli a0, a0, 27383; CHECK-NEXT:    sub sp, sp, a07384; CHECK-NEXT:    addi a0, sp, 167385; CHECK-NEXT:    csrr a1, vlenb7386; CHECK-NEXT:    add a2, a0, a17387; CHECK-NEXT:    add a3, a2, a17388; CHECK-NEXT:    vsetvli a4, zero, e16, m1, ta, ma7389; CHECK-NEXT:    vsseg4e16.v v8, (a0)7390; CHECK-NEXT:    vl1re16.v v10, (a3)7391; CHECK-NEXT:    add a1, a3, a17392; CHECK-NEXT:    vl1re16.v v11, (a1)7393; CHECK-NEXT:    vl1re16.v v8, (a0)7394; CHECK-NEXT:    vl1re16.v v9, (a2)7395; CHECK-NEXT:    csrr a0, vlenb7396; CHECK-NEXT:    slli a0, a0, 27397; CHECK-NEXT:    add sp, sp, a07398; CHECK-NEXT:    addi sp, sp, 167399; CHECK-NEXT:    ret7400;7401; ZVBB-LABEL: vector_interleave_nxv16f16_nxv4f16:7402; ZVBB:       # %bb.0:7403; ZVBB-NEXT:    addi sp, sp, -167404; ZVBB-NEXT:    csrr a0, vlenb7405; ZVBB-NEXT:    slli a0, a0, 27406; ZVBB-NEXT:    sub sp, sp, a07407; ZVBB-NEXT:    addi a0, sp, 167408; ZVBB-NEXT:    csrr a1, vlenb7409; ZVBB-NEXT:    add a2, a0, a17410; ZVBB-NEXT:    add a3, a2, a17411; ZVBB-NEXT:    vsetvli a4, zero, e16, m1, ta, ma7412; ZVBB-NEXT:    vsseg4e16.v v8, (a0)7413; ZVBB-NEXT:    vl1re16.v v10, (a3)7414; ZVBB-NEXT:    add a1, a3, a17415; ZVBB-NEXT:    vl1re16.v v11, (a1)7416; ZVBB-NEXT:    vl1re16.v v8, (a0)7417; ZVBB-NEXT:    vl1re16.v v9, (a2)7418; ZVBB-NEXT:    csrr a0, vlenb7419; ZVBB-NEXT:    slli a0, a0, 27420; ZVBB-NEXT:    add sp, sp, a07421; ZVBB-NEXT:    addi sp, sp, 167422; ZVBB-NEXT:    ret7423  %res = call <vscale x 16 x half> @llvm.vector.interleave4.nxv16f16(<vscale x 4 x half> %v0, <vscale x 4 x half> %v1, <vscale x 4 x half> %v2, <vscale x 4 x half> %v3)7424  ret <vscale x 16 x half> %res7425}7426 7427define <vscale x 32 x half> @vector_interleave_nxv32f16_nxv8f16(<vscale x 8 x half> %v0, <vscale x 8 x half> %v1, <vscale x 8 x half> %v2, <vscale x 8 x half> %v3) nounwind {7428; CHECK-LABEL: vector_interleave_nxv32f16_nxv8f16:7429; CHECK:       # %bb.0:7430; CHECK-NEXT:    addi sp, sp, -167431; CHECK-NEXT:    csrr a0, vlenb7432; CHECK-NEXT:    slli a0, a0, 37433; CHECK-NEXT:    sub sp, sp, a07434; CHECK-NEXT:    addi a0, sp, 167435; CHECK-NEXT:    csrr a1, vlenb7436; CHECK-NEXT:    slli a1, a1, 17437; CHECK-NEXT:    add a2, a0, a17438; CHECK-NEXT:    vsetvli a3, zero, e16, m2, ta, ma7439; CHECK-NEXT:    vsseg4e16.v v8, (a0)7440; CHECK-NEXT:    add a3, a2, a17441; CHECK-NEXT:    vl2re16.v v12, (a3)7442; CHECK-NEXT:    add a1, a3, a17443; CHECK-NEXT:    vl2re16.v v14, (a1)7444; CHECK-NEXT:    vl2re16.v v8, (a0)7445; CHECK-NEXT:    vl2re16.v v10, (a2)7446; CHECK-NEXT:    csrr a0, vlenb7447; CHECK-NEXT:    slli a0, a0, 37448; CHECK-NEXT:    add sp, sp, a07449; CHECK-NEXT:    addi sp, sp, 167450; CHECK-NEXT:    ret7451;7452; ZVBB-LABEL: vector_interleave_nxv32f16_nxv8f16:7453; ZVBB:       # %bb.0:7454; ZVBB-NEXT:    addi sp, sp, -167455; ZVBB-NEXT:    csrr a0, vlenb7456; ZVBB-NEXT:    slli a0, a0, 37457; ZVBB-NEXT:    sub sp, sp, a07458; ZVBB-NEXT:    addi a0, sp, 167459; ZVBB-NEXT:    csrr a1, vlenb7460; ZVBB-NEXT:    slli a1, a1, 17461; ZVBB-NEXT:    add a2, a0, a17462; ZVBB-NEXT:    vsetvli a3, zero, e16, m2, ta, ma7463; ZVBB-NEXT:    vsseg4e16.v v8, (a0)7464; ZVBB-NEXT:    add a3, a2, a17465; ZVBB-NEXT:    vl2re16.v v12, (a3)7466; ZVBB-NEXT:    add a1, a3, a17467; ZVBB-NEXT:    vl2re16.v v14, (a1)7468; ZVBB-NEXT:    vl2re16.v v8, (a0)7469; ZVBB-NEXT:    vl2re16.v v10, (a2)7470; ZVBB-NEXT:    csrr a0, vlenb7471; ZVBB-NEXT:    slli a0, a0, 37472; ZVBB-NEXT:    add sp, sp, a07473; ZVBB-NEXT:    addi sp, sp, 167474; ZVBB-NEXT:    ret7475  %res = call <vscale x 32 x half> @llvm.vector.interleave4.nxv32f16(<vscale x 8 x half> %v0, <vscale x 8 x half> %v1, <vscale x 8 x half> %v2, <vscale x 8 x half> %v3)7476  ret <vscale x 32 x half> %res7477}7478 7479define <vscale x 8 x bfloat> @vector_interleave_nxv8bf16_nxv2bf16(<vscale x 2 x bfloat> %v0, <vscale x 2 x bfloat> %v1, <vscale x 2 x bfloat> %v2, <vscale x 2 x bfloat> %v3) nounwind {7480; CHECK-LABEL: vector_interleave_nxv8bf16_nxv2bf16:7481; CHECK:       # %bb.0:7482; CHECK-NEXT:    addi sp, sp, -167483; CHECK-NEXT:    csrr a0, vlenb7484; CHECK-NEXT:    slli a0, a0, 17485; CHECK-NEXT:    sub sp, sp, a07486; CHECK-NEXT:    addi a0, sp, 167487; CHECK-NEXT:    csrr a1, vlenb7488; CHECK-NEXT:    srli a2, a1, 17489; CHECK-NEXT:    add a3, a0, a27490; CHECK-NEXT:    vsetvli a4, zero, e16, mf2, ta, ma7491; CHECK-NEXT:    vsseg4e16.v v8, (a0)7492; CHECK-NEXT:    add a4, a3, a27493; CHECK-NEXT:    add a2, a4, a27494; CHECK-NEXT:    vle16.v v9, (a4)7495; CHECK-NEXT:    vle16.v v8, (a2)7496; CHECK-NEXT:    srli a1, a1, 27497; CHECK-NEXT:    vsetvli a2, zero, e16, m1, ta, ma7498; CHECK-NEXT:    vslideup.vx v9, v8, a17499; CHECK-NEXT:    vsetvli a2, zero, e16, mf2, ta, ma7500; CHECK-NEXT:    vle16.v v10, (a3)7501; CHECK-NEXT:    vle16.v v8, (a0)7502; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma7503; CHECK-NEXT:    vslideup.vx v8, v10, a17504; CHECK-NEXT:    csrr a0, vlenb7505; CHECK-NEXT:    slli a0, a0, 17506; CHECK-NEXT:    add sp, sp, a07507; CHECK-NEXT:    addi sp, sp, 167508; CHECK-NEXT:    ret7509;7510; ZVBB-LABEL: vector_interleave_nxv8bf16_nxv2bf16:7511; ZVBB:       # %bb.0:7512; ZVBB-NEXT:    addi sp, sp, -167513; ZVBB-NEXT:    csrr a0, vlenb7514; ZVBB-NEXT:    slli a0, a0, 17515; ZVBB-NEXT:    sub sp, sp, a07516; ZVBB-NEXT:    addi a0, sp, 167517; ZVBB-NEXT:    csrr a1, vlenb7518; ZVBB-NEXT:    srli a2, a1, 17519; ZVBB-NEXT:    add a3, a0, a27520; ZVBB-NEXT:    vsetvli a4, zero, e16, mf2, ta, ma7521; ZVBB-NEXT:    vsseg4e16.v v8, (a0)7522; ZVBB-NEXT:    add a4, a3, a27523; ZVBB-NEXT:    add a2, a4, a27524; ZVBB-NEXT:    vle16.v v9, (a4)7525; ZVBB-NEXT:    vle16.v v8, (a2)7526; ZVBB-NEXT:    srli a1, a1, 27527; ZVBB-NEXT:    vsetvli a2, zero, e16, m1, ta, ma7528; ZVBB-NEXT:    vslideup.vx v9, v8, a17529; ZVBB-NEXT:    vsetvli a2, zero, e16, mf2, ta, ma7530; ZVBB-NEXT:    vle16.v v10, (a3)7531; ZVBB-NEXT:    vle16.v v8, (a0)7532; ZVBB-NEXT:    vsetvli a0, zero, e16, m1, ta, ma7533; ZVBB-NEXT:    vslideup.vx v8, v10, a17534; ZVBB-NEXT:    csrr a0, vlenb7535; ZVBB-NEXT:    slli a0, a0, 17536; ZVBB-NEXT:    add sp, sp, a07537; ZVBB-NEXT:    addi sp, sp, 167538; ZVBB-NEXT:    ret7539  %res = call <vscale x 8 x bfloat> @llvm.vector.interleave4.nxv8bf16(<vscale x 2 x bfloat> %v0, <vscale x 2 x bfloat> %v1, <vscale x 2 x bfloat> %v2, <vscale x 2 x bfloat> %v3)7540  ret <vscale x 8 x bfloat> %res7541}7542 7543define <vscale x 16 x bfloat> @vector_interleave_nxv16bf16_nxv4bf16(<vscale x 4 x bfloat> %v0, <vscale x 4 x bfloat> %v1, <vscale x 4 x bfloat> %v2, <vscale x 4 x bfloat> %v3) nounwind {7544; CHECK-LABEL: vector_interleave_nxv16bf16_nxv4bf16:7545; CHECK:       # %bb.0:7546; CHECK-NEXT:    addi sp, sp, -167547; CHECK-NEXT:    csrr a0, vlenb7548; CHECK-NEXT:    slli a0, a0, 27549; CHECK-NEXT:    sub sp, sp, a07550; CHECK-NEXT:    addi a0, sp, 167551; CHECK-NEXT:    csrr a1, vlenb7552; CHECK-NEXT:    add a2, a0, a17553; CHECK-NEXT:    add a3, a2, a17554; CHECK-NEXT:    vsetvli a4, zero, e16, m1, ta, ma7555; CHECK-NEXT:    vsseg4e16.v v8, (a0)7556; CHECK-NEXT:    vl1re16.v v10, (a3)7557; CHECK-NEXT:    add a1, a3, a17558; CHECK-NEXT:    vl1re16.v v11, (a1)7559; CHECK-NEXT:    vl1re16.v v8, (a0)7560; CHECK-NEXT:    vl1re16.v v9, (a2)7561; CHECK-NEXT:    csrr a0, vlenb7562; CHECK-NEXT:    slli a0, a0, 27563; CHECK-NEXT:    add sp, sp, a07564; CHECK-NEXT:    addi sp, sp, 167565; CHECK-NEXT:    ret7566;7567; ZVBB-LABEL: vector_interleave_nxv16bf16_nxv4bf16:7568; ZVBB:       # %bb.0:7569; ZVBB-NEXT:    addi sp, sp, -167570; ZVBB-NEXT:    csrr a0, vlenb7571; ZVBB-NEXT:    slli a0, a0, 27572; ZVBB-NEXT:    sub sp, sp, a07573; ZVBB-NEXT:    addi a0, sp, 167574; ZVBB-NEXT:    csrr a1, vlenb7575; ZVBB-NEXT:    add a2, a0, a17576; ZVBB-NEXT:    add a3, a2, a17577; ZVBB-NEXT:    vsetvli a4, zero, e16, m1, ta, ma7578; ZVBB-NEXT:    vsseg4e16.v v8, (a0)7579; ZVBB-NEXT:    vl1re16.v v10, (a3)7580; ZVBB-NEXT:    add a1, a3, a17581; ZVBB-NEXT:    vl1re16.v v11, (a1)7582; ZVBB-NEXT:    vl1re16.v v8, (a0)7583; ZVBB-NEXT:    vl1re16.v v9, (a2)7584; ZVBB-NEXT:    csrr a0, vlenb7585; ZVBB-NEXT:    slli a0, a0, 27586; ZVBB-NEXT:    add sp, sp, a07587; ZVBB-NEXT:    addi sp, sp, 167588; ZVBB-NEXT:    ret7589  %res = call <vscale x 16 x bfloat> @llvm.vector.interleave4.nxv16bf16(<vscale x 4 x bfloat> %v0, <vscale x 4 x bfloat> %v1, <vscale x 4 x bfloat> %v2, <vscale x 4 x bfloat> %v3)7590  ret <vscale x 16 x bfloat> %res7591}7592 7593define <vscale x 32 x bfloat> @vector_interleave_nxv32bf16_nxv8bf16(<vscale x 8 x bfloat> %v0, <vscale x 8 x bfloat> %v1, <vscale x 8 x bfloat> %v2, <vscale x 8 x bfloat> %v3) nounwind {7594; CHECK-LABEL: vector_interleave_nxv32bf16_nxv8bf16:7595; CHECK:       # %bb.0:7596; CHECK-NEXT:    addi sp, sp, -167597; CHECK-NEXT:    csrr a0, vlenb7598; CHECK-NEXT:    slli a0, a0, 37599; CHECK-NEXT:    sub sp, sp, a07600; CHECK-NEXT:    addi a0, sp, 167601; CHECK-NEXT:    csrr a1, vlenb7602; CHECK-NEXT:    slli a1, a1, 17603; CHECK-NEXT:    add a2, a0, a17604; CHECK-NEXT:    vsetvli a3, zero, e16, m2, ta, ma7605; CHECK-NEXT:    vsseg4e16.v v8, (a0)7606; CHECK-NEXT:    add a3, a2, a17607; CHECK-NEXT:    vl2re16.v v12, (a3)7608; CHECK-NEXT:    add a1, a3, a17609; CHECK-NEXT:    vl2re16.v v14, (a1)7610; CHECK-NEXT:    vl2re16.v v8, (a0)7611; CHECK-NEXT:    vl2re16.v v10, (a2)7612; CHECK-NEXT:    csrr a0, vlenb7613; CHECK-NEXT:    slli a0, a0, 37614; CHECK-NEXT:    add sp, sp, a07615; CHECK-NEXT:    addi sp, sp, 167616; CHECK-NEXT:    ret7617;7618; ZVBB-LABEL: vector_interleave_nxv32bf16_nxv8bf16:7619; ZVBB:       # %bb.0:7620; ZVBB-NEXT:    addi sp, sp, -167621; ZVBB-NEXT:    csrr a0, vlenb7622; ZVBB-NEXT:    slli a0, a0, 37623; ZVBB-NEXT:    sub sp, sp, a07624; ZVBB-NEXT:    addi a0, sp, 167625; ZVBB-NEXT:    csrr a1, vlenb7626; ZVBB-NEXT:    slli a1, a1, 17627; ZVBB-NEXT:    add a2, a0, a17628; ZVBB-NEXT:    vsetvli a3, zero, e16, m2, ta, ma7629; ZVBB-NEXT:    vsseg4e16.v v8, (a0)7630; ZVBB-NEXT:    add a3, a2, a17631; ZVBB-NEXT:    vl2re16.v v12, (a3)7632; ZVBB-NEXT:    add a1, a3, a17633; ZVBB-NEXT:    vl2re16.v v14, (a1)7634; ZVBB-NEXT:    vl2re16.v v8, (a0)7635; ZVBB-NEXT:    vl2re16.v v10, (a2)7636; ZVBB-NEXT:    csrr a0, vlenb7637; ZVBB-NEXT:    slli a0, a0, 37638; ZVBB-NEXT:    add sp, sp, a07639; ZVBB-NEXT:    addi sp, sp, 167640; ZVBB-NEXT:    ret7641  %res = call <vscale x 32 x bfloat> @llvm.vector.interleave4.nxv32bf16(<vscale x 8 x bfloat> %v0, <vscale x 8 x bfloat> %v1, <vscale x 8 x bfloat> %v2, <vscale x 8 x bfloat> %v3)7642  ret <vscale x 32 x bfloat> %res7643}7644 7645define <vscale x 4 x float> @vector_interleave_nxv4f32_nxv1f32(<vscale x 1 x float> %v0, <vscale x 1 x float> %v1, <vscale x 1 x float> %v2, <vscale x 1 x float> %v3) nounwind {7646; CHECK-LABEL: vector_interleave_nxv4f32_nxv1f32:7647; CHECK:       # %bb.0:7648; CHECK-NEXT:    addi sp, sp, -167649; CHECK-NEXT:    csrr a0, vlenb7650; CHECK-NEXT:    slli a0, a0, 17651; CHECK-NEXT:    sub sp, sp, a07652; CHECK-NEXT:    addi a0, sp, 167653; CHECK-NEXT:    csrr a1, vlenb7654; CHECK-NEXT:    srli a2, a1, 17655; CHECK-NEXT:    add a3, a0, a27656; CHECK-NEXT:    vsetvli a4, zero, e32, mf2, ta, ma7657; CHECK-NEXT:    vsseg4e32.v v8, (a0)7658; CHECK-NEXT:    add a4, a3, a27659; CHECK-NEXT:    add a2, a4, a27660; CHECK-NEXT:    vle32.v v9, (a4)7661; CHECK-NEXT:    vle32.v v8, (a2)7662; CHECK-NEXT:    srli a1, a1, 37663; CHECK-NEXT:    vsetvli a2, zero, e32, m1, ta, ma7664; CHECK-NEXT:    vslideup.vx v9, v8, a17665; CHECK-NEXT:    vsetvli a2, zero, e32, mf2, ta, ma7666; CHECK-NEXT:    vle32.v v10, (a3)7667; CHECK-NEXT:    vle32.v v8, (a0)7668; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma7669; CHECK-NEXT:    vslideup.vx v8, v10, a17670; CHECK-NEXT:    csrr a0, vlenb7671; CHECK-NEXT:    slli a0, a0, 17672; CHECK-NEXT:    add sp, sp, a07673; CHECK-NEXT:    addi sp, sp, 167674; CHECK-NEXT:    ret7675;7676; ZVBB-LABEL: vector_interleave_nxv4f32_nxv1f32:7677; ZVBB:       # %bb.0:7678; ZVBB-NEXT:    addi sp, sp, -167679; ZVBB-NEXT:    csrr a0, vlenb7680; ZVBB-NEXT:    slli a0, a0, 17681; ZVBB-NEXT:    sub sp, sp, a07682; ZVBB-NEXT:    addi a0, sp, 167683; ZVBB-NEXT:    csrr a1, vlenb7684; ZVBB-NEXT:    srli a2, a1, 17685; ZVBB-NEXT:    add a3, a0, a27686; ZVBB-NEXT:    vsetvli a4, zero, e32, mf2, ta, ma7687; ZVBB-NEXT:    vsseg4e32.v v8, (a0)7688; ZVBB-NEXT:    add a4, a3, a27689; ZVBB-NEXT:    add a2, a4, a27690; ZVBB-NEXT:    vle32.v v9, (a4)7691; ZVBB-NEXT:    vle32.v v8, (a2)7692; ZVBB-NEXT:    srli a1, a1, 37693; ZVBB-NEXT:    vsetvli a2, zero, e32, m1, ta, ma7694; ZVBB-NEXT:    vslideup.vx v9, v8, a17695; ZVBB-NEXT:    vsetvli a2, zero, e32, mf2, ta, ma7696; ZVBB-NEXT:    vle32.v v10, (a3)7697; ZVBB-NEXT:    vle32.v v8, (a0)7698; ZVBB-NEXT:    vsetvli a0, zero, e32, m1, ta, ma7699; ZVBB-NEXT:    vslideup.vx v8, v10, a17700; ZVBB-NEXT:    csrr a0, vlenb7701; ZVBB-NEXT:    slli a0, a0, 17702; ZVBB-NEXT:    add sp, sp, a07703; ZVBB-NEXT:    addi sp, sp, 167704; ZVBB-NEXT:    ret7705  %res = call <vscale x 4 x float> @llvm.vector.interleave4.nxv4f32(<vscale x 1 x float> %v0, <vscale x 1 x float> %v1, <vscale x 1 x float> %v2, <vscale x 1 x float> %v3)7706  ret <vscale x 4 x float> %res7707}7708 7709define <vscale x 8 x float> @vector_interleave_nxv8f32_nxv2f32(<vscale x 2 x float> %v0, <vscale x 2 x float> %v1, <vscale x 2 x float> %v2, <vscale x 2 x float> %v3) nounwind {7710; CHECK-LABEL: vector_interleave_nxv8f32_nxv2f32:7711; CHECK:       # %bb.0:7712; CHECK-NEXT:    addi sp, sp, -167713; CHECK-NEXT:    csrr a0, vlenb7714; CHECK-NEXT:    slli a0, a0, 27715; CHECK-NEXT:    sub sp, sp, a07716; CHECK-NEXT:    addi a0, sp, 167717; CHECK-NEXT:    csrr a1, vlenb7718; CHECK-NEXT:    add a2, a0, a17719; CHECK-NEXT:    add a3, a2, a17720; CHECK-NEXT:    vsetvli a4, zero, e32, m1, ta, ma7721; CHECK-NEXT:    vsseg4e32.v v8, (a0)7722; CHECK-NEXT:    vl1re32.v v10, (a3)7723; CHECK-NEXT:    add a1, a3, a17724; CHECK-NEXT:    vl1re32.v v11, (a1)7725; CHECK-NEXT:    vl1re32.v v8, (a0)7726; CHECK-NEXT:    vl1re32.v v9, (a2)7727; CHECK-NEXT:    csrr a0, vlenb7728; CHECK-NEXT:    slli a0, a0, 27729; CHECK-NEXT:    add sp, sp, a07730; CHECK-NEXT:    addi sp, sp, 167731; CHECK-NEXT:    ret7732;7733; ZVBB-LABEL: vector_interleave_nxv8f32_nxv2f32:7734; ZVBB:       # %bb.0:7735; ZVBB-NEXT:    addi sp, sp, -167736; ZVBB-NEXT:    csrr a0, vlenb7737; ZVBB-NEXT:    slli a0, a0, 27738; ZVBB-NEXT:    sub sp, sp, a07739; ZVBB-NEXT:    addi a0, sp, 167740; ZVBB-NEXT:    csrr a1, vlenb7741; ZVBB-NEXT:    add a2, a0, a17742; ZVBB-NEXT:    add a3, a2, a17743; ZVBB-NEXT:    vsetvli a4, zero, e32, m1, ta, ma7744; ZVBB-NEXT:    vsseg4e32.v v8, (a0)7745; ZVBB-NEXT:    vl1re32.v v10, (a3)7746; ZVBB-NEXT:    add a1, a3, a17747; ZVBB-NEXT:    vl1re32.v v11, (a1)7748; ZVBB-NEXT:    vl1re32.v v8, (a0)7749; ZVBB-NEXT:    vl1re32.v v9, (a2)7750; ZVBB-NEXT:    csrr a0, vlenb7751; ZVBB-NEXT:    slli a0, a0, 27752; ZVBB-NEXT:    add sp, sp, a07753; ZVBB-NEXT:    addi sp, sp, 167754; ZVBB-NEXT:    ret7755  %res = call <vscale x 8 x float> @llvm.vector.interleave4.nxv8f32(<vscale x 2 x float> %v0, <vscale x 2 x float> %v1, <vscale x 2 x float> %v2, <vscale x 2 x float> %v3)7756  ret <vscale x 8 x float> %res7757}7758 7759define <vscale x 16 x float> @vector_interleave_nxv16f32_nxv4f32(<vscale x 4 x float> %v0, <vscale x 4 x float> %v1, <vscale x 4 x float> %v2, <vscale x 4 x float> %v3) nounwind {7760; CHECK-LABEL: vector_interleave_nxv16f32_nxv4f32:7761; CHECK:       # %bb.0:7762; CHECK-NEXT:    addi sp, sp, -167763; CHECK-NEXT:    csrr a0, vlenb7764; CHECK-NEXT:    slli a0, a0, 37765; CHECK-NEXT:    sub sp, sp, a07766; CHECK-NEXT:    addi a0, sp, 167767; CHECK-NEXT:    csrr a1, vlenb7768; CHECK-NEXT:    slli a1, a1, 17769; CHECK-NEXT:    add a2, a0, a17770; CHECK-NEXT:    vsetvli a3, zero, e32, m2, ta, ma7771; CHECK-NEXT:    vsseg4e32.v v8, (a0)7772; CHECK-NEXT:    add a3, a2, a17773; CHECK-NEXT:    vl2re32.v v12, (a3)7774; CHECK-NEXT:    add a1, a3, a17775; CHECK-NEXT:    vl2re32.v v14, (a1)7776; CHECK-NEXT:    vl2re32.v v8, (a0)7777; CHECK-NEXT:    vl2re32.v v10, (a2)7778; CHECK-NEXT:    csrr a0, vlenb7779; CHECK-NEXT:    slli a0, a0, 37780; CHECK-NEXT:    add sp, sp, a07781; CHECK-NEXT:    addi sp, sp, 167782; CHECK-NEXT:    ret7783;7784; ZVBB-LABEL: vector_interleave_nxv16f32_nxv4f32:7785; ZVBB:       # %bb.0:7786; ZVBB-NEXT:    addi sp, sp, -167787; ZVBB-NEXT:    csrr a0, vlenb7788; ZVBB-NEXT:    slli a0, a0, 37789; ZVBB-NEXT:    sub sp, sp, a07790; ZVBB-NEXT:    addi a0, sp, 167791; ZVBB-NEXT:    csrr a1, vlenb7792; ZVBB-NEXT:    slli a1, a1, 17793; ZVBB-NEXT:    add a2, a0, a17794; ZVBB-NEXT:    vsetvli a3, zero, e32, m2, ta, ma7795; ZVBB-NEXT:    vsseg4e32.v v8, (a0)7796; ZVBB-NEXT:    add a3, a2, a17797; ZVBB-NEXT:    vl2re32.v v12, (a3)7798; ZVBB-NEXT:    add a1, a3, a17799; ZVBB-NEXT:    vl2re32.v v14, (a1)7800; ZVBB-NEXT:    vl2re32.v v8, (a0)7801; ZVBB-NEXT:    vl2re32.v v10, (a2)7802; ZVBB-NEXT:    csrr a0, vlenb7803; ZVBB-NEXT:    slli a0, a0, 37804; ZVBB-NEXT:    add sp, sp, a07805; ZVBB-NEXT:    addi sp, sp, 167806; ZVBB-NEXT:    ret7807  %res = call <vscale x 16 x float> @llvm.vector.interleave4.nxv16f32(<vscale x 4 x float> %v0, <vscale x 4 x float> %v1, <vscale x 4 x float> %v2, <vscale x 4 x float> %v3)7808  ret <vscale x 16 x float> %res7809}7810 7811define <vscale x 4 x double> @vector_interleave_nxv4f64_nxv1f64(<vscale x 1 x double> %v0, <vscale x 1 x double> %v1, <vscale x 1 x double> %v2, <vscale x 1 x double> %v3) nounwind {7812; CHECK-LABEL: vector_interleave_nxv4f64_nxv1f64:7813; CHECK:       # %bb.0:7814; CHECK-NEXT:    addi sp, sp, -167815; CHECK-NEXT:    csrr a0, vlenb7816; CHECK-NEXT:    slli a0, a0, 27817; CHECK-NEXT:    sub sp, sp, a07818; CHECK-NEXT:    addi a0, sp, 167819; CHECK-NEXT:    csrr a1, vlenb7820; CHECK-NEXT:    add a2, a0, a17821; CHECK-NEXT:    add a3, a2, a17822; CHECK-NEXT:    vsetvli a4, zero, e64, m1, ta, ma7823; CHECK-NEXT:    vsseg4e64.v v8, (a0)7824; CHECK-NEXT:    vl1re64.v v10, (a3)7825; CHECK-NEXT:    add a1, a3, a17826; CHECK-NEXT:    vl1re64.v v11, (a1)7827; CHECK-NEXT:    vl1re64.v v8, (a0)7828; CHECK-NEXT:    vl1re64.v v9, (a2)7829; CHECK-NEXT:    csrr a0, vlenb7830; CHECK-NEXT:    slli a0, a0, 27831; CHECK-NEXT:    add sp, sp, a07832; CHECK-NEXT:    addi sp, sp, 167833; CHECK-NEXT:    ret7834;7835; ZVBB-LABEL: vector_interleave_nxv4f64_nxv1f64:7836; ZVBB:       # %bb.0:7837; ZVBB-NEXT:    addi sp, sp, -167838; ZVBB-NEXT:    csrr a0, vlenb7839; ZVBB-NEXT:    slli a0, a0, 27840; ZVBB-NEXT:    sub sp, sp, a07841; ZVBB-NEXT:    addi a0, sp, 167842; ZVBB-NEXT:    csrr a1, vlenb7843; ZVBB-NEXT:    add a2, a0, a17844; ZVBB-NEXT:    add a3, a2, a17845; ZVBB-NEXT:    vsetvli a4, zero, e64, m1, ta, ma7846; ZVBB-NEXT:    vsseg4e64.v v8, (a0)7847; ZVBB-NEXT:    vl1re64.v v10, (a3)7848; ZVBB-NEXT:    add a1, a3, a17849; ZVBB-NEXT:    vl1re64.v v11, (a1)7850; ZVBB-NEXT:    vl1re64.v v8, (a0)7851; ZVBB-NEXT:    vl1re64.v v9, (a2)7852; ZVBB-NEXT:    csrr a0, vlenb7853; ZVBB-NEXT:    slli a0, a0, 27854; ZVBB-NEXT:    add sp, sp, a07855; ZVBB-NEXT:    addi sp, sp, 167856; ZVBB-NEXT:    ret7857  %res = call <vscale x 4 x double> @llvm.vector.interleave4.nxv4f64(<vscale x 1 x double> %v0, <vscale x 1 x double> %v1, <vscale x 1 x double> %v2, <vscale x 1 x double> %v3)7858  ret <vscale x 4 x double> %res7859}7860 7861define <vscale x 8 x double> @vector_interleave_nxv8f64_nxv2f64(<vscale x 2 x double> %v0, <vscale x 2 x double> %v1, <vscale x 2 x double> %v2, <vscale x 2 x double> %v3) nounwind {7862; CHECK-LABEL: vector_interleave_nxv8f64_nxv2f64:7863; CHECK:       # %bb.0:7864; CHECK-NEXT:    addi sp, sp, -167865; CHECK-NEXT:    csrr a0, vlenb7866; CHECK-NEXT:    slli a0, a0, 37867; CHECK-NEXT:    sub sp, sp, a07868; CHECK-NEXT:    addi a0, sp, 167869; CHECK-NEXT:    csrr a1, vlenb7870; CHECK-NEXT:    slli a1, a1, 17871; CHECK-NEXT:    add a2, a0, a17872; CHECK-NEXT:    vsetvli a3, zero, e64, m2, ta, ma7873; CHECK-NEXT:    vsseg4e64.v v8, (a0)7874; CHECK-NEXT:    add a3, a2, a17875; CHECK-NEXT:    vl2re64.v v12, (a3)7876; CHECK-NEXT:    add a1, a3, a17877; CHECK-NEXT:    vl2re64.v v14, (a1)7878; CHECK-NEXT:    vl2re64.v v8, (a0)7879; CHECK-NEXT:    vl2re64.v v10, (a2)7880; CHECK-NEXT:    csrr a0, vlenb7881; CHECK-NEXT:    slli a0, a0, 37882; CHECK-NEXT:    add sp, sp, a07883; CHECK-NEXT:    addi sp, sp, 167884; CHECK-NEXT:    ret7885;7886; ZVBB-LABEL: vector_interleave_nxv8f64_nxv2f64:7887; ZVBB:       # %bb.0:7888; ZVBB-NEXT:    addi sp, sp, -167889; ZVBB-NEXT:    csrr a0, vlenb7890; ZVBB-NEXT:    slli a0, a0, 37891; ZVBB-NEXT:    sub sp, sp, a07892; ZVBB-NEXT:    addi a0, sp, 167893; ZVBB-NEXT:    csrr a1, vlenb7894; ZVBB-NEXT:    slli a1, a1, 17895; ZVBB-NEXT:    add a2, a0, a17896; ZVBB-NEXT:    vsetvli a3, zero, e64, m2, ta, ma7897; ZVBB-NEXT:    vsseg4e64.v v8, (a0)7898; ZVBB-NEXT:    add a3, a2, a17899; ZVBB-NEXT:    vl2re64.v v12, (a3)7900; ZVBB-NEXT:    add a1, a3, a17901; ZVBB-NEXT:    vl2re64.v v14, (a1)7902; ZVBB-NEXT:    vl2re64.v v8, (a0)7903; ZVBB-NEXT:    vl2re64.v v10, (a2)7904; ZVBB-NEXT:    csrr a0, vlenb7905; ZVBB-NEXT:    slli a0, a0, 37906; ZVBB-NEXT:    add sp, sp, a07907; ZVBB-NEXT:    addi sp, sp, 167908; ZVBB-NEXT:    ret7909  %res = call <vscale x 8 x double> @llvm.vector.interleave4.nxv6f64(<vscale x 2 x double> %v0, <vscale x 2 x double> %v1, <vscale x 2 x double> %v2, <vscale x 2 x double> %v3)7910  ret <vscale x 8 x double> %res7911}7912 7913define <vscale x 10 x half> @vector_interleave_nxv10f16_nxv2f16(<vscale x 2 x half> %v0, <vscale x 2 x half> %v1, <vscale x 2 x half> %v2, <vscale x 2 x half> %v3, <vscale x 2 x half> %v4) nounwind {7914; CHECK-LABEL: vector_interleave_nxv10f16_nxv2f16:7915; CHECK:       # %bb.0:7916; CHECK-NEXT:    addi sp, sp, -167917; CHECK-NEXT:    csrr a0, vlenb7918; CHECK-NEXT:    slli a1, a0, 17919; CHECK-NEXT:    add a0, a1, a07920; CHECK-NEXT:    sub sp, sp, a07921; CHECK-NEXT:    addi a0, sp, 167922; CHECK-NEXT:    csrr a1, vlenb7923; CHECK-NEXT:    srli a2, a1, 17924; CHECK-NEXT:    add a3, a0, a27925; CHECK-NEXT:    add a4, a3, a27926; CHECK-NEXT:    vsetvli a5, zero, e16, mf2, ta, ma7927; CHECK-NEXT:    vsseg5e16.v v8, (a0)7928; CHECK-NEXT:    add a5, a4, a27929; CHECK-NEXT:    vle16.v v8, (a5)7930; CHECK-NEXT:    vle16.v v9, (a4)7931; CHECK-NEXT:    srli a1, a1, 27932; CHECK-NEXT:    vle16.v v10, (a3)7933; CHECK-NEXT:    vsetvli a3, zero, e16, m1, ta, ma7934; CHECK-NEXT:    vslideup.vx v9, v8, a17935; CHECK-NEXT:    vsetvli a3, zero, e16, mf2, ta, ma7936; CHECK-NEXT:    vle16.v v8, (a0)7937; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma7938; CHECK-NEXT:    vslideup.vx v8, v10, a17939; CHECK-NEXT:    add a2, a5, a27940; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma7941; CHECK-NEXT:    vle16.v v10, (a2)7942; CHECK-NEXT:    csrr a0, vlenb7943; CHECK-NEXT:    slli a1, a0, 17944; CHECK-NEXT:    add a0, a1, a07945; CHECK-NEXT:    add sp, sp, a07946; CHECK-NEXT:    addi sp, sp, 167947; CHECK-NEXT:    ret7948;7949; ZVBB-LABEL: vector_interleave_nxv10f16_nxv2f16:7950; ZVBB:       # %bb.0:7951; ZVBB-NEXT:    addi sp, sp, -167952; ZVBB-NEXT:    csrr a0, vlenb7953; ZVBB-NEXT:    slli a1, a0, 17954; ZVBB-NEXT:    add a0, a1, a07955; ZVBB-NEXT:    sub sp, sp, a07956; ZVBB-NEXT:    addi a0, sp, 167957; ZVBB-NEXT:    csrr a1, vlenb7958; ZVBB-NEXT:    srli a2, a1, 17959; ZVBB-NEXT:    add a3, a0, a27960; ZVBB-NEXT:    add a4, a3, a27961; ZVBB-NEXT:    vsetvli a5, zero, e16, mf2, ta, ma7962; ZVBB-NEXT:    vsseg5e16.v v8, (a0)7963; ZVBB-NEXT:    add a5, a4, a27964; ZVBB-NEXT:    vle16.v v8, (a5)7965; ZVBB-NEXT:    vle16.v v9, (a4)7966; ZVBB-NEXT:    srli a1, a1, 27967; ZVBB-NEXT:    vle16.v v10, (a3)7968; ZVBB-NEXT:    vsetvli a3, zero, e16, m1, ta, ma7969; ZVBB-NEXT:    vslideup.vx v9, v8, a17970; ZVBB-NEXT:    vsetvli a3, zero, e16, mf2, ta, ma7971; ZVBB-NEXT:    vle16.v v8, (a0)7972; ZVBB-NEXT:    vsetvli a0, zero, e16, m1, ta, ma7973; ZVBB-NEXT:    vslideup.vx v8, v10, a17974; ZVBB-NEXT:    add a2, a5, a27975; ZVBB-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma7976; ZVBB-NEXT:    vle16.v v10, (a2)7977; ZVBB-NEXT:    csrr a0, vlenb7978; ZVBB-NEXT:    slli a1, a0, 17979; ZVBB-NEXT:    add a0, a1, a07980; ZVBB-NEXT:    add sp, sp, a07981; ZVBB-NEXT:    addi sp, sp, 167982; ZVBB-NEXT:    ret7983  %res = call <vscale x 10 x half> @llvm.vector.interleave5.nxv10f16(<vscale x 2 x half> %v0, <vscale x 2 x half> %v1, <vscale x 2 x half> %v2, <vscale x 2 x half> %v3, <vscale x 2 x half> %v4)7984  ret <vscale x 10 x half> %res7985}7986 7987define <vscale x 20 x half> @vector_interleave_nxv20f16_nxv4f16(<vscale x 4 x half> %v0, <vscale x 4 x half> %v1, <vscale x 4 x half> %v2, <vscale x 4 x half> %v3, <vscale x 4 x half> %v4) nounwind {7988; CHECK-LABEL: vector_interleave_nxv20f16_nxv4f16:7989; CHECK:       # %bb.0:7990; CHECK-NEXT:    addi sp, sp, -167991; CHECK-NEXT:    csrr a0, vlenb7992; CHECK-NEXT:    slli a1, a0, 27993; CHECK-NEXT:    add a0, a1, a07994; CHECK-NEXT:    sub sp, sp, a07995; CHECK-NEXT:    addi a0, sp, 167996; CHECK-NEXT:    csrr a1, vlenb7997; CHECK-NEXT:    add a2, a0, a17998; CHECK-NEXT:    add a3, a2, a17999; CHECK-NEXT:    vsetvli a4, zero, e16, m1, ta, ma8000; CHECK-NEXT:    vsseg5e16.v v8, (a0)8001; CHECK-NEXT:    vl1re16.v v10, (a3)8002; CHECK-NEXT:    add a3, a3, a18003; CHECK-NEXT:    vl1re16.v v11, (a3)8004; CHECK-NEXT:    vl1re16.v v8, (a0)8005; CHECK-NEXT:    vl1re16.v v9, (a2)8006; CHECK-NEXT:    add a1, a3, a18007; CHECK-NEXT:    vl1re16.v v12, (a1)8008; CHECK-NEXT:    csrr a0, vlenb8009; CHECK-NEXT:    slli a1, a0, 28010; CHECK-NEXT:    add a0, a1, a08011; CHECK-NEXT:    add sp, sp, a08012; CHECK-NEXT:    addi sp, sp, 168013; CHECK-NEXT:    ret8014;8015; ZVBB-LABEL: vector_interleave_nxv20f16_nxv4f16:8016; ZVBB:       # %bb.0:8017; ZVBB-NEXT:    addi sp, sp, -168018; ZVBB-NEXT:    csrr a0, vlenb8019; ZVBB-NEXT:    slli a1, a0, 28020; ZVBB-NEXT:    add a0, a1, a08021; ZVBB-NEXT:    sub sp, sp, a08022; ZVBB-NEXT:    addi a0, sp, 168023; ZVBB-NEXT:    csrr a1, vlenb8024; ZVBB-NEXT:    add a2, a0, a18025; ZVBB-NEXT:    add a3, a2, a18026; ZVBB-NEXT:    vsetvli a4, zero, e16, m1, ta, ma8027; ZVBB-NEXT:    vsseg5e16.v v8, (a0)8028; ZVBB-NEXT:    vl1re16.v v10, (a3)8029; ZVBB-NEXT:    add a3, a3, a18030; ZVBB-NEXT:    vl1re16.v v11, (a3)8031; ZVBB-NEXT:    vl1re16.v v8, (a0)8032; ZVBB-NEXT:    vl1re16.v v9, (a2)8033; ZVBB-NEXT:    add a1, a3, a18034; ZVBB-NEXT:    vl1re16.v v12, (a1)8035; ZVBB-NEXT:    csrr a0, vlenb8036; ZVBB-NEXT:    slli a1, a0, 28037; ZVBB-NEXT:    add a0, a1, a08038; ZVBB-NEXT:    add sp, sp, a08039; ZVBB-NEXT:    addi sp, sp, 168040; ZVBB-NEXT:    ret8041  %res = call <vscale x 20 x half> @llvm.vector.interleave5.nxv20f16(<vscale x 4 x half> %v0, <vscale x 4 x half> %v1, <vscale x 4 x half> %v2, <vscale x 4 x half> %v3, <vscale x 4 x half> %v4)8042  ret <vscale x 20 x half> %res8043}8044 8045define <vscale x 40 x half> @vector_interleave_nxv40f16_nxv8f16(<vscale x 8 x half> %v0, <vscale x 8 x half> %v1, <vscale x 8 x half> %v2, <vscale x 8 x half> %v3, <vscale x 8 x half> %v4) nounwind {8046; RV32-LABEL: vector_interleave_nxv40f16_nxv8f16:8047; RV32:       # %bb.0:8048; RV32-NEXT:    addi sp, sp, -808049; RV32-NEXT:    sw ra, 76(sp) # 4-byte Folded Spill8050; RV32-NEXT:    sw s0, 72(sp) # 4-byte Folded Spill8051; RV32-NEXT:    addi s0, sp, 808052; RV32-NEXT:    csrr a0, vlenb8053; RV32-NEXT:    li a1, 288054; RV32-NEXT:    mul a0, a0, a18055; RV32-NEXT:    sub sp, sp, a08056; RV32-NEXT:    andi sp, sp, -648057; RV32-NEXT:    vsetvli a0, zero, e16, m1, ta, ma8058; RV32-NEXT:    vmv2r.v v20, v168059; RV32-NEXT:    addi a0, sp, 648060; RV32-NEXT:    vmv2r.v v18, v128061; RV32-NEXT:    csrr a1, vlenb8062; RV32-NEXT:    slli a2, a1, 28063; RV32-NEXT:    add a1, a2, a18064; RV32-NEXT:    add a1, sp, a18065; RV32-NEXT:    addi a1, a1, 648066; RV32-NEXT:    csrr a2, vlenb8067; RV32-NEXT:    vmv2r.v v16, v88068; RV32-NEXT:    vmv2r.v v22, v168069; RV32-NEXT:    vmv2r.v v24, v188070; RV32-NEXT:    vmv1r.v v26, v208071; RV32-NEXT:    add a3, a0, a28072; RV32-NEXT:    vmv1r.v v23, v108073; RV32-NEXT:    add a4, a1, a28074; RV32-NEXT:    add a5, a4, a28075; RV32-NEXT:    vmv1r.v v25, v148076; RV32-NEXT:    add a6, a5, a28077; RV32-NEXT:    vmv1r.v v18, v118078; RV32-NEXT:    vsseg5e16.v v22, (a0)8079; RV32-NEXT:    vmv1r.v v20, v158080; RV32-NEXT:    vsseg5e16.v v17, (a1)8081; RV32-NEXT:    vl1re16.v v16, (a6)8082; RV32-NEXT:    add a6, a6, a28083; RV32-NEXT:    vl1re16.v v17, (a6)8084; RV32-NEXT:    add a6, a3, a28085; RV32-NEXT:    vl1re16.v v10, (a6)8086; RV32-NEXT:    add a6, a6, a28087; RV32-NEXT:    vl1re16.v v11, (a6)8088; RV32-NEXT:    vl1re16.v v8, (a0)8089; RV32-NEXT:    vl1re16.v v9, (a3)8090; RV32-NEXT:    vl1re16.v v14, (a4)8091; RV32-NEXT:    csrr a0, vlenb8092; RV32-NEXT:    li a3, 108093; RV32-NEXT:    mul a0, a0, a38094; RV32-NEXT:    add a0, sp, a08095; RV32-NEXT:    addi a0, a0, 648096; RV32-NEXT:    add a6, a6, a28097; RV32-NEXT:    vl1re16.v v15, (a5)8098; RV32-NEXT:    vl1re16.v v12, (a6)8099; RV32-NEXT:    vl1re16.v v13, (a1)8100; RV32-NEXT:    slli a2, a2, 38101; RV32-NEXT:    add a2, a0, a28102; RV32-NEXT:    vs2r.v v16, (a2)8103; RV32-NEXT:    vs8r.v v8, (a0)8104; RV32-NEXT:    vl8re16.v v16, (a2)8105; RV32-NEXT:    vl8re16.v v8, (a0)8106; RV32-NEXT:    addi sp, s0, -808107; RV32-NEXT:    lw ra, 76(sp) # 4-byte Folded Reload8108; RV32-NEXT:    lw s0, 72(sp) # 4-byte Folded Reload8109; RV32-NEXT:    addi sp, sp, 808110; RV32-NEXT:    ret8111;8112; RV64-LABEL: vector_interleave_nxv40f16_nxv8f16:8113; RV64:       # %bb.0:8114; RV64-NEXT:    addi sp, sp, -808115; RV64-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill8116; RV64-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill8117; RV64-NEXT:    addi s0, sp, 808118; RV64-NEXT:    csrr a0, vlenb8119; RV64-NEXT:    li a1, 288120; RV64-NEXT:    mul a0, a0, a18121; RV64-NEXT:    sub sp, sp, a08122; RV64-NEXT:    andi sp, sp, -648123; RV64-NEXT:    vsetvli a0, zero, e16, m1, ta, ma8124; RV64-NEXT:    vmv2r.v v20, v168125; RV64-NEXT:    addi a0, sp, 648126; RV64-NEXT:    vmv2r.v v18, v128127; RV64-NEXT:    csrr a1, vlenb8128; RV64-NEXT:    slli a2, a1, 28129; RV64-NEXT:    add a1, a2, a18130; RV64-NEXT:    add a1, sp, a18131; RV64-NEXT:    addi a1, a1, 648132; RV64-NEXT:    csrr a2, vlenb8133; RV64-NEXT:    vmv2r.v v16, v88134; RV64-NEXT:    vmv2r.v v22, v168135; RV64-NEXT:    vmv2r.v v24, v188136; RV64-NEXT:    vmv1r.v v26, v208137; RV64-NEXT:    add a3, a0, a28138; RV64-NEXT:    vmv1r.v v23, v108139; RV64-NEXT:    add a4, a1, a28140; RV64-NEXT:    add a5, a4, a28141; RV64-NEXT:    vmv1r.v v25, v148142; RV64-NEXT:    add a6, a5, a28143; RV64-NEXT:    vmv1r.v v18, v118144; RV64-NEXT:    vsseg5e16.v v22, (a0)8145; RV64-NEXT:    vmv1r.v v20, v158146; RV64-NEXT:    vsseg5e16.v v17, (a1)8147; RV64-NEXT:    vl1re16.v v16, (a6)8148; RV64-NEXT:    add a6, a6, a28149; RV64-NEXT:    vl1re16.v v17, (a6)8150; RV64-NEXT:    add a6, a3, a28151; RV64-NEXT:    vl1re16.v v10, (a6)8152; RV64-NEXT:    add a6, a6, a28153; RV64-NEXT:    vl1re16.v v11, (a6)8154; RV64-NEXT:    vl1re16.v v8, (a0)8155; RV64-NEXT:    vl1re16.v v9, (a3)8156; RV64-NEXT:    vl1re16.v v14, (a4)8157; RV64-NEXT:    csrr a0, vlenb8158; RV64-NEXT:    li a3, 108159; RV64-NEXT:    mul a0, a0, a38160; RV64-NEXT:    add a0, sp, a08161; RV64-NEXT:    addi a0, a0, 648162; RV64-NEXT:    add a6, a6, a28163; RV64-NEXT:    vl1re16.v v15, (a5)8164; RV64-NEXT:    vl1re16.v v12, (a6)8165; RV64-NEXT:    vl1re16.v v13, (a1)8166; RV64-NEXT:    slli a2, a2, 38167; RV64-NEXT:    add a2, a0, a28168; RV64-NEXT:    vs2r.v v16, (a2)8169; RV64-NEXT:    vs8r.v v8, (a0)8170; RV64-NEXT:    vl8re16.v v16, (a2)8171; RV64-NEXT:    vl8re16.v v8, (a0)8172; RV64-NEXT:    addi sp, s0, -808173; RV64-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload8174; RV64-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload8175; RV64-NEXT:    addi sp, sp, 808176; RV64-NEXT:    ret8177;8178; ZVBB-RV32-LABEL: vector_interleave_nxv40f16_nxv8f16:8179; ZVBB-RV32:       # %bb.0:8180; ZVBB-RV32-NEXT:    addi sp, sp, -808181; ZVBB-RV32-NEXT:    sw ra, 76(sp) # 4-byte Folded Spill8182; ZVBB-RV32-NEXT:    sw s0, 72(sp) # 4-byte Folded Spill8183; ZVBB-RV32-NEXT:    addi s0, sp, 808184; ZVBB-RV32-NEXT:    csrr a0, vlenb8185; ZVBB-RV32-NEXT:    li a1, 288186; ZVBB-RV32-NEXT:    mul a0, a0, a18187; ZVBB-RV32-NEXT:    sub sp, sp, a08188; ZVBB-RV32-NEXT:    andi sp, sp, -648189; ZVBB-RV32-NEXT:    vsetvli a0, zero, e16, m1, ta, ma8190; ZVBB-RV32-NEXT:    vmv2r.v v20, v168191; ZVBB-RV32-NEXT:    addi a0, sp, 648192; ZVBB-RV32-NEXT:    vmv2r.v v18, v128193; ZVBB-RV32-NEXT:    csrr a1, vlenb8194; ZVBB-RV32-NEXT:    slli a2, a1, 28195; ZVBB-RV32-NEXT:    add a1, a2, a18196; ZVBB-RV32-NEXT:    add a1, sp, a18197; ZVBB-RV32-NEXT:    addi a1, a1, 648198; ZVBB-RV32-NEXT:    csrr a2, vlenb8199; ZVBB-RV32-NEXT:    vmv2r.v v16, v88200; ZVBB-RV32-NEXT:    vmv2r.v v22, v168201; ZVBB-RV32-NEXT:    vmv2r.v v24, v188202; ZVBB-RV32-NEXT:    vmv1r.v v26, v208203; ZVBB-RV32-NEXT:    add a3, a0, a28204; ZVBB-RV32-NEXT:    vmv1r.v v23, v108205; ZVBB-RV32-NEXT:    add a4, a1, a28206; ZVBB-RV32-NEXT:    add a5, a4, a28207; ZVBB-RV32-NEXT:    vmv1r.v v25, v148208; ZVBB-RV32-NEXT:    add a6, a5, a28209; ZVBB-RV32-NEXT:    vmv1r.v v18, v118210; ZVBB-RV32-NEXT:    vsseg5e16.v v22, (a0)8211; ZVBB-RV32-NEXT:    vmv1r.v v20, v158212; ZVBB-RV32-NEXT:    vsseg5e16.v v17, (a1)8213; ZVBB-RV32-NEXT:    vl1re16.v v16, (a6)8214; ZVBB-RV32-NEXT:    add a6, a6, a28215; ZVBB-RV32-NEXT:    vl1re16.v v17, (a6)8216; ZVBB-RV32-NEXT:    add a6, a3, a28217; ZVBB-RV32-NEXT:    vl1re16.v v10, (a6)8218; ZVBB-RV32-NEXT:    add a6, a6, a28219; ZVBB-RV32-NEXT:    vl1re16.v v11, (a6)8220; ZVBB-RV32-NEXT:    vl1re16.v v8, (a0)8221; ZVBB-RV32-NEXT:    vl1re16.v v9, (a3)8222; ZVBB-RV32-NEXT:    vl1re16.v v14, (a4)8223; ZVBB-RV32-NEXT:    csrr a0, vlenb8224; ZVBB-RV32-NEXT:    li a3, 108225; ZVBB-RV32-NEXT:    mul a0, a0, a38226; ZVBB-RV32-NEXT:    add a0, sp, a08227; ZVBB-RV32-NEXT:    addi a0, a0, 648228; ZVBB-RV32-NEXT:    add a6, a6, a28229; ZVBB-RV32-NEXT:    vl1re16.v v15, (a5)8230; ZVBB-RV32-NEXT:    vl1re16.v v12, (a6)8231; ZVBB-RV32-NEXT:    vl1re16.v v13, (a1)8232; ZVBB-RV32-NEXT:    slli a2, a2, 38233; ZVBB-RV32-NEXT:    add a2, a0, a28234; ZVBB-RV32-NEXT:    vs2r.v v16, (a2)8235; ZVBB-RV32-NEXT:    vs8r.v v8, (a0)8236; ZVBB-RV32-NEXT:    vl8re16.v v16, (a2)8237; ZVBB-RV32-NEXT:    vl8re16.v v8, (a0)8238; ZVBB-RV32-NEXT:    addi sp, s0, -808239; ZVBB-RV32-NEXT:    lw ra, 76(sp) # 4-byte Folded Reload8240; ZVBB-RV32-NEXT:    lw s0, 72(sp) # 4-byte Folded Reload8241; ZVBB-RV32-NEXT:    addi sp, sp, 808242; ZVBB-RV32-NEXT:    ret8243;8244; ZVBB-RV64-LABEL: vector_interleave_nxv40f16_nxv8f16:8245; ZVBB-RV64:       # %bb.0:8246; ZVBB-RV64-NEXT:    addi sp, sp, -808247; ZVBB-RV64-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill8248; ZVBB-RV64-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill8249; ZVBB-RV64-NEXT:    addi s0, sp, 808250; ZVBB-RV64-NEXT:    csrr a0, vlenb8251; ZVBB-RV64-NEXT:    li a1, 288252; ZVBB-RV64-NEXT:    mul a0, a0, a18253; ZVBB-RV64-NEXT:    sub sp, sp, a08254; ZVBB-RV64-NEXT:    andi sp, sp, -648255; ZVBB-RV64-NEXT:    vsetvli a0, zero, e16, m1, ta, ma8256; ZVBB-RV64-NEXT:    vmv2r.v v20, v168257; ZVBB-RV64-NEXT:    addi a0, sp, 648258; ZVBB-RV64-NEXT:    vmv2r.v v18, v128259; ZVBB-RV64-NEXT:    csrr a1, vlenb8260; ZVBB-RV64-NEXT:    slli a2, a1, 28261; ZVBB-RV64-NEXT:    add a1, a2, a18262; ZVBB-RV64-NEXT:    add a1, sp, a18263; ZVBB-RV64-NEXT:    addi a1, a1, 648264; ZVBB-RV64-NEXT:    csrr a2, vlenb8265; ZVBB-RV64-NEXT:    vmv2r.v v16, v88266; ZVBB-RV64-NEXT:    vmv2r.v v22, v168267; ZVBB-RV64-NEXT:    vmv2r.v v24, v188268; ZVBB-RV64-NEXT:    vmv1r.v v26, v208269; ZVBB-RV64-NEXT:    add a3, a0, a28270; ZVBB-RV64-NEXT:    vmv1r.v v23, v108271; ZVBB-RV64-NEXT:    add a4, a1, a28272; ZVBB-RV64-NEXT:    add a5, a4, a28273; ZVBB-RV64-NEXT:    vmv1r.v v25, v148274; ZVBB-RV64-NEXT:    add a6, a5, a28275; ZVBB-RV64-NEXT:    vmv1r.v v18, v118276; ZVBB-RV64-NEXT:    vsseg5e16.v v22, (a0)8277; ZVBB-RV64-NEXT:    vmv1r.v v20, v158278; ZVBB-RV64-NEXT:    vsseg5e16.v v17, (a1)8279; ZVBB-RV64-NEXT:    vl1re16.v v16, (a6)8280; ZVBB-RV64-NEXT:    add a6, a6, a28281; ZVBB-RV64-NEXT:    vl1re16.v v17, (a6)8282; ZVBB-RV64-NEXT:    add a6, a3, a28283; ZVBB-RV64-NEXT:    vl1re16.v v10, (a6)8284; ZVBB-RV64-NEXT:    add a6, a6, a28285; ZVBB-RV64-NEXT:    vl1re16.v v11, (a6)8286; ZVBB-RV64-NEXT:    vl1re16.v v8, (a0)8287; ZVBB-RV64-NEXT:    vl1re16.v v9, (a3)8288; ZVBB-RV64-NEXT:    vl1re16.v v14, (a4)8289; ZVBB-RV64-NEXT:    csrr a0, vlenb8290; ZVBB-RV64-NEXT:    li a3, 108291; ZVBB-RV64-NEXT:    mul a0, a0, a38292; ZVBB-RV64-NEXT:    add a0, sp, a08293; ZVBB-RV64-NEXT:    addi a0, a0, 648294; ZVBB-RV64-NEXT:    add a6, a6, a28295; ZVBB-RV64-NEXT:    vl1re16.v v15, (a5)8296; ZVBB-RV64-NEXT:    vl1re16.v v12, (a6)8297; ZVBB-RV64-NEXT:    vl1re16.v v13, (a1)8298; ZVBB-RV64-NEXT:    slli a2, a2, 38299; ZVBB-RV64-NEXT:    add a2, a0, a28300; ZVBB-RV64-NEXT:    vs2r.v v16, (a2)8301; ZVBB-RV64-NEXT:    vs8r.v v8, (a0)8302; ZVBB-RV64-NEXT:    vl8re16.v v16, (a2)8303; ZVBB-RV64-NEXT:    vl8re16.v v8, (a0)8304; ZVBB-RV64-NEXT:    addi sp, s0, -808305; ZVBB-RV64-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload8306; ZVBB-RV64-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload8307; ZVBB-RV64-NEXT:    addi sp, sp, 808308; ZVBB-RV64-NEXT:    ret8309;8310; ZIP-LABEL: vector_interleave_nxv40f16_nxv8f16:8311; ZIP:       # %bb.0:8312; ZIP-NEXT:    addi sp, sp, -808313; ZIP-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill8314; ZIP-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill8315; ZIP-NEXT:    addi s0, sp, 808316; ZIP-NEXT:    csrr a0, vlenb8317; ZIP-NEXT:    li a1, 288318; ZIP-NEXT:    mul a0, a0, a18319; ZIP-NEXT:    sub sp, sp, a08320; ZIP-NEXT:    andi sp, sp, -648321; ZIP-NEXT:    vsetvli a0, zero, e16, m1, ta, ma8322; ZIP-NEXT:    vmv2r.v v20, v168323; ZIP-NEXT:    addi a0, sp, 648324; ZIP-NEXT:    vmv2r.v v18, v128325; ZIP-NEXT:    csrr a1, vlenb8326; ZIP-NEXT:    slli a2, a1, 28327; ZIP-NEXT:    add a1, a2, a18328; ZIP-NEXT:    add a1, sp, a18329; ZIP-NEXT:    addi a1, a1, 648330; ZIP-NEXT:    csrr a2, vlenb8331; ZIP-NEXT:    vmv2r.v v16, v88332; ZIP-NEXT:    vmv2r.v v22, v168333; ZIP-NEXT:    vmv2r.v v24, v188334; ZIP-NEXT:    vmv1r.v v26, v208335; ZIP-NEXT:    add a3, a0, a28336; ZIP-NEXT:    vmv1r.v v23, v108337; ZIP-NEXT:    add a4, a1, a28338; ZIP-NEXT:    add a5, a4, a28339; ZIP-NEXT:    vmv1r.v v25, v148340; ZIP-NEXT:    add a6, a5, a28341; ZIP-NEXT:    vmv1r.v v18, v118342; ZIP-NEXT:    vsseg5e16.v v22, (a0)8343; ZIP-NEXT:    vmv1r.v v20, v158344; ZIP-NEXT:    vsseg5e16.v v17, (a1)8345; ZIP-NEXT:    vl1re16.v v16, (a6)8346; ZIP-NEXT:    add a6, a6, a28347; ZIP-NEXT:    vl1re16.v v17, (a6)8348; ZIP-NEXT:    add a6, a3, a28349; ZIP-NEXT:    vl1re16.v v10, (a6)8350; ZIP-NEXT:    add a6, a6, a28351; ZIP-NEXT:    vl1re16.v v11, (a6)8352; ZIP-NEXT:    vl1re16.v v8, (a0)8353; ZIP-NEXT:    vl1re16.v v9, (a3)8354; ZIP-NEXT:    vl1re16.v v14, (a4)8355; ZIP-NEXT:    csrr a0, vlenb8356; ZIP-NEXT:    li a3, 108357; ZIP-NEXT:    mul a0, a0, a38358; ZIP-NEXT:    add a0, sp, a08359; ZIP-NEXT:    addi a0, a0, 648360; ZIP-NEXT:    add a6, a6, a28361; ZIP-NEXT:    vl1re16.v v15, (a5)8362; ZIP-NEXT:    vl1re16.v v12, (a6)8363; ZIP-NEXT:    vl1re16.v v13, (a1)8364; ZIP-NEXT:    slli a2, a2, 38365; ZIP-NEXT:    add a2, a0, a28366; ZIP-NEXT:    vs2r.v v16, (a2)8367; ZIP-NEXT:    vs8r.v v8, (a0)8368; ZIP-NEXT:    vl8re16.v v16, (a2)8369; ZIP-NEXT:    vl8re16.v v8, (a0)8370; ZIP-NEXT:    addi sp, s0, -808371; ZIP-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload8372; ZIP-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload8373; ZIP-NEXT:    addi sp, sp, 808374; ZIP-NEXT:    ret8375  %res = call <vscale x 40 x half> @llvm.vector.interleave5.nxv40f16(<vscale x 8 x half> %v0, <vscale x 8 x half> %v1, <vscale x 8 x half> %v2, <vscale x 8 x half> %v3, <vscale x 8 x half> %v4)8376  ret <vscale x 40 x half> %res8377}8378 8379define <vscale x 10 x bfloat> @vector_interleave_nxv10bf16_nxv2bf16(<vscale x 2 x bfloat> %v0, <vscale x 2 x bfloat> %v1, <vscale x 2 x bfloat> %v2, <vscale x 2 x bfloat> %v3, <vscale x 2 x bfloat> %v4) nounwind {8380; CHECK-LABEL: vector_interleave_nxv10bf16_nxv2bf16:8381; CHECK:       # %bb.0:8382; CHECK-NEXT:    addi sp, sp, -168383; CHECK-NEXT:    csrr a0, vlenb8384; CHECK-NEXT:    slli a1, a0, 18385; CHECK-NEXT:    add a0, a1, a08386; CHECK-NEXT:    sub sp, sp, a08387; CHECK-NEXT:    addi a0, sp, 168388; CHECK-NEXT:    csrr a1, vlenb8389; CHECK-NEXT:    srli a2, a1, 18390; CHECK-NEXT:    add a3, a0, a28391; CHECK-NEXT:    add a4, a3, a28392; CHECK-NEXT:    vsetvli a5, zero, e16, mf2, ta, ma8393; CHECK-NEXT:    vsseg5e16.v v8, (a0)8394; CHECK-NEXT:    add a5, a4, a28395; CHECK-NEXT:    vle16.v v8, (a5)8396; CHECK-NEXT:    vle16.v v9, (a4)8397; CHECK-NEXT:    srli a1, a1, 28398; CHECK-NEXT:    vle16.v v10, (a3)8399; CHECK-NEXT:    vsetvli a3, zero, e16, m1, ta, ma8400; CHECK-NEXT:    vslideup.vx v9, v8, a18401; CHECK-NEXT:    vsetvli a3, zero, e16, mf2, ta, ma8402; CHECK-NEXT:    vle16.v v8, (a0)8403; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma8404; CHECK-NEXT:    vslideup.vx v8, v10, a18405; CHECK-NEXT:    add a2, a5, a28406; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma8407; CHECK-NEXT:    vle16.v v10, (a2)8408; CHECK-NEXT:    csrr a0, vlenb8409; CHECK-NEXT:    slli a1, a0, 18410; CHECK-NEXT:    add a0, a1, a08411; CHECK-NEXT:    add sp, sp, a08412; CHECK-NEXT:    addi sp, sp, 168413; CHECK-NEXT:    ret8414;8415; ZVBB-LABEL: vector_interleave_nxv10bf16_nxv2bf16:8416; ZVBB:       # %bb.0:8417; ZVBB-NEXT:    addi sp, sp, -168418; ZVBB-NEXT:    csrr a0, vlenb8419; ZVBB-NEXT:    slli a1, a0, 18420; ZVBB-NEXT:    add a0, a1, a08421; ZVBB-NEXT:    sub sp, sp, a08422; ZVBB-NEXT:    addi a0, sp, 168423; ZVBB-NEXT:    csrr a1, vlenb8424; ZVBB-NEXT:    srli a2, a1, 18425; ZVBB-NEXT:    add a3, a0, a28426; ZVBB-NEXT:    add a4, a3, a28427; ZVBB-NEXT:    vsetvli a5, zero, e16, mf2, ta, ma8428; ZVBB-NEXT:    vsseg5e16.v v8, (a0)8429; ZVBB-NEXT:    add a5, a4, a28430; ZVBB-NEXT:    vle16.v v8, (a5)8431; ZVBB-NEXT:    vle16.v v9, (a4)8432; ZVBB-NEXT:    srli a1, a1, 28433; ZVBB-NEXT:    vle16.v v10, (a3)8434; ZVBB-NEXT:    vsetvli a3, zero, e16, m1, ta, ma8435; ZVBB-NEXT:    vslideup.vx v9, v8, a18436; ZVBB-NEXT:    vsetvli a3, zero, e16, mf2, ta, ma8437; ZVBB-NEXT:    vle16.v v8, (a0)8438; ZVBB-NEXT:    vsetvli a0, zero, e16, m1, ta, ma8439; ZVBB-NEXT:    vslideup.vx v8, v10, a18440; ZVBB-NEXT:    add a2, a5, a28441; ZVBB-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma8442; ZVBB-NEXT:    vle16.v v10, (a2)8443; ZVBB-NEXT:    csrr a0, vlenb8444; ZVBB-NEXT:    slli a1, a0, 18445; ZVBB-NEXT:    add a0, a1, a08446; ZVBB-NEXT:    add sp, sp, a08447; ZVBB-NEXT:    addi sp, sp, 168448; ZVBB-NEXT:    ret8449  %res = call <vscale x 10 x bfloat> @llvm.vector.interleave5.nxv10bf16(<vscale x 2 x bfloat> %v0, <vscale x 2 x bfloat> %v1, <vscale x 2 x bfloat> %v2, <vscale x 2 x bfloat> %v3, <vscale x 2 x bfloat> %v4)8450  ret <vscale x 10 x bfloat> %res8451}8452 8453define <vscale x 20 x bfloat> @vector_interleave_nxv20bf16_nxv4bf16(<vscale x 4 x bfloat> %v0, <vscale x 4 x bfloat> %v1, <vscale x 4 x bfloat> %v2, <vscale x 4 x bfloat> %v3, <vscale x 4 x bfloat> %v4) nounwind {8454; CHECK-LABEL: vector_interleave_nxv20bf16_nxv4bf16:8455; CHECK:       # %bb.0:8456; CHECK-NEXT:    addi sp, sp, -168457; CHECK-NEXT:    csrr a0, vlenb8458; CHECK-NEXT:    slli a1, a0, 28459; CHECK-NEXT:    add a0, a1, a08460; CHECK-NEXT:    sub sp, sp, a08461; CHECK-NEXT:    addi a0, sp, 168462; CHECK-NEXT:    csrr a1, vlenb8463; CHECK-NEXT:    add a2, a0, a18464; CHECK-NEXT:    add a3, a2, a18465; CHECK-NEXT:    vsetvli a4, zero, e16, m1, ta, ma8466; CHECK-NEXT:    vsseg5e16.v v8, (a0)8467; CHECK-NEXT:    vl1re16.v v10, (a3)8468; CHECK-NEXT:    add a3, a3, a18469; CHECK-NEXT:    vl1re16.v v11, (a3)8470; CHECK-NEXT:    vl1re16.v v8, (a0)8471; CHECK-NEXT:    vl1re16.v v9, (a2)8472; CHECK-NEXT:    add a1, a3, a18473; CHECK-NEXT:    vl1re16.v v12, (a1)8474; CHECK-NEXT:    csrr a0, vlenb8475; CHECK-NEXT:    slli a1, a0, 28476; CHECK-NEXT:    add a0, a1, a08477; CHECK-NEXT:    add sp, sp, a08478; CHECK-NEXT:    addi sp, sp, 168479; CHECK-NEXT:    ret8480;8481; ZVBB-LABEL: vector_interleave_nxv20bf16_nxv4bf16:8482; ZVBB:       # %bb.0:8483; ZVBB-NEXT:    addi sp, sp, -168484; ZVBB-NEXT:    csrr a0, vlenb8485; ZVBB-NEXT:    slli a1, a0, 28486; ZVBB-NEXT:    add a0, a1, a08487; ZVBB-NEXT:    sub sp, sp, a08488; ZVBB-NEXT:    addi a0, sp, 168489; ZVBB-NEXT:    csrr a1, vlenb8490; ZVBB-NEXT:    add a2, a0, a18491; ZVBB-NEXT:    add a3, a2, a18492; ZVBB-NEXT:    vsetvli a4, zero, e16, m1, ta, ma8493; ZVBB-NEXT:    vsseg5e16.v v8, (a0)8494; ZVBB-NEXT:    vl1re16.v v10, (a3)8495; ZVBB-NEXT:    add a3, a3, a18496; ZVBB-NEXT:    vl1re16.v v11, (a3)8497; ZVBB-NEXT:    vl1re16.v v8, (a0)8498; ZVBB-NEXT:    vl1re16.v v9, (a2)8499; ZVBB-NEXT:    add a1, a3, a18500; ZVBB-NEXT:    vl1re16.v v12, (a1)8501; ZVBB-NEXT:    csrr a0, vlenb8502; ZVBB-NEXT:    slli a1, a0, 28503; ZVBB-NEXT:    add a0, a1, a08504; ZVBB-NEXT:    add sp, sp, a08505; ZVBB-NEXT:    addi sp, sp, 168506; ZVBB-NEXT:    ret8507  %res = call <vscale x 20 x bfloat> @llvm.vector.interleave5.nxv20bf16(<vscale x 4 x bfloat> %v0, <vscale x 4 x bfloat> %v1, <vscale x 4 x bfloat> %v2, <vscale x 4 x bfloat> %v3, <vscale x 4 x bfloat> %v4)8508  ret <vscale x 20 x bfloat> %res8509}8510 8511define <vscale x 40 x bfloat> @vector_interleave_nxv40bf16_nxv8bf16(<vscale x 8 x bfloat> %v0, <vscale x 8 x bfloat> %v1, <vscale x 8 x bfloat> %v2, <vscale x 8 x bfloat> %v3, <vscale x 8 x bfloat> %v4) nounwind {8512; RV32-LABEL: vector_interleave_nxv40bf16_nxv8bf16:8513; RV32:       # %bb.0:8514; RV32-NEXT:    addi sp, sp, -808515; RV32-NEXT:    sw ra, 76(sp) # 4-byte Folded Spill8516; RV32-NEXT:    sw s0, 72(sp) # 4-byte Folded Spill8517; RV32-NEXT:    addi s0, sp, 808518; RV32-NEXT:    csrr a0, vlenb8519; RV32-NEXT:    li a1, 288520; RV32-NEXT:    mul a0, a0, a18521; RV32-NEXT:    sub sp, sp, a08522; RV32-NEXT:    andi sp, sp, -648523; RV32-NEXT:    vsetvli a0, zero, e16, m1, ta, ma8524; RV32-NEXT:    vmv2r.v v20, v168525; RV32-NEXT:    addi a0, sp, 648526; RV32-NEXT:    vmv2r.v v18, v128527; RV32-NEXT:    csrr a1, vlenb8528; RV32-NEXT:    slli a2, a1, 28529; RV32-NEXT:    add a1, a2, a18530; RV32-NEXT:    add a1, sp, a18531; RV32-NEXT:    addi a1, a1, 648532; RV32-NEXT:    csrr a2, vlenb8533; RV32-NEXT:    vmv2r.v v16, v88534; RV32-NEXT:    vmv2r.v v22, v168535; RV32-NEXT:    vmv2r.v v24, v188536; RV32-NEXT:    vmv1r.v v26, v208537; RV32-NEXT:    add a3, a0, a28538; RV32-NEXT:    vmv1r.v v23, v108539; RV32-NEXT:    add a4, a1, a28540; RV32-NEXT:    add a5, a4, a28541; RV32-NEXT:    vmv1r.v v25, v148542; RV32-NEXT:    add a6, a5, a28543; RV32-NEXT:    vmv1r.v v18, v118544; RV32-NEXT:    vsseg5e16.v v22, (a0)8545; RV32-NEXT:    vmv1r.v v20, v158546; RV32-NEXT:    vsseg5e16.v v17, (a1)8547; RV32-NEXT:    vl1re16.v v16, (a6)8548; RV32-NEXT:    add a6, a6, a28549; RV32-NEXT:    vl1re16.v v17, (a6)8550; RV32-NEXT:    add a6, a3, a28551; RV32-NEXT:    vl1re16.v v10, (a6)8552; RV32-NEXT:    add a6, a6, a28553; RV32-NEXT:    vl1re16.v v11, (a6)8554; RV32-NEXT:    vl1re16.v v8, (a0)8555; RV32-NEXT:    vl1re16.v v9, (a3)8556; RV32-NEXT:    vl1re16.v v14, (a4)8557; RV32-NEXT:    csrr a0, vlenb8558; RV32-NEXT:    li a3, 108559; RV32-NEXT:    mul a0, a0, a38560; RV32-NEXT:    add a0, sp, a08561; RV32-NEXT:    addi a0, a0, 648562; RV32-NEXT:    add a6, a6, a28563; RV32-NEXT:    vl1re16.v v15, (a5)8564; RV32-NEXT:    vl1re16.v v12, (a6)8565; RV32-NEXT:    vl1re16.v v13, (a1)8566; RV32-NEXT:    slli a2, a2, 38567; RV32-NEXT:    add a2, a0, a28568; RV32-NEXT:    vs2r.v v16, (a2)8569; RV32-NEXT:    vs8r.v v8, (a0)8570; RV32-NEXT:    vl8re16.v v16, (a2)8571; RV32-NEXT:    vl8re16.v v8, (a0)8572; RV32-NEXT:    addi sp, s0, -808573; RV32-NEXT:    lw ra, 76(sp) # 4-byte Folded Reload8574; RV32-NEXT:    lw s0, 72(sp) # 4-byte Folded Reload8575; RV32-NEXT:    addi sp, sp, 808576; RV32-NEXT:    ret8577;8578; RV64-LABEL: vector_interleave_nxv40bf16_nxv8bf16:8579; RV64:       # %bb.0:8580; RV64-NEXT:    addi sp, sp, -808581; RV64-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill8582; RV64-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill8583; RV64-NEXT:    addi s0, sp, 808584; RV64-NEXT:    csrr a0, vlenb8585; RV64-NEXT:    li a1, 288586; RV64-NEXT:    mul a0, a0, a18587; RV64-NEXT:    sub sp, sp, a08588; RV64-NEXT:    andi sp, sp, -648589; RV64-NEXT:    vsetvli a0, zero, e16, m1, ta, ma8590; RV64-NEXT:    vmv2r.v v20, v168591; RV64-NEXT:    addi a0, sp, 648592; RV64-NEXT:    vmv2r.v v18, v128593; RV64-NEXT:    csrr a1, vlenb8594; RV64-NEXT:    slli a2, a1, 28595; RV64-NEXT:    add a1, a2, a18596; RV64-NEXT:    add a1, sp, a18597; RV64-NEXT:    addi a1, a1, 648598; RV64-NEXT:    csrr a2, vlenb8599; RV64-NEXT:    vmv2r.v v16, v88600; RV64-NEXT:    vmv2r.v v22, v168601; RV64-NEXT:    vmv2r.v v24, v188602; RV64-NEXT:    vmv1r.v v26, v208603; RV64-NEXT:    add a3, a0, a28604; RV64-NEXT:    vmv1r.v v23, v108605; RV64-NEXT:    add a4, a1, a28606; RV64-NEXT:    add a5, a4, a28607; RV64-NEXT:    vmv1r.v v25, v148608; RV64-NEXT:    add a6, a5, a28609; RV64-NEXT:    vmv1r.v v18, v118610; RV64-NEXT:    vsseg5e16.v v22, (a0)8611; RV64-NEXT:    vmv1r.v v20, v158612; RV64-NEXT:    vsseg5e16.v v17, (a1)8613; RV64-NEXT:    vl1re16.v v16, (a6)8614; RV64-NEXT:    add a6, a6, a28615; RV64-NEXT:    vl1re16.v v17, (a6)8616; RV64-NEXT:    add a6, a3, a28617; RV64-NEXT:    vl1re16.v v10, (a6)8618; RV64-NEXT:    add a6, a6, a28619; RV64-NEXT:    vl1re16.v v11, (a6)8620; RV64-NEXT:    vl1re16.v v8, (a0)8621; RV64-NEXT:    vl1re16.v v9, (a3)8622; RV64-NEXT:    vl1re16.v v14, (a4)8623; RV64-NEXT:    csrr a0, vlenb8624; RV64-NEXT:    li a3, 108625; RV64-NEXT:    mul a0, a0, a38626; RV64-NEXT:    add a0, sp, a08627; RV64-NEXT:    addi a0, a0, 648628; RV64-NEXT:    add a6, a6, a28629; RV64-NEXT:    vl1re16.v v15, (a5)8630; RV64-NEXT:    vl1re16.v v12, (a6)8631; RV64-NEXT:    vl1re16.v v13, (a1)8632; RV64-NEXT:    slli a2, a2, 38633; RV64-NEXT:    add a2, a0, a28634; RV64-NEXT:    vs2r.v v16, (a2)8635; RV64-NEXT:    vs8r.v v8, (a0)8636; RV64-NEXT:    vl8re16.v v16, (a2)8637; RV64-NEXT:    vl8re16.v v8, (a0)8638; RV64-NEXT:    addi sp, s0, -808639; RV64-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload8640; RV64-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload8641; RV64-NEXT:    addi sp, sp, 808642; RV64-NEXT:    ret8643;8644; ZVBB-RV32-LABEL: vector_interleave_nxv40bf16_nxv8bf16:8645; ZVBB-RV32:       # %bb.0:8646; ZVBB-RV32-NEXT:    addi sp, sp, -808647; ZVBB-RV32-NEXT:    sw ra, 76(sp) # 4-byte Folded Spill8648; ZVBB-RV32-NEXT:    sw s0, 72(sp) # 4-byte Folded Spill8649; ZVBB-RV32-NEXT:    addi s0, sp, 808650; ZVBB-RV32-NEXT:    csrr a0, vlenb8651; ZVBB-RV32-NEXT:    li a1, 288652; ZVBB-RV32-NEXT:    mul a0, a0, a18653; ZVBB-RV32-NEXT:    sub sp, sp, a08654; ZVBB-RV32-NEXT:    andi sp, sp, -648655; ZVBB-RV32-NEXT:    vsetvli a0, zero, e16, m1, ta, ma8656; ZVBB-RV32-NEXT:    vmv2r.v v20, v168657; ZVBB-RV32-NEXT:    addi a0, sp, 648658; ZVBB-RV32-NEXT:    vmv2r.v v18, v128659; ZVBB-RV32-NEXT:    csrr a1, vlenb8660; ZVBB-RV32-NEXT:    slli a2, a1, 28661; ZVBB-RV32-NEXT:    add a1, a2, a18662; ZVBB-RV32-NEXT:    add a1, sp, a18663; ZVBB-RV32-NEXT:    addi a1, a1, 648664; ZVBB-RV32-NEXT:    csrr a2, vlenb8665; ZVBB-RV32-NEXT:    vmv2r.v v16, v88666; ZVBB-RV32-NEXT:    vmv2r.v v22, v168667; ZVBB-RV32-NEXT:    vmv2r.v v24, v188668; ZVBB-RV32-NEXT:    vmv1r.v v26, v208669; ZVBB-RV32-NEXT:    add a3, a0, a28670; ZVBB-RV32-NEXT:    vmv1r.v v23, v108671; ZVBB-RV32-NEXT:    add a4, a1, a28672; ZVBB-RV32-NEXT:    add a5, a4, a28673; ZVBB-RV32-NEXT:    vmv1r.v v25, v148674; ZVBB-RV32-NEXT:    add a6, a5, a28675; ZVBB-RV32-NEXT:    vmv1r.v v18, v118676; ZVBB-RV32-NEXT:    vsseg5e16.v v22, (a0)8677; ZVBB-RV32-NEXT:    vmv1r.v v20, v158678; ZVBB-RV32-NEXT:    vsseg5e16.v v17, (a1)8679; ZVBB-RV32-NEXT:    vl1re16.v v16, (a6)8680; ZVBB-RV32-NEXT:    add a6, a6, a28681; ZVBB-RV32-NEXT:    vl1re16.v v17, (a6)8682; ZVBB-RV32-NEXT:    add a6, a3, a28683; ZVBB-RV32-NEXT:    vl1re16.v v10, (a6)8684; ZVBB-RV32-NEXT:    add a6, a6, a28685; ZVBB-RV32-NEXT:    vl1re16.v v11, (a6)8686; ZVBB-RV32-NEXT:    vl1re16.v v8, (a0)8687; ZVBB-RV32-NEXT:    vl1re16.v v9, (a3)8688; ZVBB-RV32-NEXT:    vl1re16.v v14, (a4)8689; ZVBB-RV32-NEXT:    csrr a0, vlenb8690; ZVBB-RV32-NEXT:    li a3, 108691; ZVBB-RV32-NEXT:    mul a0, a0, a38692; ZVBB-RV32-NEXT:    add a0, sp, a08693; ZVBB-RV32-NEXT:    addi a0, a0, 648694; ZVBB-RV32-NEXT:    add a6, a6, a28695; ZVBB-RV32-NEXT:    vl1re16.v v15, (a5)8696; ZVBB-RV32-NEXT:    vl1re16.v v12, (a6)8697; ZVBB-RV32-NEXT:    vl1re16.v v13, (a1)8698; ZVBB-RV32-NEXT:    slli a2, a2, 38699; ZVBB-RV32-NEXT:    add a2, a0, a28700; ZVBB-RV32-NEXT:    vs2r.v v16, (a2)8701; ZVBB-RV32-NEXT:    vs8r.v v8, (a0)8702; ZVBB-RV32-NEXT:    vl8re16.v v16, (a2)8703; ZVBB-RV32-NEXT:    vl8re16.v v8, (a0)8704; ZVBB-RV32-NEXT:    addi sp, s0, -808705; ZVBB-RV32-NEXT:    lw ra, 76(sp) # 4-byte Folded Reload8706; ZVBB-RV32-NEXT:    lw s0, 72(sp) # 4-byte Folded Reload8707; ZVBB-RV32-NEXT:    addi sp, sp, 808708; ZVBB-RV32-NEXT:    ret8709;8710; ZVBB-RV64-LABEL: vector_interleave_nxv40bf16_nxv8bf16:8711; ZVBB-RV64:       # %bb.0:8712; ZVBB-RV64-NEXT:    addi sp, sp, -808713; ZVBB-RV64-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill8714; ZVBB-RV64-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill8715; ZVBB-RV64-NEXT:    addi s0, sp, 808716; ZVBB-RV64-NEXT:    csrr a0, vlenb8717; ZVBB-RV64-NEXT:    li a1, 288718; ZVBB-RV64-NEXT:    mul a0, a0, a18719; ZVBB-RV64-NEXT:    sub sp, sp, a08720; ZVBB-RV64-NEXT:    andi sp, sp, -648721; ZVBB-RV64-NEXT:    vsetvli a0, zero, e16, m1, ta, ma8722; ZVBB-RV64-NEXT:    vmv2r.v v20, v168723; ZVBB-RV64-NEXT:    addi a0, sp, 648724; ZVBB-RV64-NEXT:    vmv2r.v v18, v128725; ZVBB-RV64-NEXT:    csrr a1, vlenb8726; ZVBB-RV64-NEXT:    slli a2, a1, 28727; ZVBB-RV64-NEXT:    add a1, a2, a18728; ZVBB-RV64-NEXT:    add a1, sp, a18729; ZVBB-RV64-NEXT:    addi a1, a1, 648730; ZVBB-RV64-NEXT:    csrr a2, vlenb8731; ZVBB-RV64-NEXT:    vmv2r.v v16, v88732; ZVBB-RV64-NEXT:    vmv2r.v v22, v168733; ZVBB-RV64-NEXT:    vmv2r.v v24, v188734; ZVBB-RV64-NEXT:    vmv1r.v v26, v208735; ZVBB-RV64-NEXT:    add a3, a0, a28736; ZVBB-RV64-NEXT:    vmv1r.v v23, v108737; ZVBB-RV64-NEXT:    add a4, a1, a28738; ZVBB-RV64-NEXT:    add a5, a4, a28739; ZVBB-RV64-NEXT:    vmv1r.v v25, v148740; ZVBB-RV64-NEXT:    add a6, a5, a28741; ZVBB-RV64-NEXT:    vmv1r.v v18, v118742; ZVBB-RV64-NEXT:    vsseg5e16.v v22, (a0)8743; ZVBB-RV64-NEXT:    vmv1r.v v20, v158744; ZVBB-RV64-NEXT:    vsseg5e16.v v17, (a1)8745; ZVBB-RV64-NEXT:    vl1re16.v v16, (a6)8746; ZVBB-RV64-NEXT:    add a6, a6, a28747; ZVBB-RV64-NEXT:    vl1re16.v v17, (a6)8748; ZVBB-RV64-NEXT:    add a6, a3, a28749; ZVBB-RV64-NEXT:    vl1re16.v v10, (a6)8750; ZVBB-RV64-NEXT:    add a6, a6, a28751; ZVBB-RV64-NEXT:    vl1re16.v v11, (a6)8752; ZVBB-RV64-NEXT:    vl1re16.v v8, (a0)8753; ZVBB-RV64-NEXT:    vl1re16.v v9, (a3)8754; ZVBB-RV64-NEXT:    vl1re16.v v14, (a4)8755; ZVBB-RV64-NEXT:    csrr a0, vlenb8756; ZVBB-RV64-NEXT:    li a3, 108757; ZVBB-RV64-NEXT:    mul a0, a0, a38758; ZVBB-RV64-NEXT:    add a0, sp, a08759; ZVBB-RV64-NEXT:    addi a0, a0, 648760; ZVBB-RV64-NEXT:    add a6, a6, a28761; ZVBB-RV64-NEXT:    vl1re16.v v15, (a5)8762; ZVBB-RV64-NEXT:    vl1re16.v v12, (a6)8763; ZVBB-RV64-NEXT:    vl1re16.v v13, (a1)8764; ZVBB-RV64-NEXT:    slli a2, a2, 38765; ZVBB-RV64-NEXT:    add a2, a0, a28766; ZVBB-RV64-NEXT:    vs2r.v v16, (a2)8767; ZVBB-RV64-NEXT:    vs8r.v v8, (a0)8768; ZVBB-RV64-NEXT:    vl8re16.v v16, (a2)8769; ZVBB-RV64-NEXT:    vl8re16.v v8, (a0)8770; ZVBB-RV64-NEXT:    addi sp, s0, -808771; ZVBB-RV64-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload8772; ZVBB-RV64-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload8773; ZVBB-RV64-NEXT:    addi sp, sp, 808774; ZVBB-RV64-NEXT:    ret8775;8776; ZIP-LABEL: vector_interleave_nxv40bf16_nxv8bf16:8777; ZIP:       # %bb.0:8778; ZIP-NEXT:    addi sp, sp, -808779; ZIP-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill8780; ZIP-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill8781; ZIP-NEXT:    addi s0, sp, 808782; ZIP-NEXT:    csrr a0, vlenb8783; ZIP-NEXT:    li a1, 288784; ZIP-NEXT:    mul a0, a0, a18785; ZIP-NEXT:    sub sp, sp, a08786; ZIP-NEXT:    andi sp, sp, -648787; ZIP-NEXT:    vsetvli a0, zero, e16, m1, ta, ma8788; ZIP-NEXT:    vmv2r.v v20, v168789; ZIP-NEXT:    addi a0, sp, 648790; ZIP-NEXT:    vmv2r.v v18, v128791; ZIP-NEXT:    csrr a1, vlenb8792; ZIP-NEXT:    slli a2, a1, 28793; ZIP-NEXT:    add a1, a2, a18794; ZIP-NEXT:    add a1, sp, a18795; ZIP-NEXT:    addi a1, a1, 648796; ZIP-NEXT:    csrr a2, vlenb8797; ZIP-NEXT:    vmv2r.v v16, v88798; ZIP-NEXT:    vmv2r.v v22, v168799; ZIP-NEXT:    vmv2r.v v24, v188800; ZIP-NEXT:    vmv1r.v v26, v208801; ZIP-NEXT:    add a3, a0, a28802; ZIP-NEXT:    vmv1r.v v23, v108803; ZIP-NEXT:    add a4, a1, a28804; ZIP-NEXT:    add a5, a4, a28805; ZIP-NEXT:    vmv1r.v v25, v148806; ZIP-NEXT:    add a6, a5, a28807; ZIP-NEXT:    vmv1r.v v18, v118808; ZIP-NEXT:    vsseg5e16.v v22, (a0)8809; ZIP-NEXT:    vmv1r.v v20, v158810; ZIP-NEXT:    vsseg5e16.v v17, (a1)8811; ZIP-NEXT:    vl1re16.v v16, (a6)8812; ZIP-NEXT:    add a6, a6, a28813; ZIP-NEXT:    vl1re16.v v17, (a6)8814; ZIP-NEXT:    add a6, a3, a28815; ZIP-NEXT:    vl1re16.v v10, (a6)8816; ZIP-NEXT:    add a6, a6, a28817; ZIP-NEXT:    vl1re16.v v11, (a6)8818; ZIP-NEXT:    vl1re16.v v8, (a0)8819; ZIP-NEXT:    vl1re16.v v9, (a3)8820; ZIP-NEXT:    vl1re16.v v14, (a4)8821; ZIP-NEXT:    csrr a0, vlenb8822; ZIP-NEXT:    li a3, 108823; ZIP-NEXT:    mul a0, a0, a38824; ZIP-NEXT:    add a0, sp, a08825; ZIP-NEXT:    addi a0, a0, 648826; ZIP-NEXT:    add a6, a6, a28827; ZIP-NEXT:    vl1re16.v v15, (a5)8828; ZIP-NEXT:    vl1re16.v v12, (a6)8829; ZIP-NEXT:    vl1re16.v v13, (a1)8830; ZIP-NEXT:    slli a2, a2, 38831; ZIP-NEXT:    add a2, a0, a28832; ZIP-NEXT:    vs2r.v v16, (a2)8833; ZIP-NEXT:    vs8r.v v8, (a0)8834; ZIP-NEXT:    vl8re16.v v16, (a2)8835; ZIP-NEXT:    vl8re16.v v8, (a0)8836; ZIP-NEXT:    addi sp, s0, -808837; ZIP-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload8838; ZIP-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload8839; ZIP-NEXT:    addi sp, sp, 808840; ZIP-NEXT:    ret8841  %res = call <vscale x 40 x bfloat> @llvm.vector.interleave5.nxv40bf16(<vscale x 8 x bfloat> %v0, <vscale x 8 x bfloat> %v1, <vscale x 8 x bfloat> %v2, <vscale x 8 x bfloat> %v3, <vscale x 8 x bfloat> %v4)8842  ret <vscale x 40 x bfloat> %res8843}8844 8845define <vscale x 5 x float> @vector_interleave_nxv5f32_nxv1f32(<vscale x 1 x float> %v0, <vscale x 1 x float> %v1, <vscale x 1 x float> %v2, <vscale x 1 x float> %v3, <vscale x 1 x float> %v4) nounwind {8846; CHECK-LABEL: vector_interleave_nxv5f32_nxv1f32:8847; CHECK:       # %bb.0:8848; CHECK-NEXT:    addi sp, sp, -168849; CHECK-NEXT:    csrr a0, vlenb8850; CHECK-NEXT:    slli a1, a0, 18851; CHECK-NEXT:    add a0, a1, a08852; CHECK-NEXT:    sub sp, sp, a08853; CHECK-NEXT:    addi a0, sp, 168854; CHECK-NEXT:    csrr a1, vlenb8855; CHECK-NEXT:    srli a2, a1, 18856; CHECK-NEXT:    add a3, a0, a28857; CHECK-NEXT:    add a4, a3, a28858; CHECK-NEXT:    vsetvli a5, zero, e32, mf2, ta, ma8859; CHECK-NEXT:    vsseg5e32.v v8, (a0)8860; CHECK-NEXT:    add a5, a4, a28861; CHECK-NEXT:    vle32.v v8, (a5)8862; CHECK-NEXT:    vle32.v v9, (a4)8863; CHECK-NEXT:    srli a1, a1, 38864; CHECK-NEXT:    vle32.v v10, (a3)8865; CHECK-NEXT:    vsetvli a3, zero, e32, m1, ta, ma8866; CHECK-NEXT:    vslideup.vx v9, v8, a18867; CHECK-NEXT:    vsetvli a3, zero, e32, mf2, ta, ma8868; CHECK-NEXT:    vle32.v v8, (a0)8869; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma8870; CHECK-NEXT:    vslideup.vx v8, v10, a18871; CHECK-NEXT:    add a2, a5, a28872; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma8873; CHECK-NEXT:    vle32.v v10, (a2)8874; CHECK-NEXT:    csrr a0, vlenb8875; CHECK-NEXT:    slli a1, a0, 18876; CHECK-NEXT:    add a0, a1, a08877; CHECK-NEXT:    add sp, sp, a08878; CHECK-NEXT:    addi sp, sp, 168879; CHECK-NEXT:    ret8880;8881; ZVBB-LABEL: vector_interleave_nxv5f32_nxv1f32:8882; ZVBB:       # %bb.0:8883; ZVBB-NEXT:    addi sp, sp, -168884; ZVBB-NEXT:    csrr a0, vlenb8885; ZVBB-NEXT:    slli a1, a0, 18886; ZVBB-NEXT:    add a0, a1, a08887; ZVBB-NEXT:    sub sp, sp, a08888; ZVBB-NEXT:    addi a0, sp, 168889; ZVBB-NEXT:    csrr a1, vlenb8890; ZVBB-NEXT:    srli a2, a1, 18891; ZVBB-NEXT:    add a3, a0, a28892; ZVBB-NEXT:    add a4, a3, a28893; ZVBB-NEXT:    vsetvli a5, zero, e32, mf2, ta, ma8894; ZVBB-NEXT:    vsseg5e32.v v8, (a0)8895; ZVBB-NEXT:    add a5, a4, a28896; ZVBB-NEXT:    vle32.v v8, (a5)8897; ZVBB-NEXT:    vle32.v v9, (a4)8898; ZVBB-NEXT:    srli a1, a1, 38899; ZVBB-NEXT:    vle32.v v10, (a3)8900; ZVBB-NEXT:    vsetvli a3, zero, e32, m1, ta, ma8901; ZVBB-NEXT:    vslideup.vx v9, v8, a18902; ZVBB-NEXT:    vsetvli a3, zero, e32, mf2, ta, ma8903; ZVBB-NEXT:    vle32.v v8, (a0)8904; ZVBB-NEXT:    vsetvli a0, zero, e32, m1, ta, ma8905; ZVBB-NEXT:    vslideup.vx v8, v10, a18906; ZVBB-NEXT:    add a2, a5, a28907; ZVBB-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma8908; ZVBB-NEXT:    vle32.v v10, (a2)8909; ZVBB-NEXT:    csrr a0, vlenb8910; ZVBB-NEXT:    slli a1, a0, 18911; ZVBB-NEXT:    add a0, a1, a08912; ZVBB-NEXT:    add sp, sp, a08913; ZVBB-NEXT:    addi sp, sp, 168914; ZVBB-NEXT:    ret8915  %res = call <vscale x 5 x float> @llvm.vector.interleave5.nxv5f32(<vscale x 1 x float> %v0, <vscale x 1 x float> %v1, <vscale x 1 x float> %v2, <vscale x 1 x float> %v3, <vscale x 1 x float> %v4)8916  ret <vscale x 5 x float> %res8917}8918 8919define <vscale x 10 x float> @vector_interleave_nxv10f32_nxv2f32(<vscale x 2 x float> %v0, <vscale x 2 x float> %v1, <vscale x 2 x float> %v2, <vscale x 2 x float> %v3, <vscale x 2 x float> %v4) nounwind {8920; CHECK-LABEL: vector_interleave_nxv10f32_nxv2f32:8921; CHECK:       # %bb.0:8922; CHECK-NEXT:    addi sp, sp, -168923; CHECK-NEXT:    csrr a0, vlenb8924; CHECK-NEXT:    slli a1, a0, 28925; CHECK-NEXT:    add a0, a1, a08926; CHECK-NEXT:    sub sp, sp, a08927; CHECK-NEXT:    addi a0, sp, 168928; CHECK-NEXT:    csrr a1, vlenb8929; CHECK-NEXT:    add a2, a0, a18930; CHECK-NEXT:    add a3, a2, a18931; CHECK-NEXT:    vsetvli a4, zero, e32, m1, ta, ma8932; CHECK-NEXT:    vsseg5e32.v v8, (a0)8933; CHECK-NEXT:    vl1re32.v v10, (a3)8934; CHECK-NEXT:    add a3, a3, a18935; CHECK-NEXT:    vl1re32.v v11, (a3)8936; CHECK-NEXT:    vl1re32.v v8, (a0)8937; CHECK-NEXT:    vl1re32.v v9, (a2)8938; CHECK-NEXT:    add a1, a3, a18939; CHECK-NEXT:    vl1re32.v v12, (a1)8940; CHECK-NEXT:    csrr a0, vlenb8941; CHECK-NEXT:    slli a1, a0, 28942; CHECK-NEXT:    add a0, a1, a08943; CHECK-NEXT:    add sp, sp, a08944; CHECK-NEXT:    addi sp, sp, 168945; CHECK-NEXT:    ret8946;8947; ZVBB-LABEL: vector_interleave_nxv10f32_nxv2f32:8948; ZVBB:       # %bb.0:8949; ZVBB-NEXT:    addi sp, sp, -168950; ZVBB-NEXT:    csrr a0, vlenb8951; ZVBB-NEXT:    slli a1, a0, 28952; ZVBB-NEXT:    add a0, a1, a08953; ZVBB-NEXT:    sub sp, sp, a08954; ZVBB-NEXT:    addi a0, sp, 168955; ZVBB-NEXT:    csrr a1, vlenb8956; ZVBB-NEXT:    add a2, a0, a18957; ZVBB-NEXT:    add a3, a2, a18958; ZVBB-NEXT:    vsetvli a4, zero, e32, m1, ta, ma8959; ZVBB-NEXT:    vsseg5e32.v v8, (a0)8960; ZVBB-NEXT:    vl1re32.v v10, (a3)8961; ZVBB-NEXT:    add a3, a3, a18962; ZVBB-NEXT:    vl1re32.v v11, (a3)8963; ZVBB-NEXT:    vl1re32.v v8, (a0)8964; ZVBB-NEXT:    vl1re32.v v9, (a2)8965; ZVBB-NEXT:    add a1, a3, a18966; ZVBB-NEXT:    vl1re32.v v12, (a1)8967; ZVBB-NEXT:    csrr a0, vlenb8968; ZVBB-NEXT:    slli a1, a0, 28969; ZVBB-NEXT:    add a0, a1, a08970; ZVBB-NEXT:    add sp, sp, a08971; ZVBB-NEXT:    addi sp, sp, 168972; ZVBB-NEXT:    ret8973  %res = call <vscale x 10 x float> @llvm.vector.interleave5.nxv10f32(<vscale x 2 x float> %v0, <vscale x 2 x float> %v1, <vscale x 2 x float> %v2, <vscale x 2 x float> %v3, <vscale x 2 x float> %v4)8974  ret <vscale x 10 x float> %res8975}8976 8977define <vscale x 20 x float> @vector_interleave_nxv20f32_nxv4f32(<vscale x 4 x float> %v0, <vscale x 4 x float> %v1, <vscale x 4 x float> %v2, <vscale x 4 x float> %v3, <vscale x 4 x float> %v4) nounwind {8978; RV32-LABEL: vector_interleave_nxv20f32_nxv4f32:8979; RV32:       # %bb.0:8980; RV32-NEXT:    addi sp, sp, -808981; RV32-NEXT:    sw ra, 76(sp) # 4-byte Folded Spill8982; RV32-NEXT:    sw s0, 72(sp) # 4-byte Folded Spill8983; RV32-NEXT:    addi s0, sp, 808984; RV32-NEXT:    csrr a0, vlenb8985; RV32-NEXT:    li a1, 288986; RV32-NEXT:    mul a0, a0, a18987; RV32-NEXT:    sub sp, sp, a08988; RV32-NEXT:    andi sp, sp, -648989; RV32-NEXT:    vsetvli a0, zero, e32, m1, ta, ma8990; RV32-NEXT:    vmv2r.v v20, v168991; RV32-NEXT:    addi a0, sp, 648992; RV32-NEXT:    vmv2r.v v18, v128993; RV32-NEXT:    csrr a1, vlenb8994; RV32-NEXT:    slli a2, a1, 28995; RV32-NEXT:    add a1, a2, a18996; RV32-NEXT:    add a1, sp, a18997; RV32-NEXT:    addi a1, a1, 648998; RV32-NEXT:    csrr a2, vlenb8999; RV32-NEXT:    vmv2r.v v16, v89000; RV32-NEXT:    vmv2r.v v22, v169001; RV32-NEXT:    vmv2r.v v24, v189002; RV32-NEXT:    vmv1r.v v26, v209003; RV32-NEXT:    add a3, a0, a29004; RV32-NEXT:    vmv1r.v v23, v109005; RV32-NEXT:    add a4, a1, a29006; RV32-NEXT:    add a5, a4, a29007; RV32-NEXT:    vmv1r.v v25, v149008; RV32-NEXT:    add a6, a5, a29009; RV32-NEXT:    vmv1r.v v18, v119010; RV32-NEXT:    vsseg5e32.v v22, (a0)9011; RV32-NEXT:    vmv1r.v v20, v159012; RV32-NEXT:    vsseg5e32.v v17, (a1)9013; RV32-NEXT:    vl1re32.v v16, (a6)9014; RV32-NEXT:    add a6, a6, a29015; RV32-NEXT:    vl1re32.v v17, (a6)9016; RV32-NEXT:    add a6, a3, a29017; RV32-NEXT:    vl1re32.v v10, (a6)9018; RV32-NEXT:    add a6, a6, a29019; RV32-NEXT:    vl1re32.v v11, (a6)9020; RV32-NEXT:    vl1re32.v v8, (a0)9021; RV32-NEXT:    vl1re32.v v9, (a3)9022; RV32-NEXT:    vl1re32.v v14, (a4)9023; RV32-NEXT:    csrr a0, vlenb9024; RV32-NEXT:    li a3, 109025; RV32-NEXT:    mul a0, a0, a39026; RV32-NEXT:    add a0, sp, a09027; RV32-NEXT:    addi a0, a0, 649028; RV32-NEXT:    add a6, a6, a29029; RV32-NEXT:    vl1re32.v v15, (a5)9030; RV32-NEXT:    vl1re32.v v12, (a6)9031; RV32-NEXT:    vl1re32.v v13, (a1)9032; RV32-NEXT:    slli a2, a2, 39033; RV32-NEXT:    add a2, a0, a29034; RV32-NEXT:    vs2r.v v16, (a2)9035; RV32-NEXT:    vs8r.v v8, (a0)9036; RV32-NEXT:    vl8re32.v v16, (a2)9037; RV32-NEXT:    vl8re32.v v8, (a0)9038; RV32-NEXT:    addi sp, s0, -809039; RV32-NEXT:    lw ra, 76(sp) # 4-byte Folded Reload9040; RV32-NEXT:    lw s0, 72(sp) # 4-byte Folded Reload9041; RV32-NEXT:    addi sp, sp, 809042; RV32-NEXT:    ret9043;9044; RV64-LABEL: vector_interleave_nxv20f32_nxv4f32:9045; RV64:       # %bb.0:9046; RV64-NEXT:    addi sp, sp, -809047; RV64-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill9048; RV64-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill9049; RV64-NEXT:    addi s0, sp, 809050; RV64-NEXT:    csrr a0, vlenb9051; RV64-NEXT:    li a1, 289052; RV64-NEXT:    mul a0, a0, a19053; RV64-NEXT:    sub sp, sp, a09054; RV64-NEXT:    andi sp, sp, -649055; RV64-NEXT:    vsetvli a0, zero, e32, m1, ta, ma9056; RV64-NEXT:    vmv2r.v v20, v169057; RV64-NEXT:    addi a0, sp, 649058; RV64-NEXT:    vmv2r.v v18, v129059; RV64-NEXT:    csrr a1, vlenb9060; RV64-NEXT:    slli a2, a1, 29061; RV64-NEXT:    add a1, a2, a19062; RV64-NEXT:    add a1, sp, a19063; RV64-NEXT:    addi a1, a1, 649064; RV64-NEXT:    csrr a2, vlenb9065; RV64-NEXT:    vmv2r.v v16, v89066; RV64-NEXT:    vmv2r.v v22, v169067; RV64-NEXT:    vmv2r.v v24, v189068; RV64-NEXT:    vmv1r.v v26, v209069; RV64-NEXT:    add a3, a0, a29070; RV64-NEXT:    vmv1r.v v23, v109071; RV64-NEXT:    add a4, a1, a29072; RV64-NEXT:    add a5, a4, a29073; RV64-NEXT:    vmv1r.v v25, v149074; RV64-NEXT:    add a6, a5, a29075; RV64-NEXT:    vmv1r.v v18, v119076; RV64-NEXT:    vsseg5e32.v v22, (a0)9077; RV64-NEXT:    vmv1r.v v20, v159078; RV64-NEXT:    vsseg5e32.v v17, (a1)9079; RV64-NEXT:    vl1re32.v v16, (a6)9080; RV64-NEXT:    add a6, a6, a29081; RV64-NEXT:    vl1re32.v v17, (a6)9082; RV64-NEXT:    add a6, a3, a29083; RV64-NEXT:    vl1re32.v v10, (a6)9084; RV64-NEXT:    add a6, a6, a29085; RV64-NEXT:    vl1re32.v v11, (a6)9086; RV64-NEXT:    vl1re32.v v8, (a0)9087; RV64-NEXT:    vl1re32.v v9, (a3)9088; RV64-NEXT:    vl1re32.v v14, (a4)9089; RV64-NEXT:    csrr a0, vlenb9090; RV64-NEXT:    li a3, 109091; RV64-NEXT:    mul a0, a0, a39092; RV64-NEXT:    add a0, sp, a09093; RV64-NEXT:    addi a0, a0, 649094; RV64-NEXT:    add a6, a6, a29095; RV64-NEXT:    vl1re32.v v15, (a5)9096; RV64-NEXT:    vl1re32.v v12, (a6)9097; RV64-NEXT:    vl1re32.v v13, (a1)9098; RV64-NEXT:    slli a2, a2, 39099; RV64-NEXT:    add a2, a0, a29100; RV64-NEXT:    vs2r.v v16, (a2)9101; RV64-NEXT:    vs8r.v v8, (a0)9102; RV64-NEXT:    vl8re32.v v16, (a2)9103; RV64-NEXT:    vl8re32.v v8, (a0)9104; RV64-NEXT:    addi sp, s0, -809105; RV64-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload9106; RV64-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload9107; RV64-NEXT:    addi sp, sp, 809108; RV64-NEXT:    ret9109;9110; ZVBB-RV32-LABEL: vector_interleave_nxv20f32_nxv4f32:9111; ZVBB-RV32:       # %bb.0:9112; ZVBB-RV32-NEXT:    addi sp, sp, -809113; ZVBB-RV32-NEXT:    sw ra, 76(sp) # 4-byte Folded Spill9114; ZVBB-RV32-NEXT:    sw s0, 72(sp) # 4-byte Folded Spill9115; ZVBB-RV32-NEXT:    addi s0, sp, 809116; ZVBB-RV32-NEXT:    csrr a0, vlenb9117; ZVBB-RV32-NEXT:    li a1, 289118; ZVBB-RV32-NEXT:    mul a0, a0, a19119; ZVBB-RV32-NEXT:    sub sp, sp, a09120; ZVBB-RV32-NEXT:    andi sp, sp, -649121; ZVBB-RV32-NEXT:    vsetvli a0, zero, e32, m1, ta, ma9122; ZVBB-RV32-NEXT:    vmv2r.v v20, v169123; ZVBB-RV32-NEXT:    addi a0, sp, 649124; ZVBB-RV32-NEXT:    vmv2r.v v18, v129125; ZVBB-RV32-NEXT:    csrr a1, vlenb9126; ZVBB-RV32-NEXT:    slli a2, a1, 29127; ZVBB-RV32-NEXT:    add a1, a2, a19128; ZVBB-RV32-NEXT:    add a1, sp, a19129; ZVBB-RV32-NEXT:    addi a1, a1, 649130; ZVBB-RV32-NEXT:    csrr a2, vlenb9131; ZVBB-RV32-NEXT:    vmv2r.v v16, v89132; ZVBB-RV32-NEXT:    vmv2r.v v22, v169133; ZVBB-RV32-NEXT:    vmv2r.v v24, v189134; ZVBB-RV32-NEXT:    vmv1r.v v26, v209135; ZVBB-RV32-NEXT:    add a3, a0, a29136; ZVBB-RV32-NEXT:    vmv1r.v v23, v109137; ZVBB-RV32-NEXT:    add a4, a1, a29138; ZVBB-RV32-NEXT:    add a5, a4, a29139; ZVBB-RV32-NEXT:    vmv1r.v v25, v149140; ZVBB-RV32-NEXT:    add a6, a5, a29141; ZVBB-RV32-NEXT:    vmv1r.v v18, v119142; ZVBB-RV32-NEXT:    vsseg5e32.v v22, (a0)9143; ZVBB-RV32-NEXT:    vmv1r.v v20, v159144; ZVBB-RV32-NEXT:    vsseg5e32.v v17, (a1)9145; ZVBB-RV32-NEXT:    vl1re32.v v16, (a6)9146; ZVBB-RV32-NEXT:    add a6, a6, a29147; ZVBB-RV32-NEXT:    vl1re32.v v17, (a6)9148; ZVBB-RV32-NEXT:    add a6, a3, a29149; ZVBB-RV32-NEXT:    vl1re32.v v10, (a6)9150; ZVBB-RV32-NEXT:    add a6, a6, a29151; ZVBB-RV32-NEXT:    vl1re32.v v11, (a6)9152; ZVBB-RV32-NEXT:    vl1re32.v v8, (a0)9153; ZVBB-RV32-NEXT:    vl1re32.v v9, (a3)9154; ZVBB-RV32-NEXT:    vl1re32.v v14, (a4)9155; ZVBB-RV32-NEXT:    csrr a0, vlenb9156; ZVBB-RV32-NEXT:    li a3, 109157; ZVBB-RV32-NEXT:    mul a0, a0, a39158; ZVBB-RV32-NEXT:    add a0, sp, a09159; ZVBB-RV32-NEXT:    addi a0, a0, 649160; ZVBB-RV32-NEXT:    add a6, a6, a29161; ZVBB-RV32-NEXT:    vl1re32.v v15, (a5)9162; ZVBB-RV32-NEXT:    vl1re32.v v12, (a6)9163; ZVBB-RV32-NEXT:    vl1re32.v v13, (a1)9164; ZVBB-RV32-NEXT:    slli a2, a2, 39165; ZVBB-RV32-NEXT:    add a2, a0, a29166; ZVBB-RV32-NEXT:    vs2r.v v16, (a2)9167; ZVBB-RV32-NEXT:    vs8r.v v8, (a0)9168; ZVBB-RV32-NEXT:    vl8re32.v v16, (a2)9169; ZVBB-RV32-NEXT:    vl8re32.v v8, (a0)9170; ZVBB-RV32-NEXT:    addi sp, s0, -809171; ZVBB-RV32-NEXT:    lw ra, 76(sp) # 4-byte Folded Reload9172; ZVBB-RV32-NEXT:    lw s0, 72(sp) # 4-byte Folded Reload9173; ZVBB-RV32-NEXT:    addi sp, sp, 809174; ZVBB-RV32-NEXT:    ret9175;9176; ZVBB-RV64-LABEL: vector_interleave_nxv20f32_nxv4f32:9177; ZVBB-RV64:       # %bb.0:9178; ZVBB-RV64-NEXT:    addi sp, sp, -809179; ZVBB-RV64-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill9180; ZVBB-RV64-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill9181; ZVBB-RV64-NEXT:    addi s0, sp, 809182; ZVBB-RV64-NEXT:    csrr a0, vlenb9183; ZVBB-RV64-NEXT:    li a1, 289184; ZVBB-RV64-NEXT:    mul a0, a0, a19185; ZVBB-RV64-NEXT:    sub sp, sp, a09186; ZVBB-RV64-NEXT:    andi sp, sp, -649187; ZVBB-RV64-NEXT:    vsetvli a0, zero, e32, m1, ta, ma9188; ZVBB-RV64-NEXT:    vmv2r.v v20, v169189; ZVBB-RV64-NEXT:    addi a0, sp, 649190; ZVBB-RV64-NEXT:    vmv2r.v v18, v129191; ZVBB-RV64-NEXT:    csrr a1, vlenb9192; ZVBB-RV64-NEXT:    slli a2, a1, 29193; ZVBB-RV64-NEXT:    add a1, a2, a19194; ZVBB-RV64-NEXT:    add a1, sp, a19195; ZVBB-RV64-NEXT:    addi a1, a1, 649196; ZVBB-RV64-NEXT:    csrr a2, vlenb9197; ZVBB-RV64-NEXT:    vmv2r.v v16, v89198; ZVBB-RV64-NEXT:    vmv2r.v v22, v169199; ZVBB-RV64-NEXT:    vmv2r.v v24, v189200; ZVBB-RV64-NEXT:    vmv1r.v v26, v209201; ZVBB-RV64-NEXT:    add a3, a0, a29202; ZVBB-RV64-NEXT:    vmv1r.v v23, v109203; ZVBB-RV64-NEXT:    add a4, a1, a29204; ZVBB-RV64-NEXT:    add a5, a4, a29205; ZVBB-RV64-NEXT:    vmv1r.v v25, v149206; ZVBB-RV64-NEXT:    add a6, a5, a29207; ZVBB-RV64-NEXT:    vmv1r.v v18, v119208; ZVBB-RV64-NEXT:    vsseg5e32.v v22, (a0)9209; ZVBB-RV64-NEXT:    vmv1r.v v20, v159210; ZVBB-RV64-NEXT:    vsseg5e32.v v17, (a1)9211; ZVBB-RV64-NEXT:    vl1re32.v v16, (a6)9212; ZVBB-RV64-NEXT:    add a6, a6, a29213; ZVBB-RV64-NEXT:    vl1re32.v v17, (a6)9214; ZVBB-RV64-NEXT:    add a6, a3, a29215; ZVBB-RV64-NEXT:    vl1re32.v v10, (a6)9216; ZVBB-RV64-NEXT:    add a6, a6, a29217; ZVBB-RV64-NEXT:    vl1re32.v v11, (a6)9218; ZVBB-RV64-NEXT:    vl1re32.v v8, (a0)9219; ZVBB-RV64-NEXT:    vl1re32.v v9, (a3)9220; ZVBB-RV64-NEXT:    vl1re32.v v14, (a4)9221; ZVBB-RV64-NEXT:    csrr a0, vlenb9222; ZVBB-RV64-NEXT:    li a3, 109223; ZVBB-RV64-NEXT:    mul a0, a0, a39224; ZVBB-RV64-NEXT:    add a0, sp, a09225; ZVBB-RV64-NEXT:    addi a0, a0, 649226; ZVBB-RV64-NEXT:    add a6, a6, a29227; ZVBB-RV64-NEXT:    vl1re32.v v15, (a5)9228; ZVBB-RV64-NEXT:    vl1re32.v v12, (a6)9229; ZVBB-RV64-NEXT:    vl1re32.v v13, (a1)9230; ZVBB-RV64-NEXT:    slli a2, a2, 39231; ZVBB-RV64-NEXT:    add a2, a0, a29232; ZVBB-RV64-NEXT:    vs2r.v v16, (a2)9233; ZVBB-RV64-NEXT:    vs8r.v v8, (a0)9234; ZVBB-RV64-NEXT:    vl8re32.v v16, (a2)9235; ZVBB-RV64-NEXT:    vl8re32.v v8, (a0)9236; ZVBB-RV64-NEXT:    addi sp, s0, -809237; ZVBB-RV64-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload9238; ZVBB-RV64-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload9239; ZVBB-RV64-NEXT:    addi sp, sp, 809240; ZVBB-RV64-NEXT:    ret9241;9242; ZIP-LABEL: vector_interleave_nxv20f32_nxv4f32:9243; ZIP:       # %bb.0:9244; ZIP-NEXT:    addi sp, sp, -809245; ZIP-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill9246; ZIP-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill9247; ZIP-NEXT:    addi s0, sp, 809248; ZIP-NEXT:    csrr a0, vlenb9249; ZIP-NEXT:    li a1, 289250; ZIP-NEXT:    mul a0, a0, a19251; ZIP-NEXT:    sub sp, sp, a09252; ZIP-NEXT:    andi sp, sp, -649253; ZIP-NEXT:    vsetvli a0, zero, e32, m1, ta, ma9254; ZIP-NEXT:    vmv2r.v v20, v169255; ZIP-NEXT:    addi a0, sp, 649256; ZIP-NEXT:    vmv2r.v v18, v129257; ZIP-NEXT:    csrr a1, vlenb9258; ZIP-NEXT:    slli a2, a1, 29259; ZIP-NEXT:    add a1, a2, a19260; ZIP-NEXT:    add a1, sp, a19261; ZIP-NEXT:    addi a1, a1, 649262; ZIP-NEXT:    csrr a2, vlenb9263; ZIP-NEXT:    vmv2r.v v16, v89264; ZIP-NEXT:    vmv2r.v v22, v169265; ZIP-NEXT:    vmv2r.v v24, v189266; ZIP-NEXT:    vmv1r.v v26, v209267; ZIP-NEXT:    add a3, a0, a29268; ZIP-NEXT:    vmv1r.v v23, v109269; ZIP-NEXT:    add a4, a1, a29270; ZIP-NEXT:    add a5, a4, a29271; ZIP-NEXT:    vmv1r.v v25, v149272; ZIP-NEXT:    add a6, a5, a29273; ZIP-NEXT:    vmv1r.v v18, v119274; ZIP-NEXT:    vsseg5e32.v v22, (a0)9275; ZIP-NEXT:    vmv1r.v v20, v159276; ZIP-NEXT:    vsseg5e32.v v17, (a1)9277; ZIP-NEXT:    vl1re32.v v16, (a6)9278; ZIP-NEXT:    add a6, a6, a29279; ZIP-NEXT:    vl1re32.v v17, (a6)9280; ZIP-NEXT:    add a6, a3, a29281; ZIP-NEXT:    vl1re32.v v10, (a6)9282; ZIP-NEXT:    add a6, a6, a29283; ZIP-NEXT:    vl1re32.v v11, (a6)9284; ZIP-NEXT:    vl1re32.v v8, (a0)9285; ZIP-NEXT:    vl1re32.v v9, (a3)9286; ZIP-NEXT:    vl1re32.v v14, (a4)9287; ZIP-NEXT:    csrr a0, vlenb9288; ZIP-NEXT:    li a3, 109289; ZIP-NEXT:    mul a0, a0, a39290; ZIP-NEXT:    add a0, sp, a09291; ZIP-NEXT:    addi a0, a0, 649292; ZIP-NEXT:    add a6, a6, a29293; ZIP-NEXT:    vl1re32.v v15, (a5)9294; ZIP-NEXT:    vl1re32.v v12, (a6)9295; ZIP-NEXT:    vl1re32.v v13, (a1)9296; ZIP-NEXT:    slli a2, a2, 39297; ZIP-NEXT:    add a2, a0, a29298; ZIP-NEXT:    vs2r.v v16, (a2)9299; ZIP-NEXT:    vs8r.v v8, (a0)9300; ZIP-NEXT:    vl8re32.v v16, (a2)9301; ZIP-NEXT:    vl8re32.v v8, (a0)9302; ZIP-NEXT:    addi sp, s0, -809303; ZIP-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload9304; ZIP-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload9305; ZIP-NEXT:    addi sp, sp, 809306; ZIP-NEXT:    ret9307  %res = call <vscale x 20 x float> @llvm.vector.interleave5.nxv20f32(<vscale x 4 x float> %v0, <vscale x 4 x float> %v1, <vscale x 4 x float> %v2, <vscale x 4 x float> %v3, <vscale x 4 x float> %v4)9308  ret <vscale x 20 x float> %res9309}9310 9311define <vscale x 5 x double> @vector_interleave_nxv5f64_nxv1f64(<vscale x 1 x double> %v0, <vscale x 1 x double> %v1, <vscale x 1 x double> %v2, <vscale x 1 x double> %v3, <vscale x 1 x double> %v4) nounwind {9312; CHECK-LABEL: vector_interleave_nxv5f64_nxv1f64:9313; CHECK:       # %bb.0:9314; CHECK-NEXT:    addi sp, sp, -169315; CHECK-NEXT:    csrr a0, vlenb9316; CHECK-NEXT:    slli a1, a0, 29317; CHECK-NEXT:    add a0, a1, a09318; CHECK-NEXT:    sub sp, sp, a09319; CHECK-NEXT:    addi a0, sp, 169320; CHECK-NEXT:    csrr a1, vlenb9321; CHECK-NEXT:    add a2, a0, a19322; CHECK-NEXT:    add a3, a2, a19323; CHECK-NEXT:    vsetvli a4, zero, e64, m1, ta, ma9324; CHECK-NEXT:    vsseg5e64.v v8, (a0)9325; CHECK-NEXT:    vl1re64.v v10, (a3)9326; CHECK-NEXT:    add a3, a3, a19327; CHECK-NEXT:    vl1re64.v v11, (a3)9328; CHECK-NEXT:    vl1re64.v v8, (a0)9329; CHECK-NEXT:    vl1re64.v v9, (a2)9330; CHECK-NEXT:    add a1, a3, a19331; CHECK-NEXT:    vl1re64.v v12, (a1)9332; CHECK-NEXT:    csrr a0, vlenb9333; CHECK-NEXT:    slli a1, a0, 29334; CHECK-NEXT:    add a0, a1, a09335; CHECK-NEXT:    add sp, sp, a09336; CHECK-NEXT:    addi sp, sp, 169337; CHECK-NEXT:    ret9338;9339; ZVBB-LABEL: vector_interleave_nxv5f64_nxv1f64:9340; ZVBB:       # %bb.0:9341; ZVBB-NEXT:    addi sp, sp, -169342; ZVBB-NEXT:    csrr a0, vlenb9343; ZVBB-NEXT:    slli a1, a0, 29344; ZVBB-NEXT:    add a0, a1, a09345; ZVBB-NEXT:    sub sp, sp, a09346; ZVBB-NEXT:    addi a0, sp, 169347; ZVBB-NEXT:    csrr a1, vlenb9348; ZVBB-NEXT:    add a2, a0, a19349; ZVBB-NEXT:    add a3, a2, a19350; ZVBB-NEXT:    vsetvli a4, zero, e64, m1, ta, ma9351; ZVBB-NEXT:    vsseg5e64.v v8, (a0)9352; ZVBB-NEXT:    vl1re64.v v10, (a3)9353; ZVBB-NEXT:    add a3, a3, a19354; ZVBB-NEXT:    vl1re64.v v11, (a3)9355; ZVBB-NEXT:    vl1re64.v v8, (a0)9356; ZVBB-NEXT:    vl1re64.v v9, (a2)9357; ZVBB-NEXT:    add a1, a3, a19358; ZVBB-NEXT:    vl1re64.v v12, (a1)9359; ZVBB-NEXT:    csrr a0, vlenb9360; ZVBB-NEXT:    slli a1, a0, 29361; ZVBB-NEXT:    add a0, a1, a09362; ZVBB-NEXT:    add sp, sp, a09363; ZVBB-NEXT:    addi sp, sp, 169364; ZVBB-NEXT:    ret9365  %res = call <vscale x 5 x double> @llvm.vector.interleave5.nxv5f64(<vscale x 1 x double> %v0, <vscale x 1 x double> %v1, <vscale x 1 x double> %v2, <vscale x 1 x double> %v3, <vscale x 1 x double> %v4)9366  ret <vscale x 5 x double> %res9367}9368 9369define <vscale x 10 x double> @vector_interleave_nxv10f64_nxv2f64(<vscale x 2 x double> %v0, <vscale x 2 x double> %v1, <vscale x 2 x double> %v2, <vscale x 2 x double> %v3, <vscale x 2 x double> %v4) nounwind {9370; RV32-LABEL: vector_interleave_nxv10f64_nxv2f64:9371; RV32:       # %bb.0:9372; RV32-NEXT:    addi sp, sp, -809373; RV32-NEXT:    sw ra, 76(sp) # 4-byte Folded Spill9374; RV32-NEXT:    sw s0, 72(sp) # 4-byte Folded Spill9375; RV32-NEXT:    addi s0, sp, 809376; RV32-NEXT:    csrr a0, vlenb9377; RV32-NEXT:    li a1, 289378; RV32-NEXT:    mul a0, a0, a19379; RV32-NEXT:    sub sp, sp, a09380; RV32-NEXT:    andi sp, sp, -649381; RV32-NEXT:    vsetvli a0, zero, e64, m1, ta, ma9382; RV32-NEXT:    vmv2r.v v20, v169383; RV32-NEXT:    addi a0, sp, 649384; RV32-NEXT:    vmv2r.v v18, v129385; RV32-NEXT:    csrr a1, vlenb9386; RV32-NEXT:    slli a2, a1, 29387; RV32-NEXT:    add a1, a2, a19388; RV32-NEXT:    add a1, sp, a19389; RV32-NEXT:    addi a1, a1, 649390; RV32-NEXT:    csrr a2, vlenb9391; RV32-NEXT:    vmv2r.v v16, v89392; RV32-NEXT:    vmv2r.v v22, v169393; RV32-NEXT:    vmv2r.v v24, v189394; RV32-NEXT:    vmv1r.v v26, v209395; RV32-NEXT:    add a3, a0, a29396; RV32-NEXT:    vmv1r.v v23, v109397; RV32-NEXT:    add a4, a1, a29398; RV32-NEXT:    add a5, a4, a29399; RV32-NEXT:    vmv1r.v v25, v149400; RV32-NEXT:    add a6, a5, a29401; RV32-NEXT:    vmv1r.v v18, v119402; RV32-NEXT:    vsseg5e64.v v22, (a0)9403; RV32-NEXT:    vmv1r.v v20, v159404; RV32-NEXT:    vsseg5e64.v v17, (a1)9405; RV32-NEXT:    vl1re64.v v16, (a6)9406; RV32-NEXT:    add a6, a6, a29407; RV32-NEXT:    vl1re64.v v17, (a6)9408; RV32-NEXT:    add a6, a3, a29409; RV32-NEXT:    vl1re64.v v10, (a6)9410; RV32-NEXT:    add a6, a6, a29411; RV32-NEXT:    vl1re64.v v11, (a6)9412; RV32-NEXT:    vl1re64.v v8, (a0)9413; RV32-NEXT:    vl1re64.v v9, (a3)9414; RV32-NEXT:    vl1re64.v v14, (a4)9415; RV32-NEXT:    csrr a0, vlenb9416; RV32-NEXT:    li a3, 109417; RV32-NEXT:    mul a0, a0, a39418; RV32-NEXT:    add a0, sp, a09419; RV32-NEXT:    addi a0, a0, 649420; RV32-NEXT:    add a6, a6, a29421; RV32-NEXT:    vl1re64.v v15, (a5)9422; RV32-NEXT:    vl1re64.v v12, (a6)9423; RV32-NEXT:    vl1re64.v v13, (a1)9424; RV32-NEXT:    slli a2, a2, 39425; RV32-NEXT:    add a2, a0, a29426; RV32-NEXT:    vs2r.v v16, (a2)9427; RV32-NEXT:    vs8r.v v8, (a0)9428; RV32-NEXT:    vl8re64.v v16, (a2)9429; RV32-NEXT:    vl8re64.v v8, (a0)9430; RV32-NEXT:    addi sp, s0, -809431; RV32-NEXT:    lw ra, 76(sp) # 4-byte Folded Reload9432; RV32-NEXT:    lw s0, 72(sp) # 4-byte Folded Reload9433; RV32-NEXT:    addi sp, sp, 809434; RV32-NEXT:    ret9435;9436; RV64-LABEL: vector_interleave_nxv10f64_nxv2f64:9437; RV64:       # %bb.0:9438; RV64-NEXT:    addi sp, sp, -809439; RV64-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill9440; RV64-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill9441; RV64-NEXT:    addi s0, sp, 809442; RV64-NEXT:    csrr a0, vlenb9443; RV64-NEXT:    li a1, 289444; RV64-NEXT:    mul a0, a0, a19445; RV64-NEXT:    sub sp, sp, a09446; RV64-NEXT:    andi sp, sp, -649447; RV64-NEXT:    vsetvli a0, zero, e64, m1, ta, ma9448; RV64-NEXT:    vmv2r.v v20, v169449; RV64-NEXT:    addi a0, sp, 649450; RV64-NEXT:    vmv2r.v v18, v129451; RV64-NEXT:    csrr a1, vlenb9452; RV64-NEXT:    slli a2, a1, 29453; RV64-NEXT:    add a1, a2, a19454; RV64-NEXT:    add a1, sp, a19455; RV64-NEXT:    addi a1, a1, 649456; RV64-NEXT:    csrr a2, vlenb9457; RV64-NEXT:    vmv2r.v v16, v89458; RV64-NEXT:    vmv2r.v v22, v169459; RV64-NEXT:    vmv2r.v v24, v189460; RV64-NEXT:    vmv1r.v v26, v209461; RV64-NEXT:    add a3, a0, a29462; RV64-NEXT:    vmv1r.v v23, v109463; RV64-NEXT:    add a4, a1, a29464; RV64-NEXT:    add a5, a4, a29465; RV64-NEXT:    vmv1r.v v25, v149466; RV64-NEXT:    add a6, a5, a29467; RV64-NEXT:    vmv1r.v v18, v119468; RV64-NEXT:    vsseg5e64.v v22, (a0)9469; RV64-NEXT:    vmv1r.v v20, v159470; RV64-NEXT:    vsseg5e64.v v17, (a1)9471; RV64-NEXT:    vl1re64.v v16, (a6)9472; RV64-NEXT:    add a6, a6, a29473; RV64-NEXT:    vl1re64.v v17, (a6)9474; RV64-NEXT:    add a6, a3, a29475; RV64-NEXT:    vl1re64.v v10, (a6)9476; RV64-NEXT:    add a6, a6, a29477; RV64-NEXT:    vl1re64.v v11, (a6)9478; RV64-NEXT:    vl1re64.v v8, (a0)9479; RV64-NEXT:    vl1re64.v v9, (a3)9480; RV64-NEXT:    vl1re64.v v14, (a4)9481; RV64-NEXT:    csrr a0, vlenb9482; RV64-NEXT:    li a3, 109483; RV64-NEXT:    mul a0, a0, a39484; RV64-NEXT:    add a0, sp, a09485; RV64-NEXT:    addi a0, a0, 649486; RV64-NEXT:    add a6, a6, a29487; RV64-NEXT:    vl1re64.v v15, (a5)9488; RV64-NEXT:    vl1re64.v v12, (a6)9489; RV64-NEXT:    vl1re64.v v13, (a1)9490; RV64-NEXT:    slli a2, a2, 39491; RV64-NEXT:    add a2, a0, a29492; RV64-NEXT:    vs2r.v v16, (a2)9493; RV64-NEXT:    vs8r.v v8, (a0)9494; RV64-NEXT:    vl8re64.v v16, (a2)9495; RV64-NEXT:    vl8re64.v v8, (a0)9496; RV64-NEXT:    addi sp, s0, -809497; RV64-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload9498; RV64-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload9499; RV64-NEXT:    addi sp, sp, 809500; RV64-NEXT:    ret9501;9502; ZVBB-RV32-LABEL: vector_interleave_nxv10f64_nxv2f64:9503; ZVBB-RV32:       # %bb.0:9504; ZVBB-RV32-NEXT:    addi sp, sp, -809505; ZVBB-RV32-NEXT:    sw ra, 76(sp) # 4-byte Folded Spill9506; ZVBB-RV32-NEXT:    sw s0, 72(sp) # 4-byte Folded Spill9507; ZVBB-RV32-NEXT:    addi s0, sp, 809508; ZVBB-RV32-NEXT:    csrr a0, vlenb9509; ZVBB-RV32-NEXT:    li a1, 289510; ZVBB-RV32-NEXT:    mul a0, a0, a19511; ZVBB-RV32-NEXT:    sub sp, sp, a09512; ZVBB-RV32-NEXT:    andi sp, sp, -649513; ZVBB-RV32-NEXT:    vsetvli a0, zero, e64, m1, ta, ma9514; ZVBB-RV32-NEXT:    vmv2r.v v20, v169515; ZVBB-RV32-NEXT:    addi a0, sp, 649516; ZVBB-RV32-NEXT:    vmv2r.v v18, v129517; ZVBB-RV32-NEXT:    csrr a1, vlenb9518; ZVBB-RV32-NEXT:    slli a2, a1, 29519; ZVBB-RV32-NEXT:    add a1, a2, a19520; ZVBB-RV32-NEXT:    add a1, sp, a19521; ZVBB-RV32-NEXT:    addi a1, a1, 649522; ZVBB-RV32-NEXT:    csrr a2, vlenb9523; ZVBB-RV32-NEXT:    vmv2r.v v16, v89524; ZVBB-RV32-NEXT:    vmv2r.v v22, v169525; ZVBB-RV32-NEXT:    vmv2r.v v24, v189526; ZVBB-RV32-NEXT:    vmv1r.v v26, v209527; ZVBB-RV32-NEXT:    add a3, a0, a29528; ZVBB-RV32-NEXT:    vmv1r.v v23, v109529; ZVBB-RV32-NEXT:    add a4, a1, a29530; ZVBB-RV32-NEXT:    add a5, a4, a29531; ZVBB-RV32-NEXT:    vmv1r.v v25, v149532; ZVBB-RV32-NEXT:    add a6, a5, a29533; ZVBB-RV32-NEXT:    vmv1r.v v18, v119534; ZVBB-RV32-NEXT:    vsseg5e64.v v22, (a0)9535; ZVBB-RV32-NEXT:    vmv1r.v v20, v159536; ZVBB-RV32-NEXT:    vsseg5e64.v v17, (a1)9537; ZVBB-RV32-NEXT:    vl1re64.v v16, (a6)9538; ZVBB-RV32-NEXT:    add a6, a6, a29539; ZVBB-RV32-NEXT:    vl1re64.v v17, (a6)9540; ZVBB-RV32-NEXT:    add a6, a3, a29541; ZVBB-RV32-NEXT:    vl1re64.v v10, (a6)9542; ZVBB-RV32-NEXT:    add a6, a6, a29543; ZVBB-RV32-NEXT:    vl1re64.v v11, (a6)9544; ZVBB-RV32-NEXT:    vl1re64.v v8, (a0)9545; ZVBB-RV32-NEXT:    vl1re64.v v9, (a3)9546; ZVBB-RV32-NEXT:    vl1re64.v v14, (a4)9547; ZVBB-RV32-NEXT:    csrr a0, vlenb9548; ZVBB-RV32-NEXT:    li a3, 109549; ZVBB-RV32-NEXT:    mul a0, a0, a39550; ZVBB-RV32-NEXT:    add a0, sp, a09551; ZVBB-RV32-NEXT:    addi a0, a0, 649552; ZVBB-RV32-NEXT:    add a6, a6, a29553; ZVBB-RV32-NEXT:    vl1re64.v v15, (a5)9554; ZVBB-RV32-NEXT:    vl1re64.v v12, (a6)9555; ZVBB-RV32-NEXT:    vl1re64.v v13, (a1)9556; ZVBB-RV32-NEXT:    slli a2, a2, 39557; ZVBB-RV32-NEXT:    add a2, a0, a29558; ZVBB-RV32-NEXT:    vs2r.v v16, (a2)9559; ZVBB-RV32-NEXT:    vs8r.v v8, (a0)9560; ZVBB-RV32-NEXT:    vl8re64.v v16, (a2)9561; ZVBB-RV32-NEXT:    vl8re64.v v8, (a0)9562; ZVBB-RV32-NEXT:    addi sp, s0, -809563; ZVBB-RV32-NEXT:    lw ra, 76(sp) # 4-byte Folded Reload9564; ZVBB-RV32-NEXT:    lw s0, 72(sp) # 4-byte Folded Reload9565; ZVBB-RV32-NEXT:    addi sp, sp, 809566; ZVBB-RV32-NEXT:    ret9567;9568; ZVBB-RV64-LABEL: vector_interleave_nxv10f64_nxv2f64:9569; ZVBB-RV64:       # %bb.0:9570; ZVBB-RV64-NEXT:    addi sp, sp, -809571; ZVBB-RV64-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill9572; ZVBB-RV64-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill9573; ZVBB-RV64-NEXT:    addi s0, sp, 809574; ZVBB-RV64-NEXT:    csrr a0, vlenb9575; ZVBB-RV64-NEXT:    li a1, 289576; ZVBB-RV64-NEXT:    mul a0, a0, a19577; ZVBB-RV64-NEXT:    sub sp, sp, a09578; ZVBB-RV64-NEXT:    andi sp, sp, -649579; ZVBB-RV64-NEXT:    vsetvli a0, zero, e64, m1, ta, ma9580; ZVBB-RV64-NEXT:    vmv2r.v v20, v169581; ZVBB-RV64-NEXT:    addi a0, sp, 649582; ZVBB-RV64-NEXT:    vmv2r.v v18, v129583; ZVBB-RV64-NEXT:    csrr a1, vlenb9584; ZVBB-RV64-NEXT:    slli a2, a1, 29585; ZVBB-RV64-NEXT:    add a1, a2, a19586; ZVBB-RV64-NEXT:    add a1, sp, a19587; ZVBB-RV64-NEXT:    addi a1, a1, 649588; ZVBB-RV64-NEXT:    csrr a2, vlenb9589; ZVBB-RV64-NEXT:    vmv2r.v v16, v89590; ZVBB-RV64-NEXT:    vmv2r.v v22, v169591; ZVBB-RV64-NEXT:    vmv2r.v v24, v189592; ZVBB-RV64-NEXT:    vmv1r.v v26, v209593; ZVBB-RV64-NEXT:    add a3, a0, a29594; ZVBB-RV64-NEXT:    vmv1r.v v23, v109595; ZVBB-RV64-NEXT:    add a4, a1, a29596; ZVBB-RV64-NEXT:    add a5, a4, a29597; ZVBB-RV64-NEXT:    vmv1r.v v25, v149598; ZVBB-RV64-NEXT:    add a6, a5, a29599; ZVBB-RV64-NEXT:    vmv1r.v v18, v119600; ZVBB-RV64-NEXT:    vsseg5e64.v v22, (a0)9601; ZVBB-RV64-NEXT:    vmv1r.v v20, v159602; ZVBB-RV64-NEXT:    vsseg5e64.v v17, (a1)9603; ZVBB-RV64-NEXT:    vl1re64.v v16, (a6)9604; ZVBB-RV64-NEXT:    add a6, a6, a29605; ZVBB-RV64-NEXT:    vl1re64.v v17, (a6)9606; ZVBB-RV64-NEXT:    add a6, a3, a29607; ZVBB-RV64-NEXT:    vl1re64.v v10, (a6)9608; ZVBB-RV64-NEXT:    add a6, a6, a29609; ZVBB-RV64-NEXT:    vl1re64.v v11, (a6)9610; ZVBB-RV64-NEXT:    vl1re64.v v8, (a0)9611; ZVBB-RV64-NEXT:    vl1re64.v v9, (a3)9612; ZVBB-RV64-NEXT:    vl1re64.v v14, (a4)9613; ZVBB-RV64-NEXT:    csrr a0, vlenb9614; ZVBB-RV64-NEXT:    li a3, 109615; ZVBB-RV64-NEXT:    mul a0, a0, a39616; ZVBB-RV64-NEXT:    add a0, sp, a09617; ZVBB-RV64-NEXT:    addi a0, a0, 649618; ZVBB-RV64-NEXT:    add a6, a6, a29619; ZVBB-RV64-NEXT:    vl1re64.v v15, (a5)9620; ZVBB-RV64-NEXT:    vl1re64.v v12, (a6)9621; ZVBB-RV64-NEXT:    vl1re64.v v13, (a1)9622; ZVBB-RV64-NEXT:    slli a2, a2, 39623; ZVBB-RV64-NEXT:    add a2, a0, a29624; ZVBB-RV64-NEXT:    vs2r.v v16, (a2)9625; ZVBB-RV64-NEXT:    vs8r.v v8, (a0)9626; ZVBB-RV64-NEXT:    vl8re64.v v16, (a2)9627; ZVBB-RV64-NEXT:    vl8re64.v v8, (a0)9628; ZVBB-RV64-NEXT:    addi sp, s0, -809629; ZVBB-RV64-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload9630; ZVBB-RV64-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload9631; ZVBB-RV64-NEXT:    addi sp, sp, 809632; ZVBB-RV64-NEXT:    ret9633;9634; ZIP-LABEL: vector_interleave_nxv10f64_nxv2f64:9635; ZIP:       # %bb.0:9636; ZIP-NEXT:    addi sp, sp, -809637; ZIP-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill9638; ZIP-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill9639; ZIP-NEXT:    addi s0, sp, 809640; ZIP-NEXT:    csrr a0, vlenb9641; ZIP-NEXT:    li a1, 289642; ZIP-NEXT:    mul a0, a0, a19643; ZIP-NEXT:    sub sp, sp, a09644; ZIP-NEXT:    andi sp, sp, -649645; ZIP-NEXT:    vsetvli a0, zero, e64, m1, ta, ma9646; ZIP-NEXT:    vmv2r.v v20, v169647; ZIP-NEXT:    addi a0, sp, 649648; ZIP-NEXT:    vmv2r.v v18, v129649; ZIP-NEXT:    csrr a1, vlenb9650; ZIP-NEXT:    slli a2, a1, 29651; ZIP-NEXT:    add a1, a2, a19652; ZIP-NEXT:    add a1, sp, a19653; ZIP-NEXT:    addi a1, a1, 649654; ZIP-NEXT:    csrr a2, vlenb9655; ZIP-NEXT:    vmv2r.v v16, v89656; ZIP-NEXT:    vmv2r.v v22, v169657; ZIP-NEXT:    vmv2r.v v24, v189658; ZIP-NEXT:    vmv1r.v v26, v209659; ZIP-NEXT:    add a3, a0, a29660; ZIP-NEXT:    vmv1r.v v23, v109661; ZIP-NEXT:    add a4, a1, a29662; ZIP-NEXT:    add a5, a4, a29663; ZIP-NEXT:    vmv1r.v v25, v149664; ZIP-NEXT:    add a6, a5, a29665; ZIP-NEXT:    vmv1r.v v18, v119666; ZIP-NEXT:    vsseg5e64.v v22, (a0)9667; ZIP-NEXT:    vmv1r.v v20, v159668; ZIP-NEXT:    vsseg5e64.v v17, (a1)9669; ZIP-NEXT:    vl1re64.v v16, (a6)9670; ZIP-NEXT:    add a6, a6, a29671; ZIP-NEXT:    vl1re64.v v17, (a6)9672; ZIP-NEXT:    add a6, a3, a29673; ZIP-NEXT:    vl1re64.v v10, (a6)9674; ZIP-NEXT:    add a6, a6, a29675; ZIP-NEXT:    vl1re64.v v11, (a6)9676; ZIP-NEXT:    vl1re64.v v8, (a0)9677; ZIP-NEXT:    vl1re64.v v9, (a3)9678; ZIP-NEXT:    vl1re64.v v14, (a4)9679; ZIP-NEXT:    csrr a0, vlenb9680; ZIP-NEXT:    li a3, 109681; ZIP-NEXT:    mul a0, a0, a39682; ZIP-NEXT:    add a0, sp, a09683; ZIP-NEXT:    addi a0, a0, 649684; ZIP-NEXT:    add a6, a6, a29685; ZIP-NEXT:    vl1re64.v v15, (a5)9686; ZIP-NEXT:    vl1re64.v v12, (a6)9687; ZIP-NEXT:    vl1re64.v v13, (a1)9688; ZIP-NEXT:    slli a2, a2, 39689; ZIP-NEXT:    add a2, a0, a29690; ZIP-NEXT:    vs2r.v v16, (a2)9691; ZIP-NEXT:    vs8r.v v8, (a0)9692; ZIP-NEXT:    vl8re64.v v16, (a2)9693; ZIP-NEXT:    vl8re64.v v8, (a0)9694; ZIP-NEXT:    addi sp, s0, -809695; ZIP-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload9696; ZIP-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload9697; ZIP-NEXT:    addi sp, sp, 809698; ZIP-NEXT:    ret9699  %res = call <vscale x 10 x double> @llvm.vector.interleave5.nxv10f64(<vscale x 2 x double> %v0, <vscale x 2 x double> %v1, <vscale x 2 x double> %v2, <vscale x 2 x double> %v3, <vscale x 2 x double> %v4)9700  ret <vscale x 10 x double> %res9701}9702 9703define <vscale x 12 x half> @vector_interleave_nxv12f16_nxv2f16(<vscale x 2 x half> %v0, <vscale x 2 x half> %v1, <vscale x 2 x half> %v2, <vscale x 2 x half> %v3, <vscale x 2 x half> %v4, <vscale x 2 x half> %v5) nounwind {9704; CHECK-LABEL: vector_interleave_nxv12f16_nxv2f16:9705; CHECK:       # %bb.0:9706; CHECK-NEXT:    addi sp, sp, -169707; CHECK-NEXT:    csrr a0, vlenb9708; CHECK-NEXT:    slli a1, a0, 19709; CHECK-NEXT:    add a0, a1, a09710; CHECK-NEXT:    sub sp, sp, a09711; CHECK-NEXT:    addi a0, sp, 169712; CHECK-NEXT:    csrr a1, vlenb9713; CHECK-NEXT:    srli a2, a1, 19714; CHECK-NEXT:    add a3, a0, a29715; CHECK-NEXT:    add a4, a3, a29716; CHECK-NEXT:    add a5, a4, a29717; CHECK-NEXT:    vsetvli a6, zero, e16, mf2, ta, ma9718; CHECK-NEXT:    vsseg6e16.v v8, (a0)9719; CHECK-NEXT:    add a6, a5, a29720; CHECK-NEXT:    add a2, a6, a29721; CHECK-NEXT:    vle16.v v10, (a6)9722; CHECK-NEXT:    vle16.v v8, (a2)9723; CHECK-NEXT:    srli a1, a1, 29724; CHECK-NEXT:    vle16.v v11, (a5)9725; CHECK-NEXT:    vsetvli a2, zero, e16, m1, ta, ma9726; CHECK-NEXT:    vslideup.vx v10, v8, a19727; CHECK-NEXT:    vsetvli a2, zero, e16, mf2, ta, ma9728; CHECK-NEXT:    vle16.v v9, (a4)9729; CHECK-NEXT:    vsetvli a2, zero, e16, m1, ta, ma9730; CHECK-NEXT:    vslideup.vx v9, v11, a19731; CHECK-NEXT:    vsetvli a2, zero, e16, mf2, ta, ma9732; CHECK-NEXT:    vle16.v v11, (a3)9733; CHECK-NEXT:    vle16.v v8, (a0)9734; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma9735; CHECK-NEXT:    vslideup.vx v8, v11, a19736; CHECK-NEXT:    csrr a0, vlenb9737; CHECK-NEXT:    slli a1, a0, 19738; CHECK-NEXT:    add a0, a1, a09739; CHECK-NEXT:    add sp, sp, a09740; CHECK-NEXT:    addi sp, sp, 169741; CHECK-NEXT:    ret9742;9743; ZVBB-LABEL: vector_interleave_nxv12f16_nxv2f16:9744; ZVBB:       # %bb.0:9745; ZVBB-NEXT:    addi sp, sp, -169746; ZVBB-NEXT:    csrr a0, vlenb9747; ZVBB-NEXT:    slli a1, a0, 19748; ZVBB-NEXT:    add a0, a1, a09749; ZVBB-NEXT:    sub sp, sp, a09750; ZVBB-NEXT:    addi a0, sp, 169751; ZVBB-NEXT:    csrr a1, vlenb9752; ZVBB-NEXT:    srli a2, a1, 19753; ZVBB-NEXT:    add a3, a0, a29754; ZVBB-NEXT:    add a4, a3, a29755; ZVBB-NEXT:    add a5, a4, a29756; ZVBB-NEXT:    vsetvli a6, zero, e16, mf2, ta, ma9757; ZVBB-NEXT:    vsseg6e16.v v8, (a0)9758; ZVBB-NEXT:    add a6, a5, a29759; ZVBB-NEXT:    add a2, a6, a29760; ZVBB-NEXT:    vle16.v v10, (a6)9761; ZVBB-NEXT:    vle16.v v8, (a2)9762; ZVBB-NEXT:    srli a1, a1, 29763; ZVBB-NEXT:    vle16.v v11, (a5)9764; ZVBB-NEXT:    vsetvli a2, zero, e16, m1, ta, ma9765; ZVBB-NEXT:    vslideup.vx v10, v8, a19766; ZVBB-NEXT:    vsetvli a2, zero, e16, mf2, ta, ma9767; ZVBB-NEXT:    vle16.v v9, (a4)9768; ZVBB-NEXT:    vsetvli a2, zero, e16, m1, ta, ma9769; ZVBB-NEXT:    vslideup.vx v9, v11, a19770; ZVBB-NEXT:    vsetvli a2, zero, e16, mf2, ta, ma9771; ZVBB-NEXT:    vle16.v v11, (a3)9772; ZVBB-NEXT:    vle16.v v8, (a0)9773; ZVBB-NEXT:    vsetvli a0, zero, e16, m1, ta, ma9774; ZVBB-NEXT:    vslideup.vx v8, v11, a19775; ZVBB-NEXT:    csrr a0, vlenb9776; ZVBB-NEXT:    slli a1, a0, 19777; ZVBB-NEXT:    add a0, a1, a09778; ZVBB-NEXT:    add sp, sp, a09779; ZVBB-NEXT:    addi sp, sp, 169780; ZVBB-NEXT:    ret9781  %res = call <vscale x 12 x half> @llvm.vector.interleave6.nxv12f16(<vscale x 2 x half> %v0, <vscale x 2 x half> %v1, <vscale x 2 x half> %v2, <vscale x 2 x half> %v3, <vscale x 2 x half> %v4, <vscale x 2 x half> %v5)9782  ret <vscale x 12 x half> %res9783}9784 9785define <vscale x 24 x half> @vector_interleave_nxv24f16_nxv4f16(<vscale x 4 x half> %v0, <vscale x 4 x half> %v1, <vscale x 4 x half> %v2, <vscale x 4 x half> %v3, <vscale x 4 x half> %v4, <vscale x 4 x half> %v5) nounwind {9786; CHECK-LABEL: vector_interleave_nxv24f16_nxv4f16:9787; CHECK:       # %bb.0:9788; CHECK-NEXT:    addi sp, sp, -169789; CHECK-NEXT:    csrr a0, vlenb9790; CHECK-NEXT:    li a1, 69791; CHECK-NEXT:    mul a0, a0, a19792; CHECK-NEXT:    sub sp, sp, a09793; CHECK-NEXT:    addi a0, sp, 169794; CHECK-NEXT:    csrr a1, vlenb9795; CHECK-NEXT:    add a2, a0, a19796; CHECK-NEXT:    add a3, a2, a19797; CHECK-NEXT:    vsetvli a4, zero, e16, m1, ta, ma9798; CHECK-NEXT:    vsseg6e16.v v8, (a0)9799; CHECK-NEXT:    vl1re16.v v10, (a3)9800; CHECK-NEXT:    add a3, a3, a19801; CHECK-NEXT:    vl1re16.v v11, (a3)9802; CHECK-NEXT:    add a3, a3, a19803; CHECK-NEXT:    vl1re16.v v8, (a0)9804; CHECK-NEXT:    vl1re16.v v9, (a2)9805; CHECK-NEXT:    vl1re16.v v12, (a3)9806; CHECK-NEXT:    add a1, a3, a19807; CHECK-NEXT:    vl1re16.v v13, (a1)9808; CHECK-NEXT:    csrr a0, vlenb9809; CHECK-NEXT:    li a1, 69810; CHECK-NEXT:    mul a0, a0, a19811; CHECK-NEXT:    add sp, sp, a09812; CHECK-NEXT:    addi sp, sp, 169813; CHECK-NEXT:    ret9814;9815; ZVBB-LABEL: vector_interleave_nxv24f16_nxv4f16:9816; ZVBB:       # %bb.0:9817; ZVBB-NEXT:    addi sp, sp, -169818; ZVBB-NEXT:    csrr a0, vlenb9819; ZVBB-NEXT:    li a1, 69820; ZVBB-NEXT:    mul a0, a0, a19821; ZVBB-NEXT:    sub sp, sp, a09822; ZVBB-NEXT:    addi a0, sp, 169823; ZVBB-NEXT:    csrr a1, vlenb9824; ZVBB-NEXT:    add a2, a0, a19825; ZVBB-NEXT:    add a3, a2, a19826; ZVBB-NEXT:    vsetvli a4, zero, e16, m1, ta, ma9827; ZVBB-NEXT:    vsseg6e16.v v8, (a0)9828; ZVBB-NEXT:    vl1re16.v v10, (a3)9829; ZVBB-NEXT:    add a3, a3, a19830; ZVBB-NEXT:    vl1re16.v v11, (a3)9831; ZVBB-NEXT:    add a3, a3, a19832; ZVBB-NEXT:    vl1re16.v v8, (a0)9833; ZVBB-NEXT:    vl1re16.v v9, (a2)9834; ZVBB-NEXT:    vl1re16.v v12, (a3)9835; ZVBB-NEXT:    add a1, a3, a19836; ZVBB-NEXT:    vl1re16.v v13, (a1)9837; ZVBB-NEXT:    csrr a0, vlenb9838; ZVBB-NEXT:    li a1, 69839; ZVBB-NEXT:    mul a0, a0, a19840; ZVBB-NEXT:    add sp, sp, a09841; ZVBB-NEXT:    addi sp, sp, 169842; ZVBB-NEXT:    ret9843  %res = call <vscale x 24 x half> @llvm.vector.interleave6.nxv24f16(<vscale x 4 x half> %v0, <vscale x 4 x half> %v1, <vscale x 4 x half> %v2, <vscale x 4 x half> %v3, <vscale x 4 x half> %v4, <vscale x 4 x half> %v5)9844  ret <vscale x 24 x half> %res9845}9846 9847define <vscale x 48 x half> @vector_interleave_nxv48f16_nxv8f16(<vscale x 8 x half> %v0, <vscale x 8 x half> %v1, <vscale x 8 x half> %v2, <vscale x 8 x half> %v3, <vscale x 8 x half> %v4, <vscale x 8 x half> %v5) nounwind {9848; RV32-LABEL: vector_interleave_nxv48f16_nxv8f16:9849; RV32:       # %bb.0:9850; RV32-NEXT:    addi sp, sp, -809851; RV32-NEXT:    sw ra, 76(sp) # 4-byte Folded Spill9852; RV32-NEXT:    sw s0, 72(sp) # 4-byte Folded Spill9853; RV32-NEXT:    addi s0, sp, 809854; RV32-NEXT:    csrr a0, vlenb9855; RV32-NEXT:    li a1, 289856; RV32-NEXT:    mul a0, a0, a19857; RV32-NEXT:    sub sp, sp, a09858; RV32-NEXT:    andi sp, sp, -649859; RV32-NEXT:    vsetvli a0, zero, e16, m1, ta, ma9860; RV32-NEXT:    vmv2r.v v20, v149861; RV32-NEXT:    vmv2r.v v22, v129862; RV32-NEXT:    vmv2r.v v24, v109863; RV32-NEXT:    csrr a1, vlenb9864; RV32-NEXT:    li a0, 69865; RV32-NEXT:    mul a1, a1, a09866; RV32-NEXT:    add a1, sp, a19867; RV32-NEXT:    addi a1, a1, 649868; RV32-NEXT:    vmv1r.v v10, v259869; RV32-NEXT:    vmv1r.v v11, v239870; RV32-NEXT:    vmv1r.v v12, v219871; RV32-NEXT:    addi a0, sp, 649872; RV32-NEXT:    vmv1r.v v13, v179873; RV32-NEXT:    csrr a2, vlenb9874; RV32-NEXT:    vmv1r.v v14, v199875; RV32-NEXT:    vsseg6e16.v v9, (a1)9876; RV32-NEXT:    vmv1r.v v9, v249877; RV32-NEXT:    add a5, a1, a29878; RV32-NEXT:    vmv1r.v v10, v229879; RV32-NEXT:    add a3, a0, a29880; RV32-NEXT:    vmv1r.v v11, v209881; RV32-NEXT:    add a4, a3, a29882; RV32-NEXT:    vmv1r.v v12, v169883; RV32-NEXT:    add a6, a5, a29884; RV32-NEXT:    vmv1r.v v13, v189885; RV32-NEXT:    vsseg6e16.v v8, (a0)9886; RV32-NEXT:    vl1re16.v v14, (a1)9887; RV32-NEXT:    add a1, a6, a29888; RV32-NEXT:    vl1re16.v v15, (a5)9889; RV32-NEXT:    add a5, a1, a29890; RV32-NEXT:    vl1re16.v v18, (a5)9891; RV32-NEXT:    add a5, a5, a29892; RV32-NEXT:    vl1re16.v v19, (a5)9893; RV32-NEXT:    add a5, a4, a29894; RV32-NEXT:    vl1re16.v v16, (a6)9895; RV32-NEXT:    add a6, a5, a29896; RV32-NEXT:    vl1re16.v v12, (a6)9897; RV32-NEXT:    add a6, a6, a29898; RV32-NEXT:    vl1re16.v v13, (a6)9899; RV32-NEXT:    csrr a6, vlenb9900; RV32-NEXT:    li a7, 129901; RV32-NEXT:    mul a6, a6, a79902; RV32-NEXT:    add a6, sp, a69903; RV32-NEXT:    addi a6, a6, 649904; RV32-NEXT:    vl1re16.v v17, (a1)9905; RV32-NEXT:    vl1re16.v v10, (a4)9906; RV32-NEXT:    vl1re16.v v11, (a5)9907; RV32-NEXT:    vl1re16.v v8, (a0)9908; RV32-NEXT:    vl1re16.v v9, (a3)9909; RV32-NEXT:    slli a2, a2, 39910; RV32-NEXT:    add a2, a6, a29911; RV32-NEXT:    vs4r.v v16, (a2)9912; RV32-NEXT:    vs8r.v v8, (a6)9913; RV32-NEXT:    vl8re16.v v16, (a2)9914; RV32-NEXT:    vl8re16.v v8, (a6)9915; RV32-NEXT:    addi sp, s0, -809916; RV32-NEXT:    lw ra, 76(sp) # 4-byte Folded Reload9917; RV32-NEXT:    lw s0, 72(sp) # 4-byte Folded Reload9918; RV32-NEXT:    addi sp, sp, 809919; RV32-NEXT:    ret9920;9921; RV64-LABEL: vector_interleave_nxv48f16_nxv8f16:9922; RV64:       # %bb.0:9923; RV64-NEXT:    addi sp, sp, -809924; RV64-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill9925; RV64-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill9926; RV64-NEXT:    addi s0, sp, 809927; RV64-NEXT:    csrr a0, vlenb9928; RV64-NEXT:    li a1, 289929; RV64-NEXT:    mul a0, a0, a19930; RV64-NEXT:    sub sp, sp, a09931; RV64-NEXT:    andi sp, sp, -649932; RV64-NEXT:    vsetvli a0, zero, e16, m1, ta, ma9933; RV64-NEXT:    vmv2r.v v20, v149934; RV64-NEXT:    vmv2r.v v22, v129935; RV64-NEXT:    vmv2r.v v24, v109936; RV64-NEXT:    csrr a1, vlenb9937; RV64-NEXT:    li a0, 69938; RV64-NEXT:    mul a1, a1, a09939; RV64-NEXT:    add a1, sp, a19940; RV64-NEXT:    addi a1, a1, 649941; RV64-NEXT:    vmv1r.v v10, v259942; RV64-NEXT:    vmv1r.v v11, v239943; RV64-NEXT:    vmv1r.v v12, v219944; RV64-NEXT:    addi a0, sp, 649945; RV64-NEXT:    vmv1r.v v13, v179946; RV64-NEXT:    csrr a2, vlenb9947; RV64-NEXT:    vmv1r.v v14, v199948; RV64-NEXT:    vsseg6e16.v v9, (a1)9949; RV64-NEXT:    vmv1r.v v9, v249950; RV64-NEXT:    add a5, a1, a29951; RV64-NEXT:    vmv1r.v v10, v229952; RV64-NEXT:    add a3, a0, a29953; RV64-NEXT:    vmv1r.v v11, v209954; RV64-NEXT:    add a4, a3, a29955; RV64-NEXT:    vmv1r.v v12, v169956; RV64-NEXT:    add a6, a5, a29957; RV64-NEXT:    vmv1r.v v13, v189958; RV64-NEXT:    vsseg6e16.v v8, (a0)9959; RV64-NEXT:    vl1re16.v v14, (a1)9960; RV64-NEXT:    add a1, a6, a29961; RV64-NEXT:    vl1re16.v v15, (a5)9962; RV64-NEXT:    add a5, a1, a29963; RV64-NEXT:    vl1re16.v v18, (a5)9964; RV64-NEXT:    add a5, a5, a29965; RV64-NEXT:    vl1re16.v v19, (a5)9966; RV64-NEXT:    add a5, a4, a29967; RV64-NEXT:    vl1re16.v v16, (a6)9968; RV64-NEXT:    add a6, a5, a29969; RV64-NEXT:    vl1re16.v v12, (a6)9970; RV64-NEXT:    add a6, a6, a29971; RV64-NEXT:    vl1re16.v v13, (a6)9972; RV64-NEXT:    csrr a6, vlenb9973; RV64-NEXT:    li a7, 129974; RV64-NEXT:    mul a6, a6, a79975; RV64-NEXT:    add a6, sp, a69976; RV64-NEXT:    addi a6, a6, 649977; RV64-NEXT:    vl1re16.v v17, (a1)9978; RV64-NEXT:    vl1re16.v v10, (a4)9979; RV64-NEXT:    vl1re16.v v11, (a5)9980; RV64-NEXT:    vl1re16.v v8, (a0)9981; RV64-NEXT:    vl1re16.v v9, (a3)9982; RV64-NEXT:    slli a2, a2, 39983; RV64-NEXT:    add a2, a6, a29984; RV64-NEXT:    vs4r.v v16, (a2)9985; RV64-NEXT:    vs8r.v v8, (a6)9986; RV64-NEXT:    vl8re16.v v16, (a2)9987; RV64-NEXT:    vl8re16.v v8, (a6)9988; RV64-NEXT:    addi sp, s0, -809989; RV64-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload9990; RV64-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload9991; RV64-NEXT:    addi sp, sp, 809992; RV64-NEXT:    ret9993;9994; ZVBB-RV32-LABEL: vector_interleave_nxv48f16_nxv8f16:9995; ZVBB-RV32:       # %bb.0:9996; ZVBB-RV32-NEXT:    addi sp, sp, -809997; ZVBB-RV32-NEXT:    sw ra, 76(sp) # 4-byte Folded Spill9998; ZVBB-RV32-NEXT:    sw s0, 72(sp) # 4-byte Folded Spill9999; ZVBB-RV32-NEXT:    addi s0, sp, 8010000; ZVBB-RV32-NEXT:    csrr a0, vlenb10001; ZVBB-RV32-NEXT:    li a1, 2810002; ZVBB-RV32-NEXT:    mul a0, a0, a110003; ZVBB-RV32-NEXT:    sub sp, sp, a010004; ZVBB-RV32-NEXT:    andi sp, sp, -6410005; ZVBB-RV32-NEXT:    vsetvli a0, zero, e16, m1, ta, ma10006; ZVBB-RV32-NEXT:    vmv2r.v v20, v1410007; ZVBB-RV32-NEXT:    vmv2r.v v22, v1210008; ZVBB-RV32-NEXT:    vmv2r.v v24, v1010009; ZVBB-RV32-NEXT:    csrr a1, vlenb10010; ZVBB-RV32-NEXT:    li a0, 610011; ZVBB-RV32-NEXT:    mul a1, a1, a010012; ZVBB-RV32-NEXT:    add a1, sp, a110013; ZVBB-RV32-NEXT:    addi a1, a1, 6410014; ZVBB-RV32-NEXT:    vmv1r.v v10, v2510015; ZVBB-RV32-NEXT:    vmv1r.v v11, v2310016; ZVBB-RV32-NEXT:    vmv1r.v v12, v2110017; ZVBB-RV32-NEXT:    addi a0, sp, 6410018; ZVBB-RV32-NEXT:    vmv1r.v v13, v1710019; ZVBB-RV32-NEXT:    csrr a2, vlenb10020; ZVBB-RV32-NEXT:    vmv1r.v v14, v1910021; ZVBB-RV32-NEXT:    vsseg6e16.v v9, (a1)10022; ZVBB-RV32-NEXT:    vmv1r.v v9, v2410023; ZVBB-RV32-NEXT:    add a5, a1, a210024; ZVBB-RV32-NEXT:    vmv1r.v v10, v2210025; ZVBB-RV32-NEXT:    add a3, a0, a210026; ZVBB-RV32-NEXT:    vmv1r.v v11, v2010027; ZVBB-RV32-NEXT:    add a4, a3, a210028; ZVBB-RV32-NEXT:    vmv1r.v v12, v1610029; ZVBB-RV32-NEXT:    add a6, a5, a210030; ZVBB-RV32-NEXT:    vmv1r.v v13, v1810031; ZVBB-RV32-NEXT:    vsseg6e16.v v8, (a0)10032; ZVBB-RV32-NEXT:    vl1re16.v v14, (a1)10033; ZVBB-RV32-NEXT:    add a1, a6, a210034; ZVBB-RV32-NEXT:    vl1re16.v v15, (a5)10035; ZVBB-RV32-NEXT:    add a5, a1, a210036; ZVBB-RV32-NEXT:    vl1re16.v v18, (a5)10037; ZVBB-RV32-NEXT:    add a5, a5, a210038; ZVBB-RV32-NEXT:    vl1re16.v v19, (a5)10039; ZVBB-RV32-NEXT:    add a5, a4, a210040; ZVBB-RV32-NEXT:    vl1re16.v v16, (a6)10041; ZVBB-RV32-NEXT:    add a6, a5, a210042; ZVBB-RV32-NEXT:    vl1re16.v v12, (a6)10043; ZVBB-RV32-NEXT:    add a6, a6, a210044; ZVBB-RV32-NEXT:    vl1re16.v v13, (a6)10045; ZVBB-RV32-NEXT:    csrr a6, vlenb10046; ZVBB-RV32-NEXT:    li a7, 1210047; ZVBB-RV32-NEXT:    mul a6, a6, a710048; ZVBB-RV32-NEXT:    add a6, sp, a610049; ZVBB-RV32-NEXT:    addi a6, a6, 6410050; ZVBB-RV32-NEXT:    vl1re16.v v17, (a1)10051; ZVBB-RV32-NEXT:    vl1re16.v v10, (a4)10052; ZVBB-RV32-NEXT:    vl1re16.v v11, (a5)10053; ZVBB-RV32-NEXT:    vl1re16.v v8, (a0)10054; ZVBB-RV32-NEXT:    vl1re16.v v9, (a3)10055; ZVBB-RV32-NEXT:    slli a2, a2, 310056; ZVBB-RV32-NEXT:    add a2, a6, a210057; ZVBB-RV32-NEXT:    vs4r.v v16, (a2)10058; ZVBB-RV32-NEXT:    vs8r.v v8, (a6)10059; ZVBB-RV32-NEXT:    vl8re16.v v16, (a2)10060; ZVBB-RV32-NEXT:    vl8re16.v v8, (a6)10061; ZVBB-RV32-NEXT:    addi sp, s0, -8010062; ZVBB-RV32-NEXT:    lw ra, 76(sp) # 4-byte Folded Reload10063; ZVBB-RV32-NEXT:    lw s0, 72(sp) # 4-byte Folded Reload10064; ZVBB-RV32-NEXT:    addi sp, sp, 8010065; ZVBB-RV32-NEXT:    ret10066;10067; ZVBB-RV64-LABEL: vector_interleave_nxv48f16_nxv8f16:10068; ZVBB-RV64:       # %bb.0:10069; ZVBB-RV64-NEXT:    addi sp, sp, -8010070; ZVBB-RV64-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill10071; ZVBB-RV64-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill10072; ZVBB-RV64-NEXT:    addi s0, sp, 8010073; ZVBB-RV64-NEXT:    csrr a0, vlenb10074; ZVBB-RV64-NEXT:    li a1, 2810075; ZVBB-RV64-NEXT:    mul a0, a0, a110076; ZVBB-RV64-NEXT:    sub sp, sp, a010077; ZVBB-RV64-NEXT:    andi sp, sp, -6410078; ZVBB-RV64-NEXT:    vsetvli a0, zero, e16, m1, ta, ma10079; ZVBB-RV64-NEXT:    vmv2r.v v20, v1410080; ZVBB-RV64-NEXT:    vmv2r.v v22, v1210081; ZVBB-RV64-NEXT:    vmv2r.v v24, v1010082; ZVBB-RV64-NEXT:    csrr a1, vlenb10083; ZVBB-RV64-NEXT:    li a0, 610084; ZVBB-RV64-NEXT:    mul a1, a1, a010085; ZVBB-RV64-NEXT:    add a1, sp, a110086; ZVBB-RV64-NEXT:    addi a1, a1, 6410087; ZVBB-RV64-NEXT:    vmv1r.v v10, v2510088; ZVBB-RV64-NEXT:    vmv1r.v v11, v2310089; ZVBB-RV64-NEXT:    vmv1r.v v12, v2110090; ZVBB-RV64-NEXT:    addi a0, sp, 6410091; ZVBB-RV64-NEXT:    vmv1r.v v13, v1710092; ZVBB-RV64-NEXT:    csrr a2, vlenb10093; ZVBB-RV64-NEXT:    vmv1r.v v14, v1910094; ZVBB-RV64-NEXT:    vsseg6e16.v v9, (a1)10095; ZVBB-RV64-NEXT:    vmv1r.v v9, v2410096; ZVBB-RV64-NEXT:    add a5, a1, a210097; ZVBB-RV64-NEXT:    vmv1r.v v10, v2210098; ZVBB-RV64-NEXT:    add a3, a0, a210099; ZVBB-RV64-NEXT:    vmv1r.v v11, v2010100; ZVBB-RV64-NEXT:    add a4, a3, a210101; ZVBB-RV64-NEXT:    vmv1r.v v12, v1610102; ZVBB-RV64-NEXT:    add a6, a5, a210103; ZVBB-RV64-NEXT:    vmv1r.v v13, v1810104; ZVBB-RV64-NEXT:    vsseg6e16.v v8, (a0)10105; ZVBB-RV64-NEXT:    vl1re16.v v14, (a1)10106; ZVBB-RV64-NEXT:    add a1, a6, a210107; ZVBB-RV64-NEXT:    vl1re16.v v15, (a5)10108; ZVBB-RV64-NEXT:    add a5, a1, a210109; ZVBB-RV64-NEXT:    vl1re16.v v18, (a5)10110; ZVBB-RV64-NEXT:    add a5, a5, a210111; ZVBB-RV64-NEXT:    vl1re16.v v19, (a5)10112; ZVBB-RV64-NEXT:    add a5, a4, a210113; ZVBB-RV64-NEXT:    vl1re16.v v16, (a6)10114; ZVBB-RV64-NEXT:    add a6, a5, a210115; ZVBB-RV64-NEXT:    vl1re16.v v12, (a6)10116; ZVBB-RV64-NEXT:    add a6, a6, a210117; ZVBB-RV64-NEXT:    vl1re16.v v13, (a6)10118; ZVBB-RV64-NEXT:    csrr a6, vlenb10119; ZVBB-RV64-NEXT:    li a7, 1210120; ZVBB-RV64-NEXT:    mul a6, a6, a710121; ZVBB-RV64-NEXT:    add a6, sp, a610122; ZVBB-RV64-NEXT:    addi a6, a6, 6410123; ZVBB-RV64-NEXT:    vl1re16.v v17, (a1)10124; ZVBB-RV64-NEXT:    vl1re16.v v10, (a4)10125; ZVBB-RV64-NEXT:    vl1re16.v v11, (a5)10126; ZVBB-RV64-NEXT:    vl1re16.v v8, (a0)10127; ZVBB-RV64-NEXT:    vl1re16.v v9, (a3)10128; ZVBB-RV64-NEXT:    slli a2, a2, 310129; ZVBB-RV64-NEXT:    add a2, a6, a210130; ZVBB-RV64-NEXT:    vs4r.v v16, (a2)10131; ZVBB-RV64-NEXT:    vs8r.v v8, (a6)10132; ZVBB-RV64-NEXT:    vl8re16.v v16, (a2)10133; ZVBB-RV64-NEXT:    vl8re16.v v8, (a6)10134; ZVBB-RV64-NEXT:    addi sp, s0, -8010135; ZVBB-RV64-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload10136; ZVBB-RV64-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload10137; ZVBB-RV64-NEXT:    addi sp, sp, 8010138; ZVBB-RV64-NEXT:    ret10139;10140; ZIP-LABEL: vector_interleave_nxv48f16_nxv8f16:10141; ZIP:       # %bb.0:10142; ZIP-NEXT:    addi sp, sp, -8010143; ZIP-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill10144; ZIP-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill10145; ZIP-NEXT:    addi s0, sp, 8010146; ZIP-NEXT:    csrr a0, vlenb10147; ZIP-NEXT:    li a1, 2810148; ZIP-NEXT:    mul a0, a0, a110149; ZIP-NEXT:    sub sp, sp, a010150; ZIP-NEXT:    andi sp, sp, -6410151; ZIP-NEXT:    vsetvli a0, zero, e16, m1, ta, ma10152; ZIP-NEXT:    vmv2r.v v20, v1410153; ZIP-NEXT:    vmv2r.v v22, v1210154; ZIP-NEXT:    vmv2r.v v24, v1010155; ZIP-NEXT:    csrr a1, vlenb10156; ZIP-NEXT:    li a0, 610157; ZIP-NEXT:    mul a1, a1, a010158; ZIP-NEXT:    add a1, sp, a110159; ZIP-NEXT:    addi a1, a1, 6410160; ZIP-NEXT:    vmv1r.v v10, v2510161; ZIP-NEXT:    vmv1r.v v11, v2310162; ZIP-NEXT:    vmv1r.v v12, v2110163; ZIP-NEXT:    addi a0, sp, 6410164; ZIP-NEXT:    vmv1r.v v13, v1710165; ZIP-NEXT:    csrr a2, vlenb10166; ZIP-NEXT:    vmv1r.v v14, v1910167; ZIP-NEXT:    vsseg6e16.v v9, (a1)10168; ZIP-NEXT:    vmv1r.v v9, v2410169; ZIP-NEXT:    add a5, a1, a210170; ZIP-NEXT:    vmv1r.v v10, v2210171; ZIP-NEXT:    add a3, a0, a210172; ZIP-NEXT:    vmv1r.v v11, v2010173; ZIP-NEXT:    add a4, a3, a210174; ZIP-NEXT:    vmv1r.v v12, v1610175; ZIP-NEXT:    add a6, a5, a210176; ZIP-NEXT:    vmv1r.v v13, v1810177; ZIP-NEXT:    vsseg6e16.v v8, (a0)10178; ZIP-NEXT:    vl1re16.v v14, (a1)10179; ZIP-NEXT:    add a1, a6, a210180; ZIP-NEXT:    vl1re16.v v15, (a5)10181; ZIP-NEXT:    add a5, a1, a210182; ZIP-NEXT:    vl1re16.v v18, (a5)10183; ZIP-NEXT:    add a5, a5, a210184; ZIP-NEXT:    vl1re16.v v19, (a5)10185; ZIP-NEXT:    add a5, a4, a210186; ZIP-NEXT:    vl1re16.v v16, (a6)10187; ZIP-NEXT:    add a6, a5, a210188; ZIP-NEXT:    vl1re16.v v12, (a6)10189; ZIP-NEXT:    add a6, a6, a210190; ZIP-NEXT:    vl1re16.v v13, (a6)10191; ZIP-NEXT:    csrr a6, vlenb10192; ZIP-NEXT:    li a7, 1210193; ZIP-NEXT:    mul a6, a6, a710194; ZIP-NEXT:    add a6, sp, a610195; ZIP-NEXT:    addi a6, a6, 6410196; ZIP-NEXT:    vl1re16.v v17, (a1)10197; ZIP-NEXT:    vl1re16.v v10, (a4)10198; ZIP-NEXT:    vl1re16.v v11, (a5)10199; ZIP-NEXT:    vl1re16.v v8, (a0)10200; ZIP-NEXT:    vl1re16.v v9, (a3)10201; ZIP-NEXT:    slli a2, a2, 310202; ZIP-NEXT:    add a2, a6, a210203; ZIP-NEXT:    vs4r.v v16, (a2)10204; ZIP-NEXT:    vs8r.v v8, (a6)10205; ZIP-NEXT:    vl8re16.v v16, (a2)10206; ZIP-NEXT:    vl8re16.v v8, (a6)10207; ZIP-NEXT:    addi sp, s0, -8010208; ZIP-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload10209; ZIP-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload10210; ZIP-NEXT:    addi sp, sp, 8010211; ZIP-NEXT:    ret10212  %res = call <vscale x 48 x half> @llvm.vector.interleave6.nxv48f16(<vscale x 8 x half> %v0, <vscale x 8 x half> %v1, <vscale x 8 x half> %v2, <vscale x 8 x half> %v3, <vscale x 8 x half> %v4, <vscale x 8 x half> %v5)10213  ret <vscale x 48 x half> %res10214}10215 10216define <vscale x 12 x bfloat> @vector_interleave_nxv12bf16_nxv2bf16(<vscale x 2 x bfloat> %v0, <vscale x 2 x bfloat> %v1, <vscale x 2 x bfloat> %v2, <vscale x 2 x bfloat> %v3, <vscale x 2 x bfloat> %v4, <vscale x 2 x bfloat> %v5) nounwind {10217; CHECK-LABEL: vector_interleave_nxv12bf16_nxv2bf16:10218; CHECK:       # %bb.0:10219; CHECK-NEXT:    addi sp, sp, -1610220; CHECK-NEXT:    csrr a0, vlenb10221; CHECK-NEXT:    slli a1, a0, 110222; CHECK-NEXT:    add a0, a1, a010223; CHECK-NEXT:    sub sp, sp, a010224; CHECK-NEXT:    addi a0, sp, 1610225; CHECK-NEXT:    csrr a1, vlenb10226; CHECK-NEXT:    srli a2, a1, 110227; CHECK-NEXT:    add a3, a0, a210228; CHECK-NEXT:    add a4, a3, a210229; CHECK-NEXT:    add a5, a4, a210230; CHECK-NEXT:    vsetvli a6, zero, e16, mf2, ta, ma10231; CHECK-NEXT:    vsseg6e16.v v8, (a0)10232; CHECK-NEXT:    add a6, a5, a210233; CHECK-NEXT:    add a2, a6, a210234; CHECK-NEXT:    vle16.v v10, (a6)10235; CHECK-NEXT:    vle16.v v8, (a2)10236; CHECK-NEXT:    srli a1, a1, 210237; CHECK-NEXT:    vle16.v v11, (a5)10238; CHECK-NEXT:    vsetvli a2, zero, e16, m1, ta, ma10239; CHECK-NEXT:    vslideup.vx v10, v8, a110240; CHECK-NEXT:    vsetvli a2, zero, e16, mf2, ta, ma10241; CHECK-NEXT:    vle16.v v9, (a4)10242; CHECK-NEXT:    vsetvli a2, zero, e16, m1, ta, ma10243; CHECK-NEXT:    vslideup.vx v9, v11, a110244; CHECK-NEXT:    vsetvli a2, zero, e16, mf2, ta, ma10245; CHECK-NEXT:    vle16.v v11, (a3)10246; CHECK-NEXT:    vle16.v v8, (a0)10247; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma10248; CHECK-NEXT:    vslideup.vx v8, v11, a110249; CHECK-NEXT:    csrr a0, vlenb10250; CHECK-NEXT:    slli a1, a0, 110251; CHECK-NEXT:    add a0, a1, a010252; CHECK-NEXT:    add sp, sp, a010253; CHECK-NEXT:    addi sp, sp, 1610254; CHECK-NEXT:    ret10255;10256; ZVBB-LABEL: vector_interleave_nxv12bf16_nxv2bf16:10257; ZVBB:       # %bb.0:10258; ZVBB-NEXT:    addi sp, sp, -1610259; ZVBB-NEXT:    csrr a0, vlenb10260; ZVBB-NEXT:    slli a1, a0, 110261; ZVBB-NEXT:    add a0, a1, a010262; ZVBB-NEXT:    sub sp, sp, a010263; ZVBB-NEXT:    addi a0, sp, 1610264; ZVBB-NEXT:    csrr a1, vlenb10265; ZVBB-NEXT:    srli a2, a1, 110266; ZVBB-NEXT:    add a3, a0, a210267; ZVBB-NEXT:    add a4, a3, a210268; ZVBB-NEXT:    add a5, a4, a210269; ZVBB-NEXT:    vsetvli a6, zero, e16, mf2, ta, ma10270; ZVBB-NEXT:    vsseg6e16.v v8, (a0)10271; ZVBB-NEXT:    add a6, a5, a210272; ZVBB-NEXT:    add a2, a6, a210273; ZVBB-NEXT:    vle16.v v10, (a6)10274; ZVBB-NEXT:    vle16.v v8, (a2)10275; ZVBB-NEXT:    srli a1, a1, 210276; ZVBB-NEXT:    vle16.v v11, (a5)10277; ZVBB-NEXT:    vsetvli a2, zero, e16, m1, ta, ma10278; ZVBB-NEXT:    vslideup.vx v10, v8, a110279; ZVBB-NEXT:    vsetvli a2, zero, e16, mf2, ta, ma10280; ZVBB-NEXT:    vle16.v v9, (a4)10281; ZVBB-NEXT:    vsetvli a2, zero, e16, m1, ta, ma10282; ZVBB-NEXT:    vslideup.vx v9, v11, a110283; ZVBB-NEXT:    vsetvli a2, zero, e16, mf2, ta, ma10284; ZVBB-NEXT:    vle16.v v11, (a3)10285; ZVBB-NEXT:    vle16.v v8, (a0)10286; ZVBB-NEXT:    vsetvli a0, zero, e16, m1, ta, ma10287; ZVBB-NEXT:    vslideup.vx v8, v11, a110288; ZVBB-NEXT:    csrr a0, vlenb10289; ZVBB-NEXT:    slli a1, a0, 110290; ZVBB-NEXT:    add a0, a1, a010291; ZVBB-NEXT:    add sp, sp, a010292; ZVBB-NEXT:    addi sp, sp, 1610293; ZVBB-NEXT:    ret10294  %res = call <vscale x 12 x bfloat> @llvm.vector.interleave6.nxv12bf16(<vscale x 2 x bfloat> %v0, <vscale x 2 x bfloat> %v1, <vscale x 2 x bfloat> %v2, <vscale x 2 x bfloat> %v3, <vscale x 2 x bfloat> %v4, <vscale x 2 x bfloat> %v5)10295  ret <vscale x 12 x bfloat> %res10296}10297 10298define <vscale x 24 x bfloat> @vector_interleave_nxv24bf16_nxv4bf16(<vscale x 4 x bfloat> %v0, <vscale x 4 x bfloat> %v1, <vscale x 4 x bfloat> %v2, <vscale x 4 x bfloat> %v3, <vscale x 4 x bfloat> %v4, <vscale x 4 x bfloat> %v5) nounwind {10299; CHECK-LABEL: vector_interleave_nxv24bf16_nxv4bf16:10300; CHECK:       # %bb.0:10301; CHECK-NEXT:    addi sp, sp, -1610302; CHECK-NEXT:    csrr a0, vlenb10303; CHECK-NEXT:    li a1, 610304; CHECK-NEXT:    mul a0, a0, a110305; CHECK-NEXT:    sub sp, sp, a010306; CHECK-NEXT:    addi a0, sp, 1610307; CHECK-NEXT:    csrr a1, vlenb10308; CHECK-NEXT:    add a2, a0, a110309; CHECK-NEXT:    add a3, a2, a110310; CHECK-NEXT:    vsetvli a4, zero, e16, m1, ta, ma10311; CHECK-NEXT:    vsseg6e16.v v8, (a0)10312; CHECK-NEXT:    vl1re16.v v10, (a3)10313; CHECK-NEXT:    add a3, a3, a110314; CHECK-NEXT:    vl1re16.v v11, (a3)10315; CHECK-NEXT:    add a3, a3, a110316; CHECK-NEXT:    vl1re16.v v8, (a0)10317; CHECK-NEXT:    vl1re16.v v9, (a2)10318; CHECK-NEXT:    vl1re16.v v12, (a3)10319; CHECK-NEXT:    add a1, a3, a110320; CHECK-NEXT:    vl1re16.v v13, (a1)10321; CHECK-NEXT:    csrr a0, vlenb10322; CHECK-NEXT:    li a1, 610323; CHECK-NEXT:    mul a0, a0, a110324; CHECK-NEXT:    add sp, sp, a010325; CHECK-NEXT:    addi sp, sp, 1610326; CHECK-NEXT:    ret10327;10328; ZVBB-LABEL: vector_interleave_nxv24bf16_nxv4bf16:10329; ZVBB:       # %bb.0:10330; ZVBB-NEXT:    addi sp, sp, -1610331; ZVBB-NEXT:    csrr a0, vlenb10332; ZVBB-NEXT:    li a1, 610333; ZVBB-NEXT:    mul a0, a0, a110334; ZVBB-NEXT:    sub sp, sp, a010335; ZVBB-NEXT:    addi a0, sp, 1610336; ZVBB-NEXT:    csrr a1, vlenb10337; ZVBB-NEXT:    add a2, a0, a110338; ZVBB-NEXT:    add a3, a2, a110339; ZVBB-NEXT:    vsetvli a4, zero, e16, m1, ta, ma10340; ZVBB-NEXT:    vsseg6e16.v v8, (a0)10341; ZVBB-NEXT:    vl1re16.v v10, (a3)10342; ZVBB-NEXT:    add a3, a3, a110343; ZVBB-NEXT:    vl1re16.v v11, (a3)10344; ZVBB-NEXT:    add a3, a3, a110345; ZVBB-NEXT:    vl1re16.v v8, (a0)10346; ZVBB-NEXT:    vl1re16.v v9, (a2)10347; ZVBB-NEXT:    vl1re16.v v12, (a3)10348; ZVBB-NEXT:    add a1, a3, a110349; ZVBB-NEXT:    vl1re16.v v13, (a1)10350; ZVBB-NEXT:    csrr a0, vlenb10351; ZVBB-NEXT:    li a1, 610352; ZVBB-NEXT:    mul a0, a0, a110353; ZVBB-NEXT:    add sp, sp, a010354; ZVBB-NEXT:    addi sp, sp, 1610355; ZVBB-NEXT:    ret10356  %res = call <vscale x 24 x bfloat> @llvm.vector.interleave6.nxv24bf16(<vscale x 4 x bfloat> %v0, <vscale x 4 x bfloat> %v1, <vscale x 4 x bfloat> %v2, <vscale x 4 x bfloat> %v3, <vscale x 4 x bfloat> %v4, <vscale x 4 x bfloat> %v5)10357  ret <vscale x 24 x bfloat> %res10358}10359 10360define <vscale x 48 x bfloat> @vector_interleave_nxv48bf16_nxv8bf16(<vscale x 8 x bfloat> %v0, <vscale x 8 x bfloat> %v1, <vscale x 8 x bfloat> %v2, <vscale x 8 x bfloat> %v3, <vscale x 8 x bfloat> %v4, <vscale x 8 x bfloat> %v5) nounwind {10361; RV32-LABEL: vector_interleave_nxv48bf16_nxv8bf16:10362; RV32:       # %bb.0:10363; RV32-NEXT:    addi sp, sp, -8010364; RV32-NEXT:    sw ra, 76(sp) # 4-byte Folded Spill10365; RV32-NEXT:    sw s0, 72(sp) # 4-byte Folded Spill10366; RV32-NEXT:    addi s0, sp, 8010367; RV32-NEXT:    csrr a0, vlenb10368; RV32-NEXT:    li a1, 2810369; RV32-NEXT:    mul a0, a0, a110370; RV32-NEXT:    sub sp, sp, a010371; RV32-NEXT:    andi sp, sp, -6410372; RV32-NEXT:    vsetvli a0, zero, e16, m1, ta, ma10373; RV32-NEXT:    vmv2r.v v20, v1410374; RV32-NEXT:    vmv2r.v v22, v1210375; RV32-NEXT:    vmv2r.v v24, v1010376; RV32-NEXT:    csrr a1, vlenb10377; RV32-NEXT:    li a0, 610378; RV32-NEXT:    mul a1, a1, a010379; RV32-NEXT:    add a1, sp, a110380; RV32-NEXT:    addi a1, a1, 6410381; RV32-NEXT:    vmv1r.v v10, v2510382; RV32-NEXT:    vmv1r.v v11, v2310383; RV32-NEXT:    vmv1r.v v12, v2110384; RV32-NEXT:    addi a0, sp, 6410385; RV32-NEXT:    vmv1r.v v13, v1710386; RV32-NEXT:    csrr a2, vlenb10387; RV32-NEXT:    vmv1r.v v14, v1910388; RV32-NEXT:    vsseg6e16.v v9, (a1)10389; RV32-NEXT:    vmv1r.v v9, v2410390; RV32-NEXT:    add a5, a1, a210391; RV32-NEXT:    vmv1r.v v10, v2210392; RV32-NEXT:    add a3, a0, a210393; RV32-NEXT:    vmv1r.v v11, v2010394; RV32-NEXT:    add a4, a3, a210395; RV32-NEXT:    vmv1r.v v12, v1610396; RV32-NEXT:    add a6, a5, a210397; RV32-NEXT:    vmv1r.v v13, v1810398; RV32-NEXT:    vsseg6e16.v v8, (a0)10399; RV32-NEXT:    vl1re16.v v14, (a1)10400; RV32-NEXT:    add a1, a6, a210401; RV32-NEXT:    vl1re16.v v15, (a5)10402; RV32-NEXT:    add a5, a1, a210403; RV32-NEXT:    vl1re16.v v18, (a5)10404; RV32-NEXT:    add a5, a5, a210405; RV32-NEXT:    vl1re16.v v19, (a5)10406; RV32-NEXT:    add a5, a4, a210407; RV32-NEXT:    vl1re16.v v16, (a6)10408; RV32-NEXT:    add a6, a5, a210409; RV32-NEXT:    vl1re16.v v12, (a6)10410; RV32-NEXT:    add a6, a6, a210411; RV32-NEXT:    vl1re16.v v13, (a6)10412; RV32-NEXT:    csrr a6, vlenb10413; RV32-NEXT:    li a7, 1210414; RV32-NEXT:    mul a6, a6, a710415; RV32-NEXT:    add a6, sp, a610416; RV32-NEXT:    addi a6, a6, 6410417; RV32-NEXT:    vl1re16.v v17, (a1)10418; RV32-NEXT:    vl1re16.v v10, (a4)10419; RV32-NEXT:    vl1re16.v v11, (a5)10420; RV32-NEXT:    vl1re16.v v8, (a0)10421; RV32-NEXT:    vl1re16.v v9, (a3)10422; RV32-NEXT:    slli a2, a2, 310423; RV32-NEXT:    add a2, a6, a210424; RV32-NEXT:    vs4r.v v16, (a2)10425; RV32-NEXT:    vs8r.v v8, (a6)10426; RV32-NEXT:    vl8re16.v v16, (a2)10427; RV32-NEXT:    vl8re16.v v8, (a6)10428; RV32-NEXT:    addi sp, s0, -8010429; RV32-NEXT:    lw ra, 76(sp) # 4-byte Folded Reload10430; RV32-NEXT:    lw s0, 72(sp) # 4-byte Folded Reload10431; RV32-NEXT:    addi sp, sp, 8010432; RV32-NEXT:    ret10433;10434; RV64-LABEL: vector_interleave_nxv48bf16_nxv8bf16:10435; RV64:       # %bb.0:10436; RV64-NEXT:    addi sp, sp, -8010437; RV64-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill10438; RV64-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill10439; RV64-NEXT:    addi s0, sp, 8010440; RV64-NEXT:    csrr a0, vlenb10441; RV64-NEXT:    li a1, 2810442; RV64-NEXT:    mul a0, a0, a110443; RV64-NEXT:    sub sp, sp, a010444; RV64-NEXT:    andi sp, sp, -6410445; RV64-NEXT:    vsetvli a0, zero, e16, m1, ta, ma10446; RV64-NEXT:    vmv2r.v v20, v1410447; RV64-NEXT:    vmv2r.v v22, v1210448; RV64-NEXT:    vmv2r.v v24, v1010449; RV64-NEXT:    csrr a1, vlenb10450; RV64-NEXT:    li a0, 610451; RV64-NEXT:    mul a1, a1, a010452; RV64-NEXT:    add a1, sp, a110453; RV64-NEXT:    addi a1, a1, 6410454; RV64-NEXT:    vmv1r.v v10, v2510455; RV64-NEXT:    vmv1r.v v11, v2310456; RV64-NEXT:    vmv1r.v v12, v2110457; RV64-NEXT:    addi a0, sp, 6410458; RV64-NEXT:    vmv1r.v v13, v1710459; RV64-NEXT:    csrr a2, vlenb10460; RV64-NEXT:    vmv1r.v v14, v1910461; RV64-NEXT:    vsseg6e16.v v9, (a1)10462; RV64-NEXT:    vmv1r.v v9, v2410463; RV64-NEXT:    add a5, a1, a210464; RV64-NEXT:    vmv1r.v v10, v2210465; RV64-NEXT:    add a3, a0, a210466; RV64-NEXT:    vmv1r.v v11, v2010467; RV64-NEXT:    add a4, a3, a210468; RV64-NEXT:    vmv1r.v v12, v1610469; RV64-NEXT:    add a6, a5, a210470; RV64-NEXT:    vmv1r.v v13, v1810471; RV64-NEXT:    vsseg6e16.v v8, (a0)10472; RV64-NEXT:    vl1re16.v v14, (a1)10473; RV64-NEXT:    add a1, a6, a210474; RV64-NEXT:    vl1re16.v v15, (a5)10475; RV64-NEXT:    add a5, a1, a210476; RV64-NEXT:    vl1re16.v v18, (a5)10477; RV64-NEXT:    add a5, a5, a210478; RV64-NEXT:    vl1re16.v v19, (a5)10479; RV64-NEXT:    add a5, a4, a210480; RV64-NEXT:    vl1re16.v v16, (a6)10481; RV64-NEXT:    add a6, a5, a210482; RV64-NEXT:    vl1re16.v v12, (a6)10483; RV64-NEXT:    add a6, a6, a210484; RV64-NEXT:    vl1re16.v v13, (a6)10485; RV64-NEXT:    csrr a6, vlenb10486; RV64-NEXT:    li a7, 1210487; RV64-NEXT:    mul a6, a6, a710488; RV64-NEXT:    add a6, sp, a610489; RV64-NEXT:    addi a6, a6, 6410490; RV64-NEXT:    vl1re16.v v17, (a1)10491; RV64-NEXT:    vl1re16.v v10, (a4)10492; RV64-NEXT:    vl1re16.v v11, (a5)10493; RV64-NEXT:    vl1re16.v v8, (a0)10494; RV64-NEXT:    vl1re16.v v9, (a3)10495; RV64-NEXT:    slli a2, a2, 310496; RV64-NEXT:    add a2, a6, a210497; RV64-NEXT:    vs4r.v v16, (a2)10498; RV64-NEXT:    vs8r.v v8, (a6)10499; RV64-NEXT:    vl8re16.v v16, (a2)10500; RV64-NEXT:    vl8re16.v v8, (a6)10501; RV64-NEXT:    addi sp, s0, -8010502; RV64-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload10503; RV64-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload10504; RV64-NEXT:    addi sp, sp, 8010505; RV64-NEXT:    ret10506;10507; ZVBB-RV32-LABEL: vector_interleave_nxv48bf16_nxv8bf16:10508; ZVBB-RV32:       # %bb.0:10509; ZVBB-RV32-NEXT:    addi sp, sp, -8010510; ZVBB-RV32-NEXT:    sw ra, 76(sp) # 4-byte Folded Spill10511; ZVBB-RV32-NEXT:    sw s0, 72(sp) # 4-byte Folded Spill10512; ZVBB-RV32-NEXT:    addi s0, sp, 8010513; ZVBB-RV32-NEXT:    csrr a0, vlenb10514; ZVBB-RV32-NEXT:    li a1, 2810515; ZVBB-RV32-NEXT:    mul a0, a0, a110516; ZVBB-RV32-NEXT:    sub sp, sp, a010517; ZVBB-RV32-NEXT:    andi sp, sp, -6410518; ZVBB-RV32-NEXT:    vsetvli a0, zero, e16, m1, ta, ma10519; ZVBB-RV32-NEXT:    vmv2r.v v20, v1410520; ZVBB-RV32-NEXT:    vmv2r.v v22, v1210521; ZVBB-RV32-NEXT:    vmv2r.v v24, v1010522; ZVBB-RV32-NEXT:    csrr a1, vlenb10523; ZVBB-RV32-NEXT:    li a0, 610524; ZVBB-RV32-NEXT:    mul a1, a1, a010525; ZVBB-RV32-NEXT:    add a1, sp, a110526; ZVBB-RV32-NEXT:    addi a1, a1, 6410527; ZVBB-RV32-NEXT:    vmv1r.v v10, v2510528; ZVBB-RV32-NEXT:    vmv1r.v v11, v2310529; ZVBB-RV32-NEXT:    vmv1r.v v12, v2110530; ZVBB-RV32-NEXT:    addi a0, sp, 6410531; ZVBB-RV32-NEXT:    vmv1r.v v13, v1710532; ZVBB-RV32-NEXT:    csrr a2, vlenb10533; ZVBB-RV32-NEXT:    vmv1r.v v14, v1910534; ZVBB-RV32-NEXT:    vsseg6e16.v v9, (a1)10535; ZVBB-RV32-NEXT:    vmv1r.v v9, v2410536; ZVBB-RV32-NEXT:    add a5, a1, a210537; ZVBB-RV32-NEXT:    vmv1r.v v10, v2210538; ZVBB-RV32-NEXT:    add a3, a0, a210539; ZVBB-RV32-NEXT:    vmv1r.v v11, v2010540; ZVBB-RV32-NEXT:    add a4, a3, a210541; ZVBB-RV32-NEXT:    vmv1r.v v12, v1610542; ZVBB-RV32-NEXT:    add a6, a5, a210543; ZVBB-RV32-NEXT:    vmv1r.v v13, v1810544; ZVBB-RV32-NEXT:    vsseg6e16.v v8, (a0)10545; ZVBB-RV32-NEXT:    vl1re16.v v14, (a1)10546; ZVBB-RV32-NEXT:    add a1, a6, a210547; ZVBB-RV32-NEXT:    vl1re16.v v15, (a5)10548; ZVBB-RV32-NEXT:    add a5, a1, a210549; ZVBB-RV32-NEXT:    vl1re16.v v18, (a5)10550; ZVBB-RV32-NEXT:    add a5, a5, a210551; ZVBB-RV32-NEXT:    vl1re16.v v19, (a5)10552; ZVBB-RV32-NEXT:    add a5, a4, a210553; ZVBB-RV32-NEXT:    vl1re16.v v16, (a6)10554; ZVBB-RV32-NEXT:    add a6, a5, a210555; ZVBB-RV32-NEXT:    vl1re16.v v12, (a6)10556; ZVBB-RV32-NEXT:    add a6, a6, a210557; ZVBB-RV32-NEXT:    vl1re16.v v13, (a6)10558; ZVBB-RV32-NEXT:    csrr a6, vlenb10559; ZVBB-RV32-NEXT:    li a7, 1210560; ZVBB-RV32-NEXT:    mul a6, a6, a710561; ZVBB-RV32-NEXT:    add a6, sp, a610562; ZVBB-RV32-NEXT:    addi a6, a6, 6410563; ZVBB-RV32-NEXT:    vl1re16.v v17, (a1)10564; ZVBB-RV32-NEXT:    vl1re16.v v10, (a4)10565; ZVBB-RV32-NEXT:    vl1re16.v v11, (a5)10566; ZVBB-RV32-NEXT:    vl1re16.v v8, (a0)10567; ZVBB-RV32-NEXT:    vl1re16.v v9, (a3)10568; ZVBB-RV32-NEXT:    slli a2, a2, 310569; ZVBB-RV32-NEXT:    add a2, a6, a210570; ZVBB-RV32-NEXT:    vs4r.v v16, (a2)10571; ZVBB-RV32-NEXT:    vs8r.v v8, (a6)10572; ZVBB-RV32-NEXT:    vl8re16.v v16, (a2)10573; ZVBB-RV32-NEXT:    vl8re16.v v8, (a6)10574; ZVBB-RV32-NEXT:    addi sp, s0, -8010575; ZVBB-RV32-NEXT:    lw ra, 76(sp) # 4-byte Folded Reload10576; ZVBB-RV32-NEXT:    lw s0, 72(sp) # 4-byte Folded Reload10577; ZVBB-RV32-NEXT:    addi sp, sp, 8010578; ZVBB-RV32-NEXT:    ret10579;10580; ZVBB-RV64-LABEL: vector_interleave_nxv48bf16_nxv8bf16:10581; ZVBB-RV64:       # %bb.0:10582; ZVBB-RV64-NEXT:    addi sp, sp, -8010583; ZVBB-RV64-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill10584; ZVBB-RV64-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill10585; ZVBB-RV64-NEXT:    addi s0, sp, 8010586; ZVBB-RV64-NEXT:    csrr a0, vlenb10587; ZVBB-RV64-NEXT:    li a1, 2810588; ZVBB-RV64-NEXT:    mul a0, a0, a110589; ZVBB-RV64-NEXT:    sub sp, sp, a010590; ZVBB-RV64-NEXT:    andi sp, sp, -6410591; ZVBB-RV64-NEXT:    vsetvli a0, zero, e16, m1, ta, ma10592; ZVBB-RV64-NEXT:    vmv2r.v v20, v1410593; ZVBB-RV64-NEXT:    vmv2r.v v22, v1210594; ZVBB-RV64-NEXT:    vmv2r.v v24, v1010595; ZVBB-RV64-NEXT:    csrr a1, vlenb10596; ZVBB-RV64-NEXT:    li a0, 610597; ZVBB-RV64-NEXT:    mul a1, a1, a010598; ZVBB-RV64-NEXT:    add a1, sp, a110599; ZVBB-RV64-NEXT:    addi a1, a1, 6410600; ZVBB-RV64-NEXT:    vmv1r.v v10, v2510601; ZVBB-RV64-NEXT:    vmv1r.v v11, v2310602; ZVBB-RV64-NEXT:    vmv1r.v v12, v2110603; ZVBB-RV64-NEXT:    addi a0, sp, 6410604; ZVBB-RV64-NEXT:    vmv1r.v v13, v1710605; ZVBB-RV64-NEXT:    csrr a2, vlenb10606; ZVBB-RV64-NEXT:    vmv1r.v v14, v1910607; ZVBB-RV64-NEXT:    vsseg6e16.v v9, (a1)10608; ZVBB-RV64-NEXT:    vmv1r.v v9, v2410609; ZVBB-RV64-NEXT:    add a5, a1, a210610; ZVBB-RV64-NEXT:    vmv1r.v v10, v2210611; ZVBB-RV64-NEXT:    add a3, a0, a210612; ZVBB-RV64-NEXT:    vmv1r.v v11, v2010613; ZVBB-RV64-NEXT:    add a4, a3, a210614; ZVBB-RV64-NEXT:    vmv1r.v v12, v1610615; ZVBB-RV64-NEXT:    add a6, a5, a210616; ZVBB-RV64-NEXT:    vmv1r.v v13, v1810617; ZVBB-RV64-NEXT:    vsseg6e16.v v8, (a0)10618; ZVBB-RV64-NEXT:    vl1re16.v v14, (a1)10619; ZVBB-RV64-NEXT:    add a1, a6, a210620; ZVBB-RV64-NEXT:    vl1re16.v v15, (a5)10621; ZVBB-RV64-NEXT:    add a5, a1, a210622; ZVBB-RV64-NEXT:    vl1re16.v v18, (a5)10623; ZVBB-RV64-NEXT:    add a5, a5, a210624; ZVBB-RV64-NEXT:    vl1re16.v v19, (a5)10625; ZVBB-RV64-NEXT:    add a5, a4, a210626; ZVBB-RV64-NEXT:    vl1re16.v v16, (a6)10627; ZVBB-RV64-NEXT:    add a6, a5, a210628; ZVBB-RV64-NEXT:    vl1re16.v v12, (a6)10629; ZVBB-RV64-NEXT:    add a6, a6, a210630; ZVBB-RV64-NEXT:    vl1re16.v v13, (a6)10631; ZVBB-RV64-NEXT:    csrr a6, vlenb10632; ZVBB-RV64-NEXT:    li a7, 1210633; ZVBB-RV64-NEXT:    mul a6, a6, a710634; ZVBB-RV64-NEXT:    add a6, sp, a610635; ZVBB-RV64-NEXT:    addi a6, a6, 6410636; ZVBB-RV64-NEXT:    vl1re16.v v17, (a1)10637; ZVBB-RV64-NEXT:    vl1re16.v v10, (a4)10638; ZVBB-RV64-NEXT:    vl1re16.v v11, (a5)10639; ZVBB-RV64-NEXT:    vl1re16.v v8, (a0)10640; ZVBB-RV64-NEXT:    vl1re16.v v9, (a3)10641; ZVBB-RV64-NEXT:    slli a2, a2, 310642; ZVBB-RV64-NEXT:    add a2, a6, a210643; ZVBB-RV64-NEXT:    vs4r.v v16, (a2)10644; ZVBB-RV64-NEXT:    vs8r.v v8, (a6)10645; ZVBB-RV64-NEXT:    vl8re16.v v16, (a2)10646; ZVBB-RV64-NEXT:    vl8re16.v v8, (a6)10647; ZVBB-RV64-NEXT:    addi sp, s0, -8010648; ZVBB-RV64-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload10649; ZVBB-RV64-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload10650; ZVBB-RV64-NEXT:    addi sp, sp, 8010651; ZVBB-RV64-NEXT:    ret10652;10653; ZIP-LABEL: vector_interleave_nxv48bf16_nxv8bf16:10654; ZIP:       # %bb.0:10655; ZIP-NEXT:    addi sp, sp, -8010656; ZIP-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill10657; ZIP-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill10658; ZIP-NEXT:    addi s0, sp, 8010659; ZIP-NEXT:    csrr a0, vlenb10660; ZIP-NEXT:    li a1, 2810661; ZIP-NEXT:    mul a0, a0, a110662; ZIP-NEXT:    sub sp, sp, a010663; ZIP-NEXT:    andi sp, sp, -6410664; ZIP-NEXT:    vsetvli a0, zero, e16, m1, ta, ma10665; ZIP-NEXT:    vmv2r.v v20, v1410666; ZIP-NEXT:    vmv2r.v v22, v1210667; ZIP-NEXT:    vmv2r.v v24, v1010668; ZIP-NEXT:    csrr a1, vlenb10669; ZIP-NEXT:    li a0, 610670; ZIP-NEXT:    mul a1, a1, a010671; ZIP-NEXT:    add a1, sp, a110672; ZIP-NEXT:    addi a1, a1, 6410673; ZIP-NEXT:    vmv1r.v v10, v2510674; ZIP-NEXT:    vmv1r.v v11, v2310675; ZIP-NEXT:    vmv1r.v v12, v2110676; ZIP-NEXT:    addi a0, sp, 6410677; ZIP-NEXT:    vmv1r.v v13, v1710678; ZIP-NEXT:    csrr a2, vlenb10679; ZIP-NEXT:    vmv1r.v v14, v1910680; ZIP-NEXT:    vsseg6e16.v v9, (a1)10681; ZIP-NEXT:    vmv1r.v v9, v2410682; ZIP-NEXT:    add a5, a1, a210683; ZIP-NEXT:    vmv1r.v v10, v2210684; ZIP-NEXT:    add a3, a0, a210685; ZIP-NEXT:    vmv1r.v v11, v2010686; ZIP-NEXT:    add a4, a3, a210687; ZIP-NEXT:    vmv1r.v v12, v1610688; ZIP-NEXT:    add a6, a5, a210689; ZIP-NEXT:    vmv1r.v v13, v1810690; ZIP-NEXT:    vsseg6e16.v v8, (a0)10691; ZIP-NEXT:    vl1re16.v v14, (a1)10692; ZIP-NEXT:    add a1, a6, a210693; ZIP-NEXT:    vl1re16.v v15, (a5)10694; ZIP-NEXT:    add a5, a1, a210695; ZIP-NEXT:    vl1re16.v v18, (a5)10696; ZIP-NEXT:    add a5, a5, a210697; ZIP-NEXT:    vl1re16.v v19, (a5)10698; ZIP-NEXT:    add a5, a4, a210699; ZIP-NEXT:    vl1re16.v v16, (a6)10700; ZIP-NEXT:    add a6, a5, a210701; ZIP-NEXT:    vl1re16.v v12, (a6)10702; ZIP-NEXT:    add a6, a6, a210703; ZIP-NEXT:    vl1re16.v v13, (a6)10704; ZIP-NEXT:    csrr a6, vlenb10705; ZIP-NEXT:    li a7, 1210706; ZIP-NEXT:    mul a6, a6, a710707; ZIP-NEXT:    add a6, sp, a610708; ZIP-NEXT:    addi a6, a6, 6410709; ZIP-NEXT:    vl1re16.v v17, (a1)10710; ZIP-NEXT:    vl1re16.v v10, (a4)10711; ZIP-NEXT:    vl1re16.v v11, (a5)10712; ZIP-NEXT:    vl1re16.v v8, (a0)10713; ZIP-NEXT:    vl1re16.v v9, (a3)10714; ZIP-NEXT:    slli a2, a2, 310715; ZIP-NEXT:    add a2, a6, a210716; ZIP-NEXT:    vs4r.v v16, (a2)10717; ZIP-NEXT:    vs8r.v v8, (a6)10718; ZIP-NEXT:    vl8re16.v v16, (a2)10719; ZIP-NEXT:    vl8re16.v v8, (a6)10720; ZIP-NEXT:    addi sp, s0, -8010721; ZIP-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload10722; ZIP-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload10723; ZIP-NEXT:    addi sp, sp, 8010724; ZIP-NEXT:    ret10725  %res = call <vscale x 48 x bfloat> @llvm.vector.interleave6.nxv48bf16(<vscale x 8 x bfloat> %v0, <vscale x 8 x bfloat> %v1, <vscale x 8 x bfloat> %v2, <vscale x 8 x bfloat> %v3, <vscale x 8 x bfloat> %v4, <vscale x 8 x bfloat> %v5)10726  ret <vscale x 48 x bfloat> %res10727}10728 10729define <vscale x 6 x float> @vector_interleave_nxv6f32_nxv1f32(<vscale x 1 x float> %v0, <vscale x 1 x float> %v1, <vscale x 1 x float> %v2, <vscale x 1 x float> %v3, <vscale x 1 x float> %v4, <vscale x 1 x float> %v6) nounwind {10730; CHECK-LABEL: vector_interleave_nxv6f32_nxv1f32:10731; CHECK:       # %bb.0:10732; CHECK-NEXT:    addi sp, sp, -1610733; CHECK-NEXT:    csrr a0, vlenb10734; CHECK-NEXT:    slli a1, a0, 110735; CHECK-NEXT:    add a0, a1, a010736; CHECK-NEXT:    sub sp, sp, a010737; CHECK-NEXT:    addi a0, sp, 1610738; CHECK-NEXT:    csrr a1, vlenb10739; CHECK-NEXT:    srli a2, a1, 110740; CHECK-NEXT:    add a3, a0, a210741; CHECK-NEXT:    add a4, a3, a210742; CHECK-NEXT:    add a5, a4, a210743; CHECK-NEXT:    vsetvli a6, zero, e32, mf2, ta, ma10744; CHECK-NEXT:    vsseg6e32.v v8, (a0)10745; CHECK-NEXT:    add a6, a5, a210746; CHECK-NEXT:    add a2, a6, a210747; CHECK-NEXT:    vle32.v v10, (a6)10748; CHECK-NEXT:    vle32.v v8, (a2)10749; CHECK-NEXT:    srli a1, a1, 310750; CHECK-NEXT:    vle32.v v11, (a5)10751; CHECK-NEXT:    vsetvli a2, zero, e32, m1, ta, ma10752; CHECK-NEXT:    vslideup.vx v10, v8, a110753; CHECK-NEXT:    vsetvli a2, zero, e32, mf2, ta, ma10754; CHECK-NEXT:    vle32.v v9, (a4)10755; CHECK-NEXT:    vsetvli a2, zero, e32, m1, ta, ma10756; CHECK-NEXT:    vslideup.vx v9, v11, a110757; CHECK-NEXT:    vsetvli a2, zero, e32, mf2, ta, ma10758; CHECK-NEXT:    vle32.v v11, (a3)10759; CHECK-NEXT:    vle32.v v8, (a0)10760; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma10761; CHECK-NEXT:    vslideup.vx v8, v11, a110762; CHECK-NEXT:    csrr a0, vlenb10763; CHECK-NEXT:    slli a1, a0, 110764; CHECK-NEXT:    add a0, a1, a010765; CHECK-NEXT:    add sp, sp, a010766; CHECK-NEXT:    addi sp, sp, 1610767; CHECK-NEXT:    ret10768;10769; ZVBB-LABEL: vector_interleave_nxv6f32_nxv1f32:10770; ZVBB:       # %bb.0:10771; ZVBB-NEXT:    addi sp, sp, -1610772; ZVBB-NEXT:    csrr a0, vlenb10773; ZVBB-NEXT:    slli a1, a0, 110774; ZVBB-NEXT:    add a0, a1, a010775; ZVBB-NEXT:    sub sp, sp, a010776; ZVBB-NEXT:    addi a0, sp, 1610777; ZVBB-NEXT:    csrr a1, vlenb10778; ZVBB-NEXT:    srli a2, a1, 110779; ZVBB-NEXT:    add a3, a0, a210780; ZVBB-NEXT:    add a4, a3, a210781; ZVBB-NEXT:    add a5, a4, a210782; ZVBB-NEXT:    vsetvli a6, zero, e32, mf2, ta, ma10783; ZVBB-NEXT:    vsseg6e32.v v8, (a0)10784; ZVBB-NEXT:    add a6, a5, a210785; ZVBB-NEXT:    add a2, a6, a210786; ZVBB-NEXT:    vle32.v v10, (a6)10787; ZVBB-NEXT:    vle32.v v8, (a2)10788; ZVBB-NEXT:    srli a1, a1, 310789; ZVBB-NEXT:    vle32.v v11, (a5)10790; ZVBB-NEXT:    vsetvli a2, zero, e32, m1, ta, ma10791; ZVBB-NEXT:    vslideup.vx v10, v8, a110792; ZVBB-NEXT:    vsetvli a2, zero, e32, mf2, ta, ma10793; ZVBB-NEXT:    vle32.v v9, (a4)10794; ZVBB-NEXT:    vsetvli a2, zero, e32, m1, ta, ma10795; ZVBB-NEXT:    vslideup.vx v9, v11, a110796; ZVBB-NEXT:    vsetvli a2, zero, e32, mf2, ta, ma10797; ZVBB-NEXT:    vle32.v v11, (a3)10798; ZVBB-NEXT:    vle32.v v8, (a0)10799; ZVBB-NEXT:    vsetvli a0, zero, e32, m1, ta, ma10800; ZVBB-NEXT:    vslideup.vx v8, v11, a110801; ZVBB-NEXT:    csrr a0, vlenb10802; ZVBB-NEXT:    slli a1, a0, 110803; ZVBB-NEXT:    add a0, a1, a010804; ZVBB-NEXT:    add sp, sp, a010805; ZVBB-NEXT:    addi sp, sp, 1610806; ZVBB-NEXT:    ret10807  %res = call <vscale x 6 x float> @llvm.vector.interleave6.nxv6f32(<vscale x 1 x float> %v0, <vscale x 1 x float> %v1, <vscale x 1 x float> %v2, <vscale x 1 x float> %v3, <vscale x 1 x float> %v4, <vscale x 1 x float> %v6)10808  ret <vscale x 6 x float> %res10809}10810 10811define <vscale x 12 x float> @vector_interleave_nxv12f32_nxv2f32(<vscale x 2 x float> %v0, <vscale x 2 x float> %v1, <vscale x 2 x float> %v2, <vscale x 2 x float> %v3, <vscale x 2 x float> %v4, <vscale x 2 x float> %v5) nounwind {10812; CHECK-LABEL: vector_interleave_nxv12f32_nxv2f32:10813; CHECK:       # %bb.0:10814; CHECK-NEXT:    addi sp, sp, -1610815; CHECK-NEXT:    csrr a0, vlenb10816; CHECK-NEXT:    li a1, 610817; CHECK-NEXT:    mul a0, a0, a110818; CHECK-NEXT:    sub sp, sp, a010819; CHECK-NEXT:    addi a0, sp, 1610820; CHECK-NEXT:    csrr a1, vlenb10821; CHECK-NEXT:    add a2, a0, a110822; CHECK-NEXT:    add a3, a2, a110823; CHECK-NEXT:    vsetvli a4, zero, e32, m1, ta, ma10824; CHECK-NEXT:    vsseg6e32.v v8, (a0)10825; CHECK-NEXT:    vl1re32.v v10, (a3)10826; CHECK-NEXT:    add a3, a3, a110827; CHECK-NEXT:    vl1re32.v v11, (a3)10828; CHECK-NEXT:    add a3, a3, a110829; CHECK-NEXT:    vl1re32.v v8, (a0)10830; CHECK-NEXT:    vl1re32.v v9, (a2)10831; CHECK-NEXT:    vl1re32.v v12, (a3)10832; CHECK-NEXT:    add a1, a3, a110833; CHECK-NEXT:    vl1re32.v v13, (a1)10834; CHECK-NEXT:    csrr a0, vlenb10835; CHECK-NEXT:    li a1, 610836; CHECK-NEXT:    mul a0, a0, a110837; CHECK-NEXT:    add sp, sp, a010838; CHECK-NEXT:    addi sp, sp, 1610839; CHECK-NEXT:    ret10840;10841; ZVBB-LABEL: vector_interleave_nxv12f32_nxv2f32:10842; ZVBB:       # %bb.0:10843; ZVBB-NEXT:    addi sp, sp, -1610844; ZVBB-NEXT:    csrr a0, vlenb10845; ZVBB-NEXT:    li a1, 610846; ZVBB-NEXT:    mul a0, a0, a110847; ZVBB-NEXT:    sub sp, sp, a010848; ZVBB-NEXT:    addi a0, sp, 1610849; ZVBB-NEXT:    csrr a1, vlenb10850; ZVBB-NEXT:    add a2, a0, a110851; ZVBB-NEXT:    add a3, a2, a110852; ZVBB-NEXT:    vsetvli a4, zero, e32, m1, ta, ma10853; ZVBB-NEXT:    vsseg6e32.v v8, (a0)10854; ZVBB-NEXT:    vl1re32.v v10, (a3)10855; ZVBB-NEXT:    add a3, a3, a110856; ZVBB-NEXT:    vl1re32.v v11, (a3)10857; ZVBB-NEXT:    add a3, a3, a110858; ZVBB-NEXT:    vl1re32.v v8, (a0)10859; ZVBB-NEXT:    vl1re32.v v9, (a2)10860; ZVBB-NEXT:    vl1re32.v v12, (a3)10861; ZVBB-NEXT:    add a1, a3, a110862; ZVBB-NEXT:    vl1re32.v v13, (a1)10863; ZVBB-NEXT:    csrr a0, vlenb10864; ZVBB-NEXT:    li a1, 610865; ZVBB-NEXT:    mul a0, a0, a110866; ZVBB-NEXT:    add sp, sp, a010867; ZVBB-NEXT:    addi sp, sp, 1610868; ZVBB-NEXT:    ret10869  %res = call <vscale x 12 x float> @llvm.vector.interleave6.nxv12f32(<vscale x 2 x float> %v0, <vscale x 2 x float> %v1, <vscale x 2 x float> %v2, <vscale x 2 x float> %v3, <vscale x 2 x float> %v4, <vscale x 2 x float> %v5)10870  ret <vscale x 12 x float> %res10871}10872 10873define <vscale x 24 x float> @vector_interleave_nxv24f32_nxv4f32(<vscale x 4 x float> %v0, <vscale x 4 x float> %v1, <vscale x 4 x float> %v2, <vscale x 4 x float> %v3, <vscale x 4 x float> %v4, <vscale x 4 x float> %v5) nounwind {10874; RV32-LABEL: vector_interleave_nxv24f32_nxv4f32:10875; RV32:       # %bb.0:10876; RV32-NEXT:    addi sp, sp, -8010877; RV32-NEXT:    sw ra, 76(sp) # 4-byte Folded Spill10878; RV32-NEXT:    sw s0, 72(sp) # 4-byte Folded Spill10879; RV32-NEXT:    addi s0, sp, 8010880; RV32-NEXT:    csrr a0, vlenb10881; RV32-NEXT:    li a1, 2810882; RV32-NEXT:    mul a0, a0, a110883; RV32-NEXT:    sub sp, sp, a010884; RV32-NEXT:    andi sp, sp, -6410885; RV32-NEXT:    vsetvli a0, zero, e32, m1, ta, ma10886; RV32-NEXT:    vmv2r.v v20, v1410887; RV32-NEXT:    vmv2r.v v22, v1210888; RV32-NEXT:    vmv2r.v v24, v1010889; RV32-NEXT:    csrr a1, vlenb10890; RV32-NEXT:    li a0, 610891; RV32-NEXT:    mul a1, a1, a010892; RV32-NEXT:    add a1, sp, a110893; RV32-NEXT:    addi a1, a1, 6410894; RV32-NEXT:    vmv1r.v v10, v2510895; RV32-NEXT:    vmv1r.v v11, v2310896; RV32-NEXT:    vmv1r.v v12, v2110897; RV32-NEXT:    addi a0, sp, 6410898; RV32-NEXT:    vmv1r.v v13, v1710899; RV32-NEXT:    csrr a2, vlenb10900; RV32-NEXT:    vmv1r.v v14, v1910901; RV32-NEXT:    vsseg6e32.v v9, (a1)10902; RV32-NEXT:    vmv1r.v v9, v2410903; RV32-NEXT:    add a5, a1, a210904; RV32-NEXT:    vmv1r.v v10, v2210905; RV32-NEXT:    add a3, a0, a210906; RV32-NEXT:    vmv1r.v v11, v2010907; RV32-NEXT:    add a4, a3, a210908; RV32-NEXT:    vmv1r.v v12, v1610909; RV32-NEXT:    add a6, a5, a210910; RV32-NEXT:    vmv1r.v v13, v1810911; RV32-NEXT:    vsseg6e32.v v8, (a0)10912; RV32-NEXT:    vl1re32.v v14, (a1)10913; RV32-NEXT:    add a1, a6, a210914; RV32-NEXT:    vl1re32.v v15, (a5)10915; RV32-NEXT:    add a5, a1, a210916; RV32-NEXT:    vl1re32.v v18, (a5)10917; RV32-NEXT:    add a5, a5, a210918; RV32-NEXT:    vl1re32.v v19, (a5)10919; RV32-NEXT:    add a5, a4, a210920; RV32-NEXT:    vl1re32.v v16, (a6)10921; RV32-NEXT:    add a6, a5, a210922; RV32-NEXT:    vl1re32.v v12, (a6)10923; RV32-NEXT:    add a6, a6, a210924; RV32-NEXT:    vl1re32.v v13, (a6)10925; RV32-NEXT:    csrr a6, vlenb10926; RV32-NEXT:    li a7, 1210927; RV32-NEXT:    mul a6, a6, a710928; RV32-NEXT:    add a6, sp, a610929; RV32-NEXT:    addi a6, a6, 6410930; RV32-NEXT:    vl1re32.v v17, (a1)10931; RV32-NEXT:    vl1re32.v v10, (a4)10932; RV32-NEXT:    vl1re32.v v11, (a5)10933; RV32-NEXT:    vl1re32.v v8, (a0)10934; RV32-NEXT:    vl1re32.v v9, (a3)10935; RV32-NEXT:    slli a2, a2, 310936; RV32-NEXT:    add a2, a6, a210937; RV32-NEXT:    vs4r.v v16, (a2)10938; RV32-NEXT:    vs8r.v v8, (a6)10939; RV32-NEXT:    vl8re32.v v16, (a2)10940; RV32-NEXT:    vl8re32.v v8, (a6)10941; RV32-NEXT:    addi sp, s0, -8010942; RV32-NEXT:    lw ra, 76(sp) # 4-byte Folded Reload10943; RV32-NEXT:    lw s0, 72(sp) # 4-byte Folded Reload10944; RV32-NEXT:    addi sp, sp, 8010945; RV32-NEXT:    ret10946;10947; RV64-LABEL: vector_interleave_nxv24f32_nxv4f32:10948; RV64:       # %bb.0:10949; RV64-NEXT:    addi sp, sp, -8010950; RV64-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill10951; RV64-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill10952; RV64-NEXT:    addi s0, sp, 8010953; RV64-NEXT:    csrr a0, vlenb10954; RV64-NEXT:    li a1, 2810955; RV64-NEXT:    mul a0, a0, a110956; RV64-NEXT:    sub sp, sp, a010957; RV64-NEXT:    andi sp, sp, -6410958; RV64-NEXT:    vsetvli a0, zero, e32, m1, ta, ma10959; RV64-NEXT:    vmv2r.v v20, v1410960; RV64-NEXT:    vmv2r.v v22, v1210961; RV64-NEXT:    vmv2r.v v24, v1010962; RV64-NEXT:    csrr a1, vlenb10963; RV64-NEXT:    li a0, 610964; RV64-NEXT:    mul a1, a1, a010965; RV64-NEXT:    add a1, sp, a110966; RV64-NEXT:    addi a1, a1, 6410967; RV64-NEXT:    vmv1r.v v10, v2510968; RV64-NEXT:    vmv1r.v v11, v2310969; RV64-NEXT:    vmv1r.v v12, v2110970; RV64-NEXT:    addi a0, sp, 6410971; RV64-NEXT:    vmv1r.v v13, v1710972; RV64-NEXT:    csrr a2, vlenb10973; RV64-NEXT:    vmv1r.v v14, v1910974; RV64-NEXT:    vsseg6e32.v v9, (a1)10975; RV64-NEXT:    vmv1r.v v9, v2410976; RV64-NEXT:    add a5, a1, a210977; RV64-NEXT:    vmv1r.v v10, v2210978; RV64-NEXT:    add a3, a0, a210979; RV64-NEXT:    vmv1r.v v11, v2010980; RV64-NEXT:    add a4, a3, a210981; RV64-NEXT:    vmv1r.v v12, v1610982; RV64-NEXT:    add a6, a5, a210983; RV64-NEXT:    vmv1r.v v13, v1810984; RV64-NEXT:    vsseg6e32.v v8, (a0)10985; RV64-NEXT:    vl1re32.v v14, (a1)10986; RV64-NEXT:    add a1, a6, a210987; RV64-NEXT:    vl1re32.v v15, (a5)10988; RV64-NEXT:    add a5, a1, a210989; RV64-NEXT:    vl1re32.v v18, (a5)10990; RV64-NEXT:    add a5, a5, a210991; RV64-NEXT:    vl1re32.v v19, (a5)10992; RV64-NEXT:    add a5, a4, a210993; RV64-NEXT:    vl1re32.v v16, (a6)10994; RV64-NEXT:    add a6, a5, a210995; RV64-NEXT:    vl1re32.v v12, (a6)10996; RV64-NEXT:    add a6, a6, a210997; RV64-NEXT:    vl1re32.v v13, (a6)10998; RV64-NEXT:    csrr a6, vlenb10999; RV64-NEXT:    li a7, 1211000; RV64-NEXT:    mul a6, a6, a711001; RV64-NEXT:    add a6, sp, a611002; RV64-NEXT:    addi a6, a6, 6411003; RV64-NEXT:    vl1re32.v v17, (a1)11004; RV64-NEXT:    vl1re32.v v10, (a4)11005; RV64-NEXT:    vl1re32.v v11, (a5)11006; RV64-NEXT:    vl1re32.v v8, (a0)11007; RV64-NEXT:    vl1re32.v v9, (a3)11008; RV64-NEXT:    slli a2, a2, 311009; RV64-NEXT:    add a2, a6, a211010; RV64-NEXT:    vs4r.v v16, (a2)11011; RV64-NEXT:    vs8r.v v8, (a6)11012; RV64-NEXT:    vl8re32.v v16, (a2)11013; RV64-NEXT:    vl8re32.v v8, (a6)11014; RV64-NEXT:    addi sp, s0, -8011015; RV64-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload11016; RV64-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload11017; RV64-NEXT:    addi sp, sp, 8011018; RV64-NEXT:    ret11019;11020; ZVBB-RV32-LABEL: vector_interleave_nxv24f32_nxv4f32:11021; ZVBB-RV32:       # %bb.0:11022; ZVBB-RV32-NEXT:    addi sp, sp, -8011023; ZVBB-RV32-NEXT:    sw ra, 76(sp) # 4-byte Folded Spill11024; ZVBB-RV32-NEXT:    sw s0, 72(sp) # 4-byte Folded Spill11025; ZVBB-RV32-NEXT:    addi s0, sp, 8011026; ZVBB-RV32-NEXT:    csrr a0, vlenb11027; ZVBB-RV32-NEXT:    li a1, 2811028; ZVBB-RV32-NEXT:    mul a0, a0, a111029; ZVBB-RV32-NEXT:    sub sp, sp, a011030; ZVBB-RV32-NEXT:    andi sp, sp, -6411031; ZVBB-RV32-NEXT:    vsetvli a0, zero, e32, m1, ta, ma11032; ZVBB-RV32-NEXT:    vmv2r.v v20, v1411033; ZVBB-RV32-NEXT:    vmv2r.v v22, v1211034; ZVBB-RV32-NEXT:    vmv2r.v v24, v1011035; ZVBB-RV32-NEXT:    csrr a1, vlenb11036; ZVBB-RV32-NEXT:    li a0, 611037; ZVBB-RV32-NEXT:    mul a1, a1, a011038; ZVBB-RV32-NEXT:    add a1, sp, a111039; ZVBB-RV32-NEXT:    addi a1, a1, 6411040; ZVBB-RV32-NEXT:    vmv1r.v v10, v2511041; ZVBB-RV32-NEXT:    vmv1r.v v11, v2311042; ZVBB-RV32-NEXT:    vmv1r.v v12, v2111043; ZVBB-RV32-NEXT:    addi a0, sp, 6411044; ZVBB-RV32-NEXT:    vmv1r.v v13, v1711045; ZVBB-RV32-NEXT:    csrr a2, vlenb11046; ZVBB-RV32-NEXT:    vmv1r.v v14, v1911047; ZVBB-RV32-NEXT:    vsseg6e32.v v9, (a1)11048; ZVBB-RV32-NEXT:    vmv1r.v v9, v2411049; ZVBB-RV32-NEXT:    add a5, a1, a211050; ZVBB-RV32-NEXT:    vmv1r.v v10, v2211051; ZVBB-RV32-NEXT:    add a3, a0, a211052; ZVBB-RV32-NEXT:    vmv1r.v v11, v2011053; ZVBB-RV32-NEXT:    add a4, a3, a211054; ZVBB-RV32-NEXT:    vmv1r.v v12, v1611055; ZVBB-RV32-NEXT:    add a6, a5, a211056; ZVBB-RV32-NEXT:    vmv1r.v v13, v1811057; ZVBB-RV32-NEXT:    vsseg6e32.v v8, (a0)11058; ZVBB-RV32-NEXT:    vl1re32.v v14, (a1)11059; ZVBB-RV32-NEXT:    add a1, a6, a211060; ZVBB-RV32-NEXT:    vl1re32.v v15, (a5)11061; ZVBB-RV32-NEXT:    add a5, a1, a211062; ZVBB-RV32-NEXT:    vl1re32.v v18, (a5)11063; ZVBB-RV32-NEXT:    add a5, a5, a211064; ZVBB-RV32-NEXT:    vl1re32.v v19, (a5)11065; ZVBB-RV32-NEXT:    add a5, a4, a211066; ZVBB-RV32-NEXT:    vl1re32.v v16, (a6)11067; ZVBB-RV32-NEXT:    add a6, a5, a211068; ZVBB-RV32-NEXT:    vl1re32.v v12, (a6)11069; ZVBB-RV32-NEXT:    add a6, a6, a211070; ZVBB-RV32-NEXT:    vl1re32.v v13, (a6)11071; ZVBB-RV32-NEXT:    csrr a6, vlenb11072; ZVBB-RV32-NEXT:    li a7, 1211073; ZVBB-RV32-NEXT:    mul a6, a6, a711074; ZVBB-RV32-NEXT:    add a6, sp, a611075; ZVBB-RV32-NEXT:    addi a6, a6, 6411076; ZVBB-RV32-NEXT:    vl1re32.v v17, (a1)11077; ZVBB-RV32-NEXT:    vl1re32.v v10, (a4)11078; ZVBB-RV32-NEXT:    vl1re32.v v11, (a5)11079; ZVBB-RV32-NEXT:    vl1re32.v v8, (a0)11080; ZVBB-RV32-NEXT:    vl1re32.v v9, (a3)11081; ZVBB-RV32-NEXT:    slli a2, a2, 311082; ZVBB-RV32-NEXT:    add a2, a6, a211083; ZVBB-RV32-NEXT:    vs4r.v v16, (a2)11084; ZVBB-RV32-NEXT:    vs8r.v v8, (a6)11085; ZVBB-RV32-NEXT:    vl8re32.v v16, (a2)11086; ZVBB-RV32-NEXT:    vl8re32.v v8, (a6)11087; ZVBB-RV32-NEXT:    addi sp, s0, -8011088; ZVBB-RV32-NEXT:    lw ra, 76(sp) # 4-byte Folded Reload11089; ZVBB-RV32-NEXT:    lw s0, 72(sp) # 4-byte Folded Reload11090; ZVBB-RV32-NEXT:    addi sp, sp, 8011091; ZVBB-RV32-NEXT:    ret11092;11093; ZVBB-RV64-LABEL: vector_interleave_nxv24f32_nxv4f32:11094; ZVBB-RV64:       # %bb.0:11095; ZVBB-RV64-NEXT:    addi sp, sp, -8011096; ZVBB-RV64-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill11097; ZVBB-RV64-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill11098; ZVBB-RV64-NEXT:    addi s0, sp, 8011099; ZVBB-RV64-NEXT:    csrr a0, vlenb11100; ZVBB-RV64-NEXT:    li a1, 2811101; ZVBB-RV64-NEXT:    mul a0, a0, a111102; ZVBB-RV64-NEXT:    sub sp, sp, a011103; ZVBB-RV64-NEXT:    andi sp, sp, -6411104; ZVBB-RV64-NEXT:    vsetvli a0, zero, e32, m1, ta, ma11105; ZVBB-RV64-NEXT:    vmv2r.v v20, v1411106; ZVBB-RV64-NEXT:    vmv2r.v v22, v1211107; ZVBB-RV64-NEXT:    vmv2r.v v24, v1011108; ZVBB-RV64-NEXT:    csrr a1, vlenb11109; ZVBB-RV64-NEXT:    li a0, 611110; ZVBB-RV64-NEXT:    mul a1, a1, a011111; ZVBB-RV64-NEXT:    add a1, sp, a111112; ZVBB-RV64-NEXT:    addi a1, a1, 6411113; ZVBB-RV64-NEXT:    vmv1r.v v10, v2511114; ZVBB-RV64-NEXT:    vmv1r.v v11, v2311115; ZVBB-RV64-NEXT:    vmv1r.v v12, v2111116; ZVBB-RV64-NEXT:    addi a0, sp, 6411117; ZVBB-RV64-NEXT:    vmv1r.v v13, v1711118; ZVBB-RV64-NEXT:    csrr a2, vlenb11119; ZVBB-RV64-NEXT:    vmv1r.v v14, v1911120; ZVBB-RV64-NEXT:    vsseg6e32.v v9, (a1)11121; ZVBB-RV64-NEXT:    vmv1r.v v9, v2411122; ZVBB-RV64-NEXT:    add a5, a1, a211123; ZVBB-RV64-NEXT:    vmv1r.v v10, v2211124; ZVBB-RV64-NEXT:    add a3, a0, a211125; ZVBB-RV64-NEXT:    vmv1r.v v11, v2011126; ZVBB-RV64-NEXT:    add a4, a3, a211127; ZVBB-RV64-NEXT:    vmv1r.v v12, v1611128; ZVBB-RV64-NEXT:    add a6, a5, a211129; ZVBB-RV64-NEXT:    vmv1r.v v13, v1811130; ZVBB-RV64-NEXT:    vsseg6e32.v v8, (a0)11131; ZVBB-RV64-NEXT:    vl1re32.v v14, (a1)11132; ZVBB-RV64-NEXT:    add a1, a6, a211133; ZVBB-RV64-NEXT:    vl1re32.v v15, (a5)11134; ZVBB-RV64-NEXT:    add a5, a1, a211135; ZVBB-RV64-NEXT:    vl1re32.v v18, (a5)11136; ZVBB-RV64-NEXT:    add a5, a5, a211137; ZVBB-RV64-NEXT:    vl1re32.v v19, (a5)11138; ZVBB-RV64-NEXT:    add a5, a4, a211139; ZVBB-RV64-NEXT:    vl1re32.v v16, (a6)11140; ZVBB-RV64-NEXT:    add a6, a5, a211141; ZVBB-RV64-NEXT:    vl1re32.v v12, (a6)11142; ZVBB-RV64-NEXT:    add a6, a6, a211143; ZVBB-RV64-NEXT:    vl1re32.v v13, (a6)11144; ZVBB-RV64-NEXT:    csrr a6, vlenb11145; ZVBB-RV64-NEXT:    li a7, 1211146; ZVBB-RV64-NEXT:    mul a6, a6, a711147; ZVBB-RV64-NEXT:    add a6, sp, a611148; ZVBB-RV64-NEXT:    addi a6, a6, 6411149; ZVBB-RV64-NEXT:    vl1re32.v v17, (a1)11150; ZVBB-RV64-NEXT:    vl1re32.v v10, (a4)11151; ZVBB-RV64-NEXT:    vl1re32.v v11, (a5)11152; ZVBB-RV64-NEXT:    vl1re32.v v8, (a0)11153; ZVBB-RV64-NEXT:    vl1re32.v v9, (a3)11154; ZVBB-RV64-NEXT:    slli a2, a2, 311155; ZVBB-RV64-NEXT:    add a2, a6, a211156; ZVBB-RV64-NEXT:    vs4r.v v16, (a2)11157; ZVBB-RV64-NEXT:    vs8r.v v8, (a6)11158; ZVBB-RV64-NEXT:    vl8re32.v v16, (a2)11159; ZVBB-RV64-NEXT:    vl8re32.v v8, (a6)11160; ZVBB-RV64-NEXT:    addi sp, s0, -8011161; ZVBB-RV64-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload11162; ZVBB-RV64-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload11163; ZVBB-RV64-NEXT:    addi sp, sp, 8011164; ZVBB-RV64-NEXT:    ret11165;11166; ZIP-LABEL: vector_interleave_nxv24f32_nxv4f32:11167; ZIP:       # %bb.0:11168; ZIP-NEXT:    addi sp, sp, -8011169; ZIP-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill11170; ZIP-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill11171; ZIP-NEXT:    addi s0, sp, 8011172; ZIP-NEXT:    csrr a0, vlenb11173; ZIP-NEXT:    li a1, 2811174; ZIP-NEXT:    mul a0, a0, a111175; ZIP-NEXT:    sub sp, sp, a011176; ZIP-NEXT:    andi sp, sp, -6411177; ZIP-NEXT:    vsetvli a0, zero, e32, m1, ta, ma11178; ZIP-NEXT:    vmv2r.v v20, v1411179; ZIP-NEXT:    vmv2r.v v22, v1211180; ZIP-NEXT:    vmv2r.v v24, v1011181; ZIP-NEXT:    csrr a1, vlenb11182; ZIP-NEXT:    li a0, 611183; ZIP-NEXT:    mul a1, a1, a011184; ZIP-NEXT:    add a1, sp, a111185; ZIP-NEXT:    addi a1, a1, 6411186; ZIP-NEXT:    vmv1r.v v10, v2511187; ZIP-NEXT:    vmv1r.v v11, v2311188; ZIP-NEXT:    vmv1r.v v12, v2111189; ZIP-NEXT:    addi a0, sp, 6411190; ZIP-NEXT:    vmv1r.v v13, v1711191; ZIP-NEXT:    csrr a2, vlenb11192; ZIP-NEXT:    vmv1r.v v14, v1911193; ZIP-NEXT:    vsseg6e32.v v9, (a1)11194; ZIP-NEXT:    vmv1r.v v9, v2411195; ZIP-NEXT:    add a5, a1, a211196; ZIP-NEXT:    vmv1r.v v10, v2211197; ZIP-NEXT:    add a3, a0, a211198; ZIP-NEXT:    vmv1r.v v11, v2011199; ZIP-NEXT:    add a4, a3, a211200; ZIP-NEXT:    vmv1r.v v12, v1611201; ZIP-NEXT:    add a6, a5, a211202; ZIP-NEXT:    vmv1r.v v13, v1811203; ZIP-NEXT:    vsseg6e32.v v8, (a0)11204; ZIP-NEXT:    vl1re32.v v14, (a1)11205; ZIP-NEXT:    add a1, a6, a211206; ZIP-NEXT:    vl1re32.v v15, (a5)11207; ZIP-NEXT:    add a5, a1, a211208; ZIP-NEXT:    vl1re32.v v18, (a5)11209; ZIP-NEXT:    add a5, a5, a211210; ZIP-NEXT:    vl1re32.v v19, (a5)11211; ZIP-NEXT:    add a5, a4, a211212; ZIP-NEXT:    vl1re32.v v16, (a6)11213; ZIP-NEXT:    add a6, a5, a211214; ZIP-NEXT:    vl1re32.v v12, (a6)11215; ZIP-NEXT:    add a6, a6, a211216; ZIP-NEXT:    vl1re32.v v13, (a6)11217; ZIP-NEXT:    csrr a6, vlenb11218; ZIP-NEXT:    li a7, 1211219; ZIP-NEXT:    mul a6, a6, a711220; ZIP-NEXT:    add a6, sp, a611221; ZIP-NEXT:    addi a6, a6, 6411222; ZIP-NEXT:    vl1re32.v v17, (a1)11223; ZIP-NEXT:    vl1re32.v v10, (a4)11224; ZIP-NEXT:    vl1re32.v v11, (a5)11225; ZIP-NEXT:    vl1re32.v v8, (a0)11226; ZIP-NEXT:    vl1re32.v v9, (a3)11227; ZIP-NEXT:    slli a2, a2, 311228; ZIP-NEXT:    add a2, a6, a211229; ZIP-NEXT:    vs4r.v v16, (a2)11230; ZIP-NEXT:    vs8r.v v8, (a6)11231; ZIP-NEXT:    vl8re32.v v16, (a2)11232; ZIP-NEXT:    vl8re32.v v8, (a6)11233; ZIP-NEXT:    addi sp, s0, -8011234; ZIP-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload11235; ZIP-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload11236; ZIP-NEXT:    addi sp, sp, 8011237; ZIP-NEXT:    ret11238  %res = call <vscale x 24 x float> @llvm.vector.interleave6.nxv24f32(<vscale x 4 x float> %v0, <vscale x 4 x float> %v1, <vscale x 4 x float> %v2, <vscale x 4 x float> %v3, <vscale x 4 x float> %v4, <vscale x 4 x float> %v5)11239  ret <vscale x 24 x float> %res11240}11241 11242define <vscale x 6 x double> @vector_interleave_nxv6f64_nxv1f64(<vscale x 1 x double> %v0, <vscale x 1 x double> %v1, <vscale x 1 x double> %v2, <vscale x 1 x double> %v3, <vscale x 1 x double> %v4, <vscale x 1 x double> %v5) nounwind {11243; CHECK-LABEL: vector_interleave_nxv6f64_nxv1f64:11244; CHECK:       # %bb.0:11245; CHECK-NEXT:    addi sp, sp, -1611246; CHECK-NEXT:    csrr a0, vlenb11247; CHECK-NEXT:    li a1, 611248; CHECK-NEXT:    mul a0, a0, a111249; CHECK-NEXT:    sub sp, sp, a011250; CHECK-NEXT:    addi a0, sp, 1611251; CHECK-NEXT:    csrr a1, vlenb11252; CHECK-NEXT:    add a2, a0, a111253; CHECK-NEXT:    add a3, a2, a111254; CHECK-NEXT:    vsetvli a4, zero, e64, m1, ta, ma11255; CHECK-NEXT:    vsseg6e64.v v8, (a0)11256; CHECK-NEXT:    vl1re64.v v10, (a3)11257; CHECK-NEXT:    add a3, a3, a111258; CHECK-NEXT:    vl1re64.v v11, (a3)11259; CHECK-NEXT:    add a3, a3, a111260; CHECK-NEXT:    vl1re64.v v8, (a0)11261; CHECK-NEXT:    vl1re64.v v9, (a2)11262; CHECK-NEXT:    vl1re64.v v12, (a3)11263; CHECK-NEXT:    add a1, a3, a111264; CHECK-NEXT:    vl1re64.v v13, (a1)11265; CHECK-NEXT:    csrr a0, vlenb11266; CHECK-NEXT:    li a1, 611267; CHECK-NEXT:    mul a0, a0, a111268; CHECK-NEXT:    add sp, sp, a011269; CHECK-NEXT:    addi sp, sp, 1611270; CHECK-NEXT:    ret11271;11272; ZVBB-LABEL: vector_interleave_nxv6f64_nxv1f64:11273; ZVBB:       # %bb.0:11274; ZVBB-NEXT:    addi sp, sp, -1611275; ZVBB-NEXT:    csrr a0, vlenb11276; ZVBB-NEXT:    li a1, 611277; ZVBB-NEXT:    mul a0, a0, a111278; ZVBB-NEXT:    sub sp, sp, a011279; ZVBB-NEXT:    addi a0, sp, 1611280; ZVBB-NEXT:    csrr a1, vlenb11281; ZVBB-NEXT:    add a2, a0, a111282; ZVBB-NEXT:    add a3, a2, a111283; ZVBB-NEXT:    vsetvli a4, zero, e64, m1, ta, ma11284; ZVBB-NEXT:    vsseg6e64.v v8, (a0)11285; ZVBB-NEXT:    vl1re64.v v10, (a3)11286; ZVBB-NEXT:    add a3, a3, a111287; ZVBB-NEXT:    vl1re64.v v11, (a3)11288; ZVBB-NEXT:    add a3, a3, a111289; ZVBB-NEXT:    vl1re64.v v8, (a0)11290; ZVBB-NEXT:    vl1re64.v v9, (a2)11291; ZVBB-NEXT:    vl1re64.v v12, (a3)11292; ZVBB-NEXT:    add a1, a3, a111293; ZVBB-NEXT:    vl1re64.v v13, (a1)11294; ZVBB-NEXT:    csrr a0, vlenb11295; ZVBB-NEXT:    li a1, 611296; ZVBB-NEXT:    mul a0, a0, a111297; ZVBB-NEXT:    add sp, sp, a011298; ZVBB-NEXT:    addi sp, sp, 1611299; ZVBB-NEXT:    ret11300  %res = call <vscale x 6 x double> @llvm.vector.interleave6.nxv6f64(<vscale x 1 x double> %v0, <vscale x 1 x double> %v1, <vscale x 1 x double> %v2, <vscale x 1 x double> %v3, <vscale x 1 x double> %v4, <vscale x 1 x double> %v5)11301  ret <vscale x 6 x double> %res11302}11303 11304define <vscale x 12 x double> @vector_interleave_nxv12f64_nxv2f64(<vscale x 2 x double> %v0, <vscale x 2 x double> %v1, <vscale x 2 x double> %v2, <vscale x 2 x double> %v3, <vscale x 2 x double> %v4, <vscale x 2 x double> %v5) nounwind {11305; RV32-LABEL: vector_interleave_nxv12f64_nxv2f64:11306; RV32:       # %bb.0:11307; RV32-NEXT:    addi sp, sp, -8011308; RV32-NEXT:    sw ra, 76(sp) # 4-byte Folded Spill11309; RV32-NEXT:    sw s0, 72(sp) # 4-byte Folded Spill11310; RV32-NEXT:    addi s0, sp, 8011311; RV32-NEXT:    csrr a0, vlenb11312; RV32-NEXT:    li a1, 2811313; RV32-NEXT:    mul a0, a0, a111314; RV32-NEXT:    sub sp, sp, a011315; RV32-NEXT:    andi sp, sp, -6411316; RV32-NEXT:    vsetvli a0, zero, e64, m1, ta, ma11317; RV32-NEXT:    vmv2r.v v20, v1411318; RV32-NEXT:    vmv2r.v v22, v1211319; RV32-NEXT:    vmv2r.v v24, v1011320; RV32-NEXT:    csrr a1, vlenb11321; RV32-NEXT:    li a0, 611322; RV32-NEXT:    mul a1, a1, a011323; RV32-NEXT:    add a1, sp, a111324; RV32-NEXT:    addi a1, a1, 6411325; RV32-NEXT:    vmv1r.v v10, v2511326; RV32-NEXT:    vmv1r.v v11, v2311327; RV32-NEXT:    vmv1r.v v12, v2111328; RV32-NEXT:    addi a0, sp, 6411329; RV32-NEXT:    vmv1r.v v13, v1711330; RV32-NEXT:    csrr a2, vlenb11331; RV32-NEXT:    vmv1r.v v14, v1911332; RV32-NEXT:    vsseg6e64.v v9, (a1)11333; RV32-NEXT:    vmv1r.v v9, v2411334; RV32-NEXT:    add a5, a1, a211335; RV32-NEXT:    vmv1r.v v10, v2211336; RV32-NEXT:    add a3, a0, a211337; RV32-NEXT:    vmv1r.v v11, v2011338; RV32-NEXT:    add a4, a3, a211339; RV32-NEXT:    vmv1r.v v12, v1611340; RV32-NEXT:    add a6, a5, a211341; RV32-NEXT:    vmv1r.v v13, v1811342; RV32-NEXT:    vsseg6e64.v v8, (a0)11343; RV32-NEXT:    vl1re64.v v14, (a1)11344; RV32-NEXT:    add a1, a6, a211345; RV32-NEXT:    vl1re64.v v15, (a5)11346; RV32-NEXT:    add a5, a1, a211347; RV32-NEXT:    vl1re64.v v18, (a5)11348; RV32-NEXT:    add a5, a5, a211349; RV32-NEXT:    vl1re64.v v19, (a5)11350; RV32-NEXT:    add a5, a4, a211351; RV32-NEXT:    vl1re64.v v16, (a6)11352; RV32-NEXT:    add a6, a5, a211353; RV32-NEXT:    vl1re64.v v12, (a6)11354; RV32-NEXT:    add a6, a6, a211355; RV32-NEXT:    vl1re64.v v13, (a6)11356; RV32-NEXT:    csrr a6, vlenb11357; RV32-NEXT:    li a7, 1211358; RV32-NEXT:    mul a6, a6, a711359; RV32-NEXT:    add a6, sp, a611360; RV32-NEXT:    addi a6, a6, 6411361; RV32-NEXT:    vl1re64.v v17, (a1)11362; RV32-NEXT:    vl1re64.v v10, (a4)11363; RV32-NEXT:    vl1re64.v v11, (a5)11364; RV32-NEXT:    vl1re64.v v8, (a0)11365; RV32-NEXT:    vl1re64.v v9, (a3)11366; RV32-NEXT:    slli a2, a2, 311367; RV32-NEXT:    add a2, a6, a211368; RV32-NEXT:    vs4r.v v16, (a2)11369; RV32-NEXT:    vs8r.v v8, (a6)11370; RV32-NEXT:    vl8re64.v v16, (a2)11371; RV32-NEXT:    vl8re64.v v8, (a6)11372; RV32-NEXT:    addi sp, s0, -8011373; RV32-NEXT:    lw ra, 76(sp) # 4-byte Folded Reload11374; RV32-NEXT:    lw s0, 72(sp) # 4-byte Folded Reload11375; RV32-NEXT:    addi sp, sp, 8011376; RV32-NEXT:    ret11377;11378; RV64-LABEL: vector_interleave_nxv12f64_nxv2f64:11379; RV64:       # %bb.0:11380; RV64-NEXT:    addi sp, sp, -8011381; RV64-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill11382; RV64-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill11383; RV64-NEXT:    addi s0, sp, 8011384; RV64-NEXT:    csrr a0, vlenb11385; RV64-NEXT:    li a1, 2811386; RV64-NEXT:    mul a0, a0, a111387; RV64-NEXT:    sub sp, sp, a011388; RV64-NEXT:    andi sp, sp, -6411389; RV64-NEXT:    vsetvli a0, zero, e64, m1, ta, ma11390; RV64-NEXT:    vmv2r.v v20, v1411391; RV64-NEXT:    vmv2r.v v22, v1211392; RV64-NEXT:    vmv2r.v v24, v1011393; RV64-NEXT:    csrr a1, vlenb11394; RV64-NEXT:    li a0, 611395; RV64-NEXT:    mul a1, a1, a011396; RV64-NEXT:    add a1, sp, a111397; RV64-NEXT:    addi a1, a1, 6411398; RV64-NEXT:    vmv1r.v v10, v2511399; RV64-NEXT:    vmv1r.v v11, v2311400; RV64-NEXT:    vmv1r.v v12, v2111401; RV64-NEXT:    addi a0, sp, 6411402; RV64-NEXT:    vmv1r.v v13, v1711403; RV64-NEXT:    csrr a2, vlenb11404; RV64-NEXT:    vmv1r.v v14, v1911405; RV64-NEXT:    vsseg6e64.v v9, (a1)11406; RV64-NEXT:    vmv1r.v v9, v2411407; RV64-NEXT:    add a5, a1, a211408; RV64-NEXT:    vmv1r.v v10, v2211409; RV64-NEXT:    add a3, a0, a211410; RV64-NEXT:    vmv1r.v v11, v2011411; RV64-NEXT:    add a4, a3, a211412; RV64-NEXT:    vmv1r.v v12, v1611413; RV64-NEXT:    add a6, a5, a211414; RV64-NEXT:    vmv1r.v v13, v1811415; RV64-NEXT:    vsseg6e64.v v8, (a0)11416; RV64-NEXT:    vl1re64.v v14, (a1)11417; RV64-NEXT:    add a1, a6, a211418; RV64-NEXT:    vl1re64.v v15, (a5)11419; RV64-NEXT:    add a5, a1, a211420; RV64-NEXT:    vl1re64.v v18, (a5)11421; RV64-NEXT:    add a5, a5, a211422; RV64-NEXT:    vl1re64.v v19, (a5)11423; RV64-NEXT:    add a5, a4, a211424; RV64-NEXT:    vl1re64.v v16, (a6)11425; RV64-NEXT:    add a6, a5, a211426; RV64-NEXT:    vl1re64.v v12, (a6)11427; RV64-NEXT:    add a6, a6, a211428; RV64-NEXT:    vl1re64.v v13, (a6)11429; RV64-NEXT:    csrr a6, vlenb11430; RV64-NEXT:    li a7, 1211431; RV64-NEXT:    mul a6, a6, a711432; RV64-NEXT:    add a6, sp, a611433; RV64-NEXT:    addi a6, a6, 6411434; RV64-NEXT:    vl1re64.v v17, (a1)11435; RV64-NEXT:    vl1re64.v v10, (a4)11436; RV64-NEXT:    vl1re64.v v11, (a5)11437; RV64-NEXT:    vl1re64.v v8, (a0)11438; RV64-NEXT:    vl1re64.v v9, (a3)11439; RV64-NEXT:    slli a2, a2, 311440; RV64-NEXT:    add a2, a6, a211441; RV64-NEXT:    vs4r.v v16, (a2)11442; RV64-NEXT:    vs8r.v v8, (a6)11443; RV64-NEXT:    vl8re64.v v16, (a2)11444; RV64-NEXT:    vl8re64.v v8, (a6)11445; RV64-NEXT:    addi sp, s0, -8011446; RV64-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload11447; RV64-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload11448; RV64-NEXT:    addi sp, sp, 8011449; RV64-NEXT:    ret11450;11451; ZVBB-RV32-LABEL: vector_interleave_nxv12f64_nxv2f64:11452; ZVBB-RV32:       # %bb.0:11453; ZVBB-RV32-NEXT:    addi sp, sp, -8011454; ZVBB-RV32-NEXT:    sw ra, 76(sp) # 4-byte Folded Spill11455; ZVBB-RV32-NEXT:    sw s0, 72(sp) # 4-byte Folded Spill11456; ZVBB-RV32-NEXT:    addi s0, sp, 8011457; ZVBB-RV32-NEXT:    csrr a0, vlenb11458; ZVBB-RV32-NEXT:    li a1, 2811459; ZVBB-RV32-NEXT:    mul a0, a0, a111460; ZVBB-RV32-NEXT:    sub sp, sp, a011461; ZVBB-RV32-NEXT:    andi sp, sp, -6411462; ZVBB-RV32-NEXT:    vsetvli a0, zero, e64, m1, ta, ma11463; ZVBB-RV32-NEXT:    vmv2r.v v20, v1411464; ZVBB-RV32-NEXT:    vmv2r.v v22, v1211465; ZVBB-RV32-NEXT:    vmv2r.v v24, v1011466; ZVBB-RV32-NEXT:    csrr a1, vlenb11467; ZVBB-RV32-NEXT:    li a0, 611468; ZVBB-RV32-NEXT:    mul a1, a1, a011469; ZVBB-RV32-NEXT:    add a1, sp, a111470; ZVBB-RV32-NEXT:    addi a1, a1, 6411471; ZVBB-RV32-NEXT:    vmv1r.v v10, v2511472; ZVBB-RV32-NEXT:    vmv1r.v v11, v2311473; ZVBB-RV32-NEXT:    vmv1r.v v12, v2111474; ZVBB-RV32-NEXT:    addi a0, sp, 6411475; ZVBB-RV32-NEXT:    vmv1r.v v13, v1711476; ZVBB-RV32-NEXT:    csrr a2, vlenb11477; ZVBB-RV32-NEXT:    vmv1r.v v14, v1911478; ZVBB-RV32-NEXT:    vsseg6e64.v v9, (a1)11479; ZVBB-RV32-NEXT:    vmv1r.v v9, v2411480; ZVBB-RV32-NEXT:    add a5, a1, a211481; ZVBB-RV32-NEXT:    vmv1r.v v10, v2211482; ZVBB-RV32-NEXT:    add a3, a0, a211483; ZVBB-RV32-NEXT:    vmv1r.v v11, v2011484; ZVBB-RV32-NEXT:    add a4, a3, a211485; ZVBB-RV32-NEXT:    vmv1r.v v12, v1611486; ZVBB-RV32-NEXT:    add a6, a5, a211487; ZVBB-RV32-NEXT:    vmv1r.v v13, v1811488; ZVBB-RV32-NEXT:    vsseg6e64.v v8, (a0)11489; ZVBB-RV32-NEXT:    vl1re64.v v14, (a1)11490; ZVBB-RV32-NEXT:    add a1, a6, a211491; ZVBB-RV32-NEXT:    vl1re64.v v15, (a5)11492; ZVBB-RV32-NEXT:    add a5, a1, a211493; ZVBB-RV32-NEXT:    vl1re64.v v18, (a5)11494; ZVBB-RV32-NEXT:    add a5, a5, a211495; ZVBB-RV32-NEXT:    vl1re64.v v19, (a5)11496; ZVBB-RV32-NEXT:    add a5, a4, a211497; ZVBB-RV32-NEXT:    vl1re64.v v16, (a6)11498; ZVBB-RV32-NEXT:    add a6, a5, a211499; ZVBB-RV32-NEXT:    vl1re64.v v12, (a6)11500; ZVBB-RV32-NEXT:    add a6, a6, a211501; ZVBB-RV32-NEXT:    vl1re64.v v13, (a6)11502; ZVBB-RV32-NEXT:    csrr a6, vlenb11503; ZVBB-RV32-NEXT:    li a7, 1211504; ZVBB-RV32-NEXT:    mul a6, a6, a711505; ZVBB-RV32-NEXT:    add a6, sp, a611506; ZVBB-RV32-NEXT:    addi a6, a6, 6411507; ZVBB-RV32-NEXT:    vl1re64.v v17, (a1)11508; ZVBB-RV32-NEXT:    vl1re64.v v10, (a4)11509; ZVBB-RV32-NEXT:    vl1re64.v v11, (a5)11510; ZVBB-RV32-NEXT:    vl1re64.v v8, (a0)11511; ZVBB-RV32-NEXT:    vl1re64.v v9, (a3)11512; ZVBB-RV32-NEXT:    slli a2, a2, 311513; ZVBB-RV32-NEXT:    add a2, a6, a211514; ZVBB-RV32-NEXT:    vs4r.v v16, (a2)11515; ZVBB-RV32-NEXT:    vs8r.v v8, (a6)11516; ZVBB-RV32-NEXT:    vl8re64.v v16, (a2)11517; ZVBB-RV32-NEXT:    vl8re64.v v8, (a6)11518; ZVBB-RV32-NEXT:    addi sp, s0, -8011519; ZVBB-RV32-NEXT:    lw ra, 76(sp) # 4-byte Folded Reload11520; ZVBB-RV32-NEXT:    lw s0, 72(sp) # 4-byte Folded Reload11521; ZVBB-RV32-NEXT:    addi sp, sp, 8011522; ZVBB-RV32-NEXT:    ret11523;11524; ZVBB-RV64-LABEL: vector_interleave_nxv12f64_nxv2f64:11525; ZVBB-RV64:       # %bb.0:11526; ZVBB-RV64-NEXT:    addi sp, sp, -8011527; ZVBB-RV64-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill11528; ZVBB-RV64-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill11529; ZVBB-RV64-NEXT:    addi s0, sp, 8011530; ZVBB-RV64-NEXT:    csrr a0, vlenb11531; ZVBB-RV64-NEXT:    li a1, 2811532; ZVBB-RV64-NEXT:    mul a0, a0, a111533; ZVBB-RV64-NEXT:    sub sp, sp, a011534; ZVBB-RV64-NEXT:    andi sp, sp, -6411535; ZVBB-RV64-NEXT:    vsetvli a0, zero, e64, m1, ta, ma11536; ZVBB-RV64-NEXT:    vmv2r.v v20, v1411537; ZVBB-RV64-NEXT:    vmv2r.v v22, v1211538; ZVBB-RV64-NEXT:    vmv2r.v v24, v1011539; ZVBB-RV64-NEXT:    csrr a1, vlenb11540; ZVBB-RV64-NEXT:    li a0, 611541; ZVBB-RV64-NEXT:    mul a1, a1, a011542; ZVBB-RV64-NEXT:    add a1, sp, a111543; ZVBB-RV64-NEXT:    addi a1, a1, 6411544; ZVBB-RV64-NEXT:    vmv1r.v v10, v2511545; ZVBB-RV64-NEXT:    vmv1r.v v11, v2311546; ZVBB-RV64-NEXT:    vmv1r.v v12, v2111547; ZVBB-RV64-NEXT:    addi a0, sp, 6411548; ZVBB-RV64-NEXT:    vmv1r.v v13, v1711549; ZVBB-RV64-NEXT:    csrr a2, vlenb11550; ZVBB-RV64-NEXT:    vmv1r.v v14, v1911551; ZVBB-RV64-NEXT:    vsseg6e64.v v9, (a1)11552; ZVBB-RV64-NEXT:    vmv1r.v v9, v2411553; ZVBB-RV64-NEXT:    add a5, a1, a211554; ZVBB-RV64-NEXT:    vmv1r.v v10, v2211555; ZVBB-RV64-NEXT:    add a3, a0, a211556; ZVBB-RV64-NEXT:    vmv1r.v v11, v2011557; ZVBB-RV64-NEXT:    add a4, a3, a211558; ZVBB-RV64-NEXT:    vmv1r.v v12, v1611559; ZVBB-RV64-NEXT:    add a6, a5, a211560; ZVBB-RV64-NEXT:    vmv1r.v v13, v1811561; ZVBB-RV64-NEXT:    vsseg6e64.v v8, (a0)11562; ZVBB-RV64-NEXT:    vl1re64.v v14, (a1)11563; ZVBB-RV64-NEXT:    add a1, a6, a211564; ZVBB-RV64-NEXT:    vl1re64.v v15, (a5)11565; ZVBB-RV64-NEXT:    add a5, a1, a211566; ZVBB-RV64-NEXT:    vl1re64.v v18, (a5)11567; ZVBB-RV64-NEXT:    add a5, a5, a211568; ZVBB-RV64-NEXT:    vl1re64.v v19, (a5)11569; ZVBB-RV64-NEXT:    add a5, a4, a211570; ZVBB-RV64-NEXT:    vl1re64.v v16, (a6)11571; ZVBB-RV64-NEXT:    add a6, a5, a211572; ZVBB-RV64-NEXT:    vl1re64.v v12, (a6)11573; ZVBB-RV64-NEXT:    add a6, a6, a211574; ZVBB-RV64-NEXT:    vl1re64.v v13, (a6)11575; ZVBB-RV64-NEXT:    csrr a6, vlenb11576; ZVBB-RV64-NEXT:    li a7, 1211577; ZVBB-RV64-NEXT:    mul a6, a6, a711578; ZVBB-RV64-NEXT:    add a6, sp, a611579; ZVBB-RV64-NEXT:    addi a6, a6, 6411580; ZVBB-RV64-NEXT:    vl1re64.v v17, (a1)11581; ZVBB-RV64-NEXT:    vl1re64.v v10, (a4)11582; ZVBB-RV64-NEXT:    vl1re64.v v11, (a5)11583; ZVBB-RV64-NEXT:    vl1re64.v v8, (a0)11584; ZVBB-RV64-NEXT:    vl1re64.v v9, (a3)11585; ZVBB-RV64-NEXT:    slli a2, a2, 311586; ZVBB-RV64-NEXT:    add a2, a6, a211587; ZVBB-RV64-NEXT:    vs4r.v v16, (a2)11588; ZVBB-RV64-NEXT:    vs8r.v v8, (a6)11589; ZVBB-RV64-NEXT:    vl8re64.v v16, (a2)11590; ZVBB-RV64-NEXT:    vl8re64.v v8, (a6)11591; ZVBB-RV64-NEXT:    addi sp, s0, -8011592; ZVBB-RV64-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload11593; ZVBB-RV64-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload11594; ZVBB-RV64-NEXT:    addi sp, sp, 8011595; ZVBB-RV64-NEXT:    ret11596;11597; ZIP-LABEL: vector_interleave_nxv12f64_nxv2f64:11598; ZIP:       # %bb.0:11599; ZIP-NEXT:    addi sp, sp, -8011600; ZIP-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill11601; ZIP-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill11602; ZIP-NEXT:    addi s0, sp, 8011603; ZIP-NEXT:    csrr a0, vlenb11604; ZIP-NEXT:    li a1, 2811605; ZIP-NEXT:    mul a0, a0, a111606; ZIP-NEXT:    sub sp, sp, a011607; ZIP-NEXT:    andi sp, sp, -6411608; ZIP-NEXT:    vsetvli a0, zero, e64, m1, ta, ma11609; ZIP-NEXT:    vmv2r.v v20, v1411610; ZIP-NEXT:    vmv2r.v v22, v1211611; ZIP-NEXT:    vmv2r.v v24, v1011612; ZIP-NEXT:    csrr a1, vlenb11613; ZIP-NEXT:    li a0, 611614; ZIP-NEXT:    mul a1, a1, a011615; ZIP-NEXT:    add a1, sp, a111616; ZIP-NEXT:    addi a1, a1, 6411617; ZIP-NEXT:    vmv1r.v v10, v2511618; ZIP-NEXT:    vmv1r.v v11, v2311619; ZIP-NEXT:    vmv1r.v v12, v2111620; ZIP-NEXT:    addi a0, sp, 6411621; ZIP-NEXT:    vmv1r.v v13, v1711622; ZIP-NEXT:    csrr a2, vlenb11623; ZIP-NEXT:    vmv1r.v v14, v1911624; ZIP-NEXT:    vsseg6e64.v v9, (a1)11625; ZIP-NEXT:    vmv1r.v v9, v2411626; ZIP-NEXT:    add a5, a1, a211627; ZIP-NEXT:    vmv1r.v v10, v2211628; ZIP-NEXT:    add a3, a0, a211629; ZIP-NEXT:    vmv1r.v v11, v2011630; ZIP-NEXT:    add a4, a3, a211631; ZIP-NEXT:    vmv1r.v v12, v1611632; ZIP-NEXT:    add a6, a5, a211633; ZIP-NEXT:    vmv1r.v v13, v1811634; ZIP-NEXT:    vsseg6e64.v v8, (a0)11635; ZIP-NEXT:    vl1re64.v v14, (a1)11636; ZIP-NEXT:    add a1, a6, a211637; ZIP-NEXT:    vl1re64.v v15, (a5)11638; ZIP-NEXT:    add a5, a1, a211639; ZIP-NEXT:    vl1re64.v v18, (a5)11640; ZIP-NEXT:    add a5, a5, a211641; ZIP-NEXT:    vl1re64.v v19, (a5)11642; ZIP-NEXT:    add a5, a4, a211643; ZIP-NEXT:    vl1re64.v v16, (a6)11644; ZIP-NEXT:    add a6, a5, a211645; ZIP-NEXT:    vl1re64.v v12, (a6)11646; ZIP-NEXT:    add a6, a6, a211647; ZIP-NEXT:    vl1re64.v v13, (a6)11648; ZIP-NEXT:    csrr a6, vlenb11649; ZIP-NEXT:    li a7, 1211650; ZIP-NEXT:    mul a6, a6, a711651; ZIP-NEXT:    add a6, sp, a611652; ZIP-NEXT:    addi a6, a6, 6411653; ZIP-NEXT:    vl1re64.v v17, (a1)11654; ZIP-NEXT:    vl1re64.v v10, (a4)11655; ZIP-NEXT:    vl1re64.v v11, (a5)11656; ZIP-NEXT:    vl1re64.v v8, (a0)11657; ZIP-NEXT:    vl1re64.v v9, (a3)11658; ZIP-NEXT:    slli a2, a2, 311659; ZIP-NEXT:    add a2, a6, a211660; ZIP-NEXT:    vs4r.v v16, (a2)11661; ZIP-NEXT:    vs8r.v v8, (a6)11662; ZIP-NEXT:    vl8re64.v v16, (a2)11663; ZIP-NEXT:    vl8re64.v v8, (a6)11664; ZIP-NEXT:    addi sp, s0, -8011665; ZIP-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload11666; ZIP-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload11667; ZIP-NEXT:    addi sp, sp, 8011668; ZIP-NEXT:    ret11669  %res = call <vscale x 12 x double> @llvm.vector.interleave6.nxv12f64(<vscale x 2 x double> %v0, <vscale x 2 x double> %v1, <vscale x 2 x double> %v2, <vscale x 2 x double> %v3, <vscale x 2 x double> %v4, <vscale x 2 x double> %v5)11670  ret <vscale x 12 x double> %res11671}11672 11673define <vscale x 14 x half> @vector_interleave_nxv14f16_nxv2f16(<vscale x 2 x half> %v0, <vscale x 2 x half> %v1, <vscale x 2 x half> %v2, <vscale x 2 x half> %v3, <vscale x 2 x half> %v4, <vscale x 2 x half> %v5, <vscale x 2 x half> %v6) nounwind {11674; CHECK-LABEL: vector_interleave_nxv14f16_nxv2f16:11675; CHECK:       # %bb.0:11676; CHECK-NEXT:    addi sp, sp, -1611677; CHECK-NEXT:    csrr a0, vlenb11678; CHECK-NEXT:    slli a0, a0, 211679; CHECK-NEXT:    sub sp, sp, a011680; CHECK-NEXT:    addi a0, sp, 1611681; CHECK-NEXT:    csrr a1, vlenb11682; CHECK-NEXT:    srli a2, a1, 111683; CHECK-NEXT:    add a3, a0, a211684; CHECK-NEXT:    add a4, a3, a211685; CHECK-NEXT:    add a5, a4, a211686; CHECK-NEXT:    add a6, a5, a211687; CHECK-NEXT:    vsetvli a7, zero, e16, mf2, ta, ma11688; CHECK-NEXT:    vsseg7e16.v v8, (a0)11689; CHECK-NEXT:    add a7, a6, a211690; CHECK-NEXT:    vle16.v v8, (a7)11691; CHECK-NEXT:    vle16.v v10, (a6)11692; CHECK-NEXT:    srli a1, a1, 211693; CHECK-NEXT:    add a2, a7, a211694; CHECK-NEXT:    vle16.v v12, (a5)11695; CHECK-NEXT:    vsetvli a5, zero, e16, m1, ta, ma11696; CHECK-NEXT:    vslideup.vx v10, v8, a111697; CHECK-NEXT:    vsetvli a5, zero, e16, mf2, ta, ma11698; CHECK-NEXT:    vle16.v v11, (a2)11699; CHECK-NEXT:    vle16.v v9, (a4)11700; CHECK-NEXT:    vsetvli a2, zero, e16, m1, ta, ma11701; CHECK-NEXT:    vslideup.vx v9, v12, a111702; CHECK-NEXT:    vsetvli a2, zero, e16, mf2, ta, ma11703; CHECK-NEXT:    vle16.v v12, (a3)11704; CHECK-NEXT:    vle16.v v8, (a0)11705; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma11706; CHECK-NEXT:    vslideup.vx v8, v12, a111707; CHECK-NEXT:    csrr a0, vlenb11708; CHECK-NEXT:    slli a0, a0, 211709; CHECK-NEXT:    add sp, sp, a011710; CHECK-NEXT:    addi sp, sp, 1611711; CHECK-NEXT:    ret11712;11713; ZVBB-LABEL: vector_interleave_nxv14f16_nxv2f16:11714; ZVBB:       # %bb.0:11715; ZVBB-NEXT:    addi sp, sp, -1611716; ZVBB-NEXT:    csrr a0, vlenb11717; ZVBB-NEXT:    slli a0, a0, 211718; ZVBB-NEXT:    sub sp, sp, a011719; ZVBB-NEXT:    addi a0, sp, 1611720; ZVBB-NEXT:    csrr a1, vlenb11721; ZVBB-NEXT:    srli a2, a1, 111722; ZVBB-NEXT:    add a3, a0, a211723; ZVBB-NEXT:    add a4, a3, a211724; ZVBB-NEXT:    add a5, a4, a211725; ZVBB-NEXT:    add a6, a5, a211726; ZVBB-NEXT:    vsetvli a7, zero, e16, mf2, ta, ma11727; ZVBB-NEXT:    vsseg7e16.v v8, (a0)11728; ZVBB-NEXT:    add a7, a6, a211729; ZVBB-NEXT:    vle16.v v8, (a7)11730; ZVBB-NEXT:    vle16.v v10, (a6)11731; ZVBB-NEXT:    srli a1, a1, 211732; ZVBB-NEXT:    add a2, a7, a211733; ZVBB-NEXT:    vle16.v v12, (a5)11734; ZVBB-NEXT:    vsetvli a5, zero, e16, m1, ta, ma11735; ZVBB-NEXT:    vslideup.vx v10, v8, a111736; ZVBB-NEXT:    vsetvli a5, zero, e16, mf2, ta, ma11737; ZVBB-NEXT:    vle16.v v11, (a2)11738; ZVBB-NEXT:    vle16.v v9, (a4)11739; ZVBB-NEXT:    vsetvli a2, zero, e16, m1, ta, ma11740; ZVBB-NEXT:    vslideup.vx v9, v12, a111741; ZVBB-NEXT:    vsetvli a2, zero, e16, mf2, ta, ma11742; ZVBB-NEXT:    vle16.v v12, (a3)11743; ZVBB-NEXT:    vle16.v v8, (a0)11744; ZVBB-NEXT:    vsetvli a0, zero, e16, m1, ta, ma11745; ZVBB-NEXT:    vslideup.vx v8, v12, a111746; ZVBB-NEXT:    csrr a0, vlenb11747; ZVBB-NEXT:    slli a0, a0, 211748; ZVBB-NEXT:    add sp, sp, a011749; ZVBB-NEXT:    addi sp, sp, 1611750; ZVBB-NEXT:    ret11751  %res = call <vscale x 14 x half> @llvm.vector.interleave7.nxv14f16(<vscale x 2 x half> %v0, <vscale x 2 x half> %v1, <vscale x 2 x half> %v2, <vscale x 2 x half> %v3, <vscale x 2 x half> %v4, <vscale x 2 x half> %v5, <vscale x 2 x half> %v6)11752  ret <vscale x 14 x half> %res11753}11754 11755define <vscale x 28 x half> @vector_interleave_nxv28f16_nxv4f16(<vscale x 4 x half> %v0, <vscale x 4 x half> %v1, <vscale x 4 x half> %v2, <vscale x 4 x half> %v3, <vscale x 4 x half> %v4, <vscale x 4 x half> %v5, <vscale x 4 x half> %v6) nounwind {11756; CHECK-LABEL: vector_interleave_nxv28f16_nxv4f16:11757; CHECK:       # %bb.0:11758; CHECK-NEXT:    addi sp, sp, -1611759; CHECK-NEXT:    csrr a0, vlenb11760; CHECK-NEXT:    slli a1, a0, 311761; CHECK-NEXT:    sub a0, a1, a011762; CHECK-NEXT:    sub sp, sp, a011763; CHECK-NEXT:    addi a0, sp, 1611764; CHECK-NEXT:    csrr a1, vlenb11765; CHECK-NEXT:    add a2, a0, a111766; CHECK-NEXT:    add a3, a2, a111767; CHECK-NEXT:    vsetvli a4, zero, e16, m1, ta, ma11768; CHECK-NEXT:    vsseg7e16.v v8, (a0)11769; CHECK-NEXT:    vl1re16.v v10, (a3)11770; CHECK-NEXT:    add a3, a3, a111771; CHECK-NEXT:    vl1re16.v v11, (a3)11772; CHECK-NEXT:    add a3, a3, a111773; CHECK-NEXT:    vl1re16.v v8, (a0)11774; CHECK-NEXT:    add a0, a3, a111775; CHECK-NEXT:    vl1re16.v v9, (a2)11776; CHECK-NEXT:    vl1re16.v v12, (a3)11777; CHECK-NEXT:    vl1re16.v v13, (a0)11778; CHECK-NEXT:    add a0, a0, a111779; CHECK-NEXT:    vl1re16.v v14, (a0)11780; CHECK-NEXT:    csrr a0, vlenb11781; CHECK-NEXT:    slli a1, a0, 311782; CHECK-NEXT:    sub a0, a1, a011783; CHECK-NEXT:    add sp, sp, a011784; CHECK-NEXT:    addi sp, sp, 1611785; CHECK-NEXT:    ret11786;11787; ZVBB-LABEL: vector_interleave_nxv28f16_nxv4f16:11788; ZVBB:       # %bb.0:11789; ZVBB-NEXT:    addi sp, sp, -1611790; ZVBB-NEXT:    csrr a0, vlenb11791; ZVBB-NEXT:    slli a1, a0, 311792; ZVBB-NEXT:    sub a0, a1, a011793; ZVBB-NEXT:    sub sp, sp, a011794; ZVBB-NEXT:    addi a0, sp, 1611795; ZVBB-NEXT:    csrr a1, vlenb11796; ZVBB-NEXT:    add a2, a0, a111797; ZVBB-NEXT:    add a3, a2, a111798; ZVBB-NEXT:    vsetvli a4, zero, e16, m1, ta, ma11799; ZVBB-NEXT:    vsseg7e16.v v8, (a0)11800; ZVBB-NEXT:    vl1re16.v v10, (a3)11801; ZVBB-NEXT:    add a3, a3, a111802; ZVBB-NEXT:    vl1re16.v v11, (a3)11803; ZVBB-NEXT:    add a3, a3, a111804; ZVBB-NEXT:    vl1re16.v v8, (a0)11805; ZVBB-NEXT:    add a0, a3, a111806; ZVBB-NEXT:    vl1re16.v v9, (a2)11807; ZVBB-NEXT:    vl1re16.v v12, (a3)11808; ZVBB-NEXT:    vl1re16.v v13, (a0)11809; ZVBB-NEXT:    add a0, a0, a111810; ZVBB-NEXT:    vl1re16.v v14, (a0)11811; ZVBB-NEXT:    csrr a0, vlenb11812; ZVBB-NEXT:    slli a1, a0, 311813; ZVBB-NEXT:    sub a0, a1, a011814; ZVBB-NEXT:    add sp, sp, a011815; ZVBB-NEXT:    addi sp, sp, 1611816; ZVBB-NEXT:    ret11817  %res = call <vscale x 28 x half> @llvm.vector.interleave7.nxv28f16(<vscale x 4 x half> %v0, <vscale x 4 x half> %v1, <vscale x 4 x half> %v2, <vscale x 4 x half> %v3, <vscale x 4 x half> %v4, <vscale x 4 x half> %v5, <vscale x 4 x half> %v6)11818  ret <vscale x 28 x half> %res11819}11820 11821define <vscale x 56 x half> @vector_interleave_nxv56f16_nxv8f16(<vscale x 8 x half> %v0, <vscale x 8 x half> %v1, <vscale x 8 x half> %v2, <vscale x 8 x half> %v3, <vscale x 8 x half> %v4, <vscale x 8 x half> %v5, <vscale x 8 x half> %v6) nounwind {11822; RV32-LABEL: vector_interleave_nxv56f16_nxv8f16:11823; RV32:       # %bb.0:11824; RV32-NEXT:    addi sp, sp, -8011825; RV32-NEXT:    sw ra, 76(sp) # 4-byte Folded Spill11826; RV32-NEXT:    sw s0, 72(sp) # 4-byte Folded Spill11827; RV32-NEXT:    addi s0, sp, 8011828; RV32-NEXT:    csrr a0, vlenb11829; RV32-NEXT:    slli a0, a0, 511830; RV32-NEXT:    sub sp, sp, a011831; RV32-NEXT:    andi sp, sp, -6411832; RV32-NEXT:    vsetvli a0, zero, e16, m1, ta, ma11833; RV32-NEXT:    vmv2r.v v26, v2011834; RV32-NEXT:    addi a0, sp, 6411835; RV32-NEXT:    vmv2r.v v24, v1611836; RV32-NEXT:    vmv2r.v v22, v1211837; RV32-NEXT:    vmv2r.v v20, v811838; RV32-NEXT:    vmv1r.v v1, v2011839; RV32-NEXT:    vmv1r.v v3, v2211840; RV32-NEXT:    vmv1r.v v5, v2411841; RV32-NEXT:    vmv1r.v v7, v2611842; RV32-NEXT:    vmv1r.v v2, v1011843; RV32-NEXT:    csrr a1, vlenb11844; RV32-NEXT:    slli a2, a1, 311845; RV32-NEXT:    sub a1, a2, a111846; RV32-NEXT:    add a1, sp, a111847; RV32-NEXT:    addi a1, a1, 6411848; RV32-NEXT:    csrr a2, vlenb11849; RV32-NEXT:    vmv1r.v v4, v1411850; RV32-NEXT:    add a3, a0, a211851; RV32-NEXT:    add a4, a1, a211852; RV32-NEXT:    vmv1r.v v6, v1811853; RV32-NEXT:    add a5, a4, a211854; RV32-NEXT:    vmv1r.v v22, v1111855; RV32-NEXT:    add a6, a5, a211856; RV32-NEXT:    vmv1r.v v24, v1511857; RV32-NEXT:    vsseg7e16.v v1, (a0)11858; RV32-NEXT:    vmv1r.v v26, v1911859; RV32-NEXT:    vsseg7e16.v v21, (a1)11860; RV32-NEXT:    vl1re16.v v18, (a6)11861; RV32-NEXT:    add a6, a6, a211862; RV32-NEXT:    vl1re16.v v19, (a6)11863; RV32-NEXT:    add a6, a6, a211864; RV32-NEXT:    vl1re16.v v20, (a6)11865; RV32-NEXT:    add a6, a6, a211866; RV32-NEXT:    vl1re16.v v21, (a6)11867; RV32-NEXT:    add a6, a3, a211868; RV32-NEXT:    vl1re16.v v10, (a6)11869; RV32-NEXT:    add a6, a6, a211870; RV32-NEXT:    vl1re16.v v11, (a6)11871; RV32-NEXT:    vl1re16.v v8, (a0)11872; RV32-NEXT:    vl1re16.v v16, (a4)11873; RV32-NEXT:    vl1re16.v v9, (a3)11874; RV32-NEXT:    csrr a0, vlenb11875; RV32-NEXT:    li a3, 1411876; RV32-NEXT:    mul a0, a0, a311877; RV32-NEXT:    add a0, sp, a011878; RV32-NEXT:    addi a0, a0, 6411879; RV32-NEXT:    vl1re16.v v17, (a5)11880; RV32-NEXT:    slli a3, a2, 211881; RV32-NEXT:    add a6, a6, a211882; RV32-NEXT:    vl1re16.v v12, (a6)11883; RV32-NEXT:    add a6, a6, a211884; RV32-NEXT:    vl1re16.v v13, (a6)11885; RV32-NEXT:    add a6, a6, a211886; RV32-NEXT:    slli a2, a2, 311887; RV32-NEXT:    add a3, a2, a311888; RV32-NEXT:    add a2, a0, a211889; RV32-NEXT:    vl1re16.v v14, (a6)11890; RV32-NEXT:    vl1re16.v v15, (a1)11891; RV32-NEXT:    add a3, a0, a311892; RV32-NEXT:    vs2r.v v20, (a3)11893; RV32-NEXT:    vs4r.v v16, (a2)11894; RV32-NEXT:    vs8r.v v8, (a0)11895; RV32-NEXT:    vl8re16.v v16, (a2)11896; RV32-NEXT:    vl8re16.v v8, (a0)11897; RV32-NEXT:    addi sp, s0, -8011898; RV32-NEXT:    lw ra, 76(sp) # 4-byte Folded Reload11899; RV32-NEXT:    lw s0, 72(sp) # 4-byte Folded Reload11900; RV32-NEXT:    addi sp, sp, 8011901; RV32-NEXT:    ret11902;11903; RV64-LABEL: vector_interleave_nxv56f16_nxv8f16:11904; RV64:       # %bb.0:11905; RV64-NEXT:    addi sp, sp, -8011906; RV64-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill11907; RV64-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill11908; RV64-NEXT:    addi s0, sp, 8011909; RV64-NEXT:    csrr a0, vlenb11910; RV64-NEXT:    slli a0, a0, 511911; RV64-NEXT:    sub sp, sp, a011912; RV64-NEXT:    andi sp, sp, -6411913; RV64-NEXT:    vsetvli a0, zero, e16, m1, ta, ma11914; RV64-NEXT:    vmv2r.v v26, v2011915; RV64-NEXT:    addi a0, sp, 6411916; RV64-NEXT:    vmv2r.v v24, v1611917; RV64-NEXT:    vmv2r.v v22, v1211918; RV64-NEXT:    vmv2r.v v20, v811919; RV64-NEXT:    vmv1r.v v1, v2011920; RV64-NEXT:    vmv1r.v v3, v2211921; RV64-NEXT:    vmv1r.v v5, v2411922; RV64-NEXT:    vmv1r.v v7, v2611923; RV64-NEXT:    vmv1r.v v2, v1011924; RV64-NEXT:    csrr a1, vlenb11925; RV64-NEXT:    slli a2, a1, 311926; RV64-NEXT:    sub a1, a2, a111927; RV64-NEXT:    add a1, sp, a111928; RV64-NEXT:    addi a1, a1, 6411929; RV64-NEXT:    csrr a2, vlenb11930; RV64-NEXT:    vmv1r.v v4, v1411931; RV64-NEXT:    add a3, a0, a211932; RV64-NEXT:    add a4, a1, a211933; RV64-NEXT:    vmv1r.v v6, v1811934; RV64-NEXT:    add a5, a4, a211935; RV64-NEXT:    vmv1r.v v22, v1111936; RV64-NEXT:    add a6, a5, a211937; RV64-NEXT:    vmv1r.v v24, v1511938; RV64-NEXT:    vsseg7e16.v v1, (a0)11939; RV64-NEXT:    vmv1r.v v26, v1911940; RV64-NEXT:    vsseg7e16.v v21, (a1)11941; RV64-NEXT:    vl1re16.v v18, (a6)11942; RV64-NEXT:    add a6, a6, a211943; RV64-NEXT:    vl1re16.v v19, (a6)11944; RV64-NEXT:    add a6, a6, a211945; RV64-NEXT:    vl1re16.v v20, (a6)11946; RV64-NEXT:    add a6, a6, a211947; RV64-NEXT:    vl1re16.v v21, (a6)11948; RV64-NEXT:    add a6, a3, a211949; RV64-NEXT:    vl1re16.v v10, (a6)11950; RV64-NEXT:    add a6, a6, a211951; RV64-NEXT:    vl1re16.v v11, (a6)11952; RV64-NEXT:    vl1re16.v v8, (a0)11953; RV64-NEXT:    vl1re16.v v16, (a4)11954; RV64-NEXT:    vl1re16.v v9, (a3)11955; RV64-NEXT:    csrr a0, vlenb11956; RV64-NEXT:    li a3, 1411957; RV64-NEXT:    mul a0, a0, a311958; RV64-NEXT:    add a0, sp, a011959; RV64-NEXT:    addi a0, a0, 6411960; RV64-NEXT:    vl1re16.v v17, (a5)11961; RV64-NEXT:    slli a3, a2, 211962; RV64-NEXT:    add a6, a6, a211963; RV64-NEXT:    vl1re16.v v12, (a6)11964; RV64-NEXT:    add a6, a6, a211965; RV64-NEXT:    vl1re16.v v13, (a6)11966; RV64-NEXT:    add a6, a6, a211967; RV64-NEXT:    slli a2, a2, 311968; RV64-NEXT:    add a3, a2, a311969; RV64-NEXT:    add a2, a0, a211970; RV64-NEXT:    vl1re16.v v14, (a6)11971; RV64-NEXT:    vl1re16.v v15, (a1)11972; RV64-NEXT:    add a3, a0, a311973; RV64-NEXT:    vs2r.v v20, (a3)11974; RV64-NEXT:    vs4r.v v16, (a2)11975; RV64-NEXT:    vs8r.v v8, (a0)11976; RV64-NEXT:    vl8re16.v v16, (a2)11977; RV64-NEXT:    vl8re16.v v8, (a0)11978; RV64-NEXT:    addi sp, s0, -8011979; RV64-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload11980; RV64-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload11981; RV64-NEXT:    addi sp, sp, 8011982; RV64-NEXT:    ret11983;11984; ZVBB-RV32-LABEL: vector_interleave_nxv56f16_nxv8f16:11985; ZVBB-RV32:       # %bb.0:11986; ZVBB-RV32-NEXT:    addi sp, sp, -8011987; ZVBB-RV32-NEXT:    sw ra, 76(sp) # 4-byte Folded Spill11988; ZVBB-RV32-NEXT:    sw s0, 72(sp) # 4-byte Folded Spill11989; ZVBB-RV32-NEXT:    addi s0, sp, 8011990; ZVBB-RV32-NEXT:    csrr a0, vlenb11991; ZVBB-RV32-NEXT:    slli a0, a0, 511992; ZVBB-RV32-NEXT:    sub sp, sp, a011993; ZVBB-RV32-NEXT:    andi sp, sp, -6411994; ZVBB-RV32-NEXT:    vsetvli a0, zero, e16, m1, ta, ma11995; ZVBB-RV32-NEXT:    vmv2r.v v26, v2011996; ZVBB-RV32-NEXT:    addi a0, sp, 6411997; ZVBB-RV32-NEXT:    vmv2r.v v24, v1611998; ZVBB-RV32-NEXT:    vmv2r.v v22, v1211999; ZVBB-RV32-NEXT:    vmv2r.v v20, v812000; ZVBB-RV32-NEXT:    vmv1r.v v1, v2012001; ZVBB-RV32-NEXT:    vmv1r.v v3, v2212002; ZVBB-RV32-NEXT:    vmv1r.v v5, v2412003; ZVBB-RV32-NEXT:    vmv1r.v v7, v2612004; ZVBB-RV32-NEXT:    vmv1r.v v2, v1012005; ZVBB-RV32-NEXT:    csrr a1, vlenb12006; ZVBB-RV32-NEXT:    slli a2, a1, 312007; ZVBB-RV32-NEXT:    sub a1, a2, a112008; ZVBB-RV32-NEXT:    add a1, sp, a112009; ZVBB-RV32-NEXT:    addi a1, a1, 6412010; ZVBB-RV32-NEXT:    csrr a2, vlenb12011; ZVBB-RV32-NEXT:    vmv1r.v v4, v1412012; ZVBB-RV32-NEXT:    add a3, a0, a212013; ZVBB-RV32-NEXT:    add a4, a1, a212014; ZVBB-RV32-NEXT:    vmv1r.v v6, v1812015; ZVBB-RV32-NEXT:    add a5, a4, a212016; ZVBB-RV32-NEXT:    vmv1r.v v22, v1112017; ZVBB-RV32-NEXT:    add a6, a5, a212018; ZVBB-RV32-NEXT:    vmv1r.v v24, v1512019; ZVBB-RV32-NEXT:    vsseg7e16.v v1, (a0)12020; ZVBB-RV32-NEXT:    vmv1r.v v26, v1912021; ZVBB-RV32-NEXT:    vsseg7e16.v v21, (a1)12022; ZVBB-RV32-NEXT:    vl1re16.v v18, (a6)12023; ZVBB-RV32-NEXT:    add a6, a6, a212024; ZVBB-RV32-NEXT:    vl1re16.v v19, (a6)12025; ZVBB-RV32-NEXT:    add a6, a6, a212026; ZVBB-RV32-NEXT:    vl1re16.v v20, (a6)12027; ZVBB-RV32-NEXT:    add a6, a6, a212028; ZVBB-RV32-NEXT:    vl1re16.v v21, (a6)12029; ZVBB-RV32-NEXT:    add a6, a3, a212030; ZVBB-RV32-NEXT:    vl1re16.v v10, (a6)12031; ZVBB-RV32-NEXT:    add a6, a6, a212032; ZVBB-RV32-NEXT:    vl1re16.v v11, (a6)12033; ZVBB-RV32-NEXT:    vl1re16.v v8, (a0)12034; ZVBB-RV32-NEXT:    vl1re16.v v16, (a4)12035; ZVBB-RV32-NEXT:    vl1re16.v v9, (a3)12036; ZVBB-RV32-NEXT:    csrr a0, vlenb12037; ZVBB-RV32-NEXT:    li a3, 1412038; ZVBB-RV32-NEXT:    mul a0, a0, a312039; ZVBB-RV32-NEXT:    add a0, sp, a012040; ZVBB-RV32-NEXT:    addi a0, a0, 6412041; ZVBB-RV32-NEXT:    vl1re16.v v17, (a5)12042; ZVBB-RV32-NEXT:    slli a3, a2, 212043; ZVBB-RV32-NEXT:    add a6, a6, a212044; ZVBB-RV32-NEXT:    vl1re16.v v12, (a6)12045; ZVBB-RV32-NEXT:    add a6, a6, a212046; ZVBB-RV32-NEXT:    vl1re16.v v13, (a6)12047; ZVBB-RV32-NEXT:    add a6, a6, a212048; ZVBB-RV32-NEXT:    slli a2, a2, 312049; ZVBB-RV32-NEXT:    add a3, a2, a312050; ZVBB-RV32-NEXT:    add a2, a0, a212051; ZVBB-RV32-NEXT:    vl1re16.v v14, (a6)12052; ZVBB-RV32-NEXT:    vl1re16.v v15, (a1)12053; ZVBB-RV32-NEXT:    add a3, a0, a312054; ZVBB-RV32-NEXT:    vs2r.v v20, (a3)12055; ZVBB-RV32-NEXT:    vs4r.v v16, (a2)12056; ZVBB-RV32-NEXT:    vs8r.v v8, (a0)12057; ZVBB-RV32-NEXT:    vl8re16.v v16, (a2)12058; ZVBB-RV32-NEXT:    vl8re16.v v8, (a0)12059; ZVBB-RV32-NEXT:    addi sp, s0, -8012060; ZVBB-RV32-NEXT:    lw ra, 76(sp) # 4-byte Folded Reload12061; ZVBB-RV32-NEXT:    lw s0, 72(sp) # 4-byte Folded Reload12062; ZVBB-RV32-NEXT:    addi sp, sp, 8012063; ZVBB-RV32-NEXT:    ret12064;12065; ZVBB-RV64-LABEL: vector_interleave_nxv56f16_nxv8f16:12066; ZVBB-RV64:       # %bb.0:12067; ZVBB-RV64-NEXT:    addi sp, sp, -8012068; ZVBB-RV64-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill12069; ZVBB-RV64-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill12070; ZVBB-RV64-NEXT:    addi s0, sp, 8012071; ZVBB-RV64-NEXT:    csrr a0, vlenb12072; ZVBB-RV64-NEXT:    slli a0, a0, 512073; ZVBB-RV64-NEXT:    sub sp, sp, a012074; ZVBB-RV64-NEXT:    andi sp, sp, -6412075; ZVBB-RV64-NEXT:    vsetvli a0, zero, e16, m1, ta, ma12076; ZVBB-RV64-NEXT:    vmv2r.v v26, v2012077; ZVBB-RV64-NEXT:    addi a0, sp, 6412078; ZVBB-RV64-NEXT:    vmv2r.v v24, v1612079; ZVBB-RV64-NEXT:    vmv2r.v v22, v1212080; ZVBB-RV64-NEXT:    vmv2r.v v20, v812081; ZVBB-RV64-NEXT:    vmv1r.v v1, v2012082; ZVBB-RV64-NEXT:    vmv1r.v v3, v2212083; ZVBB-RV64-NEXT:    vmv1r.v v5, v2412084; ZVBB-RV64-NEXT:    vmv1r.v v7, v2612085; ZVBB-RV64-NEXT:    vmv1r.v v2, v1012086; ZVBB-RV64-NEXT:    csrr a1, vlenb12087; ZVBB-RV64-NEXT:    slli a2, a1, 312088; ZVBB-RV64-NEXT:    sub a1, a2, a112089; ZVBB-RV64-NEXT:    add a1, sp, a112090; ZVBB-RV64-NEXT:    addi a1, a1, 6412091; ZVBB-RV64-NEXT:    csrr a2, vlenb12092; ZVBB-RV64-NEXT:    vmv1r.v v4, v1412093; ZVBB-RV64-NEXT:    add a3, a0, a212094; ZVBB-RV64-NEXT:    add a4, a1, a212095; ZVBB-RV64-NEXT:    vmv1r.v v6, v1812096; ZVBB-RV64-NEXT:    add a5, a4, a212097; ZVBB-RV64-NEXT:    vmv1r.v v22, v1112098; ZVBB-RV64-NEXT:    add a6, a5, a212099; ZVBB-RV64-NEXT:    vmv1r.v v24, v1512100; ZVBB-RV64-NEXT:    vsseg7e16.v v1, (a0)12101; ZVBB-RV64-NEXT:    vmv1r.v v26, v1912102; ZVBB-RV64-NEXT:    vsseg7e16.v v21, (a1)12103; ZVBB-RV64-NEXT:    vl1re16.v v18, (a6)12104; ZVBB-RV64-NEXT:    add a6, a6, a212105; ZVBB-RV64-NEXT:    vl1re16.v v19, (a6)12106; ZVBB-RV64-NEXT:    add a6, a6, a212107; ZVBB-RV64-NEXT:    vl1re16.v v20, (a6)12108; ZVBB-RV64-NEXT:    add a6, a6, a212109; ZVBB-RV64-NEXT:    vl1re16.v v21, (a6)12110; ZVBB-RV64-NEXT:    add a6, a3, a212111; ZVBB-RV64-NEXT:    vl1re16.v v10, (a6)12112; ZVBB-RV64-NEXT:    add a6, a6, a212113; ZVBB-RV64-NEXT:    vl1re16.v v11, (a6)12114; ZVBB-RV64-NEXT:    vl1re16.v v8, (a0)12115; ZVBB-RV64-NEXT:    vl1re16.v v16, (a4)12116; ZVBB-RV64-NEXT:    vl1re16.v v9, (a3)12117; ZVBB-RV64-NEXT:    csrr a0, vlenb12118; ZVBB-RV64-NEXT:    li a3, 1412119; ZVBB-RV64-NEXT:    mul a0, a0, a312120; ZVBB-RV64-NEXT:    add a0, sp, a012121; ZVBB-RV64-NEXT:    addi a0, a0, 6412122; ZVBB-RV64-NEXT:    vl1re16.v v17, (a5)12123; ZVBB-RV64-NEXT:    slli a3, a2, 212124; ZVBB-RV64-NEXT:    add a6, a6, a212125; ZVBB-RV64-NEXT:    vl1re16.v v12, (a6)12126; ZVBB-RV64-NEXT:    add a6, a6, a212127; ZVBB-RV64-NEXT:    vl1re16.v v13, (a6)12128; ZVBB-RV64-NEXT:    add a6, a6, a212129; ZVBB-RV64-NEXT:    slli a2, a2, 312130; ZVBB-RV64-NEXT:    add a3, a2, a312131; ZVBB-RV64-NEXT:    add a2, a0, a212132; ZVBB-RV64-NEXT:    vl1re16.v v14, (a6)12133; ZVBB-RV64-NEXT:    vl1re16.v v15, (a1)12134; ZVBB-RV64-NEXT:    add a3, a0, a312135; ZVBB-RV64-NEXT:    vs2r.v v20, (a3)12136; ZVBB-RV64-NEXT:    vs4r.v v16, (a2)12137; ZVBB-RV64-NEXT:    vs8r.v v8, (a0)12138; ZVBB-RV64-NEXT:    vl8re16.v v16, (a2)12139; ZVBB-RV64-NEXT:    vl8re16.v v8, (a0)12140; ZVBB-RV64-NEXT:    addi sp, s0, -8012141; ZVBB-RV64-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload12142; ZVBB-RV64-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload12143; ZVBB-RV64-NEXT:    addi sp, sp, 8012144; ZVBB-RV64-NEXT:    ret12145;12146; ZIP-LABEL: vector_interleave_nxv56f16_nxv8f16:12147; ZIP:       # %bb.0:12148; ZIP-NEXT:    addi sp, sp, -8012149; ZIP-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill12150; ZIP-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill12151; ZIP-NEXT:    addi s0, sp, 8012152; ZIP-NEXT:    csrr a0, vlenb12153; ZIP-NEXT:    slli a0, a0, 512154; ZIP-NEXT:    sub sp, sp, a012155; ZIP-NEXT:    andi sp, sp, -6412156; ZIP-NEXT:    vsetvli a0, zero, e16, m1, ta, ma12157; ZIP-NEXT:    vmv2r.v v26, v2012158; ZIP-NEXT:    addi a0, sp, 6412159; ZIP-NEXT:    vmv2r.v v24, v1612160; ZIP-NEXT:    vmv2r.v v22, v1212161; ZIP-NEXT:    vmv2r.v v20, v812162; ZIP-NEXT:    vmv1r.v v1, v2012163; ZIP-NEXT:    vmv1r.v v3, v2212164; ZIP-NEXT:    vmv1r.v v5, v2412165; ZIP-NEXT:    vmv1r.v v7, v2612166; ZIP-NEXT:    vmv1r.v v2, v1012167; ZIP-NEXT:    csrr a1, vlenb12168; ZIP-NEXT:    slli a2, a1, 312169; ZIP-NEXT:    sub a1, a2, a112170; ZIP-NEXT:    add a1, sp, a112171; ZIP-NEXT:    addi a1, a1, 6412172; ZIP-NEXT:    csrr a2, vlenb12173; ZIP-NEXT:    vmv1r.v v4, v1412174; ZIP-NEXT:    add a3, a0, a212175; ZIP-NEXT:    add a4, a1, a212176; ZIP-NEXT:    vmv1r.v v6, v1812177; ZIP-NEXT:    add a5, a4, a212178; ZIP-NEXT:    vmv1r.v v22, v1112179; ZIP-NEXT:    add a6, a5, a212180; ZIP-NEXT:    vmv1r.v v24, v1512181; ZIP-NEXT:    vsseg7e16.v v1, (a0)12182; ZIP-NEXT:    vmv1r.v v26, v1912183; ZIP-NEXT:    vsseg7e16.v v21, (a1)12184; ZIP-NEXT:    vl1re16.v v18, (a6)12185; ZIP-NEXT:    add a6, a6, a212186; ZIP-NEXT:    vl1re16.v v19, (a6)12187; ZIP-NEXT:    add a6, a6, a212188; ZIP-NEXT:    vl1re16.v v20, (a6)12189; ZIP-NEXT:    add a6, a6, a212190; ZIP-NEXT:    vl1re16.v v21, (a6)12191; ZIP-NEXT:    add a6, a3, a212192; ZIP-NEXT:    vl1re16.v v10, (a6)12193; ZIP-NEXT:    add a6, a6, a212194; ZIP-NEXT:    vl1re16.v v11, (a6)12195; ZIP-NEXT:    vl1re16.v v8, (a0)12196; ZIP-NEXT:    vl1re16.v v16, (a4)12197; ZIP-NEXT:    vl1re16.v v9, (a3)12198; ZIP-NEXT:    csrr a0, vlenb12199; ZIP-NEXT:    li a3, 1412200; ZIP-NEXT:    mul a0, a0, a312201; ZIP-NEXT:    add a0, sp, a012202; ZIP-NEXT:    addi a0, a0, 6412203; ZIP-NEXT:    vl1re16.v v17, (a5)12204; ZIP-NEXT:    slli a3, a2, 212205; ZIP-NEXT:    add a6, a6, a212206; ZIP-NEXT:    vl1re16.v v12, (a6)12207; ZIP-NEXT:    add a6, a6, a212208; ZIP-NEXT:    vl1re16.v v13, (a6)12209; ZIP-NEXT:    add a6, a6, a212210; ZIP-NEXT:    slli a2, a2, 312211; ZIP-NEXT:    add a3, a2, a312212; ZIP-NEXT:    add a2, a0, a212213; ZIP-NEXT:    vl1re16.v v14, (a6)12214; ZIP-NEXT:    vl1re16.v v15, (a1)12215; ZIP-NEXT:    add a3, a0, a312216; ZIP-NEXT:    vs2r.v v20, (a3)12217; ZIP-NEXT:    vs4r.v v16, (a2)12218; ZIP-NEXT:    vs8r.v v8, (a0)12219; ZIP-NEXT:    vl8re16.v v16, (a2)12220; ZIP-NEXT:    vl8re16.v v8, (a0)12221; ZIP-NEXT:    addi sp, s0, -8012222; ZIP-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload12223; ZIP-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload12224; ZIP-NEXT:    addi sp, sp, 8012225; ZIP-NEXT:    ret12226  %res = call <vscale x 56 x half> @llvm.vector.interleave7.nxv56f16(<vscale x 8 x half> %v0, <vscale x 8 x half> %v1, <vscale x 8 x half> %v2, <vscale x 8 x half> %v3, <vscale x 8 x half> %v4, <vscale x 8 x half> %v5, <vscale x 8 x half> %v6)12227  ret <vscale x 56 x half> %res12228}12229 12230define <vscale x 14 x bfloat> @vector_interleave_nxv14bf16_nxv2bf16(<vscale x 2 x bfloat> %v0, <vscale x 2 x bfloat> %v1, <vscale x 2 x bfloat> %v2, <vscale x 2 x bfloat> %v3, <vscale x 2 x bfloat> %v4, <vscale x 2 x bfloat> %v5, <vscale x 2 x bfloat> %v6) nounwind {12231; CHECK-LABEL: vector_interleave_nxv14bf16_nxv2bf16:12232; CHECK:       # %bb.0:12233; CHECK-NEXT:    addi sp, sp, -1612234; CHECK-NEXT:    csrr a0, vlenb12235; CHECK-NEXT:    slli a0, a0, 212236; CHECK-NEXT:    sub sp, sp, a012237; CHECK-NEXT:    addi a0, sp, 1612238; CHECK-NEXT:    csrr a1, vlenb12239; CHECK-NEXT:    srli a2, a1, 112240; CHECK-NEXT:    add a3, a0, a212241; CHECK-NEXT:    add a4, a3, a212242; CHECK-NEXT:    add a5, a4, a212243; CHECK-NEXT:    add a6, a5, a212244; CHECK-NEXT:    vsetvli a7, zero, e16, mf2, ta, ma12245; CHECK-NEXT:    vsseg7e16.v v8, (a0)12246; CHECK-NEXT:    add a7, a6, a212247; CHECK-NEXT:    vle16.v v8, (a7)12248; CHECK-NEXT:    vle16.v v10, (a6)12249; CHECK-NEXT:    srli a1, a1, 212250; CHECK-NEXT:    add a2, a7, a212251; CHECK-NEXT:    vle16.v v12, (a5)12252; CHECK-NEXT:    vsetvli a5, zero, e16, m1, ta, ma12253; CHECK-NEXT:    vslideup.vx v10, v8, a112254; CHECK-NEXT:    vsetvli a5, zero, e16, mf2, ta, ma12255; CHECK-NEXT:    vle16.v v11, (a2)12256; CHECK-NEXT:    vle16.v v9, (a4)12257; CHECK-NEXT:    vsetvli a2, zero, e16, m1, ta, ma12258; CHECK-NEXT:    vslideup.vx v9, v12, a112259; CHECK-NEXT:    vsetvli a2, zero, e16, mf2, ta, ma12260; CHECK-NEXT:    vle16.v v12, (a3)12261; CHECK-NEXT:    vle16.v v8, (a0)12262; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma12263; CHECK-NEXT:    vslideup.vx v8, v12, a112264; CHECK-NEXT:    csrr a0, vlenb12265; CHECK-NEXT:    slli a0, a0, 212266; CHECK-NEXT:    add sp, sp, a012267; CHECK-NEXT:    addi sp, sp, 1612268; CHECK-NEXT:    ret12269;12270; ZVBB-LABEL: vector_interleave_nxv14bf16_nxv2bf16:12271; ZVBB:       # %bb.0:12272; ZVBB-NEXT:    addi sp, sp, -1612273; ZVBB-NEXT:    csrr a0, vlenb12274; ZVBB-NEXT:    slli a0, a0, 212275; ZVBB-NEXT:    sub sp, sp, a012276; ZVBB-NEXT:    addi a0, sp, 1612277; ZVBB-NEXT:    csrr a1, vlenb12278; ZVBB-NEXT:    srli a2, a1, 112279; ZVBB-NEXT:    add a3, a0, a212280; ZVBB-NEXT:    add a4, a3, a212281; ZVBB-NEXT:    add a5, a4, a212282; ZVBB-NEXT:    add a6, a5, a212283; ZVBB-NEXT:    vsetvli a7, zero, e16, mf2, ta, ma12284; ZVBB-NEXT:    vsseg7e16.v v8, (a0)12285; ZVBB-NEXT:    add a7, a6, a212286; ZVBB-NEXT:    vle16.v v8, (a7)12287; ZVBB-NEXT:    vle16.v v10, (a6)12288; ZVBB-NEXT:    srli a1, a1, 212289; ZVBB-NEXT:    add a2, a7, a212290; ZVBB-NEXT:    vle16.v v12, (a5)12291; ZVBB-NEXT:    vsetvli a5, zero, e16, m1, ta, ma12292; ZVBB-NEXT:    vslideup.vx v10, v8, a112293; ZVBB-NEXT:    vsetvli a5, zero, e16, mf2, ta, ma12294; ZVBB-NEXT:    vle16.v v11, (a2)12295; ZVBB-NEXT:    vle16.v v9, (a4)12296; ZVBB-NEXT:    vsetvli a2, zero, e16, m1, ta, ma12297; ZVBB-NEXT:    vslideup.vx v9, v12, a112298; ZVBB-NEXT:    vsetvli a2, zero, e16, mf2, ta, ma12299; ZVBB-NEXT:    vle16.v v12, (a3)12300; ZVBB-NEXT:    vle16.v v8, (a0)12301; ZVBB-NEXT:    vsetvli a0, zero, e16, m1, ta, ma12302; ZVBB-NEXT:    vslideup.vx v8, v12, a112303; ZVBB-NEXT:    csrr a0, vlenb12304; ZVBB-NEXT:    slli a0, a0, 212305; ZVBB-NEXT:    add sp, sp, a012306; ZVBB-NEXT:    addi sp, sp, 1612307; ZVBB-NEXT:    ret12308  %res = call <vscale x 14 x bfloat> @llvm.vector.interleave7.nxv14bf16(<vscale x 2 x bfloat> %v0, <vscale x 2 x bfloat> %v1, <vscale x 2 x bfloat> %v2, <vscale x 2 x bfloat> %v3, <vscale x 2 x bfloat> %v4, <vscale x 2 x bfloat> %v5, <vscale x 2 x bfloat> %v6)12309  ret <vscale x 14 x bfloat> %res12310}12311 12312define <vscale x 28 x bfloat> @vector_interleave_nxv28bf16_nxv4bf16(<vscale x 4 x bfloat> %v0, <vscale x 4 x bfloat> %v1, <vscale x 4 x bfloat> %v2, <vscale x 4 x bfloat> %v3, <vscale x 4 x bfloat> %v4, <vscale x 4 x bfloat> %v5, <vscale x 4 x bfloat> %v6) nounwind {12313; CHECK-LABEL: vector_interleave_nxv28bf16_nxv4bf16:12314; CHECK:       # %bb.0:12315; CHECK-NEXT:    addi sp, sp, -1612316; CHECK-NEXT:    csrr a0, vlenb12317; CHECK-NEXT:    slli a1, a0, 312318; CHECK-NEXT:    sub a0, a1, a012319; CHECK-NEXT:    sub sp, sp, a012320; CHECK-NEXT:    addi a0, sp, 1612321; CHECK-NEXT:    csrr a1, vlenb12322; CHECK-NEXT:    add a2, a0, a112323; CHECK-NEXT:    add a3, a2, a112324; CHECK-NEXT:    vsetvli a4, zero, e16, m1, ta, ma12325; CHECK-NEXT:    vsseg7e16.v v8, (a0)12326; CHECK-NEXT:    vl1re16.v v10, (a3)12327; CHECK-NEXT:    add a3, a3, a112328; CHECK-NEXT:    vl1re16.v v11, (a3)12329; CHECK-NEXT:    add a3, a3, a112330; CHECK-NEXT:    vl1re16.v v8, (a0)12331; CHECK-NEXT:    add a0, a3, a112332; CHECK-NEXT:    vl1re16.v v9, (a2)12333; CHECK-NEXT:    vl1re16.v v12, (a3)12334; CHECK-NEXT:    vl1re16.v v13, (a0)12335; CHECK-NEXT:    add a0, a0, a112336; CHECK-NEXT:    vl1re16.v v14, (a0)12337; CHECK-NEXT:    csrr a0, vlenb12338; CHECK-NEXT:    slli a1, a0, 312339; CHECK-NEXT:    sub a0, a1, a012340; CHECK-NEXT:    add sp, sp, a012341; CHECK-NEXT:    addi sp, sp, 1612342; CHECK-NEXT:    ret12343;12344; ZVBB-LABEL: vector_interleave_nxv28bf16_nxv4bf16:12345; ZVBB:       # %bb.0:12346; ZVBB-NEXT:    addi sp, sp, -1612347; ZVBB-NEXT:    csrr a0, vlenb12348; ZVBB-NEXT:    slli a1, a0, 312349; ZVBB-NEXT:    sub a0, a1, a012350; ZVBB-NEXT:    sub sp, sp, a012351; ZVBB-NEXT:    addi a0, sp, 1612352; ZVBB-NEXT:    csrr a1, vlenb12353; ZVBB-NEXT:    add a2, a0, a112354; ZVBB-NEXT:    add a3, a2, a112355; ZVBB-NEXT:    vsetvli a4, zero, e16, m1, ta, ma12356; ZVBB-NEXT:    vsseg7e16.v v8, (a0)12357; ZVBB-NEXT:    vl1re16.v v10, (a3)12358; ZVBB-NEXT:    add a3, a3, a112359; ZVBB-NEXT:    vl1re16.v v11, (a3)12360; ZVBB-NEXT:    add a3, a3, a112361; ZVBB-NEXT:    vl1re16.v v8, (a0)12362; ZVBB-NEXT:    add a0, a3, a112363; ZVBB-NEXT:    vl1re16.v v9, (a2)12364; ZVBB-NEXT:    vl1re16.v v12, (a3)12365; ZVBB-NEXT:    vl1re16.v v13, (a0)12366; ZVBB-NEXT:    add a0, a0, a112367; ZVBB-NEXT:    vl1re16.v v14, (a0)12368; ZVBB-NEXT:    csrr a0, vlenb12369; ZVBB-NEXT:    slli a1, a0, 312370; ZVBB-NEXT:    sub a0, a1, a012371; ZVBB-NEXT:    add sp, sp, a012372; ZVBB-NEXT:    addi sp, sp, 1612373; ZVBB-NEXT:    ret12374  %res = call <vscale x 28 x bfloat> @llvm.vector.interleave7.nxv28bf16(<vscale x 4 x bfloat> %v0, <vscale x 4 x bfloat> %v1, <vscale x 4 x bfloat> %v2, <vscale x 4 x bfloat> %v3, <vscale x 4 x bfloat> %v4, <vscale x 4 x bfloat> %v5, <vscale x 4 x bfloat> %v6)12375  ret <vscale x 28 x bfloat> %res12376}12377 12378define <vscale x 56 x bfloat> @vector_interleave_nxv56bf16_nxv8bf16(<vscale x 8 x bfloat> %v0, <vscale x 8 x bfloat> %v1, <vscale x 8 x bfloat> %v2, <vscale x 8 x bfloat> %v3, <vscale x 8 x bfloat> %v4, <vscale x 8 x bfloat> %v5, <vscale x 8 x bfloat> %v6) nounwind {12379; RV32-LABEL: vector_interleave_nxv56bf16_nxv8bf16:12380; RV32:       # %bb.0:12381; RV32-NEXT:    addi sp, sp, -8012382; RV32-NEXT:    sw ra, 76(sp) # 4-byte Folded Spill12383; RV32-NEXT:    sw s0, 72(sp) # 4-byte Folded Spill12384; RV32-NEXT:    addi s0, sp, 8012385; RV32-NEXT:    csrr a0, vlenb12386; RV32-NEXT:    slli a0, a0, 512387; RV32-NEXT:    sub sp, sp, a012388; RV32-NEXT:    andi sp, sp, -6412389; RV32-NEXT:    vsetvli a0, zero, e16, m1, ta, ma12390; RV32-NEXT:    vmv2r.v v26, v2012391; RV32-NEXT:    addi a0, sp, 6412392; RV32-NEXT:    vmv2r.v v24, v1612393; RV32-NEXT:    vmv2r.v v22, v1212394; RV32-NEXT:    vmv2r.v v20, v812395; RV32-NEXT:    vmv1r.v v1, v2012396; RV32-NEXT:    vmv1r.v v3, v2212397; RV32-NEXT:    vmv1r.v v5, v2412398; RV32-NEXT:    vmv1r.v v7, v2612399; RV32-NEXT:    vmv1r.v v2, v1012400; RV32-NEXT:    csrr a1, vlenb12401; RV32-NEXT:    slli a2, a1, 312402; RV32-NEXT:    sub a1, a2, a112403; RV32-NEXT:    add a1, sp, a112404; RV32-NEXT:    addi a1, a1, 6412405; RV32-NEXT:    csrr a2, vlenb12406; RV32-NEXT:    vmv1r.v v4, v1412407; RV32-NEXT:    add a3, a0, a212408; RV32-NEXT:    add a4, a1, a212409; RV32-NEXT:    vmv1r.v v6, v1812410; RV32-NEXT:    add a5, a4, a212411; RV32-NEXT:    vmv1r.v v22, v1112412; RV32-NEXT:    add a6, a5, a212413; RV32-NEXT:    vmv1r.v v24, v1512414; RV32-NEXT:    vsseg7e16.v v1, (a0)12415; RV32-NEXT:    vmv1r.v v26, v1912416; RV32-NEXT:    vsseg7e16.v v21, (a1)12417; RV32-NEXT:    vl1re16.v v18, (a6)12418; RV32-NEXT:    add a6, a6, a212419; RV32-NEXT:    vl1re16.v v19, (a6)12420; RV32-NEXT:    add a6, a6, a212421; RV32-NEXT:    vl1re16.v v20, (a6)12422; RV32-NEXT:    add a6, a6, a212423; RV32-NEXT:    vl1re16.v v21, (a6)12424; RV32-NEXT:    add a6, a3, a212425; RV32-NEXT:    vl1re16.v v10, (a6)12426; RV32-NEXT:    add a6, a6, a212427; RV32-NEXT:    vl1re16.v v11, (a6)12428; RV32-NEXT:    vl1re16.v v8, (a0)12429; RV32-NEXT:    vl1re16.v v16, (a4)12430; RV32-NEXT:    vl1re16.v v9, (a3)12431; RV32-NEXT:    csrr a0, vlenb12432; RV32-NEXT:    li a3, 1412433; RV32-NEXT:    mul a0, a0, a312434; RV32-NEXT:    add a0, sp, a012435; RV32-NEXT:    addi a0, a0, 6412436; RV32-NEXT:    vl1re16.v v17, (a5)12437; RV32-NEXT:    slli a3, a2, 212438; RV32-NEXT:    add a6, a6, a212439; RV32-NEXT:    vl1re16.v v12, (a6)12440; RV32-NEXT:    add a6, a6, a212441; RV32-NEXT:    vl1re16.v v13, (a6)12442; RV32-NEXT:    add a6, a6, a212443; RV32-NEXT:    slli a2, a2, 312444; RV32-NEXT:    add a3, a2, a312445; RV32-NEXT:    add a2, a0, a212446; RV32-NEXT:    vl1re16.v v14, (a6)12447; RV32-NEXT:    vl1re16.v v15, (a1)12448; RV32-NEXT:    add a3, a0, a312449; RV32-NEXT:    vs2r.v v20, (a3)12450; RV32-NEXT:    vs4r.v v16, (a2)12451; RV32-NEXT:    vs8r.v v8, (a0)12452; RV32-NEXT:    vl8re16.v v16, (a2)12453; RV32-NEXT:    vl8re16.v v8, (a0)12454; RV32-NEXT:    addi sp, s0, -8012455; RV32-NEXT:    lw ra, 76(sp) # 4-byte Folded Reload12456; RV32-NEXT:    lw s0, 72(sp) # 4-byte Folded Reload12457; RV32-NEXT:    addi sp, sp, 8012458; RV32-NEXT:    ret12459;12460; RV64-LABEL: vector_interleave_nxv56bf16_nxv8bf16:12461; RV64:       # %bb.0:12462; RV64-NEXT:    addi sp, sp, -8012463; RV64-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill12464; RV64-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill12465; RV64-NEXT:    addi s0, sp, 8012466; RV64-NEXT:    csrr a0, vlenb12467; RV64-NEXT:    slli a0, a0, 512468; RV64-NEXT:    sub sp, sp, a012469; RV64-NEXT:    andi sp, sp, -6412470; RV64-NEXT:    vsetvli a0, zero, e16, m1, ta, ma12471; RV64-NEXT:    vmv2r.v v26, v2012472; RV64-NEXT:    addi a0, sp, 6412473; RV64-NEXT:    vmv2r.v v24, v1612474; RV64-NEXT:    vmv2r.v v22, v1212475; RV64-NEXT:    vmv2r.v v20, v812476; RV64-NEXT:    vmv1r.v v1, v2012477; RV64-NEXT:    vmv1r.v v3, v2212478; RV64-NEXT:    vmv1r.v v5, v2412479; RV64-NEXT:    vmv1r.v v7, v2612480; RV64-NEXT:    vmv1r.v v2, v1012481; RV64-NEXT:    csrr a1, vlenb12482; RV64-NEXT:    slli a2, a1, 312483; RV64-NEXT:    sub a1, a2, a112484; RV64-NEXT:    add a1, sp, a112485; RV64-NEXT:    addi a1, a1, 6412486; RV64-NEXT:    csrr a2, vlenb12487; RV64-NEXT:    vmv1r.v v4, v1412488; RV64-NEXT:    add a3, a0, a212489; RV64-NEXT:    add a4, a1, a212490; RV64-NEXT:    vmv1r.v v6, v1812491; RV64-NEXT:    add a5, a4, a212492; RV64-NEXT:    vmv1r.v v22, v1112493; RV64-NEXT:    add a6, a5, a212494; RV64-NEXT:    vmv1r.v v24, v1512495; RV64-NEXT:    vsseg7e16.v v1, (a0)12496; RV64-NEXT:    vmv1r.v v26, v1912497; RV64-NEXT:    vsseg7e16.v v21, (a1)12498; RV64-NEXT:    vl1re16.v v18, (a6)12499; RV64-NEXT:    add a6, a6, a212500; RV64-NEXT:    vl1re16.v v19, (a6)12501; RV64-NEXT:    add a6, a6, a212502; RV64-NEXT:    vl1re16.v v20, (a6)12503; RV64-NEXT:    add a6, a6, a212504; RV64-NEXT:    vl1re16.v v21, (a6)12505; RV64-NEXT:    add a6, a3, a212506; RV64-NEXT:    vl1re16.v v10, (a6)12507; RV64-NEXT:    add a6, a6, a212508; RV64-NEXT:    vl1re16.v v11, (a6)12509; RV64-NEXT:    vl1re16.v v8, (a0)12510; RV64-NEXT:    vl1re16.v v16, (a4)12511; RV64-NEXT:    vl1re16.v v9, (a3)12512; RV64-NEXT:    csrr a0, vlenb12513; RV64-NEXT:    li a3, 1412514; RV64-NEXT:    mul a0, a0, a312515; RV64-NEXT:    add a0, sp, a012516; RV64-NEXT:    addi a0, a0, 6412517; RV64-NEXT:    vl1re16.v v17, (a5)12518; RV64-NEXT:    slli a3, a2, 212519; RV64-NEXT:    add a6, a6, a212520; RV64-NEXT:    vl1re16.v v12, (a6)12521; RV64-NEXT:    add a6, a6, a212522; RV64-NEXT:    vl1re16.v v13, (a6)12523; RV64-NEXT:    add a6, a6, a212524; RV64-NEXT:    slli a2, a2, 312525; RV64-NEXT:    add a3, a2, a312526; RV64-NEXT:    add a2, a0, a212527; RV64-NEXT:    vl1re16.v v14, (a6)12528; RV64-NEXT:    vl1re16.v v15, (a1)12529; RV64-NEXT:    add a3, a0, a312530; RV64-NEXT:    vs2r.v v20, (a3)12531; RV64-NEXT:    vs4r.v v16, (a2)12532; RV64-NEXT:    vs8r.v v8, (a0)12533; RV64-NEXT:    vl8re16.v v16, (a2)12534; RV64-NEXT:    vl8re16.v v8, (a0)12535; RV64-NEXT:    addi sp, s0, -8012536; RV64-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload12537; RV64-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload12538; RV64-NEXT:    addi sp, sp, 8012539; RV64-NEXT:    ret12540;12541; ZVBB-RV32-LABEL: vector_interleave_nxv56bf16_nxv8bf16:12542; ZVBB-RV32:       # %bb.0:12543; ZVBB-RV32-NEXT:    addi sp, sp, -8012544; ZVBB-RV32-NEXT:    sw ra, 76(sp) # 4-byte Folded Spill12545; ZVBB-RV32-NEXT:    sw s0, 72(sp) # 4-byte Folded Spill12546; ZVBB-RV32-NEXT:    addi s0, sp, 8012547; ZVBB-RV32-NEXT:    csrr a0, vlenb12548; ZVBB-RV32-NEXT:    slli a0, a0, 512549; ZVBB-RV32-NEXT:    sub sp, sp, a012550; ZVBB-RV32-NEXT:    andi sp, sp, -6412551; ZVBB-RV32-NEXT:    vsetvli a0, zero, e16, m1, ta, ma12552; ZVBB-RV32-NEXT:    vmv2r.v v26, v2012553; ZVBB-RV32-NEXT:    addi a0, sp, 6412554; ZVBB-RV32-NEXT:    vmv2r.v v24, v1612555; ZVBB-RV32-NEXT:    vmv2r.v v22, v1212556; ZVBB-RV32-NEXT:    vmv2r.v v20, v812557; ZVBB-RV32-NEXT:    vmv1r.v v1, v2012558; ZVBB-RV32-NEXT:    vmv1r.v v3, v2212559; ZVBB-RV32-NEXT:    vmv1r.v v5, v2412560; ZVBB-RV32-NEXT:    vmv1r.v v7, v2612561; ZVBB-RV32-NEXT:    vmv1r.v v2, v1012562; ZVBB-RV32-NEXT:    csrr a1, vlenb12563; ZVBB-RV32-NEXT:    slli a2, a1, 312564; ZVBB-RV32-NEXT:    sub a1, a2, a112565; ZVBB-RV32-NEXT:    add a1, sp, a112566; ZVBB-RV32-NEXT:    addi a1, a1, 6412567; ZVBB-RV32-NEXT:    csrr a2, vlenb12568; ZVBB-RV32-NEXT:    vmv1r.v v4, v1412569; ZVBB-RV32-NEXT:    add a3, a0, a212570; ZVBB-RV32-NEXT:    add a4, a1, a212571; ZVBB-RV32-NEXT:    vmv1r.v v6, v1812572; ZVBB-RV32-NEXT:    add a5, a4, a212573; ZVBB-RV32-NEXT:    vmv1r.v v22, v1112574; ZVBB-RV32-NEXT:    add a6, a5, a212575; ZVBB-RV32-NEXT:    vmv1r.v v24, v1512576; ZVBB-RV32-NEXT:    vsseg7e16.v v1, (a0)12577; ZVBB-RV32-NEXT:    vmv1r.v v26, v1912578; ZVBB-RV32-NEXT:    vsseg7e16.v v21, (a1)12579; ZVBB-RV32-NEXT:    vl1re16.v v18, (a6)12580; ZVBB-RV32-NEXT:    add a6, a6, a212581; ZVBB-RV32-NEXT:    vl1re16.v v19, (a6)12582; ZVBB-RV32-NEXT:    add a6, a6, a212583; ZVBB-RV32-NEXT:    vl1re16.v v20, (a6)12584; ZVBB-RV32-NEXT:    add a6, a6, a212585; ZVBB-RV32-NEXT:    vl1re16.v v21, (a6)12586; ZVBB-RV32-NEXT:    add a6, a3, a212587; ZVBB-RV32-NEXT:    vl1re16.v v10, (a6)12588; ZVBB-RV32-NEXT:    add a6, a6, a212589; ZVBB-RV32-NEXT:    vl1re16.v v11, (a6)12590; ZVBB-RV32-NEXT:    vl1re16.v v8, (a0)12591; ZVBB-RV32-NEXT:    vl1re16.v v16, (a4)12592; ZVBB-RV32-NEXT:    vl1re16.v v9, (a3)12593; ZVBB-RV32-NEXT:    csrr a0, vlenb12594; ZVBB-RV32-NEXT:    li a3, 1412595; ZVBB-RV32-NEXT:    mul a0, a0, a312596; ZVBB-RV32-NEXT:    add a0, sp, a012597; ZVBB-RV32-NEXT:    addi a0, a0, 6412598; ZVBB-RV32-NEXT:    vl1re16.v v17, (a5)12599; ZVBB-RV32-NEXT:    slli a3, a2, 212600; ZVBB-RV32-NEXT:    add a6, a6, a212601; ZVBB-RV32-NEXT:    vl1re16.v v12, (a6)12602; ZVBB-RV32-NEXT:    add a6, a6, a212603; ZVBB-RV32-NEXT:    vl1re16.v v13, (a6)12604; ZVBB-RV32-NEXT:    add a6, a6, a212605; ZVBB-RV32-NEXT:    slli a2, a2, 312606; ZVBB-RV32-NEXT:    add a3, a2, a312607; ZVBB-RV32-NEXT:    add a2, a0, a212608; ZVBB-RV32-NEXT:    vl1re16.v v14, (a6)12609; ZVBB-RV32-NEXT:    vl1re16.v v15, (a1)12610; ZVBB-RV32-NEXT:    add a3, a0, a312611; ZVBB-RV32-NEXT:    vs2r.v v20, (a3)12612; ZVBB-RV32-NEXT:    vs4r.v v16, (a2)12613; ZVBB-RV32-NEXT:    vs8r.v v8, (a0)12614; ZVBB-RV32-NEXT:    vl8re16.v v16, (a2)12615; ZVBB-RV32-NEXT:    vl8re16.v v8, (a0)12616; ZVBB-RV32-NEXT:    addi sp, s0, -8012617; ZVBB-RV32-NEXT:    lw ra, 76(sp) # 4-byte Folded Reload12618; ZVBB-RV32-NEXT:    lw s0, 72(sp) # 4-byte Folded Reload12619; ZVBB-RV32-NEXT:    addi sp, sp, 8012620; ZVBB-RV32-NEXT:    ret12621;12622; ZVBB-RV64-LABEL: vector_interleave_nxv56bf16_nxv8bf16:12623; ZVBB-RV64:       # %bb.0:12624; ZVBB-RV64-NEXT:    addi sp, sp, -8012625; ZVBB-RV64-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill12626; ZVBB-RV64-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill12627; ZVBB-RV64-NEXT:    addi s0, sp, 8012628; ZVBB-RV64-NEXT:    csrr a0, vlenb12629; ZVBB-RV64-NEXT:    slli a0, a0, 512630; ZVBB-RV64-NEXT:    sub sp, sp, a012631; ZVBB-RV64-NEXT:    andi sp, sp, -6412632; ZVBB-RV64-NEXT:    vsetvli a0, zero, e16, m1, ta, ma12633; ZVBB-RV64-NEXT:    vmv2r.v v26, v2012634; ZVBB-RV64-NEXT:    addi a0, sp, 6412635; ZVBB-RV64-NEXT:    vmv2r.v v24, v1612636; ZVBB-RV64-NEXT:    vmv2r.v v22, v1212637; ZVBB-RV64-NEXT:    vmv2r.v v20, v812638; ZVBB-RV64-NEXT:    vmv1r.v v1, v2012639; ZVBB-RV64-NEXT:    vmv1r.v v3, v2212640; ZVBB-RV64-NEXT:    vmv1r.v v5, v2412641; ZVBB-RV64-NEXT:    vmv1r.v v7, v2612642; ZVBB-RV64-NEXT:    vmv1r.v v2, v1012643; ZVBB-RV64-NEXT:    csrr a1, vlenb12644; ZVBB-RV64-NEXT:    slli a2, a1, 312645; ZVBB-RV64-NEXT:    sub a1, a2, a112646; ZVBB-RV64-NEXT:    add a1, sp, a112647; ZVBB-RV64-NEXT:    addi a1, a1, 6412648; ZVBB-RV64-NEXT:    csrr a2, vlenb12649; ZVBB-RV64-NEXT:    vmv1r.v v4, v1412650; ZVBB-RV64-NEXT:    add a3, a0, a212651; ZVBB-RV64-NEXT:    add a4, a1, a212652; ZVBB-RV64-NEXT:    vmv1r.v v6, v1812653; ZVBB-RV64-NEXT:    add a5, a4, a212654; ZVBB-RV64-NEXT:    vmv1r.v v22, v1112655; ZVBB-RV64-NEXT:    add a6, a5, a212656; ZVBB-RV64-NEXT:    vmv1r.v v24, v1512657; ZVBB-RV64-NEXT:    vsseg7e16.v v1, (a0)12658; ZVBB-RV64-NEXT:    vmv1r.v v26, v1912659; ZVBB-RV64-NEXT:    vsseg7e16.v v21, (a1)12660; ZVBB-RV64-NEXT:    vl1re16.v v18, (a6)12661; ZVBB-RV64-NEXT:    add a6, a6, a212662; ZVBB-RV64-NEXT:    vl1re16.v v19, (a6)12663; ZVBB-RV64-NEXT:    add a6, a6, a212664; ZVBB-RV64-NEXT:    vl1re16.v v20, (a6)12665; ZVBB-RV64-NEXT:    add a6, a6, a212666; ZVBB-RV64-NEXT:    vl1re16.v v21, (a6)12667; ZVBB-RV64-NEXT:    add a6, a3, a212668; ZVBB-RV64-NEXT:    vl1re16.v v10, (a6)12669; ZVBB-RV64-NEXT:    add a6, a6, a212670; ZVBB-RV64-NEXT:    vl1re16.v v11, (a6)12671; ZVBB-RV64-NEXT:    vl1re16.v v8, (a0)12672; ZVBB-RV64-NEXT:    vl1re16.v v16, (a4)12673; ZVBB-RV64-NEXT:    vl1re16.v v9, (a3)12674; ZVBB-RV64-NEXT:    csrr a0, vlenb12675; ZVBB-RV64-NEXT:    li a3, 1412676; ZVBB-RV64-NEXT:    mul a0, a0, a312677; ZVBB-RV64-NEXT:    add a0, sp, a012678; ZVBB-RV64-NEXT:    addi a0, a0, 6412679; ZVBB-RV64-NEXT:    vl1re16.v v17, (a5)12680; ZVBB-RV64-NEXT:    slli a3, a2, 212681; ZVBB-RV64-NEXT:    add a6, a6, a212682; ZVBB-RV64-NEXT:    vl1re16.v v12, (a6)12683; ZVBB-RV64-NEXT:    add a6, a6, a212684; ZVBB-RV64-NEXT:    vl1re16.v v13, (a6)12685; ZVBB-RV64-NEXT:    add a6, a6, a212686; ZVBB-RV64-NEXT:    slli a2, a2, 312687; ZVBB-RV64-NEXT:    add a3, a2, a312688; ZVBB-RV64-NEXT:    add a2, a0, a212689; ZVBB-RV64-NEXT:    vl1re16.v v14, (a6)12690; ZVBB-RV64-NEXT:    vl1re16.v v15, (a1)12691; ZVBB-RV64-NEXT:    add a3, a0, a312692; ZVBB-RV64-NEXT:    vs2r.v v20, (a3)12693; ZVBB-RV64-NEXT:    vs4r.v v16, (a2)12694; ZVBB-RV64-NEXT:    vs8r.v v8, (a0)12695; ZVBB-RV64-NEXT:    vl8re16.v v16, (a2)12696; ZVBB-RV64-NEXT:    vl8re16.v v8, (a0)12697; ZVBB-RV64-NEXT:    addi sp, s0, -8012698; ZVBB-RV64-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload12699; ZVBB-RV64-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload12700; ZVBB-RV64-NEXT:    addi sp, sp, 8012701; ZVBB-RV64-NEXT:    ret12702;12703; ZIP-LABEL: vector_interleave_nxv56bf16_nxv8bf16:12704; ZIP:       # %bb.0:12705; ZIP-NEXT:    addi sp, sp, -8012706; ZIP-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill12707; ZIP-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill12708; ZIP-NEXT:    addi s0, sp, 8012709; ZIP-NEXT:    csrr a0, vlenb12710; ZIP-NEXT:    slli a0, a0, 512711; ZIP-NEXT:    sub sp, sp, a012712; ZIP-NEXT:    andi sp, sp, -6412713; ZIP-NEXT:    vsetvli a0, zero, e16, m1, ta, ma12714; ZIP-NEXT:    vmv2r.v v26, v2012715; ZIP-NEXT:    addi a0, sp, 6412716; ZIP-NEXT:    vmv2r.v v24, v1612717; ZIP-NEXT:    vmv2r.v v22, v1212718; ZIP-NEXT:    vmv2r.v v20, v812719; ZIP-NEXT:    vmv1r.v v1, v2012720; ZIP-NEXT:    vmv1r.v v3, v2212721; ZIP-NEXT:    vmv1r.v v5, v2412722; ZIP-NEXT:    vmv1r.v v7, v2612723; ZIP-NEXT:    vmv1r.v v2, v1012724; ZIP-NEXT:    csrr a1, vlenb12725; ZIP-NEXT:    slli a2, a1, 312726; ZIP-NEXT:    sub a1, a2, a112727; ZIP-NEXT:    add a1, sp, a112728; ZIP-NEXT:    addi a1, a1, 6412729; ZIP-NEXT:    csrr a2, vlenb12730; ZIP-NEXT:    vmv1r.v v4, v1412731; ZIP-NEXT:    add a3, a0, a212732; ZIP-NEXT:    add a4, a1, a212733; ZIP-NEXT:    vmv1r.v v6, v1812734; ZIP-NEXT:    add a5, a4, a212735; ZIP-NEXT:    vmv1r.v v22, v1112736; ZIP-NEXT:    add a6, a5, a212737; ZIP-NEXT:    vmv1r.v v24, v1512738; ZIP-NEXT:    vsseg7e16.v v1, (a0)12739; ZIP-NEXT:    vmv1r.v v26, v1912740; ZIP-NEXT:    vsseg7e16.v v21, (a1)12741; ZIP-NEXT:    vl1re16.v v18, (a6)12742; ZIP-NEXT:    add a6, a6, a212743; ZIP-NEXT:    vl1re16.v v19, (a6)12744; ZIP-NEXT:    add a6, a6, a212745; ZIP-NEXT:    vl1re16.v v20, (a6)12746; ZIP-NEXT:    add a6, a6, a212747; ZIP-NEXT:    vl1re16.v v21, (a6)12748; ZIP-NEXT:    add a6, a3, a212749; ZIP-NEXT:    vl1re16.v v10, (a6)12750; ZIP-NEXT:    add a6, a6, a212751; ZIP-NEXT:    vl1re16.v v11, (a6)12752; ZIP-NEXT:    vl1re16.v v8, (a0)12753; ZIP-NEXT:    vl1re16.v v16, (a4)12754; ZIP-NEXT:    vl1re16.v v9, (a3)12755; ZIP-NEXT:    csrr a0, vlenb12756; ZIP-NEXT:    li a3, 1412757; ZIP-NEXT:    mul a0, a0, a312758; ZIP-NEXT:    add a0, sp, a012759; ZIP-NEXT:    addi a0, a0, 6412760; ZIP-NEXT:    vl1re16.v v17, (a5)12761; ZIP-NEXT:    slli a3, a2, 212762; ZIP-NEXT:    add a6, a6, a212763; ZIP-NEXT:    vl1re16.v v12, (a6)12764; ZIP-NEXT:    add a6, a6, a212765; ZIP-NEXT:    vl1re16.v v13, (a6)12766; ZIP-NEXT:    add a6, a6, a212767; ZIP-NEXT:    slli a2, a2, 312768; ZIP-NEXT:    add a3, a2, a312769; ZIP-NEXT:    add a2, a0, a212770; ZIP-NEXT:    vl1re16.v v14, (a6)12771; ZIP-NEXT:    vl1re16.v v15, (a1)12772; ZIP-NEXT:    add a3, a0, a312773; ZIP-NEXT:    vs2r.v v20, (a3)12774; ZIP-NEXT:    vs4r.v v16, (a2)12775; ZIP-NEXT:    vs8r.v v8, (a0)12776; ZIP-NEXT:    vl8re16.v v16, (a2)12777; ZIP-NEXT:    vl8re16.v v8, (a0)12778; ZIP-NEXT:    addi sp, s0, -8012779; ZIP-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload12780; ZIP-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload12781; ZIP-NEXT:    addi sp, sp, 8012782; ZIP-NEXT:    ret12783  %res = call <vscale x 56 x bfloat> @llvm.vector.interleave7.nxv56bf16(<vscale x 8 x bfloat> %v0, <vscale x 8 x bfloat> %v1, <vscale x 8 x bfloat> %v2, <vscale x 8 x bfloat> %v3, <vscale x 8 x bfloat> %v4, <vscale x 8 x bfloat> %v5, <vscale x 8 x bfloat> %v6)12784  ret <vscale x 56 x bfloat> %res12785}12786 12787define <vscale x 7 x float> @vector_interleave_nxv7f32_nxv1f32(<vscale x 1 x float> %v0, <vscale x 1 x float> %v1, <vscale x 1 x float> %v2, <vscale x 1 x float> %v3, <vscale x 1 x float> %v4, <vscale x 1 x float> %v5, <vscale x 1 x float> %v6) nounwind {12788; CHECK-LABEL: vector_interleave_nxv7f32_nxv1f32:12789; CHECK:       # %bb.0:12790; CHECK-NEXT:    addi sp, sp, -1612791; CHECK-NEXT:    csrr a0, vlenb12792; CHECK-NEXT:    slli a0, a0, 212793; CHECK-NEXT:    sub sp, sp, a012794; CHECK-NEXT:    addi a0, sp, 1612795; CHECK-NEXT:    csrr a1, vlenb12796; CHECK-NEXT:    srli a2, a1, 112797; CHECK-NEXT:    add a3, a0, a212798; CHECK-NEXT:    add a4, a3, a212799; CHECK-NEXT:    add a5, a4, a212800; CHECK-NEXT:    add a6, a5, a212801; CHECK-NEXT:    vsetvli a7, zero, e32, mf2, ta, ma12802; CHECK-NEXT:    vsseg7e32.v v8, (a0)12803; CHECK-NEXT:    add a7, a6, a212804; CHECK-NEXT:    vle32.v v8, (a7)12805; CHECK-NEXT:    vle32.v v10, (a6)12806; CHECK-NEXT:    srli a1, a1, 312807; CHECK-NEXT:    add a2, a7, a212808; CHECK-NEXT:    vle32.v v12, (a5)12809; CHECK-NEXT:    vsetvli a5, zero, e32, m1, ta, ma12810; CHECK-NEXT:    vslideup.vx v10, v8, a112811; CHECK-NEXT:    vsetvli a5, zero, e32, mf2, ta, ma12812; CHECK-NEXT:    vle32.v v11, (a2)12813; CHECK-NEXT:    vle32.v v9, (a4)12814; CHECK-NEXT:    vsetvli a2, zero, e32, m1, ta, ma12815; CHECK-NEXT:    vslideup.vx v9, v12, a112816; CHECK-NEXT:    vsetvli a2, zero, e32, mf2, ta, ma12817; CHECK-NEXT:    vle32.v v12, (a3)12818; CHECK-NEXT:    vle32.v v8, (a0)12819; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma12820; CHECK-NEXT:    vslideup.vx v8, v12, a112821; CHECK-NEXT:    csrr a0, vlenb12822; CHECK-NEXT:    slli a0, a0, 212823; CHECK-NEXT:    add sp, sp, a012824; CHECK-NEXT:    addi sp, sp, 1612825; CHECK-NEXT:    ret12826;12827; ZVBB-LABEL: vector_interleave_nxv7f32_nxv1f32:12828; ZVBB:       # %bb.0:12829; ZVBB-NEXT:    addi sp, sp, -1612830; ZVBB-NEXT:    csrr a0, vlenb12831; ZVBB-NEXT:    slli a0, a0, 212832; ZVBB-NEXT:    sub sp, sp, a012833; ZVBB-NEXT:    addi a0, sp, 1612834; ZVBB-NEXT:    csrr a1, vlenb12835; ZVBB-NEXT:    srli a2, a1, 112836; ZVBB-NEXT:    add a3, a0, a212837; ZVBB-NEXT:    add a4, a3, a212838; ZVBB-NEXT:    add a5, a4, a212839; ZVBB-NEXT:    add a6, a5, a212840; ZVBB-NEXT:    vsetvli a7, zero, e32, mf2, ta, ma12841; ZVBB-NEXT:    vsseg7e32.v v8, (a0)12842; ZVBB-NEXT:    add a7, a6, a212843; ZVBB-NEXT:    vle32.v v8, (a7)12844; ZVBB-NEXT:    vle32.v v10, (a6)12845; ZVBB-NEXT:    srli a1, a1, 312846; ZVBB-NEXT:    add a2, a7, a212847; ZVBB-NEXT:    vle32.v v12, (a5)12848; ZVBB-NEXT:    vsetvli a5, zero, e32, m1, ta, ma12849; ZVBB-NEXT:    vslideup.vx v10, v8, a112850; ZVBB-NEXT:    vsetvli a5, zero, e32, mf2, ta, ma12851; ZVBB-NEXT:    vle32.v v11, (a2)12852; ZVBB-NEXT:    vle32.v v9, (a4)12853; ZVBB-NEXT:    vsetvli a2, zero, e32, m1, ta, ma12854; ZVBB-NEXT:    vslideup.vx v9, v12, a112855; ZVBB-NEXT:    vsetvli a2, zero, e32, mf2, ta, ma12856; ZVBB-NEXT:    vle32.v v12, (a3)12857; ZVBB-NEXT:    vle32.v v8, (a0)12858; ZVBB-NEXT:    vsetvli a0, zero, e32, m1, ta, ma12859; ZVBB-NEXT:    vslideup.vx v8, v12, a112860; ZVBB-NEXT:    csrr a0, vlenb12861; ZVBB-NEXT:    slli a0, a0, 212862; ZVBB-NEXT:    add sp, sp, a012863; ZVBB-NEXT:    addi sp, sp, 1612864; ZVBB-NEXT:    ret12865  %res = call <vscale x 7 x float> @llvm.vector.interleave7.nxv7f32(<vscale x 1 x float> %v0, <vscale x 1 x float> %v1, <vscale x 1 x float> %v2, <vscale x 1 x float> %v3, <vscale x 1 x float> %v4, <vscale x 1 x float> %v5, <vscale x 1 x float> %v6)12866  ret <vscale x 7 x float> %res12867}12868 12869define <vscale x 14 x float> @vector_interleave_nxv14f32_nxv2f32(<vscale x 2 x float> %v0, <vscale x 2 x float> %v1, <vscale x 2 x float> %v2, <vscale x 2 x float> %v3, <vscale x 2 x float> %v4, <vscale x 2 x float> %v5, <vscale x 2 x float> %v6) nounwind {12870; CHECK-LABEL: vector_interleave_nxv14f32_nxv2f32:12871; CHECK:       # %bb.0:12872; CHECK-NEXT:    addi sp, sp, -1612873; CHECK-NEXT:    csrr a0, vlenb12874; CHECK-NEXT:    slli a1, a0, 312875; CHECK-NEXT:    sub a0, a1, a012876; CHECK-NEXT:    sub sp, sp, a012877; CHECK-NEXT:    addi a0, sp, 1612878; CHECK-NEXT:    csrr a1, vlenb12879; CHECK-NEXT:    add a2, a0, a112880; CHECK-NEXT:    add a3, a2, a112881; CHECK-NEXT:    vsetvli a4, zero, e32, m1, ta, ma12882; CHECK-NEXT:    vsseg7e32.v v8, (a0)12883; CHECK-NEXT:    vl1re32.v v10, (a3)12884; CHECK-NEXT:    add a3, a3, a112885; CHECK-NEXT:    vl1re32.v v11, (a3)12886; CHECK-NEXT:    add a3, a3, a112887; CHECK-NEXT:    vl1re32.v v8, (a0)12888; CHECK-NEXT:    add a0, a3, a112889; CHECK-NEXT:    vl1re32.v v9, (a2)12890; CHECK-NEXT:    vl1re32.v v12, (a3)12891; CHECK-NEXT:    vl1re32.v v13, (a0)12892; CHECK-NEXT:    add a0, a0, a112893; CHECK-NEXT:    vl1re32.v v14, (a0)12894; CHECK-NEXT:    csrr a0, vlenb12895; CHECK-NEXT:    slli a1, a0, 312896; CHECK-NEXT:    sub a0, a1, a012897; CHECK-NEXT:    add sp, sp, a012898; CHECK-NEXT:    addi sp, sp, 1612899; CHECK-NEXT:    ret12900;12901; ZVBB-LABEL: vector_interleave_nxv14f32_nxv2f32:12902; ZVBB:       # %bb.0:12903; ZVBB-NEXT:    addi sp, sp, -1612904; ZVBB-NEXT:    csrr a0, vlenb12905; ZVBB-NEXT:    slli a1, a0, 312906; ZVBB-NEXT:    sub a0, a1, a012907; ZVBB-NEXT:    sub sp, sp, a012908; ZVBB-NEXT:    addi a0, sp, 1612909; ZVBB-NEXT:    csrr a1, vlenb12910; ZVBB-NEXT:    add a2, a0, a112911; ZVBB-NEXT:    add a3, a2, a112912; ZVBB-NEXT:    vsetvli a4, zero, e32, m1, ta, ma12913; ZVBB-NEXT:    vsseg7e32.v v8, (a0)12914; ZVBB-NEXT:    vl1re32.v v10, (a3)12915; ZVBB-NEXT:    add a3, a3, a112916; ZVBB-NEXT:    vl1re32.v v11, (a3)12917; ZVBB-NEXT:    add a3, a3, a112918; ZVBB-NEXT:    vl1re32.v v8, (a0)12919; ZVBB-NEXT:    add a0, a3, a112920; ZVBB-NEXT:    vl1re32.v v9, (a2)12921; ZVBB-NEXT:    vl1re32.v v12, (a3)12922; ZVBB-NEXT:    vl1re32.v v13, (a0)12923; ZVBB-NEXT:    add a0, a0, a112924; ZVBB-NEXT:    vl1re32.v v14, (a0)12925; ZVBB-NEXT:    csrr a0, vlenb12926; ZVBB-NEXT:    slli a1, a0, 312927; ZVBB-NEXT:    sub a0, a1, a012928; ZVBB-NEXT:    add sp, sp, a012929; ZVBB-NEXT:    addi sp, sp, 1612930; ZVBB-NEXT:    ret12931  %res = call <vscale x 14 x float> @llvm.vector.interleave7.nxv14f32(<vscale x 2 x float> %v0, <vscale x 2 x float> %v1, <vscale x 2 x float> %v2, <vscale x 2 x float> %v3, <vscale x 2 x float> %v4, <vscale x 2 x float> %v5, <vscale x 2 x float> %v6)12932  ret <vscale x 14 x float> %res12933}12934 12935define <vscale x 28 x float> @vector_interleave_nxv28f32_nxv4f32(<vscale x 4 x float> %v0, <vscale x 4 x float> %v1, <vscale x 4 x float> %v2, <vscale x 4 x float> %v3, <vscale x 4 x float> %v4, <vscale x 4 x float> %v5, <vscale x 4 x float> %v6) nounwind {12936; RV32-LABEL: vector_interleave_nxv28f32_nxv4f32:12937; RV32:       # %bb.0:12938; RV32-NEXT:    addi sp, sp, -8012939; RV32-NEXT:    sw ra, 76(sp) # 4-byte Folded Spill12940; RV32-NEXT:    sw s0, 72(sp) # 4-byte Folded Spill12941; RV32-NEXT:    addi s0, sp, 8012942; RV32-NEXT:    csrr a0, vlenb12943; RV32-NEXT:    slli a0, a0, 512944; RV32-NEXT:    sub sp, sp, a012945; RV32-NEXT:    andi sp, sp, -6412946; RV32-NEXT:    vsetvli a0, zero, e32, m1, ta, ma12947; RV32-NEXT:    vmv2r.v v26, v2012948; RV32-NEXT:    addi a0, sp, 6412949; RV32-NEXT:    vmv2r.v v24, v1612950; RV32-NEXT:    vmv2r.v v22, v1212951; RV32-NEXT:    vmv2r.v v20, v812952; RV32-NEXT:    vmv1r.v v1, v2012953; RV32-NEXT:    vmv1r.v v3, v2212954; RV32-NEXT:    vmv1r.v v5, v2412955; RV32-NEXT:    vmv1r.v v7, v2612956; RV32-NEXT:    vmv1r.v v2, v1012957; RV32-NEXT:    csrr a1, vlenb12958; RV32-NEXT:    slli a2, a1, 312959; RV32-NEXT:    sub a1, a2, a112960; RV32-NEXT:    add a1, sp, a112961; RV32-NEXT:    addi a1, a1, 6412962; RV32-NEXT:    csrr a2, vlenb12963; RV32-NEXT:    vmv1r.v v4, v1412964; RV32-NEXT:    add a3, a0, a212965; RV32-NEXT:    add a4, a1, a212966; RV32-NEXT:    vmv1r.v v6, v1812967; RV32-NEXT:    add a5, a4, a212968; RV32-NEXT:    vmv1r.v v22, v1112969; RV32-NEXT:    add a6, a5, a212970; RV32-NEXT:    vmv1r.v v24, v1512971; RV32-NEXT:    vsseg7e32.v v1, (a0)12972; RV32-NEXT:    vmv1r.v v26, v1912973; RV32-NEXT:    vsseg7e32.v v21, (a1)12974; RV32-NEXT:    vl1re32.v v18, (a6)12975; RV32-NEXT:    add a6, a6, a212976; RV32-NEXT:    vl1re32.v v19, (a6)12977; RV32-NEXT:    add a6, a6, a212978; RV32-NEXT:    vl1re32.v v20, (a6)12979; RV32-NEXT:    add a6, a6, a212980; RV32-NEXT:    vl1re32.v v21, (a6)12981; RV32-NEXT:    add a6, a3, a212982; RV32-NEXT:    vl1re32.v v10, (a6)12983; RV32-NEXT:    add a6, a6, a212984; RV32-NEXT:    vl1re32.v v11, (a6)12985; RV32-NEXT:    vl1re32.v v8, (a0)12986; RV32-NEXT:    vl1re32.v v16, (a4)12987; RV32-NEXT:    vl1re32.v v9, (a3)12988; RV32-NEXT:    csrr a0, vlenb12989; RV32-NEXT:    li a3, 1412990; RV32-NEXT:    mul a0, a0, a312991; RV32-NEXT:    add a0, sp, a012992; RV32-NEXT:    addi a0, a0, 6412993; RV32-NEXT:    vl1re32.v v17, (a5)12994; RV32-NEXT:    slli a3, a2, 212995; RV32-NEXT:    add a6, a6, a212996; RV32-NEXT:    vl1re32.v v12, (a6)12997; RV32-NEXT:    add a6, a6, a212998; RV32-NEXT:    vl1re32.v v13, (a6)12999; RV32-NEXT:    add a6, a6, a213000; RV32-NEXT:    slli a2, a2, 313001; RV32-NEXT:    add a3, a2, a313002; RV32-NEXT:    add a2, a0, a213003; RV32-NEXT:    vl1re32.v v14, (a6)13004; RV32-NEXT:    vl1re32.v v15, (a1)13005; RV32-NEXT:    add a3, a0, a313006; RV32-NEXT:    vs2r.v v20, (a3)13007; RV32-NEXT:    vs4r.v v16, (a2)13008; RV32-NEXT:    vs8r.v v8, (a0)13009; RV32-NEXT:    vl8re32.v v16, (a2)13010; RV32-NEXT:    vl8re32.v v8, (a0)13011; RV32-NEXT:    addi sp, s0, -8013012; RV32-NEXT:    lw ra, 76(sp) # 4-byte Folded Reload13013; RV32-NEXT:    lw s0, 72(sp) # 4-byte Folded Reload13014; RV32-NEXT:    addi sp, sp, 8013015; RV32-NEXT:    ret13016;13017; RV64-LABEL: vector_interleave_nxv28f32_nxv4f32:13018; RV64:       # %bb.0:13019; RV64-NEXT:    addi sp, sp, -8013020; RV64-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill13021; RV64-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill13022; RV64-NEXT:    addi s0, sp, 8013023; RV64-NEXT:    csrr a0, vlenb13024; RV64-NEXT:    slli a0, a0, 513025; RV64-NEXT:    sub sp, sp, a013026; RV64-NEXT:    andi sp, sp, -6413027; RV64-NEXT:    vsetvli a0, zero, e32, m1, ta, ma13028; RV64-NEXT:    vmv2r.v v26, v2013029; RV64-NEXT:    addi a0, sp, 6413030; RV64-NEXT:    vmv2r.v v24, v1613031; RV64-NEXT:    vmv2r.v v22, v1213032; RV64-NEXT:    vmv2r.v v20, v813033; RV64-NEXT:    vmv1r.v v1, v2013034; RV64-NEXT:    vmv1r.v v3, v2213035; RV64-NEXT:    vmv1r.v v5, v2413036; RV64-NEXT:    vmv1r.v v7, v2613037; RV64-NEXT:    vmv1r.v v2, v1013038; RV64-NEXT:    csrr a1, vlenb13039; RV64-NEXT:    slli a2, a1, 313040; RV64-NEXT:    sub a1, a2, a113041; RV64-NEXT:    add a1, sp, a113042; RV64-NEXT:    addi a1, a1, 6413043; RV64-NEXT:    csrr a2, vlenb13044; RV64-NEXT:    vmv1r.v v4, v1413045; RV64-NEXT:    add a3, a0, a213046; RV64-NEXT:    add a4, a1, a213047; RV64-NEXT:    vmv1r.v v6, v1813048; RV64-NEXT:    add a5, a4, a213049; RV64-NEXT:    vmv1r.v v22, v1113050; RV64-NEXT:    add a6, a5, a213051; RV64-NEXT:    vmv1r.v v24, v1513052; RV64-NEXT:    vsseg7e32.v v1, (a0)13053; RV64-NEXT:    vmv1r.v v26, v1913054; RV64-NEXT:    vsseg7e32.v v21, (a1)13055; RV64-NEXT:    vl1re32.v v18, (a6)13056; RV64-NEXT:    add a6, a6, a213057; RV64-NEXT:    vl1re32.v v19, (a6)13058; RV64-NEXT:    add a6, a6, a213059; RV64-NEXT:    vl1re32.v v20, (a6)13060; RV64-NEXT:    add a6, a6, a213061; RV64-NEXT:    vl1re32.v v21, (a6)13062; RV64-NEXT:    add a6, a3, a213063; RV64-NEXT:    vl1re32.v v10, (a6)13064; RV64-NEXT:    add a6, a6, a213065; RV64-NEXT:    vl1re32.v v11, (a6)13066; RV64-NEXT:    vl1re32.v v8, (a0)13067; RV64-NEXT:    vl1re32.v v16, (a4)13068; RV64-NEXT:    vl1re32.v v9, (a3)13069; RV64-NEXT:    csrr a0, vlenb13070; RV64-NEXT:    li a3, 1413071; RV64-NEXT:    mul a0, a0, a313072; RV64-NEXT:    add a0, sp, a013073; RV64-NEXT:    addi a0, a0, 6413074; RV64-NEXT:    vl1re32.v v17, (a5)13075; RV64-NEXT:    slli a3, a2, 213076; RV64-NEXT:    add a6, a6, a213077; RV64-NEXT:    vl1re32.v v12, (a6)13078; RV64-NEXT:    add a6, a6, a213079; RV64-NEXT:    vl1re32.v v13, (a6)13080; RV64-NEXT:    add a6, a6, a213081; RV64-NEXT:    slli a2, a2, 313082; RV64-NEXT:    add a3, a2, a313083; RV64-NEXT:    add a2, a0, a213084; RV64-NEXT:    vl1re32.v v14, (a6)13085; RV64-NEXT:    vl1re32.v v15, (a1)13086; RV64-NEXT:    add a3, a0, a313087; RV64-NEXT:    vs2r.v v20, (a3)13088; RV64-NEXT:    vs4r.v v16, (a2)13089; RV64-NEXT:    vs8r.v v8, (a0)13090; RV64-NEXT:    vl8re32.v v16, (a2)13091; RV64-NEXT:    vl8re32.v v8, (a0)13092; RV64-NEXT:    addi sp, s0, -8013093; RV64-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload13094; RV64-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload13095; RV64-NEXT:    addi sp, sp, 8013096; RV64-NEXT:    ret13097;13098; ZVBB-RV32-LABEL: vector_interleave_nxv28f32_nxv4f32:13099; ZVBB-RV32:       # %bb.0:13100; ZVBB-RV32-NEXT:    addi sp, sp, -8013101; ZVBB-RV32-NEXT:    sw ra, 76(sp) # 4-byte Folded Spill13102; ZVBB-RV32-NEXT:    sw s0, 72(sp) # 4-byte Folded Spill13103; ZVBB-RV32-NEXT:    addi s0, sp, 8013104; ZVBB-RV32-NEXT:    csrr a0, vlenb13105; ZVBB-RV32-NEXT:    slli a0, a0, 513106; ZVBB-RV32-NEXT:    sub sp, sp, a013107; ZVBB-RV32-NEXT:    andi sp, sp, -6413108; ZVBB-RV32-NEXT:    vsetvli a0, zero, e32, m1, ta, ma13109; ZVBB-RV32-NEXT:    vmv2r.v v26, v2013110; ZVBB-RV32-NEXT:    addi a0, sp, 6413111; ZVBB-RV32-NEXT:    vmv2r.v v24, v1613112; ZVBB-RV32-NEXT:    vmv2r.v v22, v1213113; ZVBB-RV32-NEXT:    vmv2r.v v20, v813114; ZVBB-RV32-NEXT:    vmv1r.v v1, v2013115; ZVBB-RV32-NEXT:    vmv1r.v v3, v2213116; ZVBB-RV32-NEXT:    vmv1r.v v5, v2413117; ZVBB-RV32-NEXT:    vmv1r.v v7, v2613118; ZVBB-RV32-NEXT:    vmv1r.v v2, v1013119; ZVBB-RV32-NEXT:    csrr a1, vlenb13120; ZVBB-RV32-NEXT:    slli a2, a1, 313121; ZVBB-RV32-NEXT:    sub a1, a2, a113122; ZVBB-RV32-NEXT:    add a1, sp, a113123; ZVBB-RV32-NEXT:    addi a1, a1, 6413124; ZVBB-RV32-NEXT:    csrr a2, vlenb13125; ZVBB-RV32-NEXT:    vmv1r.v v4, v1413126; ZVBB-RV32-NEXT:    add a3, a0, a213127; ZVBB-RV32-NEXT:    add a4, a1, a213128; ZVBB-RV32-NEXT:    vmv1r.v v6, v1813129; ZVBB-RV32-NEXT:    add a5, a4, a213130; ZVBB-RV32-NEXT:    vmv1r.v v22, v1113131; ZVBB-RV32-NEXT:    add a6, a5, a213132; ZVBB-RV32-NEXT:    vmv1r.v v24, v1513133; ZVBB-RV32-NEXT:    vsseg7e32.v v1, (a0)13134; ZVBB-RV32-NEXT:    vmv1r.v v26, v1913135; ZVBB-RV32-NEXT:    vsseg7e32.v v21, (a1)13136; ZVBB-RV32-NEXT:    vl1re32.v v18, (a6)13137; ZVBB-RV32-NEXT:    add a6, a6, a213138; ZVBB-RV32-NEXT:    vl1re32.v v19, (a6)13139; ZVBB-RV32-NEXT:    add a6, a6, a213140; ZVBB-RV32-NEXT:    vl1re32.v v20, (a6)13141; ZVBB-RV32-NEXT:    add a6, a6, a213142; ZVBB-RV32-NEXT:    vl1re32.v v21, (a6)13143; ZVBB-RV32-NEXT:    add a6, a3, a213144; ZVBB-RV32-NEXT:    vl1re32.v v10, (a6)13145; ZVBB-RV32-NEXT:    add a6, a6, a213146; ZVBB-RV32-NEXT:    vl1re32.v v11, (a6)13147; ZVBB-RV32-NEXT:    vl1re32.v v8, (a0)13148; ZVBB-RV32-NEXT:    vl1re32.v v16, (a4)13149; ZVBB-RV32-NEXT:    vl1re32.v v9, (a3)13150; ZVBB-RV32-NEXT:    csrr a0, vlenb13151; ZVBB-RV32-NEXT:    li a3, 1413152; ZVBB-RV32-NEXT:    mul a0, a0, a313153; ZVBB-RV32-NEXT:    add a0, sp, a013154; ZVBB-RV32-NEXT:    addi a0, a0, 6413155; ZVBB-RV32-NEXT:    vl1re32.v v17, (a5)13156; ZVBB-RV32-NEXT:    slli a3, a2, 213157; ZVBB-RV32-NEXT:    add a6, a6, a213158; ZVBB-RV32-NEXT:    vl1re32.v v12, (a6)13159; ZVBB-RV32-NEXT:    add a6, a6, a213160; ZVBB-RV32-NEXT:    vl1re32.v v13, (a6)13161; ZVBB-RV32-NEXT:    add a6, a6, a213162; ZVBB-RV32-NEXT:    slli a2, a2, 313163; ZVBB-RV32-NEXT:    add a3, a2, a313164; ZVBB-RV32-NEXT:    add a2, a0, a213165; ZVBB-RV32-NEXT:    vl1re32.v v14, (a6)13166; ZVBB-RV32-NEXT:    vl1re32.v v15, (a1)13167; ZVBB-RV32-NEXT:    add a3, a0, a313168; ZVBB-RV32-NEXT:    vs2r.v v20, (a3)13169; ZVBB-RV32-NEXT:    vs4r.v v16, (a2)13170; ZVBB-RV32-NEXT:    vs8r.v v8, (a0)13171; ZVBB-RV32-NEXT:    vl8re32.v v16, (a2)13172; ZVBB-RV32-NEXT:    vl8re32.v v8, (a0)13173; ZVBB-RV32-NEXT:    addi sp, s0, -8013174; ZVBB-RV32-NEXT:    lw ra, 76(sp) # 4-byte Folded Reload13175; ZVBB-RV32-NEXT:    lw s0, 72(sp) # 4-byte Folded Reload13176; ZVBB-RV32-NEXT:    addi sp, sp, 8013177; ZVBB-RV32-NEXT:    ret13178;13179; ZVBB-RV64-LABEL: vector_interleave_nxv28f32_nxv4f32:13180; ZVBB-RV64:       # %bb.0:13181; ZVBB-RV64-NEXT:    addi sp, sp, -8013182; ZVBB-RV64-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill13183; ZVBB-RV64-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill13184; ZVBB-RV64-NEXT:    addi s0, sp, 8013185; ZVBB-RV64-NEXT:    csrr a0, vlenb13186; ZVBB-RV64-NEXT:    slli a0, a0, 513187; ZVBB-RV64-NEXT:    sub sp, sp, a013188; ZVBB-RV64-NEXT:    andi sp, sp, -6413189; ZVBB-RV64-NEXT:    vsetvli a0, zero, e32, m1, ta, ma13190; ZVBB-RV64-NEXT:    vmv2r.v v26, v2013191; ZVBB-RV64-NEXT:    addi a0, sp, 6413192; ZVBB-RV64-NEXT:    vmv2r.v v24, v1613193; ZVBB-RV64-NEXT:    vmv2r.v v22, v1213194; ZVBB-RV64-NEXT:    vmv2r.v v20, v813195; ZVBB-RV64-NEXT:    vmv1r.v v1, v2013196; ZVBB-RV64-NEXT:    vmv1r.v v3, v2213197; ZVBB-RV64-NEXT:    vmv1r.v v5, v2413198; ZVBB-RV64-NEXT:    vmv1r.v v7, v2613199; ZVBB-RV64-NEXT:    vmv1r.v v2, v1013200; ZVBB-RV64-NEXT:    csrr a1, vlenb13201; ZVBB-RV64-NEXT:    slli a2, a1, 313202; ZVBB-RV64-NEXT:    sub a1, a2, a113203; ZVBB-RV64-NEXT:    add a1, sp, a113204; ZVBB-RV64-NEXT:    addi a1, a1, 6413205; ZVBB-RV64-NEXT:    csrr a2, vlenb13206; ZVBB-RV64-NEXT:    vmv1r.v v4, v1413207; ZVBB-RV64-NEXT:    add a3, a0, a213208; ZVBB-RV64-NEXT:    add a4, a1, a213209; ZVBB-RV64-NEXT:    vmv1r.v v6, v1813210; ZVBB-RV64-NEXT:    add a5, a4, a213211; ZVBB-RV64-NEXT:    vmv1r.v v22, v1113212; ZVBB-RV64-NEXT:    add a6, a5, a213213; ZVBB-RV64-NEXT:    vmv1r.v v24, v1513214; ZVBB-RV64-NEXT:    vsseg7e32.v v1, (a0)13215; ZVBB-RV64-NEXT:    vmv1r.v v26, v1913216; ZVBB-RV64-NEXT:    vsseg7e32.v v21, (a1)13217; ZVBB-RV64-NEXT:    vl1re32.v v18, (a6)13218; ZVBB-RV64-NEXT:    add a6, a6, a213219; ZVBB-RV64-NEXT:    vl1re32.v v19, (a6)13220; ZVBB-RV64-NEXT:    add a6, a6, a213221; ZVBB-RV64-NEXT:    vl1re32.v v20, (a6)13222; ZVBB-RV64-NEXT:    add a6, a6, a213223; ZVBB-RV64-NEXT:    vl1re32.v v21, (a6)13224; ZVBB-RV64-NEXT:    add a6, a3, a213225; ZVBB-RV64-NEXT:    vl1re32.v v10, (a6)13226; ZVBB-RV64-NEXT:    add a6, a6, a213227; ZVBB-RV64-NEXT:    vl1re32.v v11, (a6)13228; ZVBB-RV64-NEXT:    vl1re32.v v8, (a0)13229; ZVBB-RV64-NEXT:    vl1re32.v v16, (a4)13230; ZVBB-RV64-NEXT:    vl1re32.v v9, (a3)13231; ZVBB-RV64-NEXT:    csrr a0, vlenb13232; ZVBB-RV64-NEXT:    li a3, 1413233; ZVBB-RV64-NEXT:    mul a0, a0, a313234; ZVBB-RV64-NEXT:    add a0, sp, a013235; ZVBB-RV64-NEXT:    addi a0, a0, 6413236; ZVBB-RV64-NEXT:    vl1re32.v v17, (a5)13237; ZVBB-RV64-NEXT:    slli a3, a2, 213238; ZVBB-RV64-NEXT:    add a6, a6, a213239; ZVBB-RV64-NEXT:    vl1re32.v v12, (a6)13240; ZVBB-RV64-NEXT:    add a6, a6, a213241; ZVBB-RV64-NEXT:    vl1re32.v v13, (a6)13242; ZVBB-RV64-NEXT:    add a6, a6, a213243; ZVBB-RV64-NEXT:    slli a2, a2, 313244; ZVBB-RV64-NEXT:    add a3, a2, a313245; ZVBB-RV64-NEXT:    add a2, a0, a213246; ZVBB-RV64-NEXT:    vl1re32.v v14, (a6)13247; ZVBB-RV64-NEXT:    vl1re32.v v15, (a1)13248; ZVBB-RV64-NEXT:    add a3, a0, a313249; ZVBB-RV64-NEXT:    vs2r.v v20, (a3)13250; ZVBB-RV64-NEXT:    vs4r.v v16, (a2)13251; ZVBB-RV64-NEXT:    vs8r.v v8, (a0)13252; ZVBB-RV64-NEXT:    vl8re32.v v16, (a2)13253; ZVBB-RV64-NEXT:    vl8re32.v v8, (a0)13254; ZVBB-RV64-NEXT:    addi sp, s0, -8013255; ZVBB-RV64-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload13256; ZVBB-RV64-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload13257; ZVBB-RV64-NEXT:    addi sp, sp, 8013258; ZVBB-RV64-NEXT:    ret13259;13260; ZIP-LABEL: vector_interleave_nxv28f32_nxv4f32:13261; ZIP:       # %bb.0:13262; ZIP-NEXT:    addi sp, sp, -8013263; ZIP-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill13264; ZIP-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill13265; ZIP-NEXT:    addi s0, sp, 8013266; ZIP-NEXT:    csrr a0, vlenb13267; ZIP-NEXT:    slli a0, a0, 513268; ZIP-NEXT:    sub sp, sp, a013269; ZIP-NEXT:    andi sp, sp, -6413270; ZIP-NEXT:    vsetvli a0, zero, e32, m1, ta, ma13271; ZIP-NEXT:    vmv2r.v v26, v2013272; ZIP-NEXT:    addi a0, sp, 6413273; ZIP-NEXT:    vmv2r.v v24, v1613274; ZIP-NEXT:    vmv2r.v v22, v1213275; ZIP-NEXT:    vmv2r.v v20, v813276; ZIP-NEXT:    vmv1r.v v1, v2013277; ZIP-NEXT:    vmv1r.v v3, v2213278; ZIP-NEXT:    vmv1r.v v5, v2413279; ZIP-NEXT:    vmv1r.v v7, v2613280; ZIP-NEXT:    vmv1r.v v2, v1013281; ZIP-NEXT:    csrr a1, vlenb13282; ZIP-NEXT:    slli a2, a1, 313283; ZIP-NEXT:    sub a1, a2, a113284; ZIP-NEXT:    add a1, sp, a113285; ZIP-NEXT:    addi a1, a1, 6413286; ZIP-NEXT:    csrr a2, vlenb13287; ZIP-NEXT:    vmv1r.v v4, v1413288; ZIP-NEXT:    add a3, a0, a213289; ZIP-NEXT:    add a4, a1, a213290; ZIP-NEXT:    vmv1r.v v6, v1813291; ZIP-NEXT:    add a5, a4, a213292; ZIP-NEXT:    vmv1r.v v22, v1113293; ZIP-NEXT:    add a6, a5, a213294; ZIP-NEXT:    vmv1r.v v24, v1513295; ZIP-NEXT:    vsseg7e32.v v1, (a0)13296; ZIP-NEXT:    vmv1r.v v26, v1913297; ZIP-NEXT:    vsseg7e32.v v21, (a1)13298; ZIP-NEXT:    vl1re32.v v18, (a6)13299; ZIP-NEXT:    add a6, a6, a213300; ZIP-NEXT:    vl1re32.v v19, (a6)13301; ZIP-NEXT:    add a6, a6, a213302; ZIP-NEXT:    vl1re32.v v20, (a6)13303; ZIP-NEXT:    add a6, a6, a213304; ZIP-NEXT:    vl1re32.v v21, (a6)13305; ZIP-NEXT:    add a6, a3, a213306; ZIP-NEXT:    vl1re32.v v10, (a6)13307; ZIP-NEXT:    add a6, a6, a213308; ZIP-NEXT:    vl1re32.v v11, (a6)13309; ZIP-NEXT:    vl1re32.v v8, (a0)13310; ZIP-NEXT:    vl1re32.v v16, (a4)13311; ZIP-NEXT:    vl1re32.v v9, (a3)13312; ZIP-NEXT:    csrr a0, vlenb13313; ZIP-NEXT:    li a3, 1413314; ZIP-NEXT:    mul a0, a0, a313315; ZIP-NEXT:    add a0, sp, a013316; ZIP-NEXT:    addi a0, a0, 6413317; ZIP-NEXT:    vl1re32.v v17, (a5)13318; ZIP-NEXT:    slli a3, a2, 213319; ZIP-NEXT:    add a6, a6, a213320; ZIP-NEXT:    vl1re32.v v12, (a6)13321; ZIP-NEXT:    add a6, a6, a213322; ZIP-NEXT:    vl1re32.v v13, (a6)13323; ZIP-NEXT:    add a6, a6, a213324; ZIP-NEXT:    slli a2, a2, 313325; ZIP-NEXT:    add a3, a2, a313326; ZIP-NEXT:    add a2, a0, a213327; ZIP-NEXT:    vl1re32.v v14, (a6)13328; ZIP-NEXT:    vl1re32.v v15, (a1)13329; ZIP-NEXT:    add a3, a0, a313330; ZIP-NEXT:    vs2r.v v20, (a3)13331; ZIP-NEXT:    vs4r.v v16, (a2)13332; ZIP-NEXT:    vs8r.v v8, (a0)13333; ZIP-NEXT:    vl8re32.v v16, (a2)13334; ZIP-NEXT:    vl8re32.v v8, (a0)13335; ZIP-NEXT:    addi sp, s0, -8013336; ZIP-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload13337; ZIP-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload13338; ZIP-NEXT:    addi sp, sp, 8013339; ZIP-NEXT:    ret13340  %res = call <vscale x 28 x float> @llvm.vector.interleave7.nxv28f32(<vscale x 4 x float> %v0, <vscale x 4 x float> %v1, <vscale x 4 x float> %v2, <vscale x 4 x float> %v3, <vscale x 4 x float> %v4, <vscale x 4 x float> %v5, <vscale x 4 x float> %v6)13341  ret <vscale x 28 x float> %res13342}13343 13344define <vscale x 7 x double> @vector_interleave_nxv7f64_nxv1f64(<vscale x 1 x double> %v0, <vscale x 1 x double> %v1, <vscale x 1 x double> %v2, <vscale x 1 x double> %v3, <vscale x 1 x double> %v4, <vscale x 1 x double> %v5, <vscale x 1 x double> %v6) nounwind {13345; CHECK-LABEL: vector_interleave_nxv7f64_nxv1f64:13346; CHECK:       # %bb.0:13347; CHECK-NEXT:    addi sp, sp, -1613348; CHECK-NEXT:    csrr a0, vlenb13349; CHECK-NEXT:    slli a1, a0, 313350; CHECK-NEXT:    sub a0, a1, a013351; CHECK-NEXT:    sub sp, sp, a013352; CHECK-NEXT:    addi a0, sp, 1613353; CHECK-NEXT:    csrr a1, vlenb13354; CHECK-NEXT:    add a2, a0, a113355; CHECK-NEXT:    add a3, a2, a113356; CHECK-NEXT:    vsetvli a4, zero, e64, m1, ta, ma13357; CHECK-NEXT:    vsseg7e64.v v8, (a0)13358; CHECK-NEXT:    vl1re64.v v10, (a3)13359; CHECK-NEXT:    add a3, a3, a113360; CHECK-NEXT:    vl1re64.v v11, (a3)13361; CHECK-NEXT:    add a3, a3, a113362; CHECK-NEXT:    vl1re64.v v8, (a0)13363; CHECK-NEXT:    add a0, a3, a113364; CHECK-NEXT:    vl1re64.v v9, (a2)13365; CHECK-NEXT:    vl1re64.v v12, (a3)13366; CHECK-NEXT:    vl1re64.v v13, (a0)13367; CHECK-NEXT:    add a0, a0, a113368; CHECK-NEXT:    vl1re64.v v14, (a0)13369; CHECK-NEXT:    csrr a0, vlenb13370; CHECK-NEXT:    slli a1, a0, 313371; CHECK-NEXT:    sub a0, a1, a013372; CHECK-NEXT:    add sp, sp, a013373; CHECK-NEXT:    addi sp, sp, 1613374; CHECK-NEXT:    ret13375;13376; ZVBB-LABEL: vector_interleave_nxv7f64_nxv1f64:13377; ZVBB:       # %bb.0:13378; ZVBB-NEXT:    addi sp, sp, -1613379; ZVBB-NEXT:    csrr a0, vlenb13380; ZVBB-NEXT:    slli a1, a0, 313381; ZVBB-NEXT:    sub a0, a1, a013382; ZVBB-NEXT:    sub sp, sp, a013383; ZVBB-NEXT:    addi a0, sp, 1613384; ZVBB-NEXT:    csrr a1, vlenb13385; ZVBB-NEXT:    add a2, a0, a113386; ZVBB-NEXT:    add a3, a2, a113387; ZVBB-NEXT:    vsetvli a4, zero, e64, m1, ta, ma13388; ZVBB-NEXT:    vsseg7e64.v v8, (a0)13389; ZVBB-NEXT:    vl1re64.v v10, (a3)13390; ZVBB-NEXT:    add a3, a3, a113391; ZVBB-NEXT:    vl1re64.v v11, (a3)13392; ZVBB-NEXT:    add a3, a3, a113393; ZVBB-NEXT:    vl1re64.v v8, (a0)13394; ZVBB-NEXT:    add a0, a3, a113395; ZVBB-NEXT:    vl1re64.v v9, (a2)13396; ZVBB-NEXT:    vl1re64.v v12, (a3)13397; ZVBB-NEXT:    vl1re64.v v13, (a0)13398; ZVBB-NEXT:    add a0, a0, a113399; ZVBB-NEXT:    vl1re64.v v14, (a0)13400; ZVBB-NEXT:    csrr a0, vlenb13401; ZVBB-NEXT:    slli a1, a0, 313402; ZVBB-NEXT:    sub a0, a1, a013403; ZVBB-NEXT:    add sp, sp, a013404; ZVBB-NEXT:    addi sp, sp, 1613405; ZVBB-NEXT:    ret13406  %res = call <vscale x 7 x double> @llvm.vector.interleave7.nxv7f64(<vscale x 1 x double> %v0, <vscale x 1 x double> %v1, <vscale x 1 x double> %v2, <vscale x 1 x double> %v3, <vscale x 1 x double> %v4, <vscale x 1 x double> %v5, <vscale x 1 x double> %v6)13407  ret <vscale x 7 x double> %res13408}13409 13410define <vscale x 14 x double> @vector_interleave_nxv14f64_nxv2f64(<vscale x 2 x double> %v0, <vscale x 2 x double> %v1, <vscale x 2 x double> %v2, <vscale x 2 x double> %v3, <vscale x 2 x double> %v4, <vscale x 2 x double> %v5, <vscale x 2 x double> %v6) nounwind {13411; RV32-LABEL: vector_interleave_nxv14f64_nxv2f64:13412; RV32:       # %bb.0:13413; RV32-NEXT:    addi sp, sp, -8013414; RV32-NEXT:    sw ra, 76(sp) # 4-byte Folded Spill13415; RV32-NEXT:    sw s0, 72(sp) # 4-byte Folded Spill13416; RV32-NEXT:    addi s0, sp, 8013417; RV32-NEXT:    csrr a0, vlenb13418; RV32-NEXT:    slli a0, a0, 513419; RV32-NEXT:    sub sp, sp, a013420; RV32-NEXT:    andi sp, sp, -6413421; RV32-NEXT:    vsetvli a0, zero, e64, m1, ta, ma13422; RV32-NEXT:    vmv2r.v v26, v2013423; RV32-NEXT:    addi a0, sp, 6413424; RV32-NEXT:    vmv2r.v v24, v1613425; RV32-NEXT:    vmv2r.v v22, v1213426; RV32-NEXT:    vmv2r.v v20, v813427; RV32-NEXT:    vmv1r.v v1, v2013428; RV32-NEXT:    vmv1r.v v3, v2213429; RV32-NEXT:    vmv1r.v v5, v2413430; RV32-NEXT:    vmv1r.v v7, v2613431; RV32-NEXT:    vmv1r.v v2, v1013432; RV32-NEXT:    csrr a1, vlenb13433; RV32-NEXT:    slli a2, a1, 313434; RV32-NEXT:    sub a1, a2, a113435; RV32-NEXT:    add a1, sp, a113436; RV32-NEXT:    addi a1, a1, 6413437; RV32-NEXT:    csrr a2, vlenb13438; RV32-NEXT:    vmv1r.v v4, v1413439; RV32-NEXT:    add a3, a0, a213440; RV32-NEXT:    add a4, a1, a213441; RV32-NEXT:    vmv1r.v v6, v1813442; RV32-NEXT:    add a5, a4, a213443; RV32-NEXT:    vmv1r.v v22, v1113444; RV32-NEXT:    add a6, a5, a213445; RV32-NEXT:    vmv1r.v v24, v1513446; RV32-NEXT:    vsseg7e64.v v1, (a0)13447; RV32-NEXT:    vmv1r.v v26, v1913448; RV32-NEXT:    vsseg7e64.v v21, (a1)13449; RV32-NEXT:    vl1re64.v v18, (a6)13450; RV32-NEXT:    add a6, a6, a213451; RV32-NEXT:    vl1re64.v v19, (a6)13452; RV32-NEXT:    add a6, a6, a213453; RV32-NEXT:    vl1re64.v v20, (a6)13454; RV32-NEXT:    add a6, a6, a213455; RV32-NEXT:    vl1re64.v v21, (a6)13456; RV32-NEXT:    add a6, a3, a213457; RV32-NEXT:    vl1re64.v v10, (a6)13458; RV32-NEXT:    add a6, a6, a213459; RV32-NEXT:    vl1re64.v v11, (a6)13460; RV32-NEXT:    vl1re64.v v8, (a0)13461; RV32-NEXT:    vl1re64.v v16, (a4)13462; RV32-NEXT:    vl1re64.v v9, (a3)13463; RV32-NEXT:    csrr a0, vlenb13464; RV32-NEXT:    li a3, 1413465; RV32-NEXT:    mul a0, a0, a313466; RV32-NEXT:    add a0, sp, a013467; RV32-NEXT:    addi a0, a0, 6413468; RV32-NEXT:    vl1re64.v v17, (a5)13469; RV32-NEXT:    slli a3, a2, 213470; RV32-NEXT:    add a6, a6, a213471; RV32-NEXT:    vl1re64.v v12, (a6)13472; RV32-NEXT:    add a6, a6, a213473; RV32-NEXT:    vl1re64.v v13, (a6)13474; RV32-NEXT:    add a6, a6, a213475; RV32-NEXT:    slli a2, a2, 313476; RV32-NEXT:    add a3, a2, a313477; RV32-NEXT:    add a2, a0, a213478; RV32-NEXT:    vl1re64.v v14, (a6)13479; RV32-NEXT:    vl1re64.v v15, (a1)13480; RV32-NEXT:    add a3, a0, a313481; RV32-NEXT:    vs2r.v v20, (a3)13482; RV32-NEXT:    vs4r.v v16, (a2)13483; RV32-NEXT:    vs8r.v v8, (a0)13484; RV32-NEXT:    vl8re64.v v16, (a2)13485; RV32-NEXT:    vl8re64.v v8, (a0)13486; RV32-NEXT:    addi sp, s0, -8013487; RV32-NEXT:    lw ra, 76(sp) # 4-byte Folded Reload13488; RV32-NEXT:    lw s0, 72(sp) # 4-byte Folded Reload13489; RV32-NEXT:    addi sp, sp, 8013490; RV32-NEXT:    ret13491;13492; RV64-LABEL: vector_interleave_nxv14f64_nxv2f64:13493; RV64:       # %bb.0:13494; RV64-NEXT:    addi sp, sp, -8013495; RV64-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill13496; RV64-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill13497; RV64-NEXT:    addi s0, sp, 8013498; RV64-NEXT:    csrr a0, vlenb13499; RV64-NEXT:    slli a0, a0, 513500; RV64-NEXT:    sub sp, sp, a013501; RV64-NEXT:    andi sp, sp, -6413502; RV64-NEXT:    vsetvli a0, zero, e64, m1, ta, ma13503; RV64-NEXT:    vmv2r.v v26, v2013504; RV64-NEXT:    addi a0, sp, 6413505; RV64-NEXT:    vmv2r.v v24, v1613506; RV64-NEXT:    vmv2r.v v22, v1213507; RV64-NEXT:    vmv2r.v v20, v813508; RV64-NEXT:    vmv1r.v v1, v2013509; RV64-NEXT:    vmv1r.v v3, v2213510; RV64-NEXT:    vmv1r.v v5, v2413511; RV64-NEXT:    vmv1r.v v7, v2613512; RV64-NEXT:    vmv1r.v v2, v1013513; RV64-NEXT:    csrr a1, vlenb13514; RV64-NEXT:    slli a2, a1, 313515; RV64-NEXT:    sub a1, a2, a113516; RV64-NEXT:    add a1, sp, a113517; RV64-NEXT:    addi a1, a1, 6413518; RV64-NEXT:    csrr a2, vlenb13519; RV64-NEXT:    vmv1r.v v4, v1413520; RV64-NEXT:    add a3, a0, a213521; RV64-NEXT:    add a4, a1, a213522; RV64-NEXT:    vmv1r.v v6, v1813523; RV64-NEXT:    add a5, a4, a213524; RV64-NEXT:    vmv1r.v v22, v1113525; RV64-NEXT:    add a6, a5, a213526; RV64-NEXT:    vmv1r.v v24, v1513527; RV64-NEXT:    vsseg7e64.v v1, (a0)13528; RV64-NEXT:    vmv1r.v v26, v1913529; RV64-NEXT:    vsseg7e64.v v21, (a1)13530; RV64-NEXT:    vl1re64.v v18, (a6)13531; RV64-NEXT:    add a6, a6, a213532; RV64-NEXT:    vl1re64.v v19, (a6)13533; RV64-NEXT:    add a6, a6, a213534; RV64-NEXT:    vl1re64.v v20, (a6)13535; RV64-NEXT:    add a6, a6, a213536; RV64-NEXT:    vl1re64.v v21, (a6)13537; RV64-NEXT:    add a6, a3, a213538; RV64-NEXT:    vl1re64.v v10, (a6)13539; RV64-NEXT:    add a6, a6, a213540; RV64-NEXT:    vl1re64.v v11, (a6)13541; RV64-NEXT:    vl1re64.v v8, (a0)13542; RV64-NEXT:    vl1re64.v v16, (a4)13543; RV64-NEXT:    vl1re64.v v9, (a3)13544; RV64-NEXT:    csrr a0, vlenb13545; RV64-NEXT:    li a3, 1413546; RV64-NEXT:    mul a0, a0, a313547; RV64-NEXT:    add a0, sp, a013548; RV64-NEXT:    addi a0, a0, 6413549; RV64-NEXT:    vl1re64.v v17, (a5)13550; RV64-NEXT:    slli a3, a2, 213551; RV64-NEXT:    add a6, a6, a213552; RV64-NEXT:    vl1re64.v v12, (a6)13553; RV64-NEXT:    add a6, a6, a213554; RV64-NEXT:    vl1re64.v v13, (a6)13555; RV64-NEXT:    add a6, a6, a213556; RV64-NEXT:    slli a2, a2, 313557; RV64-NEXT:    add a3, a2, a313558; RV64-NEXT:    add a2, a0, a213559; RV64-NEXT:    vl1re64.v v14, (a6)13560; RV64-NEXT:    vl1re64.v v15, (a1)13561; RV64-NEXT:    add a3, a0, a313562; RV64-NEXT:    vs2r.v v20, (a3)13563; RV64-NEXT:    vs4r.v v16, (a2)13564; RV64-NEXT:    vs8r.v v8, (a0)13565; RV64-NEXT:    vl8re64.v v16, (a2)13566; RV64-NEXT:    vl8re64.v v8, (a0)13567; RV64-NEXT:    addi sp, s0, -8013568; RV64-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload13569; RV64-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload13570; RV64-NEXT:    addi sp, sp, 8013571; RV64-NEXT:    ret13572;13573; ZVBB-RV32-LABEL: vector_interleave_nxv14f64_nxv2f64:13574; ZVBB-RV32:       # %bb.0:13575; ZVBB-RV32-NEXT:    addi sp, sp, -8013576; ZVBB-RV32-NEXT:    sw ra, 76(sp) # 4-byte Folded Spill13577; ZVBB-RV32-NEXT:    sw s0, 72(sp) # 4-byte Folded Spill13578; ZVBB-RV32-NEXT:    addi s0, sp, 8013579; ZVBB-RV32-NEXT:    csrr a0, vlenb13580; ZVBB-RV32-NEXT:    slli a0, a0, 513581; ZVBB-RV32-NEXT:    sub sp, sp, a013582; ZVBB-RV32-NEXT:    andi sp, sp, -6413583; ZVBB-RV32-NEXT:    vsetvli a0, zero, e64, m1, ta, ma13584; ZVBB-RV32-NEXT:    vmv2r.v v26, v2013585; ZVBB-RV32-NEXT:    addi a0, sp, 6413586; ZVBB-RV32-NEXT:    vmv2r.v v24, v1613587; ZVBB-RV32-NEXT:    vmv2r.v v22, v1213588; ZVBB-RV32-NEXT:    vmv2r.v v20, v813589; ZVBB-RV32-NEXT:    vmv1r.v v1, v2013590; ZVBB-RV32-NEXT:    vmv1r.v v3, v2213591; ZVBB-RV32-NEXT:    vmv1r.v v5, v2413592; ZVBB-RV32-NEXT:    vmv1r.v v7, v2613593; ZVBB-RV32-NEXT:    vmv1r.v v2, v1013594; ZVBB-RV32-NEXT:    csrr a1, vlenb13595; ZVBB-RV32-NEXT:    slli a2, a1, 313596; ZVBB-RV32-NEXT:    sub a1, a2, a113597; ZVBB-RV32-NEXT:    add a1, sp, a113598; ZVBB-RV32-NEXT:    addi a1, a1, 6413599; ZVBB-RV32-NEXT:    csrr a2, vlenb13600; ZVBB-RV32-NEXT:    vmv1r.v v4, v1413601; ZVBB-RV32-NEXT:    add a3, a0, a213602; ZVBB-RV32-NEXT:    add a4, a1, a213603; ZVBB-RV32-NEXT:    vmv1r.v v6, v1813604; ZVBB-RV32-NEXT:    add a5, a4, a213605; ZVBB-RV32-NEXT:    vmv1r.v v22, v1113606; ZVBB-RV32-NEXT:    add a6, a5, a213607; ZVBB-RV32-NEXT:    vmv1r.v v24, v1513608; ZVBB-RV32-NEXT:    vsseg7e64.v v1, (a0)13609; ZVBB-RV32-NEXT:    vmv1r.v v26, v1913610; ZVBB-RV32-NEXT:    vsseg7e64.v v21, (a1)13611; ZVBB-RV32-NEXT:    vl1re64.v v18, (a6)13612; ZVBB-RV32-NEXT:    add a6, a6, a213613; ZVBB-RV32-NEXT:    vl1re64.v v19, (a6)13614; ZVBB-RV32-NEXT:    add a6, a6, a213615; ZVBB-RV32-NEXT:    vl1re64.v v20, (a6)13616; ZVBB-RV32-NEXT:    add a6, a6, a213617; ZVBB-RV32-NEXT:    vl1re64.v v21, (a6)13618; ZVBB-RV32-NEXT:    add a6, a3, a213619; ZVBB-RV32-NEXT:    vl1re64.v v10, (a6)13620; ZVBB-RV32-NEXT:    add a6, a6, a213621; ZVBB-RV32-NEXT:    vl1re64.v v11, (a6)13622; ZVBB-RV32-NEXT:    vl1re64.v v8, (a0)13623; ZVBB-RV32-NEXT:    vl1re64.v v16, (a4)13624; ZVBB-RV32-NEXT:    vl1re64.v v9, (a3)13625; ZVBB-RV32-NEXT:    csrr a0, vlenb13626; ZVBB-RV32-NEXT:    li a3, 1413627; ZVBB-RV32-NEXT:    mul a0, a0, a313628; ZVBB-RV32-NEXT:    add a0, sp, a013629; ZVBB-RV32-NEXT:    addi a0, a0, 6413630; ZVBB-RV32-NEXT:    vl1re64.v v17, (a5)13631; ZVBB-RV32-NEXT:    slli a3, a2, 213632; ZVBB-RV32-NEXT:    add a6, a6, a213633; ZVBB-RV32-NEXT:    vl1re64.v v12, (a6)13634; ZVBB-RV32-NEXT:    add a6, a6, a213635; ZVBB-RV32-NEXT:    vl1re64.v v13, (a6)13636; ZVBB-RV32-NEXT:    add a6, a6, a213637; ZVBB-RV32-NEXT:    slli a2, a2, 313638; ZVBB-RV32-NEXT:    add a3, a2, a313639; ZVBB-RV32-NEXT:    add a2, a0, a213640; ZVBB-RV32-NEXT:    vl1re64.v v14, (a6)13641; ZVBB-RV32-NEXT:    vl1re64.v v15, (a1)13642; ZVBB-RV32-NEXT:    add a3, a0, a313643; ZVBB-RV32-NEXT:    vs2r.v v20, (a3)13644; ZVBB-RV32-NEXT:    vs4r.v v16, (a2)13645; ZVBB-RV32-NEXT:    vs8r.v v8, (a0)13646; ZVBB-RV32-NEXT:    vl8re64.v v16, (a2)13647; ZVBB-RV32-NEXT:    vl8re64.v v8, (a0)13648; ZVBB-RV32-NEXT:    addi sp, s0, -8013649; ZVBB-RV32-NEXT:    lw ra, 76(sp) # 4-byte Folded Reload13650; ZVBB-RV32-NEXT:    lw s0, 72(sp) # 4-byte Folded Reload13651; ZVBB-RV32-NEXT:    addi sp, sp, 8013652; ZVBB-RV32-NEXT:    ret13653;13654; ZVBB-RV64-LABEL: vector_interleave_nxv14f64_nxv2f64:13655; ZVBB-RV64:       # %bb.0:13656; ZVBB-RV64-NEXT:    addi sp, sp, -8013657; ZVBB-RV64-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill13658; ZVBB-RV64-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill13659; ZVBB-RV64-NEXT:    addi s0, sp, 8013660; ZVBB-RV64-NEXT:    csrr a0, vlenb13661; ZVBB-RV64-NEXT:    slli a0, a0, 513662; ZVBB-RV64-NEXT:    sub sp, sp, a013663; ZVBB-RV64-NEXT:    andi sp, sp, -6413664; ZVBB-RV64-NEXT:    vsetvli a0, zero, e64, m1, ta, ma13665; ZVBB-RV64-NEXT:    vmv2r.v v26, v2013666; ZVBB-RV64-NEXT:    addi a0, sp, 6413667; ZVBB-RV64-NEXT:    vmv2r.v v24, v1613668; ZVBB-RV64-NEXT:    vmv2r.v v22, v1213669; ZVBB-RV64-NEXT:    vmv2r.v v20, v813670; ZVBB-RV64-NEXT:    vmv1r.v v1, v2013671; ZVBB-RV64-NEXT:    vmv1r.v v3, v2213672; ZVBB-RV64-NEXT:    vmv1r.v v5, v2413673; ZVBB-RV64-NEXT:    vmv1r.v v7, v2613674; ZVBB-RV64-NEXT:    vmv1r.v v2, v1013675; ZVBB-RV64-NEXT:    csrr a1, vlenb13676; ZVBB-RV64-NEXT:    slli a2, a1, 313677; ZVBB-RV64-NEXT:    sub a1, a2, a113678; ZVBB-RV64-NEXT:    add a1, sp, a113679; ZVBB-RV64-NEXT:    addi a1, a1, 6413680; ZVBB-RV64-NEXT:    csrr a2, vlenb13681; ZVBB-RV64-NEXT:    vmv1r.v v4, v1413682; ZVBB-RV64-NEXT:    add a3, a0, a213683; ZVBB-RV64-NEXT:    add a4, a1, a213684; ZVBB-RV64-NEXT:    vmv1r.v v6, v1813685; ZVBB-RV64-NEXT:    add a5, a4, a213686; ZVBB-RV64-NEXT:    vmv1r.v v22, v1113687; ZVBB-RV64-NEXT:    add a6, a5, a213688; ZVBB-RV64-NEXT:    vmv1r.v v24, v1513689; ZVBB-RV64-NEXT:    vsseg7e64.v v1, (a0)13690; ZVBB-RV64-NEXT:    vmv1r.v v26, v1913691; ZVBB-RV64-NEXT:    vsseg7e64.v v21, (a1)13692; ZVBB-RV64-NEXT:    vl1re64.v v18, (a6)13693; ZVBB-RV64-NEXT:    add a6, a6, a213694; ZVBB-RV64-NEXT:    vl1re64.v v19, (a6)13695; ZVBB-RV64-NEXT:    add a6, a6, a213696; ZVBB-RV64-NEXT:    vl1re64.v v20, (a6)13697; ZVBB-RV64-NEXT:    add a6, a6, a213698; ZVBB-RV64-NEXT:    vl1re64.v v21, (a6)13699; ZVBB-RV64-NEXT:    add a6, a3, a213700; ZVBB-RV64-NEXT:    vl1re64.v v10, (a6)13701; ZVBB-RV64-NEXT:    add a6, a6, a213702; ZVBB-RV64-NEXT:    vl1re64.v v11, (a6)13703; ZVBB-RV64-NEXT:    vl1re64.v v8, (a0)13704; ZVBB-RV64-NEXT:    vl1re64.v v16, (a4)13705; ZVBB-RV64-NEXT:    vl1re64.v v9, (a3)13706; ZVBB-RV64-NEXT:    csrr a0, vlenb13707; ZVBB-RV64-NEXT:    li a3, 1413708; ZVBB-RV64-NEXT:    mul a0, a0, a313709; ZVBB-RV64-NEXT:    add a0, sp, a013710; ZVBB-RV64-NEXT:    addi a0, a0, 6413711; ZVBB-RV64-NEXT:    vl1re64.v v17, (a5)13712; ZVBB-RV64-NEXT:    slli a3, a2, 213713; ZVBB-RV64-NEXT:    add a6, a6, a213714; ZVBB-RV64-NEXT:    vl1re64.v v12, (a6)13715; ZVBB-RV64-NEXT:    add a6, a6, a213716; ZVBB-RV64-NEXT:    vl1re64.v v13, (a6)13717; ZVBB-RV64-NEXT:    add a6, a6, a213718; ZVBB-RV64-NEXT:    slli a2, a2, 313719; ZVBB-RV64-NEXT:    add a3, a2, a313720; ZVBB-RV64-NEXT:    add a2, a0, a213721; ZVBB-RV64-NEXT:    vl1re64.v v14, (a6)13722; ZVBB-RV64-NEXT:    vl1re64.v v15, (a1)13723; ZVBB-RV64-NEXT:    add a3, a0, a313724; ZVBB-RV64-NEXT:    vs2r.v v20, (a3)13725; ZVBB-RV64-NEXT:    vs4r.v v16, (a2)13726; ZVBB-RV64-NEXT:    vs8r.v v8, (a0)13727; ZVBB-RV64-NEXT:    vl8re64.v v16, (a2)13728; ZVBB-RV64-NEXT:    vl8re64.v v8, (a0)13729; ZVBB-RV64-NEXT:    addi sp, s0, -8013730; ZVBB-RV64-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload13731; ZVBB-RV64-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload13732; ZVBB-RV64-NEXT:    addi sp, sp, 8013733; ZVBB-RV64-NEXT:    ret13734;13735; ZIP-LABEL: vector_interleave_nxv14f64_nxv2f64:13736; ZIP:       # %bb.0:13737; ZIP-NEXT:    addi sp, sp, -8013738; ZIP-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill13739; ZIP-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill13740; ZIP-NEXT:    addi s0, sp, 8013741; ZIP-NEXT:    csrr a0, vlenb13742; ZIP-NEXT:    slli a0, a0, 513743; ZIP-NEXT:    sub sp, sp, a013744; ZIP-NEXT:    andi sp, sp, -6413745; ZIP-NEXT:    vsetvli a0, zero, e64, m1, ta, ma13746; ZIP-NEXT:    vmv2r.v v26, v2013747; ZIP-NEXT:    addi a0, sp, 6413748; ZIP-NEXT:    vmv2r.v v24, v1613749; ZIP-NEXT:    vmv2r.v v22, v1213750; ZIP-NEXT:    vmv2r.v v20, v813751; ZIP-NEXT:    vmv1r.v v1, v2013752; ZIP-NEXT:    vmv1r.v v3, v2213753; ZIP-NEXT:    vmv1r.v v5, v2413754; ZIP-NEXT:    vmv1r.v v7, v2613755; ZIP-NEXT:    vmv1r.v v2, v1013756; ZIP-NEXT:    csrr a1, vlenb13757; ZIP-NEXT:    slli a2, a1, 313758; ZIP-NEXT:    sub a1, a2, a113759; ZIP-NEXT:    add a1, sp, a113760; ZIP-NEXT:    addi a1, a1, 6413761; ZIP-NEXT:    csrr a2, vlenb13762; ZIP-NEXT:    vmv1r.v v4, v1413763; ZIP-NEXT:    add a3, a0, a213764; ZIP-NEXT:    add a4, a1, a213765; ZIP-NEXT:    vmv1r.v v6, v1813766; ZIP-NEXT:    add a5, a4, a213767; ZIP-NEXT:    vmv1r.v v22, v1113768; ZIP-NEXT:    add a6, a5, a213769; ZIP-NEXT:    vmv1r.v v24, v1513770; ZIP-NEXT:    vsseg7e64.v v1, (a0)13771; ZIP-NEXT:    vmv1r.v v26, v1913772; ZIP-NEXT:    vsseg7e64.v v21, (a1)13773; ZIP-NEXT:    vl1re64.v v18, (a6)13774; ZIP-NEXT:    add a6, a6, a213775; ZIP-NEXT:    vl1re64.v v19, (a6)13776; ZIP-NEXT:    add a6, a6, a213777; ZIP-NEXT:    vl1re64.v v20, (a6)13778; ZIP-NEXT:    add a6, a6, a213779; ZIP-NEXT:    vl1re64.v v21, (a6)13780; ZIP-NEXT:    add a6, a3, a213781; ZIP-NEXT:    vl1re64.v v10, (a6)13782; ZIP-NEXT:    add a6, a6, a213783; ZIP-NEXT:    vl1re64.v v11, (a6)13784; ZIP-NEXT:    vl1re64.v v8, (a0)13785; ZIP-NEXT:    vl1re64.v v16, (a4)13786; ZIP-NEXT:    vl1re64.v v9, (a3)13787; ZIP-NEXT:    csrr a0, vlenb13788; ZIP-NEXT:    li a3, 1413789; ZIP-NEXT:    mul a0, a0, a313790; ZIP-NEXT:    add a0, sp, a013791; ZIP-NEXT:    addi a0, a0, 6413792; ZIP-NEXT:    vl1re64.v v17, (a5)13793; ZIP-NEXT:    slli a3, a2, 213794; ZIP-NEXT:    add a6, a6, a213795; ZIP-NEXT:    vl1re64.v v12, (a6)13796; ZIP-NEXT:    add a6, a6, a213797; ZIP-NEXT:    vl1re64.v v13, (a6)13798; ZIP-NEXT:    add a6, a6, a213799; ZIP-NEXT:    slli a2, a2, 313800; ZIP-NEXT:    add a3, a2, a313801; ZIP-NEXT:    add a2, a0, a213802; ZIP-NEXT:    vl1re64.v v14, (a6)13803; ZIP-NEXT:    vl1re64.v v15, (a1)13804; ZIP-NEXT:    add a3, a0, a313805; ZIP-NEXT:    vs2r.v v20, (a3)13806; ZIP-NEXT:    vs4r.v v16, (a2)13807; ZIP-NEXT:    vs8r.v v8, (a0)13808; ZIP-NEXT:    vl8re64.v v16, (a2)13809; ZIP-NEXT:    vl8re64.v v8, (a0)13810; ZIP-NEXT:    addi sp, s0, -8013811; ZIP-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload13812; ZIP-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload13813; ZIP-NEXT:    addi sp, sp, 8013814; ZIP-NEXT:    ret13815  %res = call <vscale x 14 x double> @llvm.vector.interleave7.nxv14f64(<vscale x 2 x double> %v0, <vscale x 2 x double> %v1, <vscale x 2 x double> %v2, <vscale x 2 x double> %v3, <vscale x 2 x double> %v4, <vscale x 2 x double> %v5, <vscale x 2 x double> %v6)13816  ret <vscale x 14 x double> %res13817}13818 13819define <vscale x 16 x half> @vector_interleave_nxv16f16_nxv2f16(<vscale x 2 x half> %v0, <vscale x 2 x half> %v1, <vscale x 2 x half> %v2, <vscale x 2 x half> %v3, <vscale x 2 x half> %v4, <vscale x 2 x half> %v5, <vscale x 2 x half> %v6, <vscale x 2 x half> %v7) nounwind {13820; CHECK-LABEL: vector_interleave_nxv16f16_nxv2f16:13821; CHECK:       # %bb.0:13822; CHECK-NEXT:    addi sp, sp, -1613823; CHECK-NEXT:    csrr a0, vlenb13824; CHECK-NEXT:    slli a0, a0, 213825; CHECK-NEXT:    sub sp, sp, a013826; CHECK-NEXT:    addi a0, sp, 1613827; CHECK-NEXT:    csrr a1, vlenb13828; CHECK-NEXT:    srli a2, a1, 113829; CHECK-NEXT:    add a3, a0, a213830; CHECK-NEXT:    add a4, a3, a213831; CHECK-NEXT:    add a5, a4, a213832; CHECK-NEXT:    add a6, a5, a213833; CHECK-NEXT:    add a7, a6, a213834; CHECK-NEXT:    vsetvli t0, zero, e16, mf2, ta, ma13835; CHECK-NEXT:    vsseg8e16.v v8, (a0)13836; CHECK-NEXT:    add t0, a7, a213837; CHECK-NEXT:    add a2, t0, a213838; CHECK-NEXT:    vle16.v v11, (t0)13839; CHECK-NEXT:    vle16.v v8, (a2)13840; CHECK-NEXT:    srli a1, a1, 213841; CHECK-NEXT:    vle16.v v9, (a7)13842; CHECK-NEXT:    vsetvli a2, zero, e16, m1, ta, ma13843; CHECK-NEXT:    vslideup.vx v11, v8, a113844; CHECK-NEXT:    vsetvli a2, zero, e16, mf2, ta, ma13845; CHECK-NEXT:    vle16.v v10, (a6)13846; CHECK-NEXT:    vle16.v v8, (a5)13847; CHECK-NEXT:    vsetvli a2, zero, e16, m1, ta, ma13848; CHECK-NEXT:    vslideup.vx v10, v9, a113849; CHECK-NEXT:    vsetvli a2, zero, e16, mf2, ta, ma13850; CHECK-NEXT:    vle16.v v9, (a4)13851; CHECK-NEXT:    vsetvli a2, zero, e16, m1, ta, ma13852; CHECK-NEXT:    vslideup.vx v9, v8, a113853; CHECK-NEXT:    vsetvli a2, zero, e16, mf2, ta, ma13854; CHECK-NEXT:    vle16.v v12, (a3)13855; CHECK-NEXT:    vle16.v v8, (a0)13856; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma13857; CHECK-NEXT:    vslideup.vx v8, v12, a113858; CHECK-NEXT:    csrr a0, vlenb13859; CHECK-NEXT:    slli a0, a0, 213860; CHECK-NEXT:    add sp, sp, a013861; CHECK-NEXT:    addi sp, sp, 1613862; CHECK-NEXT:    ret13863;13864; ZVBB-LABEL: vector_interleave_nxv16f16_nxv2f16:13865; ZVBB:       # %bb.0:13866; ZVBB-NEXT:    addi sp, sp, -1613867; ZVBB-NEXT:    csrr a0, vlenb13868; ZVBB-NEXT:    slli a0, a0, 213869; ZVBB-NEXT:    sub sp, sp, a013870; ZVBB-NEXT:    addi a0, sp, 1613871; ZVBB-NEXT:    csrr a1, vlenb13872; ZVBB-NEXT:    srli a2, a1, 113873; ZVBB-NEXT:    add a3, a0, a213874; ZVBB-NEXT:    add a4, a3, a213875; ZVBB-NEXT:    add a5, a4, a213876; ZVBB-NEXT:    add a6, a5, a213877; ZVBB-NEXT:    add a7, a6, a213878; ZVBB-NEXT:    vsetvli t0, zero, e16, mf2, ta, ma13879; ZVBB-NEXT:    vsseg8e16.v v8, (a0)13880; ZVBB-NEXT:    add t0, a7, a213881; ZVBB-NEXT:    add a2, t0, a213882; ZVBB-NEXT:    vle16.v v11, (t0)13883; ZVBB-NEXT:    vle16.v v8, (a2)13884; ZVBB-NEXT:    srli a1, a1, 213885; ZVBB-NEXT:    vle16.v v9, (a7)13886; ZVBB-NEXT:    vsetvli a2, zero, e16, m1, ta, ma13887; ZVBB-NEXT:    vslideup.vx v11, v8, a113888; ZVBB-NEXT:    vsetvli a2, zero, e16, mf2, ta, ma13889; ZVBB-NEXT:    vle16.v v10, (a6)13890; ZVBB-NEXT:    vle16.v v8, (a5)13891; ZVBB-NEXT:    vsetvli a2, zero, e16, m1, ta, ma13892; ZVBB-NEXT:    vslideup.vx v10, v9, a113893; ZVBB-NEXT:    vsetvli a2, zero, e16, mf2, ta, ma13894; ZVBB-NEXT:    vle16.v v9, (a4)13895; ZVBB-NEXT:    vsetvli a2, zero, e16, m1, ta, ma13896; ZVBB-NEXT:    vslideup.vx v9, v8, a113897; ZVBB-NEXT:    vsetvli a2, zero, e16, mf2, ta, ma13898; ZVBB-NEXT:    vle16.v v12, (a3)13899; ZVBB-NEXT:    vle16.v v8, (a0)13900; ZVBB-NEXT:    vsetvli a0, zero, e16, m1, ta, ma13901; ZVBB-NEXT:    vslideup.vx v8, v12, a113902; ZVBB-NEXT:    csrr a0, vlenb13903; ZVBB-NEXT:    slli a0, a0, 213904; ZVBB-NEXT:    add sp, sp, a013905; ZVBB-NEXT:    addi sp, sp, 1613906; ZVBB-NEXT:    ret13907  %res = call <vscale x 16 x half> @llvm.vector.interleave8.nxv16f16(<vscale x 2 x half> %v0, <vscale x 2 x half> %v1, <vscale x 2 x half> %v2, <vscale x 2 x half> %v3, <vscale x 2 x half> %v4, <vscale x 2 x half> %v5, <vscale x 2 x half> %v6, <vscale x 2 x half> %v7)13908  ret <vscale x 16 x half> %res13909}13910 13911define <vscale x 32 x half> @vector_interleave_nxv32f16_nxv4f16(<vscale x 4 x half> %v0, <vscale x 4 x half> %v1, <vscale x 4 x half> %v2, <vscale x 4 x half> %v3, <vscale x 4 x half> %v4, <vscale x 4 x half> %v5, <vscale x 4 x half> %v6, <vscale x 4 x half> %v7) nounwind {13912; CHECK-LABEL: vector_interleave_nxv32f16_nxv4f16:13913; CHECK:       # %bb.0:13914; CHECK-NEXT:    addi sp, sp, -1613915; CHECK-NEXT:    csrr a0, vlenb13916; CHECK-NEXT:    slli a0, a0, 313917; CHECK-NEXT:    sub sp, sp, a013918; CHECK-NEXT:    addi a0, sp, 1613919; CHECK-NEXT:    csrr a1, vlenb13920; CHECK-NEXT:    add a2, a0, a113921; CHECK-NEXT:    add a3, a2, a113922; CHECK-NEXT:    add a4, a3, a113923; CHECK-NEXT:    add a5, a4, a113924; CHECK-NEXT:    add a6, a5, a113925; CHECK-NEXT:    add a7, a6, a113926; CHECK-NEXT:    vsetvli t0, zero, e16, m1, ta, ma13927; CHECK-NEXT:    vsseg8e16.v v8, (a0)13928; CHECK-NEXT:    vl1re16.v v14, (a7)13929; CHECK-NEXT:    add a1, a7, a113930; CHECK-NEXT:    vl1re16.v v15, (a1)13931; CHECK-NEXT:    vl1re16.v v12, (a5)13932; CHECK-NEXT:    vl1re16.v v13, (a6)13933; CHECK-NEXT:    vl1re16.v v10, (a3)13934; CHECK-NEXT:    vl1re16.v v11, (a4)13935; CHECK-NEXT:    vl1re16.v v8, (a0)13936; CHECK-NEXT:    vl1re16.v v9, (a2)13937; CHECK-NEXT:    csrr a0, vlenb13938; CHECK-NEXT:    slli a0, a0, 313939; CHECK-NEXT:    add sp, sp, a013940; CHECK-NEXT:    addi sp, sp, 1613941; CHECK-NEXT:    ret13942;13943; ZVBB-LABEL: vector_interleave_nxv32f16_nxv4f16:13944; ZVBB:       # %bb.0:13945; ZVBB-NEXT:    addi sp, sp, -1613946; ZVBB-NEXT:    csrr a0, vlenb13947; ZVBB-NEXT:    slli a0, a0, 313948; ZVBB-NEXT:    sub sp, sp, a013949; ZVBB-NEXT:    addi a0, sp, 1613950; ZVBB-NEXT:    csrr a1, vlenb13951; ZVBB-NEXT:    add a2, a0, a113952; ZVBB-NEXT:    add a3, a2, a113953; ZVBB-NEXT:    add a4, a3, a113954; ZVBB-NEXT:    add a5, a4, a113955; ZVBB-NEXT:    add a6, a5, a113956; ZVBB-NEXT:    add a7, a6, a113957; ZVBB-NEXT:    vsetvli t0, zero, e16, m1, ta, ma13958; ZVBB-NEXT:    vsseg8e16.v v8, (a0)13959; ZVBB-NEXT:    vl1re16.v v14, (a7)13960; ZVBB-NEXT:    add a1, a7, a113961; ZVBB-NEXT:    vl1re16.v v15, (a1)13962; ZVBB-NEXT:    vl1re16.v v12, (a5)13963; ZVBB-NEXT:    vl1re16.v v13, (a6)13964; ZVBB-NEXT:    vl1re16.v v10, (a3)13965; ZVBB-NEXT:    vl1re16.v v11, (a4)13966; ZVBB-NEXT:    vl1re16.v v8, (a0)13967; ZVBB-NEXT:    vl1re16.v v9, (a2)13968; ZVBB-NEXT:    csrr a0, vlenb13969; ZVBB-NEXT:    slli a0, a0, 313970; ZVBB-NEXT:    add sp, sp, a013971; ZVBB-NEXT:    addi sp, sp, 1613972; ZVBB-NEXT:    ret13973  %res = call <vscale x 32 x half> @llvm.vector.interleave8.nxv32f16(<vscale x 4 x half> %v0, <vscale x 4 x half> %v1, <vscale x 4 x half> %v2, <vscale x 4 x half> %v3, <vscale x 4 x half> %v4, <vscale x 4 x half> %v5, <vscale x 4 x half> %v6, <vscale x 4 x half> %v7)13974  ret <vscale x 32 x half> %res13975}13976 13977define <vscale x 64 x half> @vector_interleave_nxv64f16_nxv8f16(<vscale x 8 x half> %v0, <vscale x 8 x half> %v1, <vscale x 8 x half> %v2, <vscale x 8 x half> %v3, <vscale x 8 x half> %v4, <vscale x 8 x half> %v5, <vscale x 8 x half> %v6, <vscale x 8 x half> %v7) nounwind {13978; CHECK-LABEL: vector_interleave_nxv64f16_nxv8f16:13979; CHECK:       # %bb.0:13980; CHECK-NEXT:    addi sp, sp, -1613981; CHECK-NEXT:    csrr a0, vlenb13982; CHECK-NEXT:    slli a0, a0, 413983; CHECK-NEXT:    sub sp, sp, a013984; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma13985; CHECK-NEXT:    vmv2r.v v28, v2213986; CHECK-NEXT:    addi a0, sp, 1613987; CHECK-NEXT:    vmv2r.v v26, v1813988; CHECK-NEXT:    csrr a1, vlenb13989; CHECK-NEXT:    slli a1, a1, 313990; CHECK-NEXT:    add a1, sp, a113991; CHECK-NEXT:    addi a1, a1, 1613992; CHECK-NEXT:    csrr a3, vlenb13993; CHECK-NEXT:    add a2, a0, a313994; CHECK-NEXT:    add a4, a1, a313995; CHECK-NEXT:    add a5, a2, a313996; CHECK-NEXT:    vmv1r.v v1, v813997; CHECK-NEXT:    vmv2r.v v24, v1413998; CHECK-NEXT:    add a6, a4, a313999; CHECK-NEXT:    vmv2r.v v22, v1014000; CHECK-NEXT:    vmv1r.v v2, v2214001; CHECK-NEXT:    add a7, a5, a314002; CHECK-NEXT:    vmv1r.v v3, v1214003; CHECK-NEXT:    add t0, a6, a314004; CHECK-NEXT:    vmv1r.v v4, v2414005; CHECK-NEXT:    add t1, a7, a314006; CHECK-NEXT:    vmv1r.v v5, v1614007; CHECK-NEXT:    add t2, t0, a314008; CHECK-NEXT:    vmv1r.v v6, v2614009; CHECK-NEXT:    add t3, t1, a314010; CHECK-NEXT:    vmv1r.v v7, v2014011; CHECK-NEXT:    add t4, t2, a314012; CHECK-NEXT:    vmv1r.v v8, v2814013; CHECK-NEXT:    vmv1r.v v22, v914014; CHECK-NEXT:    add t5, t3, a314015; CHECK-NEXT:    vmv1r.v v24, v1314016; CHECK-NEXT:    add t6, t4, a314017; CHECK-NEXT:    vmv1r.v v26, v1714018; CHECK-NEXT:    vsseg8e16.v v1, (a0)14019; CHECK-NEXT:    vmv1r.v v28, v2114020; CHECK-NEXT:    vsseg8e16.v v22, (a1)14021; CHECK-NEXT:    vl1re16.v v14, (t5)14022; CHECK-NEXT:    add t5, t5, a314023; CHECK-NEXT:    add a3, t6, a314024; CHECK-NEXT:    vl1re16.v v22, (t6)14025; CHECK-NEXT:    vl1re16.v v15, (t5)14026; CHECK-NEXT:    vl1re16.v v23, (a3)14027; CHECK-NEXT:    vl1re16.v v12, (t1)14028; CHECK-NEXT:    vl1re16.v v20, (t2)14029; CHECK-NEXT:    vl1re16.v v13, (t3)14030; CHECK-NEXT:    vl1re16.v v21, (t4)14031; CHECK-NEXT:    vl1re16.v v10, (a5)14032; CHECK-NEXT:    vl1re16.v v18, (a6)14033; CHECK-NEXT:    vl1re16.v v11, (a7)14034; CHECK-NEXT:    vl1re16.v v19, (t0)14035; CHECK-NEXT:    vl1re16.v v8, (a0)14036; CHECK-NEXT:    vl1re16.v v16, (a1)14037; CHECK-NEXT:    vl1re16.v v9, (a2)14038; CHECK-NEXT:    vl1re16.v v17, (a4)14039; CHECK-NEXT:    csrr a0, vlenb14040; CHECK-NEXT:    slli a0, a0, 414041; CHECK-NEXT:    add sp, sp, a014042; CHECK-NEXT:    addi sp, sp, 1614043; CHECK-NEXT:    ret14044;14045; ZVBB-LABEL: vector_interleave_nxv64f16_nxv8f16:14046; ZVBB:       # %bb.0:14047; ZVBB-NEXT:    addi sp, sp, -1614048; ZVBB-NEXT:    csrr a0, vlenb14049; ZVBB-NEXT:    slli a0, a0, 414050; ZVBB-NEXT:    sub sp, sp, a014051; ZVBB-NEXT:    vsetvli a0, zero, e16, m1, ta, ma14052; ZVBB-NEXT:    vmv2r.v v28, v2214053; ZVBB-NEXT:    addi a0, sp, 1614054; ZVBB-NEXT:    vmv2r.v v26, v1814055; ZVBB-NEXT:    csrr a1, vlenb14056; ZVBB-NEXT:    slli a1, a1, 314057; ZVBB-NEXT:    add a1, sp, a114058; ZVBB-NEXT:    addi a1, a1, 1614059; ZVBB-NEXT:    csrr a3, vlenb14060; ZVBB-NEXT:    add a2, a0, a314061; ZVBB-NEXT:    add a4, a1, a314062; ZVBB-NEXT:    add a5, a2, a314063; ZVBB-NEXT:    vmv1r.v v1, v814064; ZVBB-NEXT:    vmv2r.v v24, v1414065; ZVBB-NEXT:    add a6, a4, a314066; ZVBB-NEXT:    vmv2r.v v22, v1014067; ZVBB-NEXT:    vmv1r.v v2, v2214068; ZVBB-NEXT:    add a7, a5, a314069; ZVBB-NEXT:    vmv1r.v v3, v1214070; ZVBB-NEXT:    add t0, a6, a314071; ZVBB-NEXT:    vmv1r.v v4, v2414072; ZVBB-NEXT:    add t1, a7, a314073; ZVBB-NEXT:    vmv1r.v v5, v1614074; ZVBB-NEXT:    add t2, t0, a314075; ZVBB-NEXT:    vmv1r.v v6, v2614076; ZVBB-NEXT:    add t3, t1, a314077; ZVBB-NEXT:    vmv1r.v v7, v2014078; ZVBB-NEXT:    add t4, t2, a314079; ZVBB-NEXT:    vmv1r.v v8, v2814080; ZVBB-NEXT:    vmv1r.v v22, v914081; ZVBB-NEXT:    add t5, t3, a314082; ZVBB-NEXT:    vmv1r.v v24, v1314083; ZVBB-NEXT:    add t6, t4, a314084; ZVBB-NEXT:    vmv1r.v v26, v1714085; ZVBB-NEXT:    vsseg8e16.v v1, (a0)14086; ZVBB-NEXT:    vmv1r.v v28, v2114087; ZVBB-NEXT:    vsseg8e16.v v22, (a1)14088; ZVBB-NEXT:    vl1re16.v v14, (t5)14089; ZVBB-NEXT:    add t5, t5, a314090; ZVBB-NEXT:    add a3, t6, a314091; ZVBB-NEXT:    vl1re16.v v22, (t6)14092; ZVBB-NEXT:    vl1re16.v v15, (t5)14093; ZVBB-NEXT:    vl1re16.v v23, (a3)14094; ZVBB-NEXT:    vl1re16.v v12, (t1)14095; ZVBB-NEXT:    vl1re16.v v20, (t2)14096; ZVBB-NEXT:    vl1re16.v v13, (t3)14097; ZVBB-NEXT:    vl1re16.v v21, (t4)14098; ZVBB-NEXT:    vl1re16.v v10, (a5)14099; ZVBB-NEXT:    vl1re16.v v18, (a6)14100; ZVBB-NEXT:    vl1re16.v v11, (a7)14101; ZVBB-NEXT:    vl1re16.v v19, (t0)14102; ZVBB-NEXT:    vl1re16.v v8, (a0)14103; ZVBB-NEXT:    vl1re16.v v16, (a1)14104; ZVBB-NEXT:    vl1re16.v v9, (a2)14105; ZVBB-NEXT:    vl1re16.v v17, (a4)14106; ZVBB-NEXT:    csrr a0, vlenb14107; ZVBB-NEXT:    slli a0, a0, 414108; ZVBB-NEXT:    add sp, sp, a014109; ZVBB-NEXT:    addi sp, sp, 1614110; ZVBB-NEXT:    ret14111  %res = call <vscale x 64 x half> @llvm.vector.interleave8.nxv64f16(<vscale x 8 x half> %v0, <vscale x 8 x half> %v1, <vscale x 8 x half> %v2, <vscale x 8 x half> %v3, <vscale x 8 x half> %v4, <vscale x 8 x half> %v5, <vscale x 8 x half> %v6, <vscale x 8 x half> %v7)14112  ret <vscale x 64 x half> %res14113}14114 14115define <vscale x 16 x bfloat> @vector_interleave_nxv16bf16_nxv2bf16(<vscale x 2 x bfloat> %v0, <vscale x 2 x bfloat> %v1, <vscale x 2 x bfloat> %v2, <vscale x 2 x bfloat> %v3, <vscale x 2 x bfloat> %v4, <vscale x 2 x bfloat> %v5, <vscale x 2 x bfloat> %v6, <vscale x 2 x bfloat> %v7) nounwind {14116; CHECK-LABEL: vector_interleave_nxv16bf16_nxv2bf16:14117; CHECK:       # %bb.0:14118; CHECK-NEXT:    addi sp, sp, -1614119; CHECK-NEXT:    csrr a0, vlenb14120; CHECK-NEXT:    slli a0, a0, 214121; CHECK-NEXT:    sub sp, sp, a014122; CHECK-NEXT:    addi a0, sp, 1614123; CHECK-NEXT:    csrr a1, vlenb14124; CHECK-NEXT:    srli a2, a1, 114125; CHECK-NEXT:    add a3, a0, a214126; CHECK-NEXT:    add a4, a3, a214127; CHECK-NEXT:    add a5, a4, a214128; CHECK-NEXT:    add a6, a5, a214129; CHECK-NEXT:    add a7, a6, a214130; CHECK-NEXT:    vsetvli t0, zero, e16, mf2, ta, ma14131; CHECK-NEXT:    vsseg8e16.v v8, (a0)14132; CHECK-NEXT:    add t0, a7, a214133; CHECK-NEXT:    add a2, t0, a214134; CHECK-NEXT:    vle16.v v11, (t0)14135; CHECK-NEXT:    vle16.v v8, (a2)14136; CHECK-NEXT:    srli a1, a1, 214137; CHECK-NEXT:    vle16.v v9, (a7)14138; CHECK-NEXT:    vsetvli a2, zero, e16, m1, ta, ma14139; CHECK-NEXT:    vslideup.vx v11, v8, a114140; CHECK-NEXT:    vsetvli a2, zero, e16, mf2, ta, ma14141; CHECK-NEXT:    vle16.v v10, (a6)14142; CHECK-NEXT:    vle16.v v8, (a5)14143; CHECK-NEXT:    vsetvli a2, zero, e16, m1, ta, ma14144; CHECK-NEXT:    vslideup.vx v10, v9, a114145; CHECK-NEXT:    vsetvli a2, zero, e16, mf2, ta, ma14146; CHECK-NEXT:    vle16.v v9, (a4)14147; CHECK-NEXT:    vsetvli a2, zero, e16, m1, ta, ma14148; CHECK-NEXT:    vslideup.vx v9, v8, a114149; CHECK-NEXT:    vsetvli a2, zero, e16, mf2, ta, ma14150; CHECK-NEXT:    vle16.v v12, (a3)14151; CHECK-NEXT:    vle16.v v8, (a0)14152; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma14153; CHECK-NEXT:    vslideup.vx v8, v12, a114154; CHECK-NEXT:    csrr a0, vlenb14155; CHECK-NEXT:    slli a0, a0, 214156; CHECK-NEXT:    add sp, sp, a014157; CHECK-NEXT:    addi sp, sp, 1614158; CHECK-NEXT:    ret14159;14160; ZVBB-LABEL: vector_interleave_nxv16bf16_nxv2bf16:14161; ZVBB:       # %bb.0:14162; ZVBB-NEXT:    addi sp, sp, -1614163; ZVBB-NEXT:    csrr a0, vlenb14164; ZVBB-NEXT:    slli a0, a0, 214165; ZVBB-NEXT:    sub sp, sp, a014166; ZVBB-NEXT:    addi a0, sp, 1614167; ZVBB-NEXT:    csrr a1, vlenb14168; ZVBB-NEXT:    srli a2, a1, 114169; ZVBB-NEXT:    add a3, a0, a214170; ZVBB-NEXT:    add a4, a3, a214171; ZVBB-NEXT:    add a5, a4, a214172; ZVBB-NEXT:    add a6, a5, a214173; ZVBB-NEXT:    add a7, a6, a214174; ZVBB-NEXT:    vsetvli t0, zero, e16, mf2, ta, ma14175; ZVBB-NEXT:    vsseg8e16.v v8, (a0)14176; ZVBB-NEXT:    add t0, a7, a214177; ZVBB-NEXT:    add a2, t0, a214178; ZVBB-NEXT:    vle16.v v11, (t0)14179; ZVBB-NEXT:    vle16.v v8, (a2)14180; ZVBB-NEXT:    srli a1, a1, 214181; ZVBB-NEXT:    vle16.v v9, (a7)14182; ZVBB-NEXT:    vsetvli a2, zero, e16, m1, ta, ma14183; ZVBB-NEXT:    vslideup.vx v11, v8, a114184; ZVBB-NEXT:    vsetvli a2, zero, e16, mf2, ta, ma14185; ZVBB-NEXT:    vle16.v v10, (a6)14186; ZVBB-NEXT:    vle16.v v8, (a5)14187; ZVBB-NEXT:    vsetvli a2, zero, e16, m1, ta, ma14188; ZVBB-NEXT:    vslideup.vx v10, v9, a114189; ZVBB-NEXT:    vsetvli a2, zero, e16, mf2, ta, ma14190; ZVBB-NEXT:    vle16.v v9, (a4)14191; ZVBB-NEXT:    vsetvli a2, zero, e16, m1, ta, ma14192; ZVBB-NEXT:    vslideup.vx v9, v8, a114193; ZVBB-NEXT:    vsetvli a2, zero, e16, mf2, ta, ma14194; ZVBB-NEXT:    vle16.v v12, (a3)14195; ZVBB-NEXT:    vle16.v v8, (a0)14196; ZVBB-NEXT:    vsetvli a0, zero, e16, m1, ta, ma14197; ZVBB-NEXT:    vslideup.vx v8, v12, a114198; ZVBB-NEXT:    csrr a0, vlenb14199; ZVBB-NEXT:    slli a0, a0, 214200; ZVBB-NEXT:    add sp, sp, a014201; ZVBB-NEXT:    addi sp, sp, 1614202; ZVBB-NEXT:    ret14203  %res = call <vscale x 16 x bfloat> @llvm.vector.interleave8.nxv16bf16(<vscale x 2 x bfloat> %v0, <vscale x 2 x bfloat> %v1, <vscale x 2 x bfloat> %v2, <vscale x 2 x bfloat> %v3, <vscale x 2 x bfloat> %v4, <vscale x 2 x bfloat> %v5, <vscale x 2 x bfloat> %v6, <vscale x 2 x bfloat> %v7)14204  ret <vscale x 16 x bfloat> %res14205}14206 14207define <vscale x 32 x bfloat> @vector_interleave_nxv32bf16_nxv4bf16(<vscale x 4 x bfloat> %v0, <vscale x 4 x bfloat> %v1, <vscale x 4 x bfloat> %v2, <vscale x 4 x bfloat> %v3, <vscale x 4 x bfloat> %v4, <vscale x 4 x bfloat> %v5, <vscale x 4 x bfloat> %v6, <vscale x 4 x bfloat> %v7) nounwind {14208; CHECK-LABEL: vector_interleave_nxv32bf16_nxv4bf16:14209; CHECK:       # %bb.0:14210; CHECK-NEXT:    addi sp, sp, -1614211; CHECK-NEXT:    csrr a0, vlenb14212; CHECK-NEXT:    slli a0, a0, 314213; CHECK-NEXT:    sub sp, sp, a014214; CHECK-NEXT:    addi a0, sp, 1614215; CHECK-NEXT:    csrr a1, vlenb14216; CHECK-NEXT:    add a2, a0, a114217; CHECK-NEXT:    add a3, a2, a114218; CHECK-NEXT:    add a4, a3, a114219; CHECK-NEXT:    add a5, a4, a114220; CHECK-NEXT:    add a6, a5, a114221; CHECK-NEXT:    add a7, a6, a114222; CHECK-NEXT:    vsetvli t0, zero, e16, m1, ta, ma14223; CHECK-NEXT:    vsseg8e16.v v8, (a0)14224; CHECK-NEXT:    vl1re16.v v14, (a7)14225; CHECK-NEXT:    add a1, a7, a114226; CHECK-NEXT:    vl1re16.v v15, (a1)14227; CHECK-NEXT:    vl1re16.v v12, (a5)14228; CHECK-NEXT:    vl1re16.v v13, (a6)14229; CHECK-NEXT:    vl1re16.v v10, (a3)14230; CHECK-NEXT:    vl1re16.v v11, (a4)14231; CHECK-NEXT:    vl1re16.v v8, (a0)14232; CHECK-NEXT:    vl1re16.v v9, (a2)14233; CHECK-NEXT:    csrr a0, vlenb14234; CHECK-NEXT:    slli a0, a0, 314235; CHECK-NEXT:    add sp, sp, a014236; CHECK-NEXT:    addi sp, sp, 1614237; CHECK-NEXT:    ret14238;14239; ZVBB-LABEL: vector_interleave_nxv32bf16_nxv4bf16:14240; ZVBB:       # %bb.0:14241; ZVBB-NEXT:    addi sp, sp, -1614242; ZVBB-NEXT:    csrr a0, vlenb14243; ZVBB-NEXT:    slli a0, a0, 314244; ZVBB-NEXT:    sub sp, sp, a014245; ZVBB-NEXT:    addi a0, sp, 1614246; ZVBB-NEXT:    csrr a1, vlenb14247; ZVBB-NEXT:    add a2, a0, a114248; ZVBB-NEXT:    add a3, a2, a114249; ZVBB-NEXT:    add a4, a3, a114250; ZVBB-NEXT:    add a5, a4, a114251; ZVBB-NEXT:    add a6, a5, a114252; ZVBB-NEXT:    add a7, a6, a114253; ZVBB-NEXT:    vsetvli t0, zero, e16, m1, ta, ma14254; ZVBB-NEXT:    vsseg8e16.v v8, (a0)14255; ZVBB-NEXT:    vl1re16.v v14, (a7)14256; ZVBB-NEXT:    add a1, a7, a114257; ZVBB-NEXT:    vl1re16.v v15, (a1)14258; ZVBB-NEXT:    vl1re16.v v12, (a5)14259; ZVBB-NEXT:    vl1re16.v v13, (a6)14260; ZVBB-NEXT:    vl1re16.v v10, (a3)14261; ZVBB-NEXT:    vl1re16.v v11, (a4)14262; ZVBB-NEXT:    vl1re16.v v8, (a0)14263; ZVBB-NEXT:    vl1re16.v v9, (a2)14264; ZVBB-NEXT:    csrr a0, vlenb14265; ZVBB-NEXT:    slli a0, a0, 314266; ZVBB-NEXT:    add sp, sp, a014267; ZVBB-NEXT:    addi sp, sp, 1614268; ZVBB-NEXT:    ret14269  %res = call <vscale x 32 x bfloat> @llvm.vector.interleave8.nxv32bf16(<vscale x 4 x bfloat> %v0, <vscale x 4 x bfloat> %v1, <vscale x 4 x bfloat> %v2, <vscale x 4 x bfloat> %v3, <vscale x 4 x bfloat> %v4, <vscale x 4 x bfloat> %v5, <vscale x 4 x bfloat> %v6, <vscale x 4 x bfloat> %v7)14270  ret <vscale x 32 x bfloat> %res14271}14272 14273define <vscale x 64 x bfloat> @vector_interleave_nxv64bf16_nxv8bf16(<vscale x 8 x bfloat> %v0, <vscale x 8 x bfloat> %v1, <vscale x 8 x bfloat> %v2, <vscale x 8 x bfloat> %v3, <vscale x 8 x bfloat> %v4, <vscale x 8 x bfloat> %v5, <vscale x 8 x bfloat> %v6, <vscale x 8 x bfloat> %v7) nounwind {14274; CHECK-LABEL: vector_interleave_nxv64bf16_nxv8bf16:14275; CHECK:       # %bb.0:14276; CHECK-NEXT:    addi sp, sp, -1614277; CHECK-NEXT:    csrr a0, vlenb14278; CHECK-NEXT:    slli a0, a0, 414279; CHECK-NEXT:    sub sp, sp, a014280; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma14281; CHECK-NEXT:    vmv2r.v v28, v2214282; CHECK-NEXT:    addi a0, sp, 1614283; CHECK-NEXT:    vmv2r.v v26, v1814284; CHECK-NEXT:    csrr a1, vlenb14285; CHECK-NEXT:    slli a1, a1, 314286; CHECK-NEXT:    add a1, sp, a114287; CHECK-NEXT:    addi a1, a1, 1614288; CHECK-NEXT:    csrr a3, vlenb14289; CHECK-NEXT:    add a2, a0, a314290; CHECK-NEXT:    add a4, a1, a314291; CHECK-NEXT:    add a5, a2, a314292; CHECK-NEXT:    vmv1r.v v1, v814293; CHECK-NEXT:    vmv2r.v v24, v1414294; CHECK-NEXT:    add a6, a4, a314295; CHECK-NEXT:    vmv2r.v v22, v1014296; CHECK-NEXT:    vmv1r.v v2, v2214297; CHECK-NEXT:    add a7, a5, a314298; CHECK-NEXT:    vmv1r.v v3, v1214299; CHECK-NEXT:    add t0, a6, a314300; CHECK-NEXT:    vmv1r.v v4, v2414301; CHECK-NEXT:    add t1, a7, a314302; CHECK-NEXT:    vmv1r.v v5, v1614303; CHECK-NEXT:    add t2, t0, a314304; CHECK-NEXT:    vmv1r.v v6, v2614305; CHECK-NEXT:    add t3, t1, a314306; CHECK-NEXT:    vmv1r.v v7, v2014307; CHECK-NEXT:    add t4, t2, a314308; CHECK-NEXT:    vmv1r.v v8, v2814309; CHECK-NEXT:    vmv1r.v v22, v914310; CHECK-NEXT:    add t5, t3, a314311; CHECK-NEXT:    vmv1r.v v24, v1314312; CHECK-NEXT:    add t6, t4, a314313; CHECK-NEXT:    vmv1r.v v26, v1714314; CHECK-NEXT:    vsseg8e16.v v1, (a0)14315; CHECK-NEXT:    vmv1r.v v28, v2114316; CHECK-NEXT:    vsseg8e16.v v22, (a1)14317; CHECK-NEXT:    vl1re16.v v14, (t5)14318; CHECK-NEXT:    add t5, t5, a314319; CHECK-NEXT:    add a3, t6, a314320; CHECK-NEXT:    vl1re16.v v22, (t6)14321; CHECK-NEXT:    vl1re16.v v15, (t5)14322; CHECK-NEXT:    vl1re16.v v23, (a3)14323; CHECK-NEXT:    vl1re16.v v12, (t1)14324; CHECK-NEXT:    vl1re16.v v20, (t2)14325; CHECK-NEXT:    vl1re16.v v13, (t3)14326; CHECK-NEXT:    vl1re16.v v21, (t4)14327; CHECK-NEXT:    vl1re16.v v10, (a5)14328; CHECK-NEXT:    vl1re16.v v18, (a6)14329; CHECK-NEXT:    vl1re16.v v11, (a7)14330; CHECK-NEXT:    vl1re16.v v19, (t0)14331; CHECK-NEXT:    vl1re16.v v8, (a0)14332; CHECK-NEXT:    vl1re16.v v16, (a1)14333; CHECK-NEXT:    vl1re16.v v9, (a2)14334; CHECK-NEXT:    vl1re16.v v17, (a4)14335; CHECK-NEXT:    csrr a0, vlenb14336; CHECK-NEXT:    slli a0, a0, 414337; CHECK-NEXT:    add sp, sp, a014338; CHECK-NEXT:    addi sp, sp, 1614339; CHECK-NEXT:    ret14340;14341; ZVBB-LABEL: vector_interleave_nxv64bf16_nxv8bf16:14342; ZVBB:       # %bb.0:14343; ZVBB-NEXT:    addi sp, sp, -1614344; ZVBB-NEXT:    csrr a0, vlenb14345; ZVBB-NEXT:    slli a0, a0, 414346; ZVBB-NEXT:    sub sp, sp, a014347; ZVBB-NEXT:    vsetvli a0, zero, e16, m1, ta, ma14348; ZVBB-NEXT:    vmv2r.v v28, v2214349; ZVBB-NEXT:    addi a0, sp, 1614350; ZVBB-NEXT:    vmv2r.v v26, v1814351; ZVBB-NEXT:    csrr a1, vlenb14352; ZVBB-NEXT:    slli a1, a1, 314353; ZVBB-NEXT:    add a1, sp, a114354; ZVBB-NEXT:    addi a1, a1, 1614355; ZVBB-NEXT:    csrr a3, vlenb14356; ZVBB-NEXT:    add a2, a0, a314357; ZVBB-NEXT:    add a4, a1, a314358; ZVBB-NEXT:    add a5, a2, a314359; ZVBB-NEXT:    vmv1r.v v1, v814360; ZVBB-NEXT:    vmv2r.v v24, v1414361; ZVBB-NEXT:    add a6, a4, a314362; ZVBB-NEXT:    vmv2r.v v22, v1014363; ZVBB-NEXT:    vmv1r.v v2, v2214364; ZVBB-NEXT:    add a7, a5, a314365; ZVBB-NEXT:    vmv1r.v v3, v1214366; ZVBB-NEXT:    add t0, a6, a314367; ZVBB-NEXT:    vmv1r.v v4, v2414368; ZVBB-NEXT:    add t1, a7, a314369; ZVBB-NEXT:    vmv1r.v v5, v1614370; ZVBB-NEXT:    add t2, t0, a314371; ZVBB-NEXT:    vmv1r.v v6, v2614372; ZVBB-NEXT:    add t3, t1, a314373; ZVBB-NEXT:    vmv1r.v v7, v2014374; ZVBB-NEXT:    add t4, t2, a314375; ZVBB-NEXT:    vmv1r.v v8, v2814376; ZVBB-NEXT:    vmv1r.v v22, v914377; ZVBB-NEXT:    add t5, t3, a314378; ZVBB-NEXT:    vmv1r.v v24, v1314379; ZVBB-NEXT:    add t6, t4, a314380; ZVBB-NEXT:    vmv1r.v v26, v1714381; ZVBB-NEXT:    vsseg8e16.v v1, (a0)14382; ZVBB-NEXT:    vmv1r.v v28, v2114383; ZVBB-NEXT:    vsseg8e16.v v22, (a1)14384; ZVBB-NEXT:    vl1re16.v v14, (t5)14385; ZVBB-NEXT:    add t5, t5, a314386; ZVBB-NEXT:    add a3, t6, a314387; ZVBB-NEXT:    vl1re16.v v22, (t6)14388; ZVBB-NEXT:    vl1re16.v v15, (t5)14389; ZVBB-NEXT:    vl1re16.v v23, (a3)14390; ZVBB-NEXT:    vl1re16.v v12, (t1)14391; ZVBB-NEXT:    vl1re16.v v20, (t2)14392; ZVBB-NEXT:    vl1re16.v v13, (t3)14393; ZVBB-NEXT:    vl1re16.v v21, (t4)14394; ZVBB-NEXT:    vl1re16.v v10, (a5)14395; ZVBB-NEXT:    vl1re16.v v18, (a6)14396; ZVBB-NEXT:    vl1re16.v v11, (a7)14397; ZVBB-NEXT:    vl1re16.v v19, (t0)14398; ZVBB-NEXT:    vl1re16.v v8, (a0)14399; ZVBB-NEXT:    vl1re16.v v16, (a1)14400; ZVBB-NEXT:    vl1re16.v v9, (a2)14401; ZVBB-NEXT:    vl1re16.v v17, (a4)14402; ZVBB-NEXT:    csrr a0, vlenb14403; ZVBB-NEXT:    slli a0, a0, 414404; ZVBB-NEXT:    add sp, sp, a014405; ZVBB-NEXT:    addi sp, sp, 1614406; ZVBB-NEXT:    ret14407  %res = call <vscale x 64 x bfloat> @llvm.vector.interleave8.nxv64bf16(<vscale x 8 x bfloat> %v0, <vscale x 8 x bfloat> %v1, <vscale x 8 x bfloat> %v2, <vscale x 8 x bfloat> %v3, <vscale x 8 x bfloat> %v4, <vscale x 8 x bfloat> %v5, <vscale x 8 x bfloat> %v6, <vscale x 8 x bfloat> %v7)14408  ret <vscale x 64 x bfloat> %res14409}14410 14411define <vscale x 8 x float> @vector_interleave_nxv8f32_nxv1f32(<vscale x 1 x float> %v0, <vscale x 1 x float> %v1, <vscale x 1 x float> %v2, <vscale x 1 x float> %v3, <vscale x 1 x float> %v4, <vscale x 1 x float> %v5, <vscale x 1 x float> %v6, <vscale x 1 x float> %v8) nounwind {14412; CHECK-LABEL: vector_interleave_nxv8f32_nxv1f32:14413; CHECK:       # %bb.0:14414; CHECK-NEXT:    addi sp, sp, -1614415; CHECK-NEXT:    csrr a0, vlenb14416; CHECK-NEXT:    slli a0, a0, 214417; CHECK-NEXT:    sub sp, sp, a014418; CHECK-NEXT:    addi a0, sp, 1614419; CHECK-NEXT:    csrr a1, vlenb14420; CHECK-NEXT:    srli a2, a1, 114421; CHECK-NEXT:    add a3, a0, a214422; CHECK-NEXT:    add a4, a3, a214423; CHECK-NEXT:    add a5, a4, a214424; CHECK-NEXT:    add a6, a5, a214425; CHECK-NEXT:    add a7, a6, a214426; CHECK-NEXT:    vsetvli t0, zero, e32, mf2, ta, ma14427; CHECK-NEXT:    vsseg8e32.v v8, (a0)14428; CHECK-NEXT:    add t0, a7, a214429; CHECK-NEXT:    add a2, t0, a214430; CHECK-NEXT:    vle32.v v11, (t0)14431; CHECK-NEXT:    vle32.v v8, (a2)14432; CHECK-NEXT:    srli a1, a1, 314433; CHECK-NEXT:    vle32.v v9, (a7)14434; CHECK-NEXT:    vsetvli a2, zero, e32, m1, ta, ma14435; CHECK-NEXT:    vslideup.vx v11, v8, a114436; CHECK-NEXT:    vsetvli a2, zero, e32, mf2, ta, ma14437; CHECK-NEXT:    vle32.v v10, (a6)14438; CHECK-NEXT:    vle32.v v8, (a5)14439; CHECK-NEXT:    vsetvli a2, zero, e32, m1, ta, ma14440; CHECK-NEXT:    vslideup.vx v10, v9, a114441; CHECK-NEXT:    vsetvli a2, zero, e32, mf2, ta, ma14442; CHECK-NEXT:    vle32.v v9, (a4)14443; CHECK-NEXT:    vsetvli a2, zero, e32, m1, ta, ma14444; CHECK-NEXT:    vslideup.vx v9, v8, a114445; CHECK-NEXT:    vsetvli a2, zero, e32, mf2, ta, ma14446; CHECK-NEXT:    vle32.v v12, (a3)14447; CHECK-NEXT:    vle32.v v8, (a0)14448; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma14449; CHECK-NEXT:    vslideup.vx v8, v12, a114450; CHECK-NEXT:    csrr a0, vlenb14451; CHECK-NEXT:    slli a0, a0, 214452; CHECK-NEXT:    add sp, sp, a014453; CHECK-NEXT:    addi sp, sp, 1614454; CHECK-NEXT:    ret14455;14456; ZVBB-LABEL: vector_interleave_nxv8f32_nxv1f32:14457; ZVBB:       # %bb.0:14458; ZVBB-NEXT:    addi sp, sp, -1614459; ZVBB-NEXT:    csrr a0, vlenb14460; ZVBB-NEXT:    slli a0, a0, 214461; ZVBB-NEXT:    sub sp, sp, a014462; ZVBB-NEXT:    addi a0, sp, 1614463; ZVBB-NEXT:    csrr a1, vlenb14464; ZVBB-NEXT:    srli a2, a1, 114465; ZVBB-NEXT:    add a3, a0, a214466; ZVBB-NEXT:    add a4, a3, a214467; ZVBB-NEXT:    add a5, a4, a214468; ZVBB-NEXT:    add a6, a5, a214469; ZVBB-NEXT:    add a7, a6, a214470; ZVBB-NEXT:    vsetvli t0, zero, e32, mf2, ta, ma14471; ZVBB-NEXT:    vsseg8e32.v v8, (a0)14472; ZVBB-NEXT:    add t0, a7, a214473; ZVBB-NEXT:    add a2, t0, a214474; ZVBB-NEXT:    vle32.v v11, (t0)14475; ZVBB-NEXT:    vle32.v v8, (a2)14476; ZVBB-NEXT:    srli a1, a1, 314477; ZVBB-NEXT:    vle32.v v9, (a7)14478; ZVBB-NEXT:    vsetvli a2, zero, e32, m1, ta, ma14479; ZVBB-NEXT:    vslideup.vx v11, v8, a114480; ZVBB-NEXT:    vsetvli a2, zero, e32, mf2, ta, ma14481; ZVBB-NEXT:    vle32.v v10, (a6)14482; ZVBB-NEXT:    vle32.v v8, (a5)14483; ZVBB-NEXT:    vsetvli a2, zero, e32, m1, ta, ma14484; ZVBB-NEXT:    vslideup.vx v10, v9, a114485; ZVBB-NEXT:    vsetvli a2, zero, e32, mf2, ta, ma14486; ZVBB-NEXT:    vle32.v v9, (a4)14487; ZVBB-NEXT:    vsetvli a2, zero, e32, m1, ta, ma14488; ZVBB-NEXT:    vslideup.vx v9, v8, a114489; ZVBB-NEXT:    vsetvli a2, zero, e32, mf2, ta, ma14490; ZVBB-NEXT:    vle32.v v12, (a3)14491; ZVBB-NEXT:    vle32.v v8, (a0)14492; ZVBB-NEXT:    vsetvli a0, zero, e32, m1, ta, ma14493; ZVBB-NEXT:    vslideup.vx v8, v12, a114494; ZVBB-NEXT:    csrr a0, vlenb14495; ZVBB-NEXT:    slli a0, a0, 214496; ZVBB-NEXT:    add sp, sp, a014497; ZVBB-NEXT:    addi sp, sp, 1614498; ZVBB-NEXT:    ret14499  %res = call <vscale x 8 x float> @llvm.vector.interleave8.nxv8f32(<vscale x 1 x float> %v0, <vscale x 1 x float> %v1, <vscale x 1 x float> %v2, <vscale x 1 x float> %v3, <vscale x 1 x float> %v4, <vscale x 1 x float> %v5, <vscale x 1 x float> %v6, <vscale x 1 x float> %v8)14500  ret <vscale x 8 x float> %res14501}14502 14503define <vscale x 16 x float> @vector_interleave_nxv16f32_nxv2f32(<vscale x 2 x float> %v0, <vscale x 2 x float> %v1, <vscale x 2 x float> %v2, <vscale x 2 x float> %v3, <vscale x 2 x float> %v4, <vscale x 2 x float> %v5, <vscale x 2 x float> %v6, <vscale x 2 x float> %v7) nounwind {14504; CHECK-LABEL: vector_interleave_nxv16f32_nxv2f32:14505; CHECK:       # %bb.0:14506; CHECK-NEXT:    addi sp, sp, -1614507; CHECK-NEXT:    csrr a0, vlenb14508; CHECK-NEXT:    slli a0, a0, 314509; CHECK-NEXT:    sub sp, sp, a014510; CHECK-NEXT:    addi a0, sp, 1614511; CHECK-NEXT:    csrr a1, vlenb14512; CHECK-NEXT:    add a2, a0, a114513; CHECK-NEXT:    add a3, a2, a114514; CHECK-NEXT:    add a4, a3, a114515; CHECK-NEXT:    add a5, a4, a114516; CHECK-NEXT:    add a6, a5, a114517; CHECK-NEXT:    add a7, a6, a114518; CHECK-NEXT:    vsetvli t0, zero, e32, m1, ta, ma14519; CHECK-NEXT:    vsseg8e32.v v8, (a0)14520; CHECK-NEXT:    vl1re32.v v14, (a7)14521; CHECK-NEXT:    add a1, a7, a114522; CHECK-NEXT:    vl1re32.v v15, (a1)14523; CHECK-NEXT:    vl1re32.v v12, (a5)14524; CHECK-NEXT:    vl1re32.v v13, (a6)14525; CHECK-NEXT:    vl1re32.v v10, (a3)14526; CHECK-NEXT:    vl1re32.v v11, (a4)14527; CHECK-NEXT:    vl1re32.v v8, (a0)14528; CHECK-NEXT:    vl1re32.v v9, (a2)14529; CHECK-NEXT:    csrr a0, vlenb14530; CHECK-NEXT:    slli a0, a0, 314531; CHECK-NEXT:    add sp, sp, a014532; CHECK-NEXT:    addi sp, sp, 1614533; CHECK-NEXT:    ret14534;14535; ZVBB-LABEL: vector_interleave_nxv16f32_nxv2f32:14536; ZVBB:       # %bb.0:14537; ZVBB-NEXT:    addi sp, sp, -1614538; ZVBB-NEXT:    csrr a0, vlenb14539; ZVBB-NEXT:    slli a0, a0, 314540; ZVBB-NEXT:    sub sp, sp, a014541; ZVBB-NEXT:    addi a0, sp, 1614542; ZVBB-NEXT:    csrr a1, vlenb14543; ZVBB-NEXT:    add a2, a0, a114544; ZVBB-NEXT:    add a3, a2, a114545; ZVBB-NEXT:    add a4, a3, a114546; ZVBB-NEXT:    add a5, a4, a114547; ZVBB-NEXT:    add a6, a5, a114548; ZVBB-NEXT:    add a7, a6, a114549; ZVBB-NEXT:    vsetvli t0, zero, e32, m1, ta, ma14550; ZVBB-NEXT:    vsseg8e32.v v8, (a0)14551; ZVBB-NEXT:    vl1re32.v v14, (a7)14552; ZVBB-NEXT:    add a1, a7, a114553; ZVBB-NEXT:    vl1re32.v v15, (a1)14554; ZVBB-NEXT:    vl1re32.v v12, (a5)14555; ZVBB-NEXT:    vl1re32.v v13, (a6)14556; ZVBB-NEXT:    vl1re32.v v10, (a3)14557; ZVBB-NEXT:    vl1re32.v v11, (a4)14558; ZVBB-NEXT:    vl1re32.v v8, (a0)14559; ZVBB-NEXT:    vl1re32.v v9, (a2)14560; ZVBB-NEXT:    csrr a0, vlenb14561; ZVBB-NEXT:    slli a0, a0, 314562; ZVBB-NEXT:    add sp, sp, a014563; ZVBB-NEXT:    addi sp, sp, 1614564; ZVBB-NEXT:    ret14565  %res = call <vscale x 16 x float> @llvm.vector.interleave8.nxv16f32(<vscale x 2 x float> %v0, <vscale x 2 x float> %v1, <vscale x 2 x float> %v2, <vscale x 2 x float> %v3, <vscale x 2 x float> %v4, <vscale x 2 x float> %v5, <vscale x 2 x float> %v6, <vscale x 2 x float> %v7)14566  ret <vscale x 16 x float> %res14567}14568 14569define <vscale x 32 x float> @vector_interleave_nxv32f32_nxv4f32(<vscale x 4 x float> %v0, <vscale x 4 x float> %v1, <vscale x 4 x float> %v2, <vscale x 4 x float> %v3, <vscale x 4 x float> %v4, <vscale x 4 x float> %v5, <vscale x 4 x float> %v6, <vscale x 4 x float> %v7) nounwind {14570; CHECK-LABEL: vector_interleave_nxv32f32_nxv4f32:14571; CHECK:       # %bb.0:14572; CHECK-NEXT:    addi sp, sp, -1614573; CHECK-NEXT:    csrr a0, vlenb14574; CHECK-NEXT:    slli a0, a0, 414575; CHECK-NEXT:    sub sp, sp, a014576; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma14577; CHECK-NEXT:    vmv2r.v v28, v2214578; CHECK-NEXT:    addi a0, sp, 1614579; CHECK-NEXT:    vmv2r.v v26, v1814580; CHECK-NEXT:    csrr a1, vlenb14581; CHECK-NEXT:    slli a1, a1, 314582; CHECK-NEXT:    add a1, sp, a114583; CHECK-NEXT:    addi a1, a1, 1614584; CHECK-NEXT:    csrr a3, vlenb14585; CHECK-NEXT:    add a2, a0, a314586; CHECK-NEXT:    add a4, a1, a314587; CHECK-NEXT:    add a5, a2, a314588; CHECK-NEXT:    vmv1r.v v1, v814589; CHECK-NEXT:    vmv2r.v v24, v1414590; CHECK-NEXT:    add a6, a4, a314591; CHECK-NEXT:    vmv2r.v v22, v1014592; CHECK-NEXT:    vmv1r.v v2, v2214593; CHECK-NEXT:    add a7, a5, a314594; CHECK-NEXT:    vmv1r.v v3, v1214595; CHECK-NEXT:    add t0, a6, a314596; CHECK-NEXT:    vmv1r.v v4, v2414597; CHECK-NEXT:    add t1, a7, a314598; CHECK-NEXT:    vmv1r.v v5, v1614599; CHECK-NEXT:    add t2, t0, a314600; CHECK-NEXT:    vmv1r.v v6, v2614601; CHECK-NEXT:    add t3, t1, a314602; CHECK-NEXT:    vmv1r.v v7, v2014603; CHECK-NEXT:    add t4, t2, a314604; CHECK-NEXT:    vmv1r.v v8, v2814605; CHECK-NEXT:    vmv1r.v v22, v914606; CHECK-NEXT:    add t5, t3, a314607; CHECK-NEXT:    vmv1r.v v24, v1314608; CHECK-NEXT:    add t6, t4, a314609; CHECK-NEXT:    vmv1r.v v26, v1714610; CHECK-NEXT:    vsseg8e32.v v1, (a0)14611; CHECK-NEXT:    vmv1r.v v28, v2114612; CHECK-NEXT:    vsseg8e32.v v22, (a1)14613; CHECK-NEXT:    vl1re32.v v14, (t5)14614; CHECK-NEXT:    add t5, t5, a314615; CHECK-NEXT:    add a3, t6, a314616; CHECK-NEXT:    vl1re32.v v22, (t6)14617; CHECK-NEXT:    vl1re32.v v15, (t5)14618; CHECK-NEXT:    vl1re32.v v23, (a3)14619; CHECK-NEXT:    vl1re32.v v12, (t1)14620; CHECK-NEXT:    vl1re32.v v20, (t2)14621; CHECK-NEXT:    vl1re32.v v13, (t3)14622; CHECK-NEXT:    vl1re32.v v21, (t4)14623; CHECK-NEXT:    vl1re32.v v10, (a5)14624; CHECK-NEXT:    vl1re32.v v18, (a6)14625; CHECK-NEXT:    vl1re32.v v11, (a7)14626; CHECK-NEXT:    vl1re32.v v19, (t0)14627; CHECK-NEXT:    vl1re32.v v8, (a0)14628; CHECK-NEXT:    vl1re32.v v16, (a1)14629; CHECK-NEXT:    vl1re32.v v9, (a2)14630; CHECK-NEXT:    vl1re32.v v17, (a4)14631; CHECK-NEXT:    csrr a0, vlenb14632; CHECK-NEXT:    slli a0, a0, 414633; CHECK-NEXT:    add sp, sp, a014634; CHECK-NEXT:    addi sp, sp, 1614635; CHECK-NEXT:    ret14636;14637; ZVBB-LABEL: vector_interleave_nxv32f32_nxv4f32:14638; ZVBB:       # %bb.0:14639; ZVBB-NEXT:    addi sp, sp, -1614640; ZVBB-NEXT:    csrr a0, vlenb14641; ZVBB-NEXT:    slli a0, a0, 414642; ZVBB-NEXT:    sub sp, sp, a014643; ZVBB-NEXT:    vsetvli a0, zero, e32, m1, ta, ma14644; ZVBB-NEXT:    vmv2r.v v28, v2214645; ZVBB-NEXT:    addi a0, sp, 1614646; ZVBB-NEXT:    vmv2r.v v26, v1814647; ZVBB-NEXT:    csrr a1, vlenb14648; ZVBB-NEXT:    slli a1, a1, 314649; ZVBB-NEXT:    add a1, sp, a114650; ZVBB-NEXT:    addi a1, a1, 1614651; ZVBB-NEXT:    csrr a3, vlenb14652; ZVBB-NEXT:    add a2, a0, a314653; ZVBB-NEXT:    add a4, a1, a314654; ZVBB-NEXT:    add a5, a2, a314655; ZVBB-NEXT:    vmv1r.v v1, v814656; ZVBB-NEXT:    vmv2r.v v24, v1414657; ZVBB-NEXT:    add a6, a4, a314658; ZVBB-NEXT:    vmv2r.v v22, v1014659; ZVBB-NEXT:    vmv1r.v v2, v2214660; ZVBB-NEXT:    add a7, a5, a314661; ZVBB-NEXT:    vmv1r.v v3, v1214662; ZVBB-NEXT:    add t0, a6, a314663; ZVBB-NEXT:    vmv1r.v v4, v2414664; ZVBB-NEXT:    add t1, a7, a314665; ZVBB-NEXT:    vmv1r.v v5, v1614666; ZVBB-NEXT:    add t2, t0, a314667; ZVBB-NEXT:    vmv1r.v v6, v2614668; ZVBB-NEXT:    add t3, t1, a314669; ZVBB-NEXT:    vmv1r.v v7, v2014670; ZVBB-NEXT:    add t4, t2, a314671; ZVBB-NEXT:    vmv1r.v v8, v2814672; ZVBB-NEXT:    vmv1r.v v22, v914673; ZVBB-NEXT:    add t5, t3, a314674; ZVBB-NEXT:    vmv1r.v v24, v1314675; ZVBB-NEXT:    add t6, t4, a314676; ZVBB-NEXT:    vmv1r.v v26, v1714677; ZVBB-NEXT:    vsseg8e32.v v1, (a0)14678; ZVBB-NEXT:    vmv1r.v v28, v2114679; ZVBB-NEXT:    vsseg8e32.v v22, (a1)14680; ZVBB-NEXT:    vl1re32.v v14, (t5)14681; ZVBB-NEXT:    add t5, t5, a314682; ZVBB-NEXT:    add a3, t6, a314683; ZVBB-NEXT:    vl1re32.v v22, (t6)14684; ZVBB-NEXT:    vl1re32.v v15, (t5)14685; ZVBB-NEXT:    vl1re32.v v23, (a3)14686; ZVBB-NEXT:    vl1re32.v v12, (t1)14687; ZVBB-NEXT:    vl1re32.v v20, (t2)14688; ZVBB-NEXT:    vl1re32.v v13, (t3)14689; ZVBB-NEXT:    vl1re32.v v21, (t4)14690; ZVBB-NEXT:    vl1re32.v v10, (a5)14691; ZVBB-NEXT:    vl1re32.v v18, (a6)14692; ZVBB-NEXT:    vl1re32.v v11, (a7)14693; ZVBB-NEXT:    vl1re32.v v19, (t0)14694; ZVBB-NEXT:    vl1re32.v v8, (a0)14695; ZVBB-NEXT:    vl1re32.v v16, (a1)14696; ZVBB-NEXT:    vl1re32.v v9, (a2)14697; ZVBB-NEXT:    vl1re32.v v17, (a4)14698; ZVBB-NEXT:    csrr a0, vlenb14699; ZVBB-NEXT:    slli a0, a0, 414700; ZVBB-NEXT:    add sp, sp, a014701; ZVBB-NEXT:    addi sp, sp, 1614702; ZVBB-NEXT:    ret14703  %res = call <vscale x 32 x float> @llvm.vector.interleave8.nxv32f32(<vscale x 4 x float> %v0, <vscale x 4 x float> %v1, <vscale x 4 x float> %v2, <vscale x 4 x float> %v3, <vscale x 4 x float> %v4, <vscale x 4 x float> %v5, <vscale x 4 x float> %v6, <vscale x 4 x float> %v7)14704  ret <vscale x 32 x float> %res14705}14706 14707define <vscale x 8 x double> @vector_interleave_nxv8f64_nxv1f64(<vscale x 1 x double> %v0, <vscale x 1 x double> %v1, <vscale x 1 x double> %v2, <vscale x 1 x double> %v3, <vscale x 1 x double> %v4, <vscale x 1 x double> %v5, <vscale x 1 x double> %v6, <vscale x 1 x double> %v8) nounwind {14708; CHECK-LABEL: vector_interleave_nxv8f64_nxv1f64:14709; CHECK:       # %bb.0:14710; CHECK-NEXT:    addi sp, sp, -1614711; CHECK-NEXT:    csrr a0, vlenb14712; CHECK-NEXT:    slli a0, a0, 314713; CHECK-NEXT:    sub sp, sp, a014714; CHECK-NEXT:    addi a0, sp, 1614715; CHECK-NEXT:    csrr a1, vlenb14716; CHECK-NEXT:    add a2, a0, a114717; CHECK-NEXT:    add a3, a2, a114718; CHECK-NEXT:    add a4, a3, a114719; CHECK-NEXT:    add a5, a4, a114720; CHECK-NEXT:    add a6, a5, a114721; CHECK-NEXT:    add a7, a6, a114722; CHECK-NEXT:    vsetvli t0, zero, e64, m1, ta, ma14723; CHECK-NEXT:    vsseg8e64.v v8, (a0)14724; CHECK-NEXT:    vl1re64.v v14, (a7)14725; CHECK-NEXT:    add a1, a7, a114726; CHECK-NEXT:    vl1re64.v v15, (a1)14727; CHECK-NEXT:    vl1re64.v v12, (a5)14728; CHECK-NEXT:    vl1re64.v v13, (a6)14729; CHECK-NEXT:    vl1re64.v v10, (a3)14730; CHECK-NEXT:    vl1re64.v v11, (a4)14731; CHECK-NEXT:    vl1re64.v v8, (a0)14732; CHECK-NEXT:    vl1re64.v v9, (a2)14733; CHECK-NEXT:    csrr a0, vlenb14734; CHECK-NEXT:    slli a0, a0, 314735; CHECK-NEXT:    add sp, sp, a014736; CHECK-NEXT:    addi sp, sp, 1614737; CHECK-NEXT:    ret14738;14739; ZVBB-LABEL: vector_interleave_nxv8f64_nxv1f64:14740; ZVBB:       # %bb.0:14741; ZVBB-NEXT:    addi sp, sp, -1614742; ZVBB-NEXT:    csrr a0, vlenb14743; ZVBB-NEXT:    slli a0, a0, 314744; ZVBB-NEXT:    sub sp, sp, a014745; ZVBB-NEXT:    addi a0, sp, 1614746; ZVBB-NEXT:    csrr a1, vlenb14747; ZVBB-NEXT:    add a2, a0, a114748; ZVBB-NEXT:    add a3, a2, a114749; ZVBB-NEXT:    add a4, a3, a114750; ZVBB-NEXT:    add a5, a4, a114751; ZVBB-NEXT:    add a6, a5, a114752; ZVBB-NEXT:    add a7, a6, a114753; ZVBB-NEXT:    vsetvli t0, zero, e64, m1, ta, ma14754; ZVBB-NEXT:    vsseg8e64.v v8, (a0)14755; ZVBB-NEXT:    vl1re64.v v14, (a7)14756; ZVBB-NEXT:    add a1, a7, a114757; ZVBB-NEXT:    vl1re64.v v15, (a1)14758; ZVBB-NEXT:    vl1re64.v v12, (a5)14759; ZVBB-NEXT:    vl1re64.v v13, (a6)14760; ZVBB-NEXT:    vl1re64.v v10, (a3)14761; ZVBB-NEXT:    vl1re64.v v11, (a4)14762; ZVBB-NEXT:    vl1re64.v v8, (a0)14763; ZVBB-NEXT:    vl1re64.v v9, (a2)14764; ZVBB-NEXT:    csrr a0, vlenb14765; ZVBB-NEXT:    slli a0, a0, 314766; ZVBB-NEXT:    add sp, sp, a014767; ZVBB-NEXT:    addi sp, sp, 1614768; ZVBB-NEXT:    ret14769  %res = call <vscale x 8 x double> @llvm.vector.interleave8.nxv8f64(<vscale x 1 x double> %v0, <vscale x 1 x double> %v1, <vscale x 1 x double> %v2, <vscale x 1 x double> %v3, <vscale x 1 x double> %v4, <vscale x 1 x double> %v5, <vscale x 1 x double> %v6, <vscale x 1 x double> %v8)14770  ret <vscale x 8 x double> %res14771}14772 14773define <vscale x 16 x double> @vector_interleave_nxv16f64_nxv2f64(<vscale x 2 x double> %v0, <vscale x 2 x double> %v1, <vscale x 2 x double> %v2, <vscale x 2 x double> %v3, <vscale x 2 x double> %v4, <vscale x 2 x double> %v5, <vscale x 2 x double> %v6, <vscale x 2 x double> %v7) nounwind {14774; CHECK-LABEL: vector_interleave_nxv16f64_nxv2f64:14775; CHECK:       # %bb.0:14776; CHECK-NEXT:    addi sp, sp, -1614777; CHECK-NEXT:    csrr a0, vlenb14778; CHECK-NEXT:    slli a0, a0, 414779; CHECK-NEXT:    sub sp, sp, a014780; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, ma14781; CHECK-NEXT:    vmv2r.v v28, v2214782; CHECK-NEXT:    addi a0, sp, 1614783; CHECK-NEXT:    vmv2r.v v26, v1814784; CHECK-NEXT:    csrr a1, vlenb14785; CHECK-NEXT:    slli a1, a1, 314786; CHECK-NEXT:    add a1, sp, a114787; CHECK-NEXT:    addi a1, a1, 1614788; CHECK-NEXT:    csrr a3, vlenb14789; CHECK-NEXT:    add a2, a0, a314790; CHECK-NEXT:    add a4, a1, a314791; CHECK-NEXT:    add a5, a2, a314792; CHECK-NEXT:    vmv1r.v v1, v814793; CHECK-NEXT:    vmv2r.v v24, v1414794; CHECK-NEXT:    add a6, a4, a314795; CHECK-NEXT:    vmv2r.v v22, v1014796; CHECK-NEXT:    vmv1r.v v2, v2214797; CHECK-NEXT:    add a7, a5, a314798; CHECK-NEXT:    vmv1r.v v3, v1214799; CHECK-NEXT:    add t0, a6, a314800; CHECK-NEXT:    vmv1r.v v4, v2414801; CHECK-NEXT:    add t1, a7, a314802; CHECK-NEXT:    vmv1r.v v5, v1614803; CHECK-NEXT:    add t2, t0, a314804; CHECK-NEXT:    vmv1r.v v6, v2614805; CHECK-NEXT:    add t3, t1, a314806; CHECK-NEXT:    vmv1r.v v7, v2014807; CHECK-NEXT:    add t4, t2, a314808; CHECK-NEXT:    vmv1r.v v8, v2814809; CHECK-NEXT:    vmv1r.v v22, v914810; CHECK-NEXT:    add t5, t3, a314811; CHECK-NEXT:    vmv1r.v v24, v1314812; CHECK-NEXT:    add t6, t4, a314813; CHECK-NEXT:    vmv1r.v v26, v1714814; CHECK-NEXT:    vsseg8e64.v v1, (a0)14815; CHECK-NEXT:    vmv1r.v v28, v2114816; CHECK-NEXT:    vsseg8e64.v v22, (a1)14817; CHECK-NEXT:    vl1re64.v v14, (t5)14818; CHECK-NEXT:    add t5, t5, a314819; CHECK-NEXT:    add a3, t6, a314820; CHECK-NEXT:    vl1re64.v v22, (t6)14821; CHECK-NEXT:    vl1re64.v v15, (t5)14822; CHECK-NEXT:    vl1re64.v v23, (a3)14823; CHECK-NEXT:    vl1re64.v v12, (t1)14824; CHECK-NEXT:    vl1re64.v v20, (t2)14825; CHECK-NEXT:    vl1re64.v v13, (t3)14826; CHECK-NEXT:    vl1re64.v v21, (t4)14827; CHECK-NEXT:    vl1re64.v v10, (a5)14828; CHECK-NEXT:    vl1re64.v v18, (a6)14829; CHECK-NEXT:    vl1re64.v v11, (a7)14830; CHECK-NEXT:    vl1re64.v v19, (t0)14831; CHECK-NEXT:    vl1re64.v v8, (a0)14832; CHECK-NEXT:    vl1re64.v v16, (a1)14833; CHECK-NEXT:    vl1re64.v v9, (a2)14834; CHECK-NEXT:    vl1re64.v v17, (a4)14835; CHECK-NEXT:    csrr a0, vlenb14836; CHECK-NEXT:    slli a0, a0, 414837; CHECK-NEXT:    add sp, sp, a014838; CHECK-NEXT:    addi sp, sp, 1614839; CHECK-NEXT:    ret14840;14841; ZVBB-LABEL: vector_interleave_nxv16f64_nxv2f64:14842; ZVBB:       # %bb.0:14843; ZVBB-NEXT:    addi sp, sp, -1614844; ZVBB-NEXT:    csrr a0, vlenb14845; ZVBB-NEXT:    slli a0, a0, 414846; ZVBB-NEXT:    sub sp, sp, a014847; ZVBB-NEXT:    vsetvli a0, zero, e64, m1, ta, ma14848; ZVBB-NEXT:    vmv2r.v v28, v2214849; ZVBB-NEXT:    addi a0, sp, 1614850; ZVBB-NEXT:    vmv2r.v v26, v1814851; ZVBB-NEXT:    csrr a1, vlenb14852; ZVBB-NEXT:    slli a1, a1, 314853; ZVBB-NEXT:    add a1, sp, a114854; ZVBB-NEXT:    addi a1, a1, 1614855; ZVBB-NEXT:    csrr a3, vlenb14856; ZVBB-NEXT:    add a2, a0, a314857; ZVBB-NEXT:    add a4, a1, a314858; ZVBB-NEXT:    add a5, a2, a314859; ZVBB-NEXT:    vmv1r.v v1, v814860; ZVBB-NEXT:    vmv2r.v v24, v1414861; ZVBB-NEXT:    add a6, a4, a314862; ZVBB-NEXT:    vmv2r.v v22, v1014863; ZVBB-NEXT:    vmv1r.v v2, v2214864; ZVBB-NEXT:    add a7, a5, a314865; ZVBB-NEXT:    vmv1r.v v3, v1214866; ZVBB-NEXT:    add t0, a6, a314867; ZVBB-NEXT:    vmv1r.v v4, v2414868; ZVBB-NEXT:    add t1, a7, a314869; ZVBB-NEXT:    vmv1r.v v5, v1614870; ZVBB-NEXT:    add t2, t0, a314871; ZVBB-NEXT:    vmv1r.v v6, v2614872; ZVBB-NEXT:    add t3, t1, a314873; ZVBB-NEXT:    vmv1r.v v7, v2014874; ZVBB-NEXT:    add t4, t2, a314875; ZVBB-NEXT:    vmv1r.v v8, v2814876; ZVBB-NEXT:    vmv1r.v v22, v914877; ZVBB-NEXT:    add t5, t3, a314878; ZVBB-NEXT:    vmv1r.v v24, v1314879; ZVBB-NEXT:    add t6, t4, a314880; ZVBB-NEXT:    vmv1r.v v26, v1714881; ZVBB-NEXT:    vsseg8e64.v v1, (a0)14882; ZVBB-NEXT:    vmv1r.v v28, v2114883; ZVBB-NEXT:    vsseg8e64.v v22, (a1)14884; ZVBB-NEXT:    vl1re64.v v14, (t5)14885; ZVBB-NEXT:    add t5, t5, a314886; ZVBB-NEXT:    add a3, t6, a314887; ZVBB-NEXT:    vl1re64.v v22, (t6)14888; ZVBB-NEXT:    vl1re64.v v15, (t5)14889; ZVBB-NEXT:    vl1re64.v v23, (a3)14890; ZVBB-NEXT:    vl1re64.v v12, (t1)14891; ZVBB-NEXT:    vl1re64.v v20, (t2)14892; ZVBB-NEXT:    vl1re64.v v13, (t3)14893; ZVBB-NEXT:    vl1re64.v v21, (t4)14894; ZVBB-NEXT:    vl1re64.v v10, (a5)14895; ZVBB-NEXT:    vl1re64.v v18, (a6)14896; ZVBB-NEXT:    vl1re64.v v11, (a7)14897; ZVBB-NEXT:    vl1re64.v v19, (t0)14898; ZVBB-NEXT:    vl1re64.v v8, (a0)14899; ZVBB-NEXT:    vl1re64.v v16, (a1)14900; ZVBB-NEXT:    vl1re64.v v9, (a2)14901; ZVBB-NEXT:    vl1re64.v v17, (a4)14902; ZVBB-NEXT:    csrr a0, vlenb14903; ZVBB-NEXT:    slli a0, a0, 414904; ZVBB-NEXT:    add sp, sp, a014905; ZVBB-NEXT:    addi sp, sp, 1614906; ZVBB-NEXT:    ret14907  %res = call <vscale x 16 x double> @llvm.vector.interleave8.nxv16f64(<vscale x 2 x double> %v0, <vscale x 2 x double> %v1, <vscale x 2 x double> %v2, <vscale x 2 x double> %v3, <vscale x 2 x double> %v4, <vscale x 2 x double> %v5, <vscale x 2 x double> %v6, <vscale x 2 x double> %v7)14908  ret <vscale x 16 x double> %res14909}14910 14911define <vscale x 4 x i16> @interleave2_same_const_splat_nxv4i16() {14912; CHECK-LABEL: interleave2_same_const_splat_nxv4i16:14913; CHECK:       # %bb.0:14914; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma14915; CHECK-NEXT:    vmv.v.i v8, 314916; CHECK-NEXT:    ret14917;14918; ZVBB-LABEL: interleave2_same_const_splat_nxv4i16:14919; ZVBB:       # %bb.0:14920; ZVBB-NEXT:    vsetvli a0, zero, e16, m1, ta, ma14921; ZVBB-NEXT:    vmv.v.i v8, 314922; ZVBB-NEXT:    ret14923  %retval = call <vscale x 4 x i16> @llvm.vector.interleave2.nxv4i16(<vscale x 2 x i16> splat(i16 3), <vscale x 2 x i16> splat(i16 3))14924  ret <vscale x 4 x i16> %retval14925}14926 14927define <vscale x 4 x i16> @interleave2_diff_const_splat_nxv4i16() {14928; V-LABEL: interleave2_diff_const_splat_nxv4i16:14929; V:       # %bb.0:14930; V-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma14931; V-NEXT:    vmv.v.i v9, 314932; V-NEXT:    li a0, 414933; V-NEXT:    vmv.v.i v10, -114934; V-NEXT:    vwaddu.vx v8, v9, a014935; V-NEXT:    vwmaccu.vx v8, a0, v1014936; V-NEXT:    csrr a0, vlenb14937; V-NEXT:    srli a0, a0, 214938; V-NEXT:    vsetvli a1, zero, e16, m1, ta, ma14939; V-NEXT:    vslidedown.vx v9, v8, a014940; V-NEXT:    vslideup.vx v8, v9, a014941; V-NEXT:    ret14942;14943; ZVBB-LABEL: interleave2_diff_const_splat_nxv4i16:14944; ZVBB:       # %bb.0:14945; ZVBB-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma14946; ZVBB-NEXT:    vmv.v.i v8, 414947; ZVBB-NEXT:    li a0, 314948; ZVBB-NEXT:    vwsll.vi v9, v8, 1614949; ZVBB-NEXT:    vwaddu.wx v8, v9, a014950; ZVBB-NEXT:    csrr a0, vlenb14951; ZVBB-NEXT:    srli a0, a0, 214952; ZVBB-NEXT:    vsetvli a1, zero, e16, m1, ta, ma14953; ZVBB-NEXT:    vslidedown.vx v9, v8, a014954; ZVBB-NEXT:    vslideup.vx v8, v9, a014955; ZVBB-NEXT:    ret14956;14957; ZIP-LABEL: interleave2_diff_const_splat_nxv4i16:14958; ZIP:       # %bb.0:14959; ZIP-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma14960; ZIP-NEXT:    vmv.v.i v9, 414961; ZIP-NEXT:    vmv.v.i v10, 314962; ZIP-NEXT:    csrr a0, vlenb14963; ZIP-NEXT:    ri.vzip2b.vv v11, v10, v914964; ZIP-NEXT:    ri.vzip2a.vv v8, v10, v914965; ZIP-NEXT:    srli a0, a0, 214966; ZIP-NEXT:    vsetvli a1, zero, e16, m1, ta, ma14967; ZIP-NEXT:    vslideup.vx v8, v11, a014968; ZIP-NEXT:    ret14969  %retval = call <vscale x 4 x i16> @llvm.vector.interleave2.v4i16(<vscale x 2 x i16> splat(i16 3), <vscale x 2 x i16> splat(i16 4))14970  ret <vscale x 4 x i16> %retval14971}14972 14973define <vscale x 4 x i16> @interleave2_same_nonconst_splat_nxv4i16(i16 %a) {14974; CHECK-LABEL: interleave2_same_nonconst_splat_nxv4i16:14975; CHECK:       # %bb.0:14976; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, ma14977; CHECK-NEXT:    vmv.v.x v8, a014978; CHECK-NEXT:    ret14979;14980; ZVBB-LABEL: interleave2_same_nonconst_splat_nxv4i16:14981; ZVBB:       # %bb.0:14982; ZVBB-NEXT:    vsetvli a1, zero, e16, m1, ta, ma14983; ZVBB-NEXT:    vmv.v.x v8, a014984; ZVBB-NEXT:    ret14985  %ins = insertelement <vscale x 2 x i16> poison, i16 %a, i32 014986  %splat = shufflevector <vscale x 2 x i16> %ins, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer14987  %retval = call <vscale x 4 x i16> @llvm.vector.interleave2.nxv4i16(<vscale x 2 x i16> %splat, <vscale x 2 x i16> %splat)14988  ret <vscale x 4 x i16> %retval14989}14990 14991define <vscale x 4 x i16> @interleave2_diff_nonconst_splat_nxv4i16(i16 %a, i16 %b) {14992; V-LABEL: interleave2_diff_nonconst_splat_nxv4i16:14993; V:       # %bb.0:14994; V-NEXT:    vsetvli a2, zero, e16, mf2, ta, ma14995; V-NEXT:    vmv.v.x v9, a014996; V-NEXT:    vmv.v.i v10, -114997; V-NEXT:    csrr a0, vlenb14998; V-NEXT:    vwaddu.vx v8, v9, a114999; V-NEXT:    vwmaccu.vx v8, a1, v1015000; V-NEXT:    srli a0, a0, 215001; V-NEXT:    vsetvli a1, zero, e16, m1, ta, ma15002; V-NEXT:    vslidedown.vx v9, v8, a015003; V-NEXT:    vslideup.vx v8, v9, a015004; V-NEXT:    ret15005;15006; ZVBB-LABEL: interleave2_diff_nonconst_splat_nxv4i16:15007; ZVBB:       # %bb.0:15008; ZVBB-NEXT:    vsetvli a2, zero, e16, mf2, ta, ma15009; ZVBB-NEXT:    vmv.v.x v8, a115010; ZVBB-NEXT:    csrr a1, vlenb15011; ZVBB-NEXT:    vwsll.vi v9, v8, 1615012; ZVBB-NEXT:    vwaddu.wx v8, v9, a015013; ZVBB-NEXT:    srli a1, a1, 215014; ZVBB-NEXT:    vsetvli a0, zero, e16, m1, ta, ma15015; ZVBB-NEXT:    vslidedown.vx v9, v8, a115016; ZVBB-NEXT:    vslideup.vx v8, v9, a115017; ZVBB-NEXT:    ret15018;15019; ZIP-LABEL: interleave2_diff_nonconst_splat_nxv4i16:15020; ZIP:       # %bb.0:15021; ZIP-NEXT:    vsetvli a2, zero, e16, mf2, ta, ma15022; ZIP-NEXT:    vmv.v.x v9, a015023; ZIP-NEXT:    vmv.v.x v10, a115024; ZIP-NEXT:    csrr a0, vlenb15025; ZIP-NEXT:    ri.vzip2b.vv v11, v9, v1015026; ZIP-NEXT:    ri.vzip2a.vv v8, v9, v1015027; ZIP-NEXT:    srli a0, a0, 215028; ZIP-NEXT:    vsetvli a1, zero, e16, m1, ta, ma15029; ZIP-NEXT:    vslideup.vx v8, v11, a015030; ZIP-NEXT:    ret15031  %ins1 = insertelement <vscale x 2 x i16> poison, i16 %a, i32 015032  %splat1 = shufflevector <vscale x 2 x i16> %ins1, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer15033  %ins2 = insertelement <vscale x 2 x i16> poison, i16 %b, i32 015034  %splat2 = shufflevector <vscale x 2 x i16> %ins2, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer15035  %retval = call <vscale x 4 x i16> @llvm.vector.interleave2.nxv4i16(<vscale x 2 x i16> %splat1, <vscale x 2 x i16> %splat2)15036  ret <vscale x 4 x i16> %retval15037}15038 15039define <vscale x 8 x i16> @interleave4_same_const_splat_nxv8i16() {15040; CHECK-LABEL: interleave4_same_const_splat_nxv8i16:15041; CHECK:       # %bb.0:15042; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma15043; CHECK-NEXT:    vmv.v.i v8, 315044; CHECK-NEXT:    ret15045;15046; ZVBB-LABEL: interleave4_same_const_splat_nxv8i16:15047; ZVBB:       # %bb.0:15048; ZVBB-NEXT:    vsetvli a0, zero, e16, m2, ta, ma15049; ZVBB-NEXT:    vmv.v.i v8, 315050; ZVBB-NEXT:    ret15051  %retval = call <vscale x 8 x i16> @llvm.vector.interleave4.nxv8i16(<vscale x 2 x i16> splat(i16 3), <vscale x 2 x i16> splat(i16 3), <vscale x 2 x i16> splat(i16 3), <vscale x 2 x i16> splat(i16 3))15052  ret <vscale x 8 x i16> %retval15053}15054