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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc -mtriple=riscv32 -mattr='+v' -O3 %s -o - | FileCheck %s3 4define <vscale x 1 x i8> @simple_vadd_vv(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i32 %2) nounwind {5; CHECK-LABEL: simple_vadd_vv:6; CHECK: # %bb.0: # %entry7; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma8; CHECK-NEXT: vadd.vv v9, v8, v99; CHECK-NEXT: vadd.vv v8, v8, v810; CHECK-NEXT: vadd.vv v8, v8, v911; CHECK-NEXT: ret12entry:13 %a = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8(14 <vscale x 1 x i8> poison,15 <vscale x 1 x i8> %0,16 <vscale x 1 x i8> %1,17 i32 %2)18 19 %b = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8(20 <vscale x 1 x i8> poison,21 <vscale x 1 x i8> %0,22 <vscale x 1 x i8> %a,23 i32 %2)24 25 %c = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8(26 <vscale x 1 x i8> poison,27 <vscale x 1 x i8> %0,28 <vscale x 1 x i8> %b,29 i32 %2)30 31 ret <vscale x 1 x i8> %c32}33 34define <vscale x 1 x i8> @simple_vadd_vsub_vv(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i32 %2) nounwind {35; CHECK-LABEL: simple_vadd_vsub_vv:36; CHECK: # %bb.0: # %entry37; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma38; CHECK-NEXT: vsub.vv v9, v8, v939; CHECK-NEXT: vadd.vv v8, v8, v840; CHECK-NEXT: vadd.vv v8, v8, v941; CHECK-NEXT: ret42entry:43 %a = call <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.nxv1i8(44 <vscale x 1 x i8> poison,45 <vscale x 1 x i8> %0,46 <vscale x 1 x i8> %1,47 i32 %2)48 49 %b = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8(50 <vscale x 1 x i8> poison,51 <vscale x 1 x i8> %0,52 <vscale x 1 x i8> %a,53 i32 %2)54 55 %c = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8(56 <vscale x 1 x i8> poison,57 <vscale x 1 x i8> %0,58 <vscale x 1 x i8> %b,59 i32 %2)60 61 ret <vscale x 1 x i8> %c62}63 64define <vscale x 1 x i8> @simple_vmul_vv(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i32 %2) nounwind {65; CHECK-LABEL: simple_vmul_vv:66; CHECK: # %bb.0: # %entry67; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma68; CHECK-NEXT: vmul.vv v9, v8, v969; CHECK-NEXT: vmul.vv v8, v8, v870; CHECK-NEXT: vmul.vv v8, v8, v971; CHECK-NEXT: ret72entry:73 %a = call <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.nxv1i8(74 <vscale x 1 x i8> poison,75 <vscale x 1 x i8> %0,76 <vscale x 1 x i8> %1,77 i32 %2)78 79 %b = call <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.nxv1i8(80 <vscale x 1 x i8> poison,81 <vscale x 1 x i8> %0,82 <vscale x 1 x i8> %a,83 i32 %2)84 85 %c = call <vscale x 1 x i8> @llvm.riscv.vmul.nxv1i8.nxv1i8(86 <vscale x 1 x i8> poison,87 <vscale x 1 x i8> %0,88 <vscale x 1 x i8> %b,89 i32 %2)90 91 ret <vscale x 1 x i8> %c92}93 94; With passthru and masks.95define <vscale x 1 x i8> @vadd_vv_passthru(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i32 %2) nounwind {96; CHECK-LABEL: vadd_vv_passthru:97; CHECK: # %bb.0: # %entry98; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma99; CHECK-NEXT: vmv1r.v v10, v8100; CHECK-NEXT: vadd.vv v10, v8, v9101; CHECK-NEXT: vmv1r.v v9, v8102; CHECK-NEXT: vadd.vv v9, v8, v8103; CHECK-NEXT: vadd.vv v8, v9, v10104; CHECK-NEXT: ret105entry:106 %a = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8(107 <vscale x 1 x i8> %0,108 <vscale x 1 x i8> %0,109 <vscale x 1 x i8> %1,110 i32 %2)111 112 %b = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8(113 <vscale x 1 x i8> %0,114 <vscale x 1 x i8> %0,115 <vscale x 1 x i8> %a,116 i32 %2)117 118 %c = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8(119 <vscale x 1 x i8> %0,120 <vscale x 1 x i8> %0,121 <vscale x 1 x i8> %b,122 i32 %2)123 124 ret <vscale x 1 x i8> %c125}126 127define <vscale x 1 x i8> @vadd_vv_passthru_negative(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i32 %2) nounwind {128; CHECK-LABEL: vadd_vv_passthru_negative:129; CHECK: # %bb.0: # %entry130; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma131; CHECK-NEXT: vmv1r.v v10, v8132; CHECK-NEXT: vadd.vv v10, v8, v9133; CHECK-NEXT: vadd.vv v9, v8, v10134; CHECK-NEXT: vadd.vv v8, v8, v9135; CHECK-NEXT: ret136entry:137 %a = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8(138 <vscale x 1 x i8> %0,139 <vscale x 1 x i8> %0,140 <vscale x 1 x i8> %1,141 i32 %2)142 143 %b = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8(144 <vscale x 1 x i8> %1,145 <vscale x 1 x i8> %0,146 <vscale x 1 x i8> %a,147 i32 %2)148 149 %c = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8(150 <vscale x 1 x i8> %0,151 <vscale x 1 x i8> %0,152 <vscale x 1 x i8> %b,153 i32 %2)154 155 ret <vscale x 1 x i8> %c156}157 158define <vscale x 1 x i8> @vadd_vv_mask(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i32 %2, <vscale x 1 x i1> %m) nounwind {159; CHECK-LABEL: vadd_vv_mask:160; CHECK: # %bb.0: # %entry161; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu162; CHECK-NEXT: vmv1r.v v10, v8163; CHECK-NEXT: vadd.vv v10, v8, v9, v0.t164; CHECK-NEXT: vmv1r.v v9, v8165; CHECK-NEXT: vadd.vv v9, v8, v8, v0.t166; CHECK-NEXT: vadd.vv v8, v9, v10, v0.t167; CHECK-NEXT: ret168entry:169 %a = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8(170 <vscale x 1 x i8> %0,171 <vscale x 1 x i8> %0,172 <vscale x 1 x i8> %1,173 <vscale x 1 x i1> %m,174 i32 %2, i32 1)175 176 %b = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8(177 <vscale x 1 x i8> %0,178 <vscale x 1 x i8> %0,179 <vscale x 1 x i8> %a,180 <vscale x 1 x i1> %m,181 i32 %2, i32 1)182 183 %c = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8(184 <vscale x 1 x i8> %0,185 <vscale x 1 x i8> %0,186 <vscale x 1 x i8> %b,187 <vscale x 1 x i1> %m,188 i32 %2, i32 1)189 190 ret <vscale x 1 x i8> %c191}192 193define <vscale x 1 x i8> @vadd_vv_mask_negative(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i32 %2, <vscale x 1 x i1> %m, <vscale x 1 x i1> %m2) nounwind {194; CHECK-LABEL: vadd_vv_mask_negative:195; CHECK: # %bb.0: # %entry196; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu197; CHECK-NEXT: vmv1r.v v11, v8198; CHECK-NEXT: vadd.vv v11, v8, v9, v0.t199; CHECK-NEXT: vmv1r.v v9, v8200; CHECK-NEXT: vadd.vv v9, v8, v8, v0.t201; CHECK-NEXT: vmv1r.v v0, v10202; CHECK-NEXT: vadd.vv v8, v9, v11, v0.t203; CHECK-NEXT: ret204entry:205 %a = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8(206 <vscale x 1 x i8> %0,207 <vscale x 1 x i8> %0,208 <vscale x 1 x i8> %1,209 <vscale x 1 x i1> %m,210 i32 %2, i32 1)211 212 %b = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8(213 <vscale x 1 x i8> %0,214 <vscale x 1 x i8> %0,215 <vscale x 1 x i8> %a,216 <vscale x 1 x i1> %m,217 i32 %2, i32 1)218 219 %c = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8(220 <vscale x 1 x i8> %0,221 <vscale x 1 x i8> %0,222 <vscale x 1 x i8> %b,223 <vscale x 1 x i1> %m2,224 i32 %2, i32 1)225 226 ret <vscale x 1 x i8> %c227}228 229