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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s3; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s4 5define <vscale x 1 x i16> @vsext_nxv1i8_nxv1i16(<vscale x 1 x i8> %va) {6; CHECK-LABEL: vsext_nxv1i8_nxv1i16:7; CHECK: # %bb.0:8; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma9; CHECK-NEXT: vsext.vf2 v9, v810; CHECK-NEXT: vmv1r.v v8, v911; CHECK-NEXT: ret12 %evec = sext <vscale x 1 x i8> %va to <vscale x 1 x i16>13 ret <vscale x 1 x i16> %evec14}15 16define <vscale x 1 x i16> @vzext_nxv1i8_nxv1i16(<vscale x 1 x i8> %va) {17; CHECK-LABEL: vzext_nxv1i8_nxv1i16:18; CHECK: # %bb.0:19; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma20; CHECK-NEXT: vzext.vf2 v9, v821; CHECK-NEXT: vmv1r.v v8, v922; CHECK-NEXT: ret23 %evec = zext <vscale x 1 x i8> %va to <vscale x 1 x i16>24 ret <vscale x 1 x i16> %evec25}26 27define <vscale x 1 x i32> @vsext_nxv1i8_nxv1i32(<vscale x 1 x i8> %va) {28; CHECK-LABEL: vsext_nxv1i8_nxv1i32:29; CHECK: # %bb.0:30; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma31; CHECK-NEXT: vsext.vf4 v9, v832; CHECK-NEXT: vmv1r.v v8, v933; CHECK-NEXT: ret34 %evec = sext <vscale x 1 x i8> %va to <vscale x 1 x i32>35 ret <vscale x 1 x i32> %evec36}37 38define <vscale x 1 x i32> @vzext_nxv1i8_nxv1i32(<vscale x 1 x i8> %va) {39; CHECK-LABEL: vzext_nxv1i8_nxv1i32:40; CHECK: # %bb.0:41; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma42; CHECK-NEXT: vzext.vf4 v9, v843; CHECK-NEXT: vmv1r.v v8, v944; CHECK-NEXT: ret45 %evec = zext <vscale x 1 x i8> %va to <vscale x 1 x i32>46 ret <vscale x 1 x i32> %evec47}48 49define <vscale x 1 x i64> @vsext_nxv1i8_nxv1i64(<vscale x 1 x i8> %va) {50; CHECK-LABEL: vsext_nxv1i8_nxv1i64:51; CHECK: # %bb.0:52; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma53; CHECK-NEXT: vsext.vf8 v9, v854; CHECK-NEXT: vmv.v.v v8, v955; CHECK-NEXT: ret56 %evec = sext <vscale x 1 x i8> %va to <vscale x 1 x i64>57 ret <vscale x 1 x i64> %evec58}59 60define <vscale x 1 x i64> @vzext_nxv1i8_nxv1i64(<vscale x 1 x i8> %va) {61; CHECK-LABEL: vzext_nxv1i8_nxv1i64:62; CHECK: # %bb.0:63; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma64; CHECK-NEXT: vzext.vf8 v9, v865; CHECK-NEXT: vmv.v.v v8, v966; CHECK-NEXT: ret67 %evec = zext <vscale x 1 x i8> %va to <vscale x 1 x i64>68 ret <vscale x 1 x i64> %evec69}70 71define <vscale x 2 x i16> @vsext_nxv2i8_nxv2i16(<vscale x 2 x i8> %va) {72; CHECK-LABEL: vsext_nxv2i8_nxv2i16:73; CHECK: # %bb.0:74; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma75; CHECK-NEXT: vsext.vf2 v9, v876; CHECK-NEXT: vmv1r.v v8, v977; CHECK-NEXT: ret78 %evec = sext <vscale x 2 x i8> %va to <vscale x 2 x i16>79 ret <vscale x 2 x i16> %evec80}81 82define <vscale x 2 x i16> @vzext_nxv2i8_nxv2i16(<vscale x 2 x i8> %va) {83; CHECK-LABEL: vzext_nxv2i8_nxv2i16:84; CHECK: # %bb.0:85; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma86; CHECK-NEXT: vzext.vf2 v9, v887; CHECK-NEXT: vmv1r.v v8, v988; CHECK-NEXT: ret89 %evec = zext <vscale x 2 x i8> %va to <vscale x 2 x i16>90 ret <vscale x 2 x i16> %evec91}92 93define <vscale x 2 x i32> @vsext_nxv2i8_nxv2i32(<vscale x 2 x i8> %va) {94; CHECK-LABEL: vsext_nxv2i8_nxv2i32:95; CHECK: # %bb.0:96; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma97; CHECK-NEXT: vsext.vf4 v9, v898; CHECK-NEXT: vmv.v.v v8, v999; CHECK-NEXT: ret100 %evec = sext <vscale x 2 x i8> %va to <vscale x 2 x i32>101 ret <vscale x 2 x i32> %evec102}103 104define <vscale x 2 x i32> @vzext_nxv2i8_nxv2i32(<vscale x 2 x i8> %va) {105; CHECK-LABEL: vzext_nxv2i8_nxv2i32:106; CHECK: # %bb.0:107; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma108; CHECK-NEXT: vzext.vf4 v9, v8109; CHECK-NEXT: vmv.v.v v8, v9110; CHECK-NEXT: ret111 %evec = zext <vscale x 2 x i8> %va to <vscale x 2 x i32>112 ret <vscale x 2 x i32> %evec113}114 115define <vscale x 2 x i64> @vsext_nxv2i8_nxv2i64(<vscale x 2 x i8> %va) {116; CHECK-LABEL: vsext_nxv2i8_nxv2i64:117; CHECK: # %bb.0:118; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma119; CHECK-NEXT: vmv1r.v v10, v8120; CHECK-NEXT: vsext.vf8 v8, v10121; CHECK-NEXT: ret122 %evec = sext <vscale x 2 x i8> %va to <vscale x 2 x i64>123 ret <vscale x 2 x i64> %evec124}125 126define <vscale x 2 x i64> @vzext_nxv2i8_nxv2i64(<vscale x 2 x i8> %va) {127; CHECK-LABEL: vzext_nxv2i8_nxv2i64:128; CHECK: # %bb.0:129; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma130; CHECK-NEXT: vmv1r.v v10, v8131; CHECK-NEXT: vzext.vf8 v8, v10132; CHECK-NEXT: ret133 %evec = zext <vscale x 2 x i8> %va to <vscale x 2 x i64>134 ret <vscale x 2 x i64> %evec135}136 137define <vscale x 4 x i16> @vsext_nxv4i8_nxv4i16(<vscale x 4 x i8> %va) {138; CHECK-LABEL: vsext_nxv4i8_nxv4i16:139; CHECK: # %bb.0:140; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma141; CHECK-NEXT: vsext.vf2 v9, v8142; CHECK-NEXT: vmv.v.v v8, v9143; CHECK-NEXT: ret144 %evec = sext <vscale x 4 x i8> %va to <vscale x 4 x i16>145 ret <vscale x 4 x i16> %evec146}147 148define <vscale x 4 x i16> @vzext_nxv4i8_nxv4i16(<vscale x 4 x i8> %va) {149; CHECK-LABEL: vzext_nxv4i8_nxv4i16:150; CHECK: # %bb.0:151; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma152; CHECK-NEXT: vzext.vf2 v9, v8153; CHECK-NEXT: vmv.v.v v8, v9154; CHECK-NEXT: ret155 %evec = zext <vscale x 4 x i8> %va to <vscale x 4 x i16>156 ret <vscale x 4 x i16> %evec157}158 159define <vscale x 4 x i32> @vsext_nxv4i8_nxv4i32(<vscale x 4 x i8> %va) {160; CHECK-LABEL: vsext_nxv4i8_nxv4i32:161; CHECK: # %bb.0:162; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma163; CHECK-NEXT: vmv1r.v v10, v8164; CHECK-NEXT: vsext.vf4 v8, v10165; CHECK-NEXT: ret166 %evec = sext <vscale x 4 x i8> %va to <vscale x 4 x i32>167 ret <vscale x 4 x i32> %evec168}169 170define <vscale x 4 x i32> @vzext_nxv4i8_nxv4i32(<vscale x 4 x i8> %va) {171; CHECK-LABEL: vzext_nxv4i8_nxv4i32:172; CHECK: # %bb.0:173; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma174; CHECK-NEXT: vmv1r.v v10, v8175; CHECK-NEXT: vzext.vf4 v8, v10176; CHECK-NEXT: ret177 %evec = zext <vscale x 4 x i8> %va to <vscale x 4 x i32>178 ret <vscale x 4 x i32> %evec179}180 181define <vscale x 4 x i64> @vsext_nxv4i8_nxv4i64(<vscale x 4 x i8> %va) {182; CHECK-LABEL: vsext_nxv4i8_nxv4i64:183; CHECK: # %bb.0:184; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma185; CHECK-NEXT: vmv1r.v v12, v8186; CHECK-NEXT: vsext.vf8 v8, v12187; CHECK-NEXT: ret188 %evec = sext <vscale x 4 x i8> %va to <vscale x 4 x i64>189 ret <vscale x 4 x i64> %evec190}191 192define <vscale x 4 x i64> @vzext_nxv4i8_nxv4i64(<vscale x 4 x i8> %va) {193; CHECK-LABEL: vzext_nxv4i8_nxv4i64:194; CHECK: # %bb.0:195; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma196; CHECK-NEXT: vmv1r.v v12, v8197; CHECK-NEXT: vzext.vf8 v8, v12198; CHECK-NEXT: ret199 %evec = zext <vscale x 4 x i8> %va to <vscale x 4 x i64>200 ret <vscale x 4 x i64> %evec201}202 203define <vscale x 8 x i16> @vsext_nxv8i8_nxv8i16(<vscale x 8 x i8> %va) {204; CHECK-LABEL: vsext_nxv8i8_nxv8i16:205; CHECK: # %bb.0:206; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma207; CHECK-NEXT: vmv1r.v v10, v8208; CHECK-NEXT: vsext.vf2 v8, v10209; CHECK-NEXT: ret210 %evec = sext <vscale x 8 x i8> %va to <vscale x 8 x i16>211 ret <vscale x 8 x i16> %evec212}213 214define <vscale x 8 x i16> @vzext_nxv8i8_nxv8i16(<vscale x 8 x i8> %va) {215; CHECK-LABEL: vzext_nxv8i8_nxv8i16:216; CHECK: # %bb.0:217; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma218; CHECK-NEXT: vmv1r.v v10, v8219; CHECK-NEXT: vzext.vf2 v8, v10220; CHECK-NEXT: ret221 %evec = zext <vscale x 8 x i8> %va to <vscale x 8 x i16>222 ret <vscale x 8 x i16> %evec223}224 225define <vscale x 8 x i32> @vsext_nxv8i8_nxv8i32(<vscale x 8 x i8> %va) {226; CHECK-LABEL: vsext_nxv8i8_nxv8i32:227; CHECK: # %bb.0:228; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma229; CHECK-NEXT: vmv1r.v v12, v8230; CHECK-NEXT: vsext.vf4 v8, v12231; CHECK-NEXT: ret232 %evec = sext <vscale x 8 x i8> %va to <vscale x 8 x i32>233 ret <vscale x 8 x i32> %evec234}235 236define <vscale x 8 x i32> @vzext_nxv8i8_nxv8i32(<vscale x 8 x i8> %va) {237; CHECK-LABEL: vzext_nxv8i8_nxv8i32:238; CHECK: # %bb.0:239; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma240; CHECK-NEXT: vmv1r.v v12, v8241; CHECK-NEXT: vzext.vf4 v8, v12242; CHECK-NEXT: ret243 %evec = zext <vscale x 8 x i8> %va to <vscale x 8 x i32>244 ret <vscale x 8 x i32> %evec245}246 247define <vscale x 8 x i64> @vsext_nxv8i8_nxv8i64(<vscale x 8 x i8> %va) {248; CHECK-LABEL: vsext_nxv8i8_nxv8i64:249; CHECK: # %bb.0:250; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma251; CHECK-NEXT: vmv1r.v v16, v8252; CHECK-NEXT: vsext.vf8 v8, v16253; CHECK-NEXT: ret254 %evec = sext <vscale x 8 x i8> %va to <vscale x 8 x i64>255 ret <vscale x 8 x i64> %evec256}257 258define <vscale x 8 x i64> @vzext_nxv8i8_nxv8i64(<vscale x 8 x i8> %va) {259; CHECK-LABEL: vzext_nxv8i8_nxv8i64:260; CHECK: # %bb.0:261; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma262; CHECK-NEXT: vmv1r.v v16, v8263; CHECK-NEXT: vzext.vf8 v8, v16264; CHECK-NEXT: ret265 %evec = zext <vscale x 8 x i8> %va to <vscale x 8 x i64>266 ret <vscale x 8 x i64> %evec267}268 269define <vscale x 16 x i16> @vsext_nxv16i8_nxv16i16(<vscale x 16 x i8> %va) {270; CHECK-LABEL: vsext_nxv16i8_nxv16i16:271; CHECK: # %bb.0:272; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma273; CHECK-NEXT: vmv2r.v v12, v8274; CHECK-NEXT: vsext.vf2 v8, v12275; CHECK-NEXT: ret276 %evec = sext <vscale x 16 x i8> %va to <vscale x 16 x i16>277 ret <vscale x 16 x i16> %evec278}279 280define <vscale x 16 x i16> @vzext_nxv16i8_nxv16i16(<vscale x 16 x i8> %va) {281; CHECK-LABEL: vzext_nxv16i8_nxv16i16:282; CHECK: # %bb.0:283; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma284; CHECK-NEXT: vmv2r.v v12, v8285; CHECK-NEXT: vzext.vf2 v8, v12286; CHECK-NEXT: ret287 %evec = zext <vscale x 16 x i8> %va to <vscale x 16 x i16>288 ret <vscale x 16 x i16> %evec289}290 291define <vscale x 16 x i32> @vsext_nxv16i8_nxv16i32(<vscale x 16 x i8> %va) {292; CHECK-LABEL: vsext_nxv16i8_nxv16i32:293; CHECK: # %bb.0:294; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma295; CHECK-NEXT: vmv2r.v v16, v8296; CHECK-NEXT: vsext.vf4 v8, v16297; CHECK-NEXT: ret298 %evec = sext <vscale x 16 x i8> %va to <vscale x 16 x i32>299 ret <vscale x 16 x i32> %evec300}301 302define <vscale x 16 x i32> @vzext_nxv16i8_nxv16i32(<vscale x 16 x i8> %va) {303; CHECK-LABEL: vzext_nxv16i8_nxv16i32:304; CHECK: # %bb.0:305; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma306; CHECK-NEXT: vmv2r.v v16, v8307; CHECK-NEXT: vzext.vf4 v8, v16308; CHECK-NEXT: ret309 %evec = zext <vscale x 16 x i8> %va to <vscale x 16 x i32>310 ret <vscale x 16 x i32> %evec311}312 313define <vscale x 32 x i16> @vsext_nxv32i8_nxv32i16(<vscale x 32 x i8> %va) {314; CHECK-LABEL: vsext_nxv32i8_nxv32i16:315; CHECK: # %bb.0:316; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma317; CHECK-NEXT: vmv4r.v v16, v8318; CHECK-NEXT: vsext.vf2 v8, v16319; CHECK-NEXT: ret320 %evec = sext <vscale x 32 x i8> %va to <vscale x 32 x i16>321 ret <vscale x 32 x i16> %evec322}323 324define <vscale x 32 x i16> @vzext_nxv32i8_nxv32i16(<vscale x 32 x i8> %va) {325; CHECK-LABEL: vzext_nxv32i8_nxv32i16:326; CHECK: # %bb.0:327; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma328; CHECK-NEXT: vmv4r.v v16, v8329; CHECK-NEXT: vzext.vf2 v8, v16330; CHECK-NEXT: ret331 %evec = zext <vscale x 32 x i8> %va to <vscale x 32 x i16>332 ret <vscale x 32 x i16> %evec333}334 335define <vscale x 1 x i32> @vsext_nxv1i16_nxv1i32(<vscale x 1 x i16> %va) {336; CHECK-LABEL: vsext_nxv1i16_nxv1i32:337; CHECK: # %bb.0:338; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma339; CHECK-NEXT: vsext.vf2 v9, v8340; CHECK-NEXT: vmv1r.v v8, v9341; CHECK-NEXT: ret342 %evec = sext <vscale x 1 x i16> %va to <vscale x 1 x i32>343 ret <vscale x 1 x i32> %evec344}345 346define <vscale x 1 x i32> @vzext_nxv1i16_nxv1i32(<vscale x 1 x i16> %va) {347; CHECK-LABEL: vzext_nxv1i16_nxv1i32:348; CHECK: # %bb.0:349; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma350; CHECK-NEXT: vzext.vf2 v9, v8351; CHECK-NEXT: vmv1r.v v8, v9352; CHECK-NEXT: ret353 %evec = zext <vscale x 1 x i16> %va to <vscale x 1 x i32>354 ret <vscale x 1 x i32> %evec355}356 357define <vscale x 1 x i64> @vsext_nxv1i16_nxv1i64(<vscale x 1 x i16> %va) {358; CHECK-LABEL: vsext_nxv1i16_nxv1i64:359; CHECK: # %bb.0:360; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma361; CHECK-NEXT: vsext.vf4 v9, v8362; CHECK-NEXT: vmv.v.v v8, v9363; CHECK-NEXT: ret364 %evec = sext <vscale x 1 x i16> %va to <vscale x 1 x i64>365 ret <vscale x 1 x i64> %evec366}367 368define <vscale x 1 x i64> @vzext_nxv1i16_nxv1i64(<vscale x 1 x i16> %va) {369; CHECK-LABEL: vzext_nxv1i16_nxv1i64:370; CHECK: # %bb.0:371; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma372; CHECK-NEXT: vzext.vf4 v9, v8373; CHECK-NEXT: vmv.v.v v8, v9374; CHECK-NEXT: ret375 %evec = zext <vscale x 1 x i16> %va to <vscale x 1 x i64>376 ret <vscale x 1 x i64> %evec377}378 379define <vscale x 2 x i32> @vsext_nxv2i16_nxv2i32(<vscale x 2 x i16> %va) {380; CHECK-LABEL: vsext_nxv2i16_nxv2i32:381; CHECK: # %bb.0:382; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma383; CHECK-NEXT: vsext.vf2 v9, v8384; CHECK-NEXT: vmv.v.v v8, v9385; CHECK-NEXT: ret386 %evec = sext <vscale x 2 x i16> %va to <vscale x 2 x i32>387 ret <vscale x 2 x i32> %evec388}389 390define <vscale x 2 x i32> @vzext_nxv2i16_nxv2i32(<vscale x 2 x i16> %va) {391; CHECK-LABEL: vzext_nxv2i16_nxv2i32:392; CHECK: # %bb.0:393; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma394; CHECK-NEXT: vzext.vf2 v9, v8395; CHECK-NEXT: vmv.v.v v8, v9396; CHECK-NEXT: ret397 %evec = zext <vscale x 2 x i16> %va to <vscale x 2 x i32>398 ret <vscale x 2 x i32> %evec399}400 401define <vscale x 2 x i64> @vsext_nxv2i16_nxv2i64(<vscale x 2 x i16> %va) {402; CHECK-LABEL: vsext_nxv2i16_nxv2i64:403; CHECK: # %bb.0:404; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma405; CHECK-NEXT: vmv1r.v v10, v8406; CHECK-NEXT: vsext.vf4 v8, v10407; CHECK-NEXT: ret408 %evec = sext <vscale x 2 x i16> %va to <vscale x 2 x i64>409 ret <vscale x 2 x i64> %evec410}411 412define <vscale x 2 x i64> @vzext_nxv2i16_nxv2i64(<vscale x 2 x i16> %va) {413; CHECK-LABEL: vzext_nxv2i16_nxv2i64:414; CHECK: # %bb.0:415; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma416; CHECK-NEXT: vmv1r.v v10, v8417; CHECK-NEXT: vzext.vf4 v8, v10418; CHECK-NEXT: ret419 %evec = zext <vscale x 2 x i16> %va to <vscale x 2 x i64>420 ret <vscale x 2 x i64> %evec421}422 423define <vscale x 4 x i32> @vsext_nxv4i16_nxv4i32(<vscale x 4 x i16> %va) {424; CHECK-LABEL: vsext_nxv4i16_nxv4i32:425; CHECK: # %bb.0:426; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma427; CHECK-NEXT: vmv1r.v v10, v8428; CHECK-NEXT: vsext.vf2 v8, v10429; CHECK-NEXT: ret430 %evec = sext <vscale x 4 x i16> %va to <vscale x 4 x i32>431 ret <vscale x 4 x i32> %evec432}433 434define <vscale x 4 x i32> @vzext_nxv4i16_nxv4i32(<vscale x 4 x i16> %va) {435; CHECK-LABEL: vzext_nxv4i16_nxv4i32:436; CHECK: # %bb.0:437; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma438; CHECK-NEXT: vmv1r.v v10, v8439; CHECK-NEXT: vzext.vf2 v8, v10440; CHECK-NEXT: ret441 %evec = zext <vscale x 4 x i16> %va to <vscale x 4 x i32>442 ret <vscale x 4 x i32> %evec443}444 445define <vscale x 4 x i64> @vsext_nxv4i16_nxv4i64(<vscale x 4 x i16> %va) {446; CHECK-LABEL: vsext_nxv4i16_nxv4i64:447; CHECK: # %bb.0:448; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma449; CHECK-NEXT: vmv1r.v v12, v8450; CHECK-NEXT: vsext.vf4 v8, v12451; CHECK-NEXT: ret452 %evec = sext <vscale x 4 x i16> %va to <vscale x 4 x i64>453 ret <vscale x 4 x i64> %evec454}455 456define <vscale x 4 x i64> @vzext_nxv4i16_nxv4i64(<vscale x 4 x i16> %va) {457; CHECK-LABEL: vzext_nxv4i16_nxv4i64:458; CHECK: # %bb.0:459; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma460; CHECK-NEXT: vmv1r.v v12, v8461; CHECK-NEXT: vzext.vf4 v8, v12462; CHECK-NEXT: ret463 %evec = zext <vscale x 4 x i16> %va to <vscale x 4 x i64>464 ret <vscale x 4 x i64> %evec465}466 467define <vscale x 8 x i32> @vsext_nxv8i16_nxv8i32(<vscale x 8 x i16> %va) {468; CHECK-LABEL: vsext_nxv8i16_nxv8i32:469; CHECK: # %bb.0:470; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma471; CHECK-NEXT: vmv2r.v v12, v8472; CHECK-NEXT: vsext.vf2 v8, v12473; CHECK-NEXT: ret474 %evec = sext <vscale x 8 x i16> %va to <vscale x 8 x i32>475 ret <vscale x 8 x i32> %evec476}477 478define <vscale x 8 x i32> @vzext_nxv8i16_nxv8i32(<vscale x 8 x i16> %va) {479; CHECK-LABEL: vzext_nxv8i16_nxv8i32:480; CHECK: # %bb.0:481; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma482; CHECK-NEXT: vmv2r.v v12, v8483; CHECK-NEXT: vzext.vf2 v8, v12484; CHECK-NEXT: ret485 %evec = zext <vscale x 8 x i16> %va to <vscale x 8 x i32>486 ret <vscale x 8 x i32> %evec487}488 489define <vscale x 8 x i64> @vsext_nxv8i16_nxv8i64(<vscale x 8 x i16> %va) {490; CHECK-LABEL: vsext_nxv8i16_nxv8i64:491; CHECK: # %bb.0:492; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma493; CHECK-NEXT: vmv2r.v v16, v8494; CHECK-NEXT: vsext.vf4 v8, v16495; CHECK-NEXT: ret496 %evec = sext <vscale x 8 x i16> %va to <vscale x 8 x i64>497 ret <vscale x 8 x i64> %evec498}499 500define <vscale x 8 x i64> @vzext_nxv8i16_nxv8i64(<vscale x 8 x i16> %va) {501; CHECK-LABEL: vzext_nxv8i16_nxv8i64:502; CHECK: # %bb.0:503; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma504; CHECK-NEXT: vmv2r.v v16, v8505; CHECK-NEXT: vzext.vf4 v8, v16506; CHECK-NEXT: ret507 %evec = zext <vscale x 8 x i16> %va to <vscale x 8 x i64>508 ret <vscale x 8 x i64> %evec509}510 511define <vscale x 16 x i32> @vsext_nxv16i16_nxv16i32(<vscale x 16 x i16> %va) {512; CHECK-LABEL: vsext_nxv16i16_nxv16i32:513; CHECK: # %bb.0:514; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma515; CHECK-NEXT: vmv4r.v v16, v8516; CHECK-NEXT: vsext.vf2 v8, v16517; CHECK-NEXT: ret518 %evec = sext <vscale x 16 x i16> %va to <vscale x 16 x i32>519 ret <vscale x 16 x i32> %evec520}521 522define <vscale x 16 x i32> @vzext_nxv16i16_nxv16i32(<vscale x 16 x i16> %va) {523; CHECK-LABEL: vzext_nxv16i16_nxv16i32:524; CHECK: # %bb.0:525; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma526; CHECK-NEXT: vmv4r.v v16, v8527; CHECK-NEXT: vzext.vf2 v8, v16528; CHECK-NEXT: ret529 %evec = zext <vscale x 16 x i16> %va to <vscale x 16 x i32>530 ret <vscale x 16 x i32> %evec531}532 533define <vscale x 1 x i64> @vsext_nxv1i32_nxv1i64(<vscale x 1 x i32> %va) {534; CHECK-LABEL: vsext_nxv1i32_nxv1i64:535; CHECK: # %bb.0:536; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma537; CHECK-NEXT: vsext.vf2 v9, v8538; CHECK-NEXT: vmv.v.v v8, v9539; CHECK-NEXT: ret540 %evec = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>541 ret <vscale x 1 x i64> %evec542}543 544define <vscale x 1 x i64> @vzext_nxv1i32_nxv1i64(<vscale x 1 x i32> %va) {545; CHECK-LABEL: vzext_nxv1i32_nxv1i64:546; CHECK: # %bb.0:547; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma548; CHECK-NEXT: vzext.vf2 v9, v8549; CHECK-NEXT: vmv.v.v v8, v9550; CHECK-NEXT: ret551 %evec = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>552 ret <vscale x 1 x i64> %evec553}554 555define <vscale x 2 x i64> @vsext_nxv2i32_nxv2i64(<vscale x 2 x i32> %va) {556; CHECK-LABEL: vsext_nxv2i32_nxv2i64:557; CHECK: # %bb.0:558; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma559; CHECK-NEXT: vmv1r.v v10, v8560; CHECK-NEXT: vsext.vf2 v8, v10561; CHECK-NEXT: ret562 %evec = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>563 ret <vscale x 2 x i64> %evec564}565 566define <vscale x 2 x i64> @vzext_nxv2i32_nxv2i64(<vscale x 2 x i32> %va) {567; CHECK-LABEL: vzext_nxv2i32_nxv2i64:568; CHECK: # %bb.0:569; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma570; CHECK-NEXT: vmv1r.v v10, v8571; CHECK-NEXT: vzext.vf2 v8, v10572; CHECK-NEXT: ret573 %evec = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>574 ret <vscale x 2 x i64> %evec575}576 577define <vscale x 4 x i64> @vsext_nxv4i32_nxv4i64(<vscale x 4 x i32> %va) {578; CHECK-LABEL: vsext_nxv4i32_nxv4i64:579; CHECK: # %bb.0:580; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma581; CHECK-NEXT: vmv2r.v v12, v8582; CHECK-NEXT: vsext.vf2 v8, v12583; CHECK-NEXT: ret584 %evec = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>585 ret <vscale x 4 x i64> %evec586}587 588define <vscale x 4 x i64> @vzext_nxv4i32_nxv4i64(<vscale x 4 x i32> %va) {589; CHECK-LABEL: vzext_nxv4i32_nxv4i64:590; CHECK: # %bb.0:591; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma592; CHECK-NEXT: vmv2r.v v12, v8593; CHECK-NEXT: vzext.vf2 v8, v12594; CHECK-NEXT: ret595 %evec = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>596 ret <vscale x 4 x i64> %evec597}598 599define <vscale x 8 x i64> @vsext_nxv8i32_nxv8i64(<vscale x 8 x i32> %va) {600; CHECK-LABEL: vsext_nxv8i32_nxv8i64:601; CHECK: # %bb.0:602; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma603; CHECK-NEXT: vmv4r.v v16, v8604; CHECK-NEXT: vsext.vf2 v8, v16605; CHECK-NEXT: ret606 %evec = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>607 ret <vscale x 8 x i64> %evec608}609 610define <vscale x 8 x i64> @vzext_nxv8i32_nxv8i64(<vscale x 8 x i32> %va) {611; CHECK-LABEL: vzext_nxv8i32_nxv8i64:612; CHECK: # %bb.0:613; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma614; CHECK-NEXT: vmv4r.v v16, v8615; CHECK-NEXT: vzext.vf2 v8, v16616; CHECK-NEXT: ret617 %evec = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>618 ret <vscale x 8 x i64> %evec619}620