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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zvfbfmin,+v \3; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \4; RUN: --check-prefixes=CHECK,ZVFH5; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zvfbfmin,+v \6; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \7; RUN: --check-prefixes=CHECK,ZVFH8; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+zvfbfmin,+v \9; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \10; RUN: --check-prefixes=CHECK,ZVFHMIN11; RUN: llc -mtriple=riscv64 -mattr=+d,+zfhmin,+zvfhmin,+zvfbfmin,+v \12; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \13; RUN: --check-prefixes=CHECK,ZVFHMIN14; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+experimental-zvfbfa,+v \15; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \16; RUN: --check-prefixes=CHECK,ZVFBFA17; RUN: llc -mtriple=riscv64 -mattr=+d,+zfhmin,+zvfhmin,+experimental-zvfbfa,+v \18; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \19; RUN: --check-prefixes=CHECK,ZVFBFA20 21define <vscale x 1 x bfloat> @nxv1bf16(<vscale x 1 x bfloat> %v) {22; ZVFH-LABEL: nxv1bf16:23; ZVFH: # %bb.0:24; ZVFH-NEXT: lui a0, 825; ZVFH-NEXT: addi a0, a0, -126; ZVFH-NEXT: vsetvli a1, zero, e16, mf4, ta, ma27; ZVFH-NEXT: vand.vx v8, v8, a028; ZVFH-NEXT: ret29;30; ZVFHMIN-LABEL: nxv1bf16:31; ZVFHMIN: # %bb.0:32; ZVFHMIN-NEXT: lui a0, 833; ZVFHMIN-NEXT: addi a0, a0, -134; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma35; ZVFHMIN-NEXT: vand.vx v8, v8, a036; ZVFHMIN-NEXT: ret37;38; ZVFBFA-LABEL: nxv1bf16:39; ZVFBFA: # %bb.0:40; ZVFBFA-NEXT: vsetvli a0, zero, e16alt, mf4, ta, ma41; ZVFBFA-NEXT: vfabs.v v8, v842; ZVFBFA-NEXT: ret43 %r = call <vscale x 1 x bfloat> @llvm.fabs.nxv1bf16(<vscale x 1 x bfloat> %v)44 ret <vscale x 1 x bfloat> %r45}46 47define <vscale x 2 x bfloat> @nxv2bf16(<vscale x 2 x bfloat> %v) {48; ZVFH-LABEL: nxv2bf16:49; ZVFH: # %bb.0:50; ZVFH-NEXT: lui a0, 851; ZVFH-NEXT: addi a0, a0, -152; ZVFH-NEXT: vsetvli a1, zero, e16, mf2, ta, ma53; ZVFH-NEXT: vand.vx v8, v8, a054; ZVFH-NEXT: ret55;56; ZVFHMIN-LABEL: nxv2bf16:57; ZVFHMIN: # %bb.0:58; ZVFHMIN-NEXT: lui a0, 859; ZVFHMIN-NEXT: addi a0, a0, -160; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma61; ZVFHMIN-NEXT: vand.vx v8, v8, a062; ZVFHMIN-NEXT: ret63;64; ZVFBFA-LABEL: nxv2bf16:65; ZVFBFA: # %bb.0:66; ZVFBFA-NEXT: vsetvli a0, zero, e16alt, mf2, ta, ma67; ZVFBFA-NEXT: vfabs.v v8, v868; ZVFBFA-NEXT: ret69 %r = call <vscale x 2 x bfloat> @llvm.fabs.nxv2bf16(<vscale x 2 x bfloat> %v)70 ret <vscale x 2 x bfloat> %r71}72 73define <vscale x 4 x bfloat> @nxv4bf16(<vscale x 4 x bfloat> %v) {74; ZVFH-LABEL: nxv4bf16:75; ZVFH: # %bb.0:76; ZVFH-NEXT: lui a0, 877; ZVFH-NEXT: addi a0, a0, -178; ZVFH-NEXT: vsetvli a1, zero, e16, m1, ta, ma79; ZVFH-NEXT: vand.vx v8, v8, a080; ZVFH-NEXT: ret81;82; ZVFHMIN-LABEL: nxv4bf16:83; ZVFHMIN: # %bb.0:84; ZVFHMIN-NEXT: lui a0, 885; ZVFHMIN-NEXT: addi a0, a0, -186; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma87; ZVFHMIN-NEXT: vand.vx v8, v8, a088; ZVFHMIN-NEXT: ret89;90; ZVFBFA-LABEL: nxv4bf16:91; ZVFBFA: # %bb.0:92; ZVFBFA-NEXT: vsetvli a0, zero, e16alt, m1, ta, ma93; ZVFBFA-NEXT: vfabs.v v8, v894; ZVFBFA-NEXT: ret95 %r = call <vscale x 4 x bfloat> @llvm.fabs.nxv4bf16(<vscale x 4 x bfloat> %v)96 ret <vscale x 4 x bfloat> %r97}98 99define <vscale x 8 x bfloat> @nxv8bf16(<vscale x 8 x bfloat> %v) {100; ZVFH-LABEL: nxv8bf16:101; ZVFH: # %bb.0:102; ZVFH-NEXT: lui a0, 8103; ZVFH-NEXT: addi a0, a0, -1104; ZVFH-NEXT: vsetvli a1, zero, e16, m2, ta, ma105; ZVFH-NEXT: vand.vx v8, v8, a0106; ZVFH-NEXT: ret107;108; ZVFHMIN-LABEL: nxv8bf16:109; ZVFHMIN: # %bb.0:110; ZVFHMIN-NEXT: lui a0, 8111; ZVFHMIN-NEXT: addi a0, a0, -1112; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma113; ZVFHMIN-NEXT: vand.vx v8, v8, a0114; ZVFHMIN-NEXT: ret115;116; ZVFBFA-LABEL: nxv8bf16:117; ZVFBFA: # %bb.0:118; ZVFBFA-NEXT: vsetvli a0, zero, e16alt, m2, ta, ma119; ZVFBFA-NEXT: vfabs.v v8, v8120; ZVFBFA-NEXT: ret121 %r = call <vscale x 8 x bfloat> @llvm.fabs.nxv8bf16(<vscale x 8 x bfloat> %v)122 ret <vscale x 8 x bfloat> %r123}124 125define <vscale x 16 x bfloat> @nxv16bf16(<vscale x 16 x bfloat> %v) {126; ZVFH-LABEL: nxv16bf16:127; ZVFH: # %bb.0:128; ZVFH-NEXT: lui a0, 8129; ZVFH-NEXT: addi a0, a0, -1130; ZVFH-NEXT: vsetvli a1, zero, e16, m4, ta, ma131; ZVFH-NEXT: vand.vx v8, v8, a0132; ZVFH-NEXT: ret133;134; ZVFHMIN-LABEL: nxv16bf16:135; ZVFHMIN: # %bb.0:136; ZVFHMIN-NEXT: lui a0, 8137; ZVFHMIN-NEXT: addi a0, a0, -1138; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma139; ZVFHMIN-NEXT: vand.vx v8, v8, a0140; ZVFHMIN-NEXT: ret141;142; ZVFBFA-LABEL: nxv16bf16:143; ZVFBFA: # %bb.0:144; ZVFBFA-NEXT: vsetvli a0, zero, e16alt, m4, ta, ma145; ZVFBFA-NEXT: vfabs.v v8, v8146; ZVFBFA-NEXT: ret147 %r = call <vscale x 16 x bfloat> @llvm.fabs.nxv16bf16(<vscale x 16 x bfloat> %v)148 ret <vscale x 16 x bfloat> %r149}150 151define <vscale x 32 x bfloat> @nxv32bf16(<vscale x 32 x bfloat> %v) {152; ZVFH-LABEL: nxv32bf16:153; ZVFH: # %bb.0:154; ZVFH-NEXT: lui a0, 8155; ZVFH-NEXT: addi a0, a0, -1156; ZVFH-NEXT: vsetvli a1, zero, e16, m8, ta, ma157; ZVFH-NEXT: vand.vx v8, v8, a0158; ZVFH-NEXT: ret159;160; ZVFHMIN-LABEL: nxv32bf16:161; ZVFHMIN: # %bb.0:162; ZVFHMIN-NEXT: lui a0, 8163; ZVFHMIN-NEXT: addi a0, a0, -1164; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m8, ta, ma165; ZVFHMIN-NEXT: vand.vx v8, v8, a0166; ZVFHMIN-NEXT: ret167;168; ZVFBFA-LABEL: nxv32bf16:169; ZVFBFA: # %bb.0:170; ZVFBFA-NEXT: vsetvli a0, zero, e16alt, m8, ta, ma171; ZVFBFA-NEXT: vfabs.v v8, v8172; ZVFBFA-NEXT: ret173 %r = call <vscale x 32 x bfloat> @llvm.fabs.nxv32bf16(<vscale x 32 x bfloat> %v)174 ret <vscale x 32 x bfloat> %r175}176 177define <vscale x 1 x half> @vfabs_nxv1f16(<vscale x 1 x half> %v) {178; ZVFH-LABEL: vfabs_nxv1f16:179; ZVFH: # %bb.0:180; ZVFH-NEXT: vsetvli a0, zero, e16, mf4, ta, ma181; ZVFH-NEXT: vfabs.v v8, v8182; ZVFH-NEXT: ret183;184; ZVFHMIN-LABEL: vfabs_nxv1f16:185; ZVFHMIN: # %bb.0:186; ZVFHMIN-NEXT: lui a0, 8187; ZVFHMIN-NEXT: addi a0, a0, -1188; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma189; ZVFHMIN-NEXT: vand.vx v8, v8, a0190; ZVFHMIN-NEXT: ret191;192; ZVFBFA-LABEL: vfabs_nxv1f16:193; ZVFBFA: # %bb.0:194; ZVFBFA-NEXT: lui a0, 8195; ZVFBFA-NEXT: addi a0, a0, -1196; ZVFBFA-NEXT: vsetvli a1, zero, e16, mf4, ta, ma197; ZVFBFA-NEXT: vand.vx v8, v8, a0198; ZVFBFA-NEXT: ret199 %r = call <vscale x 1 x half> @llvm.fabs.nxv1f16(<vscale x 1 x half> %v)200 ret <vscale x 1 x half> %r201}202 203define <vscale x 2 x half> @vfabs_nxv2f16(<vscale x 2 x half> %v) {204; ZVFH-LABEL: vfabs_nxv2f16:205; ZVFH: # %bb.0:206; ZVFH-NEXT: vsetvli a0, zero, e16, mf2, ta, ma207; ZVFH-NEXT: vfabs.v v8, v8208; ZVFH-NEXT: ret209;210; ZVFHMIN-LABEL: vfabs_nxv2f16:211; ZVFHMIN: # %bb.0:212; ZVFHMIN-NEXT: lui a0, 8213; ZVFHMIN-NEXT: addi a0, a0, -1214; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma215; ZVFHMIN-NEXT: vand.vx v8, v8, a0216; ZVFHMIN-NEXT: ret217;218; ZVFBFA-LABEL: vfabs_nxv2f16:219; ZVFBFA: # %bb.0:220; ZVFBFA-NEXT: lui a0, 8221; ZVFBFA-NEXT: addi a0, a0, -1222; ZVFBFA-NEXT: vsetvli a1, zero, e16, mf2, ta, ma223; ZVFBFA-NEXT: vand.vx v8, v8, a0224; ZVFBFA-NEXT: ret225 %r = call <vscale x 2 x half> @llvm.fabs.nxv2f16(<vscale x 2 x half> %v)226 ret <vscale x 2 x half> %r227}228 229define <vscale x 4 x half> @vfabs_nxv4f16(<vscale x 4 x half> %v) {230; ZVFH-LABEL: vfabs_nxv4f16:231; ZVFH: # %bb.0:232; ZVFH-NEXT: vsetvli a0, zero, e16, m1, ta, ma233; ZVFH-NEXT: vfabs.v v8, v8234; ZVFH-NEXT: ret235;236; ZVFHMIN-LABEL: vfabs_nxv4f16:237; ZVFHMIN: # %bb.0:238; ZVFHMIN-NEXT: lui a0, 8239; ZVFHMIN-NEXT: addi a0, a0, -1240; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma241; ZVFHMIN-NEXT: vand.vx v8, v8, a0242; ZVFHMIN-NEXT: ret243;244; ZVFBFA-LABEL: vfabs_nxv4f16:245; ZVFBFA: # %bb.0:246; ZVFBFA-NEXT: lui a0, 8247; ZVFBFA-NEXT: addi a0, a0, -1248; ZVFBFA-NEXT: vsetvli a1, zero, e16, m1, ta, ma249; ZVFBFA-NEXT: vand.vx v8, v8, a0250; ZVFBFA-NEXT: ret251 %r = call <vscale x 4 x half> @llvm.fabs.nxv4f16(<vscale x 4 x half> %v)252 ret <vscale x 4 x half> %r253}254 255define <vscale x 8 x half> @vfabs_nxv8f16(<vscale x 8 x half> %v) {256; ZVFH-LABEL: vfabs_nxv8f16:257; ZVFH: # %bb.0:258; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma259; ZVFH-NEXT: vfabs.v v8, v8260; ZVFH-NEXT: ret261;262; ZVFHMIN-LABEL: vfabs_nxv8f16:263; ZVFHMIN: # %bb.0:264; ZVFHMIN-NEXT: lui a0, 8265; ZVFHMIN-NEXT: addi a0, a0, -1266; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma267; ZVFHMIN-NEXT: vand.vx v8, v8, a0268; ZVFHMIN-NEXT: ret269;270; ZVFBFA-LABEL: vfabs_nxv8f16:271; ZVFBFA: # %bb.0:272; ZVFBFA-NEXT: lui a0, 8273; ZVFBFA-NEXT: addi a0, a0, -1274; ZVFBFA-NEXT: vsetvli a1, zero, e16, m2, ta, ma275; ZVFBFA-NEXT: vand.vx v8, v8, a0276; ZVFBFA-NEXT: ret277 %r = call <vscale x 8 x half> @llvm.fabs.nxv8f16(<vscale x 8 x half> %v)278 ret <vscale x 8 x half> %r279}280 281define <vscale x 16 x half> @vfabs_nxv16f16(<vscale x 16 x half> %v) {282; ZVFH-LABEL: vfabs_nxv16f16:283; ZVFH: # %bb.0:284; ZVFH-NEXT: vsetvli a0, zero, e16, m4, ta, ma285; ZVFH-NEXT: vfabs.v v8, v8286; ZVFH-NEXT: ret287;288; ZVFHMIN-LABEL: vfabs_nxv16f16:289; ZVFHMIN: # %bb.0:290; ZVFHMIN-NEXT: lui a0, 8291; ZVFHMIN-NEXT: addi a0, a0, -1292; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma293; ZVFHMIN-NEXT: vand.vx v8, v8, a0294; ZVFHMIN-NEXT: ret295;296; ZVFBFA-LABEL: vfabs_nxv16f16:297; ZVFBFA: # %bb.0:298; ZVFBFA-NEXT: lui a0, 8299; ZVFBFA-NEXT: addi a0, a0, -1300; ZVFBFA-NEXT: vsetvli a1, zero, e16, m4, ta, ma301; ZVFBFA-NEXT: vand.vx v8, v8, a0302; ZVFBFA-NEXT: ret303 %r = call <vscale x 16 x half> @llvm.fabs.nxv16f16(<vscale x 16 x half> %v)304 ret <vscale x 16 x half> %r305}306 307define <vscale x 32 x half> @vfabs_nxv32f16(<vscale x 32 x half> %v) {308; ZVFH-LABEL: vfabs_nxv32f16:309; ZVFH: # %bb.0:310; ZVFH-NEXT: vsetvli a0, zero, e16, m8, ta, ma311; ZVFH-NEXT: vfabs.v v8, v8312; ZVFH-NEXT: ret313;314; ZVFHMIN-LABEL: vfabs_nxv32f16:315; ZVFHMIN: # %bb.0:316; ZVFHMIN-NEXT: lui a0, 8317; ZVFHMIN-NEXT: addi a0, a0, -1318; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m8, ta, ma319; ZVFHMIN-NEXT: vand.vx v8, v8, a0320; ZVFHMIN-NEXT: ret321;322; ZVFBFA-LABEL: vfabs_nxv32f16:323; ZVFBFA: # %bb.0:324; ZVFBFA-NEXT: lui a0, 8325; ZVFBFA-NEXT: addi a0, a0, -1326; ZVFBFA-NEXT: vsetvli a1, zero, e16, m8, ta, ma327; ZVFBFA-NEXT: vand.vx v8, v8, a0328; ZVFBFA-NEXT: ret329 %r = call <vscale x 32 x half> @llvm.fabs.nxv32f16(<vscale x 32 x half> %v)330 ret <vscale x 32 x half> %r331}332 333define <vscale x 1 x float> @vfabs_nxv1f32(<vscale x 1 x float> %v) {334; CHECK-LABEL: vfabs_nxv1f32:335; CHECK: # %bb.0:336; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma337; CHECK-NEXT: vfabs.v v8, v8338; CHECK-NEXT: ret339 %r = call <vscale x 1 x float> @llvm.fabs.nxv1f32(<vscale x 1 x float> %v)340 ret <vscale x 1 x float> %r341}342 343define <vscale x 2 x float> @vfabs_nxv2f32(<vscale x 2 x float> %v) {344; CHECK-LABEL: vfabs_nxv2f32:345; CHECK: # %bb.0:346; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma347; CHECK-NEXT: vfabs.v v8, v8348; CHECK-NEXT: ret349 %r = call <vscale x 2 x float> @llvm.fabs.nxv2f32(<vscale x 2 x float> %v)350 ret <vscale x 2 x float> %r351}352 353define <vscale x 4 x float> @vfabs_nxv4f32(<vscale x 4 x float> %v) {354; CHECK-LABEL: vfabs_nxv4f32:355; CHECK: # %bb.0:356; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma357; CHECK-NEXT: vfabs.v v8, v8358; CHECK-NEXT: ret359 %r = call <vscale x 4 x float> @llvm.fabs.nxv4f32(<vscale x 4 x float> %v)360 ret <vscale x 4 x float> %r361}362 363define <vscale x 8 x float> @vfabs_nxv8f32(<vscale x 8 x float> %v) {364; CHECK-LABEL: vfabs_nxv8f32:365; CHECK: # %bb.0:366; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma367; CHECK-NEXT: vfabs.v v8, v8368; CHECK-NEXT: ret369 %r = call <vscale x 8 x float> @llvm.fabs.nxv8f32(<vscale x 8 x float> %v)370 ret <vscale x 8 x float> %r371}372 373define <vscale x 16 x float> @vfabs_nxv16f32(<vscale x 16 x float> %v) {374; CHECK-LABEL: vfabs_nxv16f32:375; CHECK: # %bb.0:376; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma377; CHECK-NEXT: vfabs.v v8, v8378; CHECK-NEXT: ret379 %r = call <vscale x 16 x float> @llvm.fabs.nxv16f32(<vscale x 16 x float> %v)380 ret <vscale x 16 x float> %r381}382 383define <vscale x 1 x double> @vfabs_nxv1f64(<vscale x 1 x double> %v) {384; CHECK-LABEL: vfabs_nxv1f64:385; CHECK: # %bb.0:386; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma387; CHECK-NEXT: vfabs.v v8, v8388; CHECK-NEXT: ret389 %r = call <vscale x 1 x double> @llvm.fabs.nxv1f64(<vscale x 1 x double> %v)390 ret <vscale x 1 x double> %r391}392 393define <vscale x 2 x double> @vfabs_nxv2f64(<vscale x 2 x double> %v) {394; CHECK-LABEL: vfabs_nxv2f64:395; CHECK: # %bb.0:396; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma397; CHECK-NEXT: vfabs.v v8, v8398; CHECK-NEXT: ret399 %r = call <vscale x 2 x double> @llvm.fabs.nxv2f64(<vscale x 2 x double> %v)400 ret <vscale x 2 x double> %r401}402 403define <vscale x 4 x double> @vfabs_nxv4f64(<vscale x 4 x double> %v) {404; CHECK-LABEL: vfabs_nxv4f64:405; CHECK: # %bb.0:406; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma407; CHECK-NEXT: vfabs.v v8, v8408; CHECK-NEXT: ret409 %r = call <vscale x 4 x double> @llvm.fabs.nxv4f64(<vscale x 4 x double> %v)410 ret <vscale x 4 x double> %r411}412 413define <vscale x 8 x double> @vfabs_nxv8f64(<vscale x 8 x double> %v) {414; CHECK-LABEL: vfabs_nxv8f64:415; CHECK: # %bb.0:416; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma417; CHECK-NEXT: vfabs.v v8, v8418; CHECK-NEXT: ret419 %r = call <vscale x 8 x double> @llvm.fabs.nxv8f64(<vscale x 8 x double> %v)420 ret <vscale x 8 x double> %r421}422