887 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zvfbfmin,+v -target-abi=ilp32d \3; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH4; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zvfbfmin,+v -target-abi=lp64d \5; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH6; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+zvfbfmin,+v -target-abi=ilp32d \7; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN8; RUN: llc -mtriple=riscv64 -mattr=+d,+zfhmin,+zvfhmin,+zvfbfmin,+v -target-abi=lp64d \9; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN10; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+v,+experimental-zvfbfa -target-abi=ilp32d \11; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFBFA12; RUN: llc -mtriple=riscv64 -mattr=+d,+zfhmin,+zvfhmin,+v,+experimental-zvfbfa -target-abi=lp64d \13; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFBFA14 15define <vscale x 1 x bfloat> @vfabs_vv_nxv1bf16(<vscale x 1 x bfloat> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {16; ZVFH-LABEL: vfabs_vv_nxv1bf16:17; ZVFH: # %bb.0:18; ZVFH-NEXT: lui a1, 819; ZVFH-NEXT: addi a1, a1, -120; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma21; ZVFH-NEXT: vand.vx v8, v8, a1, v0.t22; ZVFH-NEXT: ret23;24; ZVFHMIN-LABEL: vfabs_vv_nxv1bf16:25; ZVFHMIN: # %bb.0:26; ZVFHMIN-NEXT: lui a1, 827; ZVFHMIN-NEXT: addi a1, a1, -128; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma29; ZVFHMIN-NEXT: vand.vx v8, v8, a1, v0.t30; ZVFHMIN-NEXT: ret31;32; ZVFBFA-LABEL: vfabs_vv_nxv1bf16:33; ZVFBFA: # %bb.0:34; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, mf4, ta, ma35; ZVFBFA-NEXT: vfabs.v v8, v8, v0.t36; ZVFBFA-NEXT: ret37 %v = call <vscale x 1 x bfloat> @llvm.vp.fabs.nxv1bf16(<vscale x 1 x bfloat> %va, <vscale x 1 x i1> %m, i32 %evl)38 ret <vscale x 1 x bfloat> %v39}40 41define <vscale x 1 x bfloat> @vfabs_vv_nxv1bf16_unmasked(<vscale x 1 x bfloat> %va, i32 zeroext %evl) {42; ZVFH-LABEL: vfabs_vv_nxv1bf16_unmasked:43; ZVFH: # %bb.0:44; ZVFH-NEXT: lui a1, 845; ZVFH-NEXT: addi a1, a1, -146; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma47; ZVFH-NEXT: vand.vx v8, v8, a148; ZVFH-NEXT: ret49;50; ZVFHMIN-LABEL: vfabs_vv_nxv1bf16_unmasked:51; ZVFHMIN: # %bb.0:52; ZVFHMIN-NEXT: lui a1, 853; ZVFHMIN-NEXT: addi a1, a1, -154; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma55; ZVFHMIN-NEXT: vand.vx v8, v8, a156; ZVFHMIN-NEXT: ret57;58; ZVFBFA-LABEL: vfabs_vv_nxv1bf16_unmasked:59; ZVFBFA: # %bb.0:60; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, mf4, ta, ma61; ZVFBFA-NEXT: vfabs.v v8, v862; ZVFBFA-NEXT: ret63 %v = call <vscale x 1 x bfloat> @llvm.vp.fabs.nxv1bf16(<vscale x 1 x bfloat> %va, <vscale x 1 x i1> splat (i1 true), i32 %evl)64 ret <vscale x 1 x bfloat> %v65}66 67define <vscale x 2 x bfloat> @vfabs_vv_nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {68; ZVFH-LABEL: vfabs_vv_nxv2bf16:69; ZVFH: # %bb.0:70; ZVFH-NEXT: lui a1, 871; ZVFH-NEXT: addi a1, a1, -172; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma73; ZVFH-NEXT: vand.vx v8, v8, a1, v0.t74; ZVFH-NEXT: ret75;76; ZVFHMIN-LABEL: vfabs_vv_nxv2bf16:77; ZVFHMIN: # %bb.0:78; ZVFHMIN-NEXT: lui a1, 879; ZVFHMIN-NEXT: addi a1, a1, -180; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma81; ZVFHMIN-NEXT: vand.vx v8, v8, a1, v0.t82; ZVFHMIN-NEXT: ret83;84; ZVFBFA-LABEL: vfabs_vv_nxv2bf16:85; ZVFBFA: # %bb.0:86; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, mf2, ta, ma87; ZVFBFA-NEXT: vfabs.v v8, v8, v0.t88; ZVFBFA-NEXT: ret89 %v = call <vscale x 2 x bfloat> @llvm.vp.fabs.nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x i1> %m, i32 %evl)90 ret <vscale x 2 x bfloat> %v91}92 93define <vscale x 2 x bfloat> @vfabs_vv_nxv2bf16_unmasked(<vscale x 2 x bfloat> %va, i32 zeroext %evl) {94; ZVFH-LABEL: vfabs_vv_nxv2bf16_unmasked:95; ZVFH: # %bb.0:96; ZVFH-NEXT: lui a1, 897; ZVFH-NEXT: addi a1, a1, -198; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma99; ZVFH-NEXT: vand.vx v8, v8, a1100; ZVFH-NEXT: ret101;102; ZVFHMIN-LABEL: vfabs_vv_nxv2bf16_unmasked:103; ZVFHMIN: # %bb.0:104; ZVFHMIN-NEXT: lui a1, 8105; ZVFHMIN-NEXT: addi a1, a1, -1106; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma107; ZVFHMIN-NEXT: vand.vx v8, v8, a1108; ZVFHMIN-NEXT: ret109;110; ZVFBFA-LABEL: vfabs_vv_nxv2bf16_unmasked:111; ZVFBFA: # %bb.0:112; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, mf2, ta, ma113; ZVFBFA-NEXT: vfabs.v v8, v8114; ZVFBFA-NEXT: ret115 %v = call <vscale x 2 x bfloat> @llvm.vp.fabs.nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)116 ret <vscale x 2 x bfloat> %v117}118 119define <vscale x 4 x bfloat> @vfabs_vv_nxv4bf16(<vscale x 4 x bfloat> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {120; ZVFH-LABEL: vfabs_vv_nxv4bf16:121; ZVFH: # %bb.0:122; ZVFH-NEXT: lui a1, 8123; ZVFH-NEXT: addi a1, a1, -1124; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma125; ZVFH-NEXT: vand.vx v8, v8, a1, v0.t126; ZVFH-NEXT: ret127;128; ZVFHMIN-LABEL: vfabs_vv_nxv4bf16:129; ZVFHMIN: # %bb.0:130; ZVFHMIN-NEXT: lui a1, 8131; ZVFHMIN-NEXT: addi a1, a1, -1132; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma133; ZVFHMIN-NEXT: vand.vx v8, v8, a1, v0.t134; ZVFHMIN-NEXT: ret135;136; ZVFBFA-LABEL: vfabs_vv_nxv4bf16:137; ZVFBFA: # %bb.0:138; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, m1, ta, ma139; ZVFBFA-NEXT: vfabs.v v8, v8, v0.t140; ZVFBFA-NEXT: ret141 %v = call <vscale x 4 x bfloat> @llvm.vp.fabs.nxv4bf16(<vscale x 4 x bfloat> %va, <vscale x 4 x i1> %m, i32 %evl)142 ret <vscale x 4 x bfloat> %v143}144 145define <vscale x 4 x bfloat> @vfabs_vv_nxv4bf16_unmasked(<vscale x 4 x bfloat> %va, i32 zeroext %evl) {146; ZVFH-LABEL: vfabs_vv_nxv4bf16_unmasked:147; ZVFH: # %bb.0:148; ZVFH-NEXT: lui a1, 8149; ZVFH-NEXT: addi a1, a1, -1150; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma151; ZVFH-NEXT: vand.vx v8, v8, a1152; ZVFH-NEXT: ret153;154; ZVFHMIN-LABEL: vfabs_vv_nxv4bf16_unmasked:155; ZVFHMIN: # %bb.0:156; ZVFHMIN-NEXT: lui a1, 8157; ZVFHMIN-NEXT: addi a1, a1, -1158; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma159; ZVFHMIN-NEXT: vand.vx v8, v8, a1160; ZVFHMIN-NEXT: ret161;162; ZVFBFA-LABEL: vfabs_vv_nxv4bf16_unmasked:163; ZVFBFA: # %bb.0:164; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, m1, ta, ma165; ZVFBFA-NEXT: vfabs.v v8, v8166; ZVFBFA-NEXT: ret167 %v = call <vscale x 4 x bfloat> @llvm.vp.fabs.nxv4bf16(<vscale x 4 x bfloat> %va, <vscale x 4 x i1> splat (i1 true), i32 %evl)168 ret <vscale x 4 x bfloat> %v169}170 171define <vscale x 8 x bfloat> @vfabs_vv_nxv8bf16(<vscale x 8 x bfloat> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {172; ZVFH-LABEL: vfabs_vv_nxv8bf16:173; ZVFH: # %bb.0:174; ZVFH-NEXT: lui a1, 8175; ZVFH-NEXT: addi a1, a1, -1176; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma177; ZVFH-NEXT: vand.vx v8, v8, a1, v0.t178; ZVFH-NEXT: ret179;180; ZVFHMIN-LABEL: vfabs_vv_nxv8bf16:181; ZVFHMIN: # %bb.0:182; ZVFHMIN-NEXT: lui a1, 8183; ZVFHMIN-NEXT: addi a1, a1, -1184; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma185; ZVFHMIN-NEXT: vand.vx v8, v8, a1, v0.t186; ZVFHMIN-NEXT: ret187;188; ZVFBFA-LABEL: vfabs_vv_nxv8bf16:189; ZVFBFA: # %bb.0:190; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, m2, ta, ma191; ZVFBFA-NEXT: vfabs.v v8, v8, v0.t192; ZVFBFA-NEXT: ret193 %v = call <vscale x 8 x bfloat> @llvm.vp.fabs.nxv8bf16(<vscale x 8 x bfloat> %va, <vscale x 8 x i1> %m, i32 %evl)194 ret <vscale x 8 x bfloat> %v195}196 197define <vscale x 8 x bfloat> @vfabs_vv_nxv8bf16_unmasked(<vscale x 8 x bfloat> %va, i32 zeroext %evl) {198; ZVFH-LABEL: vfabs_vv_nxv8bf16_unmasked:199; ZVFH: # %bb.0:200; ZVFH-NEXT: lui a1, 8201; ZVFH-NEXT: addi a1, a1, -1202; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma203; ZVFH-NEXT: vand.vx v8, v8, a1204; ZVFH-NEXT: ret205;206; ZVFHMIN-LABEL: vfabs_vv_nxv8bf16_unmasked:207; ZVFHMIN: # %bb.0:208; ZVFHMIN-NEXT: lui a1, 8209; ZVFHMIN-NEXT: addi a1, a1, -1210; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma211; ZVFHMIN-NEXT: vand.vx v8, v8, a1212; ZVFHMIN-NEXT: ret213;214; ZVFBFA-LABEL: vfabs_vv_nxv8bf16_unmasked:215; ZVFBFA: # %bb.0:216; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, m2, ta, ma217; ZVFBFA-NEXT: vfabs.v v8, v8218; ZVFBFA-NEXT: ret219 %v = call <vscale x 8 x bfloat> @llvm.vp.fabs.nxv8bf16(<vscale x 8 x bfloat> %va, <vscale x 8 x i1> splat (i1 true), i32 %evl)220 ret <vscale x 8 x bfloat> %v221}222 223define <vscale x 16 x bfloat> @vfabs_vv_nxv16bf16(<vscale x 16 x bfloat> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {224; ZVFH-LABEL: vfabs_vv_nxv16bf16:225; ZVFH: # %bb.0:226; ZVFH-NEXT: lui a1, 8227; ZVFH-NEXT: addi a1, a1, -1228; ZVFH-NEXT: vsetvli zero, a0, e16, m4, ta, ma229; ZVFH-NEXT: vand.vx v8, v8, a1, v0.t230; ZVFH-NEXT: ret231;232; ZVFHMIN-LABEL: vfabs_vv_nxv16bf16:233; ZVFHMIN: # %bb.0:234; ZVFHMIN-NEXT: lui a1, 8235; ZVFHMIN-NEXT: addi a1, a1, -1236; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma237; ZVFHMIN-NEXT: vand.vx v8, v8, a1, v0.t238; ZVFHMIN-NEXT: ret239;240; ZVFBFA-LABEL: vfabs_vv_nxv16bf16:241; ZVFBFA: # %bb.0:242; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, m4, ta, ma243; ZVFBFA-NEXT: vfabs.v v8, v8, v0.t244; ZVFBFA-NEXT: ret245 %v = call <vscale x 16 x bfloat> @llvm.vp.fabs.nxv16bf16(<vscale x 16 x bfloat> %va, <vscale x 16 x i1> %m, i32 %evl)246 ret <vscale x 16 x bfloat> %v247}248 249define <vscale x 16 x bfloat> @vfabs_vv_nxv16bf16_unmasked(<vscale x 16 x bfloat> %va, i32 zeroext %evl) {250; ZVFH-LABEL: vfabs_vv_nxv16bf16_unmasked:251; ZVFH: # %bb.0:252; ZVFH-NEXT: lui a1, 8253; ZVFH-NEXT: addi a1, a1, -1254; ZVFH-NEXT: vsetvli zero, a0, e16, m4, ta, ma255; ZVFH-NEXT: vand.vx v8, v8, a1256; ZVFH-NEXT: ret257;258; ZVFHMIN-LABEL: vfabs_vv_nxv16bf16_unmasked:259; ZVFHMIN: # %bb.0:260; ZVFHMIN-NEXT: lui a1, 8261; ZVFHMIN-NEXT: addi a1, a1, -1262; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma263; ZVFHMIN-NEXT: vand.vx v8, v8, a1264; ZVFHMIN-NEXT: ret265;266; ZVFBFA-LABEL: vfabs_vv_nxv16bf16_unmasked:267; ZVFBFA: # %bb.0:268; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, m4, ta, ma269; ZVFBFA-NEXT: vfabs.v v8, v8270; ZVFBFA-NEXT: ret271 %v = call <vscale x 16 x bfloat> @llvm.vp.fabs.nxv16bf16(<vscale x 16 x bfloat> %va, <vscale x 16 x i1> splat (i1 true), i32 %evl)272 ret <vscale x 16 x bfloat> %v273}274 275define <vscale x 32 x bfloat> @vfabs_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {276; ZVFH-LABEL: vfabs_vv_nxv32bf16:277; ZVFH: # %bb.0:278; ZVFH-NEXT: lui a1, 8279; ZVFH-NEXT: addi a1, a1, -1280; ZVFH-NEXT: vsetvli zero, a0, e16, m8, ta, ma281; ZVFH-NEXT: vand.vx v8, v8, a1, v0.t282; ZVFH-NEXT: ret283;284; ZVFHMIN-LABEL: vfabs_vv_nxv32bf16:285; ZVFHMIN: # %bb.0:286; ZVFHMIN-NEXT: lui a1, 8287; ZVFHMIN-NEXT: addi a1, a1, -1288; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma289; ZVFHMIN-NEXT: vand.vx v8, v8, a1, v0.t290; ZVFHMIN-NEXT: ret291;292; ZVFBFA-LABEL: vfabs_vv_nxv32bf16:293; ZVFBFA: # %bb.0:294; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, m8, ta, ma295; ZVFBFA-NEXT: vfabs.v v8, v8, v0.t296; ZVFBFA-NEXT: ret297 %v = call <vscale x 32 x bfloat> @llvm.vp.fabs.nxv32bf16(<vscale x 32 x bfloat> %va, <vscale x 32 x i1> %m, i32 %evl)298 ret <vscale x 32 x bfloat> %v299}300 301define <vscale x 32 x bfloat> @vfabs_vv_nxv32bf16_unmasked(<vscale x 32 x bfloat> %va, i32 zeroext %evl) {302; ZVFH-LABEL: vfabs_vv_nxv32bf16_unmasked:303; ZVFH: # %bb.0:304; ZVFH-NEXT: lui a1, 8305; ZVFH-NEXT: addi a1, a1, -1306; ZVFH-NEXT: vsetvli zero, a0, e16, m8, ta, ma307; ZVFH-NEXT: vand.vx v8, v8, a1308; ZVFH-NEXT: ret309;310; ZVFHMIN-LABEL: vfabs_vv_nxv32bf16_unmasked:311; ZVFHMIN: # %bb.0:312; ZVFHMIN-NEXT: lui a1, 8313; ZVFHMIN-NEXT: addi a1, a1, -1314; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma315; ZVFHMIN-NEXT: vand.vx v8, v8, a1316; ZVFHMIN-NEXT: ret317;318; ZVFBFA-LABEL: vfabs_vv_nxv32bf16_unmasked:319; ZVFBFA: # %bb.0:320; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, m8, ta, ma321; ZVFBFA-NEXT: vfabs.v v8, v8322; ZVFBFA-NEXT: ret323 %v = call <vscale x 32 x bfloat> @llvm.vp.fabs.nxv32bf16(<vscale x 32 x bfloat> %va, <vscale x 32 x i1> splat (i1 true), i32 %evl)324 ret <vscale x 32 x bfloat> %v325}326 327define <vscale x 1 x half> @vfabs_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {328; ZVFH-LABEL: vfabs_vv_nxv1f16:329; ZVFH: # %bb.0:330; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma331; ZVFH-NEXT: vfabs.v v8, v8, v0.t332; ZVFH-NEXT: ret333;334; ZVFHMIN-LABEL: vfabs_vv_nxv1f16:335; ZVFHMIN: # %bb.0:336; ZVFHMIN-NEXT: lui a1, 8337; ZVFHMIN-NEXT: addi a1, a1, -1338; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma339; ZVFHMIN-NEXT: vand.vx v8, v8, a1, v0.t340; ZVFHMIN-NEXT: ret341;342; ZVFBFA-LABEL: vfabs_vv_nxv1f16:343; ZVFBFA: # %bb.0:344; ZVFBFA-NEXT: lui a1, 8345; ZVFBFA-NEXT: addi a1, a1, -1346; ZVFBFA-NEXT: vsetvli zero, a0, e16, mf4, ta, ma347; ZVFBFA-NEXT: vand.vx v8, v8, a1, v0.t348; ZVFBFA-NEXT: ret349 %v = call <vscale x 1 x half> @llvm.vp.fabs.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x i1> %m, i32 %evl)350 ret <vscale x 1 x half> %v351}352 353define <vscale x 1 x half> @vfabs_vv_nxv1f16_unmasked(<vscale x 1 x half> %va, i32 zeroext %evl) {354; ZVFH-LABEL: vfabs_vv_nxv1f16_unmasked:355; ZVFH: # %bb.0:356; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma357; ZVFH-NEXT: vfabs.v v8, v8358; ZVFH-NEXT: ret359;360; ZVFHMIN-LABEL: vfabs_vv_nxv1f16_unmasked:361; ZVFHMIN: # %bb.0:362; ZVFHMIN-NEXT: lui a1, 8363; ZVFHMIN-NEXT: addi a1, a1, -1364; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma365; ZVFHMIN-NEXT: vand.vx v8, v8, a1366; ZVFHMIN-NEXT: ret367;368; ZVFBFA-LABEL: vfabs_vv_nxv1f16_unmasked:369; ZVFBFA: # %bb.0:370; ZVFBFA-NEXT: lui a1, 8371; ZVFBFA-NEXT: addi a1, a1, -1372; ZVFBFA-NEXT: vsetvli zero, a0, e16, mf4, ta, ma373; ZVFBFA-NEXT: vand.vx v8, v8, a1374; ZVFBFA-NEXT: ret375 %v = call <vscale x 1 x half> @llvm.vp.fabs.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x i1> splat (i1 true), i32 %evl)376 ret <vscale x 1 x half> %v377}378 379define <vscale x 2 x half> @vfabs_vv_nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {380; ZVFH-LABEL: vfabs_vv_nxv2f16:381; ZVFH: # %bb.0:382; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma383; ZVFH-NEXT: vfabs.v v8, v8, v0.t384; ZVFH-NEXT: ret385;386; ZVFHMIN-LABEL: vfabs_vv_nxv2f16:387; ZVFHMIN: # %bb.0:388; ZVFHMIN-NEXT: lui a1, 8389; ZVFHMIN-NEXT: addi a1, a1, -1390; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma391; ZVFHMIN-NEXT: vand.vx v8, v8, a1, v0.t392; ZVFHMIN-NEXT: ret393;394; ZVFBFA-LABEL: vfabs_vv_nxv2f16:395; ZVFBFA: # %bb.0:396; ZVFBFA-NEXT: lui a1, 8397; ZVFBFA-NEXT: addi a1, a1, -1398; ZVFBFA-NEXT: vsetvli zero, a0, e16, mf2, ta, ma399; ZVFBFA-NEXT: vand.vx v8, v8, a1, v0.t400; ZVFBFA-NEXT: ret401 %v = call <vscale x 2 x half> @llvm.vp.fabs.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x i1> %m, i32 %evl)402 ret <vscale x 2 x half> %v403}404 405define <vscale x 2 x half> @vfabs_vv_nxv2f16_unmasked(<vscale x 2 x half> %va, i32 zeroext %evl) {406; ZVFH-LABEL: vfabs_vv_nxv2f16_unmasked:407; ZVFH: # %bb.0:408; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma409; ZVFH-NEXT: vfabs.v v8, v8410; ZVFH-NEXT: ret411;412; ZVFHMIN-LABEL: vfabs_vv_nxv2f16_unmasked:413; ZVFHMIN: # %bb.0:414; ZVFHMIN-NEXT: lui a1, 8415; ZVFHMIN-NEXT: addi a1, a1, -1416; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma417; ZVFHMIN-NEXT: vand.vx v8, v8, a1418; ZVFHMIN-NEXT: ret419;420; ZVFBFA-LABEL: vfabs_vv_nxv2f16_unmasked:421; ZVFBFA: # %bb.0:422; ZVFBFA-NEXT: lui a1, 8423; ZVFBFA-NEXT: addi a1, a1, -1424; ZVFBFA-NEXT: vsetvli zero, a0, e16, mf2, ta, ma425; ZVFBFA-NEXT: vand.vx v8, v8, a1426; ZVFBFA-NEXT: ret427 %v = call <vscale x 2 x half> @llvm.vp.fabs.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)428 ret <vscale x 2 x half> %v429}430 431define <vscale x 4 x half> @vfabs_vv_nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {432; ZVFH-LABEL: vfabs_vv_nxv4f16:433; ZVFH: # %bb.0:434; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma435; ZVFH-NEXT: vfabs.v v8, v8, v0.t436; ZVFH-NEXT: ret437;438; ZVFHMIN-LABEL: vfabs_vv_nxv4f16:439; ZVFHMIN: # %bb.0:440; ZVFHMIN-NEXT: lui a1, 8441; ZVFHMIN-NEXT: addi a1, a1, -1442; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma443; ZVFHMIN-NEXT: vand.vx v8, v8, a1, v0.t444; ZVFHMIN-NEXT: ret445;446; ZVFBFA-LABEL: vfabs_vv_nxv4f16:447; ZVFBFA: # %bb.0:448; ZVFBFA-NEXT: lui a1, 8449; ZVFBFA-NEXT: addi a1, a1, -1450; ZVFBFA-NEXT: vsetvli zero, a0, e16, m1, ta, ma451; ZVFBFA-NEXT: vand.vx v8, v8, a1, v0.t452; ZVFBFA-NEXT: ret453 %v = call <vscale x 4 x half> @llvm.vp.fabs.nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x i1> %m, i32 %evl)454 ret <vscale x 4 x half> %v455}456 457define <vscale x 4 x half> @vfabs_vv_nxv4f16_unmasked(<vscale x 4 x half> %va, i32 zeroext %evl) {458; ZVFH-LABEL: vfabs_vv_nxv4f16_unmasked:459; ZVFH: # %bb.0:460; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma461; ZVFH-NEXT: vfabs.v v8, v8462; ZVFH-NEXT: ret463;464; ZVFHMIN-LABEL: vfabs_vv_nxv4f16_unmasked:465; ZVFHMIN: # %bb.0:466; ZVFHMIN-NEXT: lui a1, 8467; ZVFHMIN-NEXT: addi a1, a1, -1468; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma469; ZVFHMIN-NEXT: vand.vx v8, v8, a1470; ZVFHMIN-NEXT: ret471;472; ZVFBFA-LABEL: vfabs_vv_nxv4f16_unmasked:473; ZVFBFA: # %bb.0:474; ZVFBFA-NEXT: lui a1, 8475; ZVFBFA-NEXT: addi a1, a1, -1476; ZVFBFA-NEXT: vsetvli zero, a0, e16, m1, ta, ma477; ZVFBFA-NEXT: vand.vx v8, v8, a1478; ZVFBFA-NEXT: ret479 %v = call <vscale x 4 x half> @llvm.vp.fabs.nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x i1> splat (i1 true), i32 %evl)480 ret <vscale x 4 x half> %v481}482 483define <vscale x 8 x half> @vfabs_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {484; ZVFH-LABEL: vfabs_vv_nxv8f16:485; ZVFH: # %bb.0:486; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma487; ZVFH-NEXT: vfabs.v v8, v8, v0.t488; ZVFH-NEXT: ret489;490; ZVFHMIN-LABEL: vfabs_vv_nxv8f16:491; ZVFHMIN: # %bb.0:492; ZVFHMIN-NEXT: lui a1, 8493; ZVFHMIN-NEXT: addi a1, a1, -1494; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma495; ZVFHMIN-NEXT: vand.vx v8, v8, a1, v0.t496; ZVFHMIN-NEXT: ret497;498; ZVFBFA-LABEL: vfabs_vv_nxv8f16:499; ZVFBFA: # %bb.0:500; ZVFBFA-NEXT: lui a1, 8501; ZVFBFA-NEXT: addi a1, a1, -1502; ZVFBFA-NEXT: vsetvli zero, a0, e16, m2, ta, ma503; ZVFBFA-NEXT: vand.vx v8, v8, a1, v0.t504; ZVFBFA-NEXT: ret505 %v = call <vscale x 8 x half> @llvm.vp.fabs.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x i1> %m, i32 %evl)506 ret <vscale x 8 x half> %v507}508 509define <vscale x 8 x half> @vfabs_vv_nxv8f16_unmasked(<vscale x 8 x half> %va, i32 zeroext %evl) {510; ZVFH-LABEL: vfabs_vv_nxv8f16_unmasked:511; ZVFH: # %bb.0:512; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma513; ZVFH-NEXT: vfabs.v v8, v8514; ZVFH-NEXT: ret515;516; ZVFHMIN-LABEL: vfabs_vv_nxv8f16_unmasked:517; ZVFHMIN: # %bb.0:518; ZVFHMIN-NEXT: lui a1, 8519; ZVFHMIN-NEXT: addi a1, a1, -1520; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma521; ZVFHMIN-NEXT: vand.vx v8, v8, a1522; ZVFHMIN-NEXT: ret523;524; ZVFBFA-LABEL: vfabs_vv_nxv8f16_unmasked:525; ZVFBFA: # %bb.0:526; ZVFBFA-NEXT: lui a1, 8527; ZVFBFA-NEXT: addi a1, a1, -1528; ZVFBFA-NEXT: vsetvli zero, a0, e16, m2, ta, ma529; ZVFBFA-NEXT: vand.vx v8, v8, a1530; ZVFBFA-NEXT: ret531 %v = call <vscale x 8 x half> @llvm.vp.fabs.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x i1> splat (i1 true), i32 %evl)532 ret <vscale x 8 x half> %v533}534 535define <vscale x 16 x half> @vfabs_vv_nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {536; ZVFH-LABEL: vfabs_vv_nxv16f16:537; ZVFH: # %bb.0:538; ZVFH-NEXT: vsetvli zero, a0, e16, m4, ta, ma539; ZVFH-NEXT: vfabs.v v8, v8, v0.t540; ZVFH-NEXT: ret541;542; ZVFHMIN-LABEL: vfabs_vv_nxv16f16:543; ZVFHMIN: # %bb.0:544; ZVFHMIN-NEXT: lui a1, 8545; ZVFHMIN-NEXT: addi a1, a1, -1546; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma547; ZVFHMIN-NEXT: vand.vx v8, v8, a1, v0.t548; ZVFHMIN-NEXT: ret549;550; ZVFBFA-LABEL: vfabs_vv_nxv16f16:551; ZVFBFA: # %bb.0:552; ZVFBFA-NEXT: lui a1, 8553; ZVFBFA-NEXT: addi a1, a1, -1554; ZVFBFA-NEXT: vsetvli zero, a0, e16, m4, ta, ma555; ZVFBFA-NEXT: vand.vx v8, v8, a1, v0.t556; ZVFBFA-NEXT: ret557 %v = call <vscale x 16 x half> @llvm.vp.fabs.nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x i1> %m, i32 %evl)558 ret <vscale x 16 x half> %v559}560 561define <vscale x 16 x half> @vfabs_vv_nxv16f16_unmasked(<vscale x 16 x half> %va, i32 zeroext %evl) {562; ZVFH-LABEL: vfabs_vv_nxv16f16_unmasked:563; ZVFH: # %bb.0:564; ZVFH-NEXT: vsetvli zero, a0, e16, m4, ta, ma565; ZVFH-NEXT: vfabs.v v8, v8566; ZVFH-NEXT: ret567;568; ZVFHMIN-LABEL: vfabs_vv_nxv16f16_unmasked:569; ZVFHMIN: # %bb.0:570; ZVFHMIN-NEXT: lui a1, 8571; ZVFHMIN-NEXT: addi a1, a1, -1572; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma573; ZVFHMIN-NEXT: vand.vx v8, v8, a1574; ZVFHMIN-NEXT: ret575;576; ZVFBFA-LABEL: vfabs_vv_nxv16f16_unmasked:577; ZVFBFA: # %bb.0:578; ZVFBFA-NEXT: lui a1, 8579; ZVFBFA-NEXT: addi a1, a1, -1580; ZVFBFA-NEXT: vsetvli zero, a0, e16, m4, ta, ma581; ZVFBFA-NEXT: vand.vx v8, v8, a1582; ZVFBFA-NEXT: ret583 %v = call <vscale x 16 x half> @llvm.vp.fabs.nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x i1> splat (i1 true), i32 %evl)584 ret <vscale x 16 x half> %v585}586 587define <vscale x 32 x half> @vfabs_vv_nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {588; ZVFH-LABEL: vfabs_vv_nxv32f16:589; ZVFH: # %bb.0:590; ZVFH-NEXT: vsetvli zero, a0, e16, m8, ta, ma591; ZVFH-NEXT: vfabs.v v8, v8, v0.t592; ZVFH-NEXT: ret593;594; ZVFHMIN-LABEL: vfabs_vv_nxv32f16:595; ZVFHMIN: # %bb.0:596; ZVFHMIN-NEXT: lui a1, 8597; ZVFHMIN-NEXT: addi a1, a1, -1598; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma599; ZVFHMIN-NEXT: vand.vx v8, v8, a1, v0.t600; ZVFHMIN-NEXT: ret601;602; ZVFBFA-LABEL: vfabs_vv_nxv32f16:603; ZVFBFA: # %bb.0:604; ZVFBFA-NEXT: lui a1, 8605; ZVFBFA-NEXT: addi a1, a1, -1606; ZVFBFA-NEXT: vsetvli zero, a0, e16, m8, ta, ma607; ZVFBFA-NEXT: vand.vx v8, v8, a1, v0.t608; ZVFBFA-NEXT: ret609 %v = call <vscale x 32 x half> @llvm.vp.fabs.nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x i1> %m, i32 %evl)610 ret <vscale x 32 x half> %v611}612 613define <vscale x 32 x half> @vfabs_vv_nxv32f16_unmasked(<vscale x 32 x half> %va, i32 zeroext %evl) {614; ZVFH-LABEL: vfabs_vv_nxv32f16_unmasked:615; ZVFH: # %bb.0:616; ZVFH-NEXT: vsetvli zero, a0, e16, m8, ta, ma617; ZVFH-NEXT: vfabs.v v8, v8618; ZVFH-NEXT: ret619;620; ZVFHMIN-LABEL: vfabs_vv_nxv32f16_unmasked:621; ZVFHMIN: # %bb.0:622; ZVFHMIN-NEXT: lui a1, 8623; ZVFHMIN-NEXT: addi a1, a1, -1624; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma625; ZVFHMIN-NEXT: vand.vx v8, v8, a1626; ZVFHMIN-NEXT: ret627;628; ZVFBFA-LABEL: vfabs_vv_nxv32f16_unmasked:629; ZVFBFA: # %bb.0:630; ZVFBFA-NEXT: lui a1, 8631; ZVFBFA-NEXT: addi a1, a1, -1632; ZVFBFA-NEXT: vsetvli zero, a0, e16, m8, ta, ma633; ZVFBFA-NEXT: vand.vx v8, v8, a1634; ZVFBFA-NEXT: ret635 %v = call <vscale x 32 x half> @llvm.vp.fabs.nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x i1> splat (i1 true), i32 %evl)636 ret <vscale x 32 x half> %v637}638 639define <vscale x 1 x float> @vfabs_vv_nxv1f32(<vscale x 1 x float> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {640; CHECK-LABEL: vfabs_vv_nxv1f32:641; CHECK: # %bb.0:642; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma643; CHECK-NEXT: vfabs.v v8, v8, v0.t644; CHECK-NEXT: ret645 %v = call <vscale x 1 x float> @llvm.vp.fabs.nxv1f32(<vscale x 1 x float> %va, <vscale x 1 x i1> %m, i32 %evl)646 ret <vscale x 1 x float> %v647}648 649define <vscale x 1 x float> @vfabs_vv_nxv1f32_unmasked(<vscale x 1 x float> %va, i32 zeroext %evl) {650; CHECK-LABEL: vfabs_vv_nxv1f32_unmasked:651; CHECK: # %bb.0:652; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma653; CHECK-NEXT: vfabs.v v8, v8654; CHECK-NEXT: ret655 %v = call <vscale x 1 x float> @llvm.vp.fabs.nxv1f32(<vscale x 1 x float> %va, <vscale x 1 x i1> splat (i1 true), i32 %evl)656 ret <vscale x 1 x float> %v657}658 659define <vscale x 2 x float> @vfabs_vv_nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {660; CHECK-LABEL: vfabs_vv_nxv2f32:661; CHECK: # %bb.0:662; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma663; CHECK-NEXT: vfabs.v v8, v8, v0.t664; CHECK-NEXT: ret665 %v = call <vscale x 2 x float> @llvm.vp.fabs.nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x i1> %m, i32 %evl)666 ret <vscale x 2 x float> %v667}668 669define <vscale x 2 x float> @vfabs_vv_nxv2f32_unmasked(<vscale x 2 x float> %va, i32 zeroext %evl) {670; CHECK-LABEL: vfabs_vv_nxv2f32_unmasked:671; CHECK: # %bb.0:672; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma673; CHECK-NEXT: vfabs.v v8, v8674; CHECK-NEXT: ret675 %v = call <vscale x 2 x float> @llvm.vp.fabs.nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)676 ret <vscale x 2 x float> %v677}678 679define <vscale x 4 x float> @vfabs_vv_nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {680; CHECK-LABEL: vfabs_vv_nxv4f32:681; CHECK: # %bb.0:682; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma683; CHECK-NEXT: vfabs.v v8, v8, v0.t684; CHECK-NEXT: ret685 %v = call <vscale x 4 x float> @llvm.vp.fabs.nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x i1> %m, i32 %evl)686 ret <vscale x 4 x float> %v687}688 689define <vscale x 4 x float> @vfabs_vv_nxv4f32_unmasked(<vscale x 4 x float> %va, i32 zeroext %evl) {690; CHECK-LABEL: vfabs_vv_nxv4f32_unmasked:691; CHECK: # %bb.0:692; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma693; CHECK-NEXT: vfabs.v v8, v8694; CHECK-NEXT: ret695 %v = call <vscale x 4 x float> @llvm.vp.fabs.nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x i1> splat (i1 true), i32 %evl)696 ret <vscale x 4 x float> %v697}698 699define <vscale x 8 x float> @vfabs_vv_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {700; CHECK-LABEL: vfabs_vv_nxv8f32:701; CHECK: # %bb.0:702; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma703; CHECK-NEXT: vfabs.v v8, v8, v0.t704; CHECK-NEXT: ret705 %v = call <vscale x 8 x float> @llvm.vp.fabs.nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x i1> %m, i32 %evl)706 ret <vscale x 8 x float> %v707}708 709define <vscale x 8 x float> @vfabs_vv_nxv8f32_unmasked(<vscale x 8 x float> %va, i32 zeroext %evl) {710; CHECK-LABEL: vfabs_vv_nxv8f32_unmasked:711; CHECK: # %bb.0:712; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma713; CHECK-NEXT: vfabs.v v8, v8714; CHECK-NEXT: ret715 %v = call <vscale x 8 x float> @llvm.vp.fabs.nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x i1> splat (i1 true), i32 %evl)716 ret <vscale x 8 x float> %v717}718 719define <vscale x 16 x float> @vfabs_vv_nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {720; CHECK-LABEL: vfabs_vv_nxv16f32:721; CHECK: # %bb.0:722; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma723; CHECK-NEXT: vfabs.v v8, v8, v0.t724; CHECK-NEXT: ret725 %v = call <vscale x 16 x float> @llvm.vp.fabs.nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x i1> %m, i32 %evl)726 ret <vscale x 16 x float> %v727}728 729define <vscale x 16 x float> @vfabs_vv_nxv16f32_unmasked(<vscale x 16 x float> %va, i32 zeroext %evl) {730; CHECK-LABEL: vfabs_vv_nxv16f32_unmasked:731; CHECK: # %bb.0:732; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma733; CHECK-NEXT: vfabs.v v8, v8734; CHECK-NEXT: ret735 %v = call <vscale x 16 x float> @llvm.vp.fabs.nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x i1> splat (i1 true), i32 %evl)736 ret <vscale x 16 x float> %v737}738 739define <vscale x 1 x double> @vfabs_vv_nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {740; CHECK-LABEL: vfabs_vv_nxv1f64:741; CHECK: # %bb.0:742; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma743; CHECK-NEXT: vfabs.v v8, v8, v0.t744; CHECK-NEXT: ret745 %v = call <vscale x 1 x double> @llvm.vp.fabs.nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x i1> %m, i32 %evl)746 ret <vscale x 1 x double> %v747}748 749define <vscale x 1 x double> @vfabs_vv_nxv1f64_unmasked(<vscale x 1 x double> %va, i32 zeroext %evl) {750; CHECK-LABEL: vfabs_vv_nxv1f64_unmasked:751; CHECK: # %bb.0:752; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma753; CHECK-NEXT: vfabs.v v8, v8754; CHECK-NEXT: ret755 %v = call <vscale x 1 x double> @llvm.vp.fabs.nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x i1> splat (i1 true), i32 %evl)756 ret <vscale x 1 x double> %v757}758 759define <vscale x 2 x double> @vfabs_vv_nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {760; CHECK-LABEL: vfabs_vv_nxv2f64:761; CHECK: # %bb.0:762; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma763; CHECK-NEXT: vfabs.v v8, v8, v0.t764; CHECK-NEXT: ret765 %v = call <vscale x 2 x double> @llvm.vp.fabs.nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x i1> %m, i32 %evl)766 ret <vscale x 2 x double> %v767}768 769define <vscale x 2 x double> @vfabs_vv_nxv2f64_unmasked(<vscale x 2 x double> %va, i32 zeroext %evl) {770; CHECK-LABEL: vfabs_vv_nxv2f64_unmasked:771; CHECK: # %bb.0:772; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma773; CHECK-NEXT: vfabs.v v8, v8774; CHECK-NEXT: ret775 %v = call <vscale x 2 x double> @llvm.vp.fabs.nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)776 ret <vscale x 2 x double> %v777}778 779define <vscale x 4 x double> @vfabs_vv_nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {780; CHECK-LABEL: vfabs_vv_nxv4f64:781; CHECK: # %bb.0:782; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma783; CHECK-NEXT: vfabs.v v8, v8, v0.t784; CHECK-NEXT: ret785 %v = call <vscale x 4 x double> @llvm.vp.fabs.nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x i1> %m, i32 %evl)786 ret <vscale x 4 x double> %v787}788 789define <vscale x 4 x double> @vfabs_vv_nxv4f64_unmasked(<vscale x 4 x double> %va, i32 zeroext %evl) {790; CHECK-LABEL: vfabs_vv_nxv4f64_unmasked:791; CHECK: # %bb.0:792; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma793; CHECK-NEXT: vfabs.v v8, v8794; CHECK-NEXT: ret795 %v = call <vscale x 4 x double> @llvm.vp.fabs.nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x i1> splat (i1 true), i32 %evl)796 ret <vscale x 4 x double> %v797}798 799define <vscale x 7 x double> @vfabs_vv_nxv7f64(<vscale x 7 x double> %va, <vscale x 7 x i1> %m, i32 zeroext %evl) {800; CHECK-LABEL: vfabs_vv_nxv7f64:801; CHECK: # %bb.0:802; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma803; CHECK-NEXT: vfabs.v v8, v8, v0.t804; CHECK-NEXT: ret805 %v = call <vscale x 7 x double> @llvm.vp.fabs.nxv7f64(<vscale x 7 x double> %va, <vscale x 7 x i1> %m, i32 %evl)806 ret <vscale x 7 x double> %v807}808 809define <vscale x 7 x double> @vfabs_vv_nxv7f64_unmasked(<vscale x 7 x double> %va, i32 zeroext %evl) {810; CHECK-LABEL: vfabs_vv_nxv7f64_unmasked:811; CHECK: # %bb.0:812; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma813; CHECK-NEXT: vfabs.v v8, v8814; CHECK-NEXT: ret815 %v = call <vscale x 7 x double> @llvm.vp.fabs.nxv7f64(<vscale x 7 x double> %va, <vscale x 7 x i1> splat (i1 true), i32 %evl)816 ret <vscale x 7 x double> %v817}818 819define <vscale x 8 x double> @vfabs_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {820; CHECK-LABEL: vfabs_vv_nxv8f64:821; CHECK: # %bb.0:822; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma823; CHECK-NEXT: vfabs.v v8, v8, v0.t824; CHECK-NEXT: ret825 %v = call <vscale x 8 x double> @llvm.vp.fabs.nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x i1> %m, i32 %evl)826 ret <vscale x 8 x double> %v827}828 829define <vscale x 8 x double> @vfabs_vv_nxv8f64_unmasked(<vscale x 8 x double> %va, i32 zeroext %evl) {830; CHECK-LABEL: vfabs_vv_nxv8f64_unmasked:831; CHECK: # %bb.0:832; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma833; CHECK-NEXT: vfabs.v v8, v8834; CHECK-NEXT: ret835 %v = call <vscale x 8 x double> @llvm.vp.fabs.nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x i1> splat (i1 true), i32 %evl)836 ret <vscale x 8 x double> %v837}838 839; Test splitting.840 841define <vscale x 16 x double> @vfabs_vv_nxv16f64(<vscale x 16 x double> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {842; CHECK-LABEL: vfabs_vv_nxv16f64:843; CHECK: # %bb.0:844; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma845; CHECK-NEXT: vmv1r.v v24, v0846; CHECK-NEXT: csrr a1, vlenb847; CHECK-NEXT: srli a2, a1, 3848; CHECK-NEXT: sub a3, a0, a1849; CHECK-NEXT: vslidedown.vx v0, v0, a2850; CHECK-NEXT: sltu a2, a0, a3851; CHECK-NEXT: addi a2, a2, -1852; CHECK-NEXT: and a2, a2, a3853; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma854; CHECK-NEXT: vfabs.v v16, v16, v0.t855; CHECK-NEXT: bltu a0, a1, .LBB44_2856; CHECK-NEXT: # %bb.1:857; CHECK-NEXT: mv a0, a1858; CHECK-NEXT: .LBB44_2:859; CHECK-NEXT: vmv1r.v v0, v24860; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma861; CHECK-NEXT: vfabs.v v8, v8, v0.t862; CHECK-NEXT: ret863 %v = call <vscale x 16 x double> @llvm.vp.fabs.nxv16f64(<vscale x 16 x double> %va, <vscale x 16 x i1> %m, i32 %evl)864 ret <vscale x 16 x double> %v865}866 867define <vscale x 16 x double> @vfabs_vv_nxv16f64_unmasked(<vscale x 16 x double> %va, i32 zeroext %evl) {868; CHECK-LABEL: vfabs_vv_nxv16f64_unmasked:869; CHECK: # %bb.0:870; CHECK-NEXT: csrr a1, vlenb871; CHECK-NEXT: sub a2, a0, a1872; CHECK-NEXT: sltu a3, a0, a2873; CHECK-NEXT: addi a3, a3, -1874; CHECK-NEXT: and a2, a3, a2875; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma876; CHECK-NEXT: vfabs.v v16, v16877; CHECK-NEXT: bltu a0, a1, .LBB45_2878; CHECK-NEXT: # %bb.1:879; CHECK-NEXT: mv a0, a1880; CHECK-NEXT: .LBB45_2:881; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma882; CHECK-NEXT: vfabs.v v8, v8883; CHECK-NEXT: ret884 %v = call <vscale x 16 x double> @llvm.vp.fabs.nxv16f64(<vscale x 16 x double> %va, <vscale x 16 x i1> splat (i1 true), i32 %evl)885 ret <vscale x 16 x double> %v886}887