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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \3; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \5; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s6; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfhmin,+zvfh \7; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s8; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfhmin,+zvfh \9; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s10; RUN: sed 's/iXLen/i32/g' %s | not --crash llc -mtriple=riscv32 -mattr=+v,+zvfhmin \11; RUN: -target-abi=ilp32d 2>&1 | FileCheck %s --check-prefixes=ZVFMIN12; RUN: sed 's/iXLen/i64/g' %s | not --crash llc -mtriple=riscv64 -mattr=+v,+zvfhmin \13; RUN: -target-abi=lp64d 2>&1 | FileCheck %s --check-prefixes=ZVFMIN14 15; ZVFMIN: LLVM ERROR: Cannot select: intrinsic %llvm.riscv.vfadd16 17define <vscale x 1 x half> @intrinsic_vfadd_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, iXLen %2) nounwind {18; CHECK-LABEL: intrinsic_vfadd_vv_nxv1f16_nxv1f16_nxv1f16:19; CHECK: # %bb.0: # %entry20; CHECK-NEXT: fsrmi a1, 021; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma22; CHECK-NEXT: vfadd.vv v8, v8, v923; CHECK-NEXT: fsrm a124; CHECK-NEXT: ret25entry:26 %a = call <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.nxv1f16(27 <vscale x 1 x half> poison,28 <vscale x 1 x half> %0,29 <vscale x 1 x half> %1,30 iXLen 0, iXLen %2)31 32 ret <vscale x 1 x half> %a33}34 35define <vscale x 1 x half> @intrinsic_vfadd_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {36; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv1f16_nxv1f16_nxv1f16:37; CHECK: # %bb.0: # %entry38; CHECK-NEXT: fsrmi a1, 039; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu40; CHECK-NEXT: vfadd.vv v8, v9, v10, v0.t41; CHECK-NEXT: fsrm a142; CHECK-NEXT: ret43entry:44 %a = call <vscale x 1 x half> @llvm.riscv.vfadd.mask.nxv1f16.nxv1f16(45 <vscale x 1 x half> %0,46 <vscale x 1 x half> %1,47 <vscale x 1 x half> %2,48 <vscale x 1 x i1> %3,49 iXLen 0, iXLen %4, iXLen 1)50 51 ret <vscale x 1 x half> %a52}53 54define <vscale x 2 x half> @intrinsic_vfadd_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, iXLen %2) nounwind {55; CHECK-LABEL: intrinsic_vfadd_vv_nxv2f16_nxv2f16_nxv2f16:56; CHECK: # %bb.0: # %entry57; CHECK-NEXT: fsrmi a1, 058; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma59; CHECK-NEXT: vfadd.vv v8, v8, v960; CHECK-NEXT: fsrm a161; CHECK-NEXT: ret62entry:63 %a = call <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.nxv2f16(64 <vscale x 2 x half> poison,65 <vscale x 2 x half> %0,66 <vscale x 2 x half> %1,67 iXLen 0, iXLen %2)68 69 ret <vscale x 2 x half> %a70}71 72define <vscale x 2 x half> @intrinsic_vfadd_mask_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {73; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv2f16_nxv2f16_nxv2f16:74; CHECK: # %bb.0: # %entry75; CHECK-NEXT: fsrmi a1, 076; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu77; CHECK-NEXT: vfadd.vv v8, v9, v10, v0.t78; CHECK-NEXT: fsrm a179; CHECK-NEXT: ret80entry:81 %a = call <vscale x 2 x half> @llvm.riscv.vfadd.mask.nxv2f16.nxv2f16(82 <vscale x 2 x half> %0,83 <vscale x 2 x half> %1,84 <vscale x 2 x half> %2,85 <vscale x 2 x i1> %3,86 iXLen 0, iXLen %4, iXLen 1)87 88 ret <vscale x 2 x half> %a89}90 91define <vscale x 4 x half> @intrinsic_vfadd_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, iXLen %2) nounwind {92; CHECK-LABEL: intrinsic_vfadd_vv_nxv4f16_nxv4f16_nxv4f16:93; CHECK: # %bb.0: # %entry94; CHECK-NEXT: fsrmi a1, 095; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma96; CHECK-NEXT: vfadd.vv v8, v8, v997; CHECK-NEXT: fsrm a198; CHECK-NEXT: ret99entry:100 %a = call <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.nxv4f16(101 <vscale x 4 x half> poison,102 <vscale x 4 x half> %0,103 <vscale x 4 x half> %1,104 iXLen 0, iXLen %2)105 106 ret <vscale x 4 x half> %a107}108 109define <vscale x 4 x half> @intrinsic_vfadd_mask_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {110; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv4f16_nxv4f16_nxv4f16:111; CHECK: # %bb.0: # %entry112; CHECK-NEXT: fsrmi a1, 0113; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu114; CHECK-NEXT: vfadd.vv v8, v9, v10, v0.t115; CHECK-NEXT: fsrm a1116; CHECK-NEXT: ret117entry:118 %a = call <vscale x 4 x half> @llvm.riscv.vfadd.mask.nxv4f16.nxv4f16(119 <vscale x 4 x half> %0,120 <vscale x 4 x half> %1,121 <vscale x 4 x half> %2,122 <vscale x 4 x i1> %3,123 iXLen 0, iXLen %4, iXLen 1)124 125 ret <vscale x 4 x half> %a126}127 128define <vscale x 8 x half> @intrinsic_vfadd_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, iXLen %2) nounwind {129; CHECK-LABEL: intrinsic_vfadd_vv_nxv8f16_nxv8f16_nxv8f16:130; CHECK: # %bb.0: # %entry131; CHECK-NEXT: fsrmi a1, 0132; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma133; CHECK-NEXT: vfadd.vv v8, v8, v10134; CHECK-NEXT: fsrm a1135; CHECK-NEXT: ret136entry:137 %a = call <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.nxv8f16(138 <vscale x 8 x half> poison,139 <vscale x 8 x half> %0,140 <vscale x 8 x half> %1,141 iXLen 0, iXLen %2)142 143 ret <vscale x 8 x half> %a144}145 146define <vscale x 8 x half> @intrinsic_vfadd_mask_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {147; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv8f16_nxv8f16_nxv8f16:148; CHECK: # %bb.0: # %entry149; CHECK-NEXT: fsrmi a1, 0150; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu151; CHECK-NEXT: vfadd.vv v8, v10, v12, v0.t152; CHECK-NEXT: fsrm a1153; CHECK-NEXT: ret154entry:155 %a = call <vscale x 8 x half> @llvm.riscv.vfadd.mask.nxv8f16.nxv8f16(156 <vscale x 8 x half> %0,157 <vscale x 8 x half> %1,158 <vscale x 8 x half> %2,159 <vscale x 8 x i1> %3,160 iXLen 0, iXLen %4, iXLen 1)161 162 ret <vscale x 8 x half> %a163}164 165define <vscale x 16 x half> @intrinsic_vfadd_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, iXLen %2) nounwind {166; CHECK-LABEL: intrinsic_vfadd_vv_nxv16f16_nxv16f16_nxv16f16:167; CHECK: # %bb.0: # %entry168; CHECK-NEXT: fsrmi a1, 0169; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma170; CHECK-NEXT: vfadd.vv v8, v8, v12171; CHECK-NEXT: fsrm a1172; CHECK-NEXT: ret173entry:174 %a = call <vscale x 16 x half> @llvm.riscv.vfadd.nxv16f16.nxv16f16(175 <vscale x 16 x half> poison,176 <vscale x 16 x half> %0,177 <vscale x 16 x half> %1,178 iXLen 0, iXLen %2)179 180 ret <vscale x 16 x half> %a181}182 183define <vscale x 16 x half> @intrinsic_vfadd_mask_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {184; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv16f16_nxv16f16_nxv16f16:185; CHECK: # %bb.0: # %entry186; CHECK-NEXT: fsrmi a1, 0187; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu188; CHECK-NEXT: vfadd.vv v8, v12, v16, v0.t189; CHECK-NEXT: fsrm a1190; CHECK-NEXT: ret191entry:192 %a = call <vscale x 16 x half> @llvm.riscv.vfadd.mask.nxv16f16.nxv16f16(193 <vscale x 16 x half> %0,194 <vscale x 16 x half> %1,195 <vscale x 16 x half> %2,196 <vscale x 16 x i1> %3,197 iXLen 0, iXLen %4, iXLen 1)198 199 ret <vscale x 16 x half> %a200}201 202define <vscale x 32 x half> @intrinsic_vfadd_vv_nxv32f16_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, iXLen %2) nounwind {203; CHECK-LABEL: intrinsic_vfadd_vv_nxv32f16_nxv32f16_nxv32f16:204; CHECK: # %bb.0: # %entry205; CHECK-NEXT: fsrmi a1, 0206; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma207; CHECK-NEXT: vfadd.vv v8, v8, v16208; CHECK-NEXT: fsrm a1209; CHECK-NEXT: ret210entry:211 %a = call <vscale x 32 x half> @llvm.riscv.vfadd.nxv32f16.nxv32f16(212 <vscale x 32 x half> poison,213 <vscale x 32 x half> %0,214 <vscale x 32 x half> %1,215 iXLen 0, iXLen %2)216 217 ret <vscale x 32 x half> %a218}219 220define <vscale x 32 x half> @intrinsic_vfadd_mask_vv_nxv32f16_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {221; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv32f16_nxv32f16_nxv32f16:222; CHECK: # %bb.0: # %entry223; CHECK-NEXT: vl8re16.v v24, (a0)224; CHECK-NEXT: fsrmi a0, 0225; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu226; CHECK-NEXT: vfadd.vv v8, v16, v24, v0.t227; CHECK-NEXT: fsrm a0228; CHECK-NEXT: ret229entry:230 %a = call <vscale x 32 x half> @llvm.riscv.vfadd.mask.nxv32f16.nxv32f16(231 <vscale x 32 x half> %0,232 <vscale x 32 x half> %1,233 <vscale x 32 x half> %2,234 <vscale x 32 x i1> %3,235 iXLen 0, iXLen %4, iXLen 1)236 237 ret <vscale x 32 x half> %a238}239 240define <vscale x 1 x float> @intrinsic_vfadd_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, iXLen %2) nounwind {241; CHECK-LABEL: intrinsic_vfadd_vv_nxv1f32_nxv1f32_nxv1f32:242; CHECK: # %bb.0: # %entry243; CHECK-NEXT: fsrmi a1, 0244; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma245; CHECK-NEXT: vfadd.vv v8, v8, v9246; CHECK-NEXT: fsrm a1247; CHECK-NEXT: ret248entry:249 %a = call <vscale x 1 x float> @llvm.riscv.vfadd.nxv1f32.nxv1f32(250 <vscale x 1 x float> poison,251 <vscale x 1 x float> %0,252 <vscale x 1 x float> %1,253 iXLen 0, iXLen %2)254 255 ret <vscale x 1 x float> %a256}257 258define <vscale x 1 x float> @intrinsic_vfadd_mask_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {259; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv1f32_nxv1f32_nxv1f32:260; CHECK: # %bb.0: # %entry261; CHECK-NEXT: fsrmi a1, 0262; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu263; CHECK-NEXT: vfadd.vv v8, v9, v10, v0.t264; CHECK-NEXT: fsrm a1265; CHECK-NEXT: ret266entry:267 %a = call <vscale x 1 x float> @llvm.riscv.vfadd.mask.nxv1f32.nxv1f32(268 <vscale x 1 x float> %0,269 <vscale x 1 x float> %1,270 <vscale x 1 x float> %2,271 <vscale x 1 x i1> %3,272 iXLen 0, iXLen %4, iXLen 1)273 274 ret <vscale x 1 x float> %a275}276 277define <vscale x 2 x float> @intrinsic_vfadd_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, iXLen %2) nounwind {278; CHECK-LABEL: intrinsic_vfadd_vv_nxv2f32_nxv2f32_nxv2f32:279; CHECK: # %bb.0: # %entry280; CHECK-NEXT: fsrmi a1, 0281; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma282; CHECK-NEXT: vfadd.vv v8, v8, v9283; CHECK-NEXT: fsrm a1284; CHECK-NEXT: ret285entry:286 %a = call <vscale x 2 x float> @llvm.riscv.vfadd.nxv2f32.nxv2f32(287 <vscale x 2 x float> poison,288 <vscale x 2 x float> %0,289 <vscale x 2 x float> %1,290 iXLen 0, iXLen %2)291 292 ret <vscale x 2 x float> %a293}294 295define <vscale x 2 x float> @intrinsic_vfadd_mask_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {296; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv2f32_nxv2f32_nxv2f32:297; CHECK: # %bb.0: # %entry298; CHECK-NEXT: fsrmi a1, 0299; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu300; CHECK-NEXT: vfadd.vv v8, v9, v10, v0.t301; CHECK-NEXT: fsrm a1302; CHECK-NEXT: ret303entry:304 %a = call <vscale x 2 x float> @llvm.riscv.vfadd.mask.nxv2f32.nxv2f32(305 <vscale x 2 x float> %0,306 <vscale x 2 x float> %1,307 <vscale x 2 x float> %2,308 <vscale x 2 x i1> %3,309 iXLen 0, iXLen %4, iXLen 1)310 311 ret <vscale x 2 x float> %a312}313 314define <vscale x 4 x float> @intrinsic_vfadd_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, iXLen %2) nounwind {315; CHECK-LABEL: intrinsic_vfadd_vv_nxv4f32_nxv4f32_nxv4f32:316; CHECK: # %bb.0: # %entry317; CHECK-NEXT: fsrmi a1, 0318; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma319; CHECK-NEXT: vfadd.vv v8, v8, v10320; CHECK-NEXT: fsrm a1321; CHECK-NEXT: ret322entry:323 %a = call <vscale x 4 x float> @llvm.riscv.vfadd.nxv4f32.nxv4f32(324 <vscale x 4 x float> poison,325 <vscale x 4 x float> %0,326 <vscale x 4 x float> %1,327 iXLen 0, iXLen %2)328 329 ret <vscale x 4 x float> %a330}331 332define <vscale x 4 x float> @intrinsic_vfadd_mask_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {333; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv4f32_nxv4f32_nxv4f32:334; CHECK: # %bb.0: # %entry335; CHECK-NEXT: fsrmi a1, 0336; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu337; CHECK-NEXT: vfadd.vv v8, v10, v12, v0.t338; CHECK-NEXT: fsrm a1339; CHECK-NEXT: ret340entry:341 %a = call <vscale x 4 x float> @llvm.riscv.vfadd.mask.nxv4f32.nxv4f32(342 <vscale x 4 x float> %0,343 <vscale x 4 x float> %1,344 <vscale x 4 x float> %2,345 <vscale x 4 x i1> %3,346 iXLen 0, iXLen %4, iXLen 1)347 348 ret <vscale x 4 x float> %a349}350 351define <vscale x 8 x float> @intrinsic_vfadd_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, iXLen %2) nounwind {352; CHECK-LABEL: intrinsic_vfadd_vv_nxv8f32_nxv8f32_nxv8f32:353; CHECK: # %bb.0: # %entry354; CHECK-NEXT: fsrmi a1, 0355; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma356; CHECK-NEXT: vfadd.vv v8, v8, v12357; CHECK-NEXT: fsrm a1358; CHECK-NEXT: ret359entry:360 %a = call <vscale x 8 x float> @llvm.riscv.vfadd.nxv8f32.nxv8f32(361 <vscale x 8 x float> poison,362 <vscale x 8 x float> %0,363 <vscale x 8 x float> %1,364 iXLen 0, iXLen %2)365 366 ret <vscale x 8 x float> %a367}368 369define <vscale x 8 x float> @intrinsic_vfadd_mask_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {370; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv8f32_nxv8f32_nxv8f32:371; CHECK: # %bb.0: # %entry372; CHECK-NEXT: fsrmi a1, 0373; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu374; CHECK-NEXT: vfadd.vv v8, v12, v16, v0.t375; CHECK-NEXT: fsrm a1376; CHECK-NEXT: ret377entry:378 %a = call <vscale x 8 x float> @llvm.riscv.vfadd.mask.nxv8f32.nxv8f32(379 <vscale x 8 x float> %0,380 <vscale x 8 x float> %1,381 <vscale x 8 x float> %2,382 <vscale x 8 x i1> %3,383 iXLen 0, iXLen %4, iXLen 1)384 385 ret <vscale x 8 x float> %a386}387 388define <vscale x 16 x float> @intrinsic_vfadd_vv_nxv16f32_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, iXLen %2) nounwind {389; CHECK-LABEL: intrinsic_vfadd_vv_nxv16f32_nxv16f32_nxv16f32:390; CHECK: # %bb.0: # %entry391; CHECK-NEXT: fsrmi a1, 0392; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma393; CHECK-NEXT: vfadd.vv v8, v8, v16394; CHECK-NEXT: fsrm a1395; CHECK-NEXT: ret396entry:397 %a = call <vscale x 16 x float> @llvm.riscv.vfadd.nxv16f32.nxv16f32(398 <vscale x 16 x float> poison,399 <vscale x 16 x float> %0,400 <vscale x 16 x float> %1,401 iXLen 0, iXLen %2)402 403 ret <vscale x 16 x float> %a404}405 406define <vscale x 16 x float> @intrinsic_vfadd_mask_vv_nxv16f32_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x float> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {407; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv16f32_nxv16f32_nxv16f32:408; CHECK: # %bb.0: # %entry409; CHECK-NEXT: vl8re32.v v24, (a0)410; CHECK-NEXT: fsrmi a0, 0411; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu412; CHECK-NEXT: vfadd.vv v8, v16, v24, v0.t413; CHECK-NEXT: fsrm a0414; CHECK-NEXT: ret415entry:416 %a = call <vscale x 16 x float> @llvm.riscv.vfadd.mask.nxv16f32.nxv16f32(417 <vscale x 16 x float> %0,418 <vscale x 16 x float> %1,419 <vscale x 16 x float> %2,420 <vscale x 16 x i1> %3,421 iXLen 0, iXLen %4, iXLen 1)422 423 ret <vscale x 16 x float> %a424}425 426define <vscale x 1 x double> @intrinsic_vfadd_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, iXLen %2) nounwind {427; CHECK-LABEL: intrinsic_vfadd_vv_nxv1f64_nxv1f64_nxv1f64:428; CHECK: # %bb.0: # %entry429; CHECK-NEXT: fsrmi a1, 0430; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma431; CHECK-NEXT: vfadd.vv v8, v8, v9432; CHECK-NEXT: fsrm a1433; CHECK-NEXT: ret434entry:435 %a = call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(436 <vscale x 1 x double> poison,437 <vscale x 1 x double> %0,438 <vscale x 1 x double> %1,439 iXLen 0, iXLen %2)440 441 ret <vscale x 1 x double> %a442}443 444define <vscale x 1 x double> @intrinsic_vfadd_mask_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {445; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv1f64_nxv1f64_nxv1f64:446; CHECK: # %bb.0: # %entry447; CHECK-NEXT: fsrmi a1, 0448; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu449; CHECK-NEXT: vfadd.vv v8, v9, v10, v0.t450; CHECK-NEXT: fsrm a1451; CHECK-NEXT: ret452entry:453 %a = call <vscale x 1 x double> @llvm.riscv.vfadd.mask.nxv1f64.nxv1f64(454 <vscale x 1 x double> %0,455 <vscale x 1 x double> %1,456 <vscale x 1 x double> %2,457 <vscale x 1 x i1> %3,458 iXLen 0, iXLen %4, iXLen 1)459 460 ret <vscale x 1 x double> %a461}462 463define <vscale x 2 x double> @intrinsic_vfadd_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, iXLen %2) nounwind {464; CHECK-LABEL: intrinsic_vfadd_vv_nxv2f64_nxv2f64_nxv2f64:465; CHECK: # %bb.0: # %entry466; CHECK-NEXT: fsrmi a1, 0467; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma468; CHECK-NEXT: vfadd.vv v8, v8, v10469; CHECK-NEXT: fsrm a1470; CHECK-NEXT: ret471entry:472 %a = call <vscale x 2 x double> @llvm.riscv.vfadd.nxv2f64.nxv2f64(473 <vscale x 2 x double> poison,474 <vscale x 2 x double> %0,475 <vscale x 2 x double> %1,476 iXLen 0, iXLen %2)477 478 ret <vscale x 2 x double> %a479}480 481define <vscale x 2 x double> @intrinsic_vfadd_mask_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {482; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv2f64_nxv2f64_nxv2f64:483; CHECK: # %bb.0: # %entry484; CHECK-NEXT: fsrmi a1, 0485; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu486; CHECK-NEXT: vfadd.vv v8, v10, v12, v0.t487; CHECK-NEXT: fsrm a1488; CHECK-NEXT: ret489entry:490 %a = call <vscale x 2 x double> @llvm.riscv.vfadd.mask.nxv2f64.nxv2f64(491 <vscale x 2 x double> %0,492 <vscale x 2 x double> %1,493 <vscale x 2 x double> %2,494 <vscale x 2 x i1> %3,495 iXLen 0, iXLen %4, iXLen 1)496 497 ret <vscale x 2 x double> %a498}499 500define <vscale x 4 x double> @intrinsic_vfadd_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, iXLen %2) nounwind {501; CHECK-LABEL: intrinsic_vfadd_vv_nxv4f64_nxv4f64_nxv4f64:502; CHECK: # %bb.0: # %entry503; CHECK-NEXT: fsrmi a1, 0504; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma505; CHECK-NEXT: vfadd.vv v8, v8, v12506; CHECK-NEXT: fsrm a1507; CHECK-NEXT: ret508entry:509 %a = call <vscale x 4 x double> @llvm.riscv.vfadd.nxv4f64.nxv4f64(510 <vscale x 4 x double> poison,511 <vscale x 4 x double> %0,512 <vscale x 4 x double> %1,513 iXLen 0, iXLen %2)514 515 ret <vscale x 4 x double> %a516}517 518define <vscale x 4 x double> @intrinsic_vfadd_mask_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {519; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv4f64_nxv4f64_nxv4f64:520; CHECK: # %bb.0: # %entry521; CHECK-NEXT: fsrmi a1, 0522; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu523; CHECK-NEXT: vfadd.vv v8, v12, v16, v0.t524; CHECK-NEXT: fsrm a1525; CHECK-NEXT: ret526entry:527 %a = call <vscale x 4 x double> @llvm.riscv.vfadd.mask.nxv4f64.nxv4f64(528 <vscale x 4 x double> %0,529 <vscale x 4 x double> %1,530 <vscale x 4 x double> %2,531 <vscale x 4 x i1> %3,532 iXLen 0, iXLen %4, iXLen 1)533 534 ret <vscale x 4 x double> %a535}536 537define <vscale x 8 x double> @intrinsic_vfadd_vv_nxv8f64_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, iXLen %2) nounwind {538; CHECK-LABEL: intrinsic_vfadd_vv_nxv8f64_nxv8f64_nxv8f64:539; CHECK: # %bb.0: # %entry540; CHECK-NEXT: fsrmi a1, 0541; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma542; CHECK-NEXT: vfadd.vv v8, v8, v16543; CHECK-NEXT: fsrm a1544; CHECK-NEXT: ret545entry:546 %a = call <vscale x 8 x double> @llvm.riscv.vfadd.nxv8f64.nxv8f64(547 <vscale x 8 x double> poison,548 <vscale x 8 x double> %0,549 <vscale x 8 x double> %1,550 iXLen 0, iXLen %2)551 552 ret <vscale x 8 x double> %a553}554 555define <vscale x 8 x double> @intrinsic_vfadd_mask_vv_nxv8f64_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x double> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {556; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv8f64_nxv8f64_nxv8f64:557; CHECK: # %bb.0: # %entry558; CHECK-NEXT: vl8re64.v v24, (a0)559; CHECK-NEXT: fsrmi a0, 0560; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu561; CHECK-NEXT: vfadd.vv v8, v16, v24, v0.t562; CHECK-NEXT: fsrm a0563; CHECK-NEXT: ret564entry:565 %a = call <vscale x 8 x double> @llvm.riscv.vfadd.mask.nxv8f64.nxv8f64(566 <vscale x 8 x double> %0,567 <vscale x 8 x double> %1,568 <vscale x 8 x double> %2,569 <vscale x 8 x i1> %3,570 iXLen 0, iXLen %4, iXLen 1)571 572 ret <vscale x 8 x double> %a573}574 575define <vscale x 1 x half> @intrinsic_vfadd_vf_nxv1f16_nxv1f16_f16(<vscale x 1 x half> %0, half %1, iXLen %2) nounwind {576; CHECK-LABEL: intrinsic_vfadd_vf_nxv1f16_nxv1f16_f16:577; CHECK: # %bb.0: # %entry578; CHECK-NEXT: fsrmi a1, 0579; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma580; CHECK-NEXT: vfadd.vf v8, v8, fa0581; CHECK-NEXT: fsrm a1582; CHECK-NEXT: ret583entry:584 %a = call <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.f16(585 <vscale x 1 x half> poison,586 <vscale x 1 x half> %0,587 half %1,588 iXLen 0, iXLen %2)589 590 ret <vscale x 1 x half> %a591}592 593define <vscale x 1 x half> @intrinsic_vfadd_mask_vf_nxv1f16_nxv1f16_f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {594; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv1f16_nxv1f16_f16:595; CHECK: # %bb.0: # %entry596; CHECK-NEXT: fsrmi a1, 0597; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu598; CHECK-NEXT: vfadd.vf v8, v9, fa0, v0.t599; CHECK-NEXT: fsrm a1600; CHECK-NEXT: ret601entry:602 %a = call <vscale x 1 x half> @llvm.riscv.vfadd.mask.nxv1f16.f16(603 <vscale x 1 x half> %0,604 <vscale x 1 x half> %1,605 half %2,606 <vscale x 1 x i1> %3,607 iXLen 0, iXLen %4, iXLen 1)608 609 ret <vscale x 1 x half> %a610}611 612define <vscale x 2 x half> @intrinsic_vfadd_vf_nxv2f16_nxv2f16_f16(<vscale x 2 x half> %0, half %1, iXLen %2) nounwind {613; CHECK-LABEL: intrinsic_vfadd_vf_nxv2f16_nxv2f16_f16:614; CHECK: # %bb.0: # %entry615; CHECK-NEXT: fsrmi a1, 0616; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma617; CHECK-NEXT: vfadd.vf v8, v8, fa0618; CHECK-NEXT: fsrm a1619; CHECK-NEXT: ret620entry:621 %a = call <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.f16(622 <vscale x 2 x half> poison,623 <vscale x 2 x half> %0,624 half %1,625 iXLen 0, iXLen %2)626 627 ret <vscale x 2 x half> %a628}629 630define <vscale x 2 x half> @intrinsic_vfadd_mask_vf_nxv2f16_nxv2f16_f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {631; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv2f16_nxv2f16_f16:632; CHECK: # %bb.0: # %entry633; CHECK-NEXT: fsrmi a1, 0634; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu635; CHECK-NEXT: vfadd.vf v8, v9, fa0, v0.t636; CHECK-NEXT: fsrm a1637; CHECK-NEXT: ret638entry:639 %a = call <vscale x 2 x half> @llvm.riscv.vfadd.mask.nxv2f16.f16(640 <vscale x 2 x half> %0,641 <vscale x 2 x half> %1,642 half %2,643 <vscale x 2 x i1> %3,644 iXLen 0, iXLen %4, iXLen 1)645 646 ret <vscale x 2 x half> %a647}648 649define <vscale x 4 x half> @intrinsic_vfadd_vf_nxv4f16_nxv4f16_f16(<vscale x 4 x half> %0, half %1, iXLen %2) nounwind {650; CHECK-LABEL: intrinsic_vfadd_vf_nxv4f16_nxv4f16_f16:651; CHECK: # %bb.0: # %entry652; CHECK-NEXT: fsrmi a1, 0653; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma654; CHECK-NEXT: vfadd.vf v8, v8, fa0655; CHECK-NEXT: fsrm a1656; CHECK-NEXT: ret657entry:658 %a = call <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.f16(659 <vscale x 4 x half> poison,660 <vscale x 4 x half> %0,661 half %1,662 iXLen 0, iXLen %2)663 664 ret <vscale x 4 x half> %a665}666 667define <vscale x 4 x half> @intrinsic_vfadd_mask_vf_nxv4f16_nxv4f16_f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {668; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv4f16_nxv4f16_f16:669; CHECK: # %bb.0: # %entry670; CHECK-NEXT: fsrmi a1, 0671; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu672; CHECK-NEXT: vfadd.vf v8, v9, fa0, v0.t673; CHECK-NEXT: fsrm a1674; CHECK-NEXT: ret675entry:676 %a = call <vscale x 4 x half> @llvm.riscv.vfadd.mask.nxv4f16.f16(677 <vscale x 4 x half> %0,678 <vscale x 4 x half> %1,679 half %2,680 <vscale x 4 x i1> %3,681 iXLen 0, iXLen %4, iXLen 1)682 683 ret <vscale x 4 x half> %a684}685 686define <vscale x 8 x half> @intrinsic_vfadd_vf_nxv8f16_nxv8f16_f16(<vscale x 8 x half> %0, half %1, iXLen %2) nounwind {687; CHECK-LABEL: intrinsic_vfadd_vf_nxv8f16_nxv8f16_f16:688; CHECK: # %bb.0: # %entry689; CHECK-NEXT: fsrmi a1, 0690; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma691; CHECK-NEXT: vfadd.vf v8, v8, fa0692; CHECK-NEXT: fsrm a1693; CHECK-NEXT: ret694entry:695 %a = call <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.f16(696 <vscale x 8 x half> poison,697 <vscale x 8 x half> %0,698 half %1,699 iXLen 0, iXLen %2)700 701 ret <vscale x 8 x half> %a702}703 704define <vscale x 8 x half> @intrinsic_vfadd_mask_vf_nxv8f16_nxv8f16_f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {705; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv8f16_nxv8f16_f16:706; CHECK: # %bb.0: # %entry707; CHECK-NEXT: fsrmi a1, 0708; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu709; CHECK-NEXT: vfadd.vf v8, v10, fa0, v0.t710; CHECK-NEXT: fsrm a1711; CHECK-NEXT: ret712entry:713 %a = call <vscale x 8 x half> @llvm.riscv.vfadd.mask.nxv8f16.f16(714 <vscale x 8 x half> %0,715 <vscale x 8 x half> %1,716 half %2,717 <vscale x 8 x i1> %3,718 iXLen 0, iXLen %4, iXLen 1)719 720 ret <vscale x 8 x half> %a721}722 723define <vscale x 16 x half> @intrinsic_vfadd_vf_nxv16f16_nxv16f16_f16(<vscale x 16 x half> %0, half %1, iXLen %2) nounwind {724; CHECK-LABEL: intrinsic_vfadd_vf_nxv16f16_nxv16f16_f16:725; CHECK: # %bb.0: # %entry726; CHECK-NEXT: fsrmi a1, 0727; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma728; CHECK-NEXT: vfadd.vf v8, v8, fa0729; CHECK-NEXT: fsrm a1730; CHECK-NEXT: ret731entry:732 %a = call <vscale x 16 x half> @llvm.riscv.vfadd.nxv16f16.f16(733 <vscale x 16 x half> poison,734 <vscale x 16 x half> %0,735 half %1,736 iXLen 0, iXLen %2)737 738 ret <vscale x 16 x half> %a739}740 741define <vscale x 16 x half> @intrinsic_vfadd_mask_vf_nxv16f16_nxv16f16_f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {742; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv16f16_nxv16f16_f16:743; CHECK: # %bb.0: # %entry744; CHECK-NEXT: fsrmi a1, 0745; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu746; CHECK-NEXT: vfadd.vf v8, v12, fa0, v0.t747; CHECK-NEXT: fsrm a1748; CHECK-NEXT: ret749entry:750 %a = call <vscale x 16 x half> @llvm.riscv.vfadd.mask.nxv16f16.f16(751 <vscale x 16 x half> %0,752 <vscale x 16 x half> %1,753 half %2,754 <vscale x 16 x i1> %3,755 iXLen 0, iXLen %4, iXLen 1)756 757 ret <vscale x 16 x half> %a758}759 760define <vscale x 32 x half> @intrinsic_vfadd_vf_nxv32f16_nxv32f16_f16(<vscale x 32 x half> %0, half %1, iXLen %2) nounwind {761; CHECK-LABEL: intrinsic_vfadd_vf_nxv32f16_nxv32f16_f16:762; CHECK: # %bb.0: # %entry763; CHECK-NEXT: fsrmi a1, 0764; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma765; CHECK-NEXT: vfadd.vf v8, v8, fa0766; CHECK-NEXT: fsrm a1767; CHECK-NEXT: ret768entry:769 %a = call <vscale x 32 x half> @llvm.riscv.vfadd.nxv32f16.f16(770 <vscale x 32 x half> poison,771 <vscale x 32 x half> %0,772 half %1,773 iXLen 0, iXLen %2)774 775 ret <vscale x 32 x half> %a776}777 778define <vscale x 32 x half> @intrinsic_vfadd_mask_vf_nxv32f16_nxv32f16_f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, half %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {779; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv32f16_nxv32f16_f16:780; CHECK: # %bb.0: # %entry781; CHECK-NEXT: fsrmi a1, 0782; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu783; CHECK-NEXT: vfadd.vf v8, v16, fa0, v0.t784; CHECK-NEXT: fsrm a1785; CHECK-NEXT: ret786entry:787 %a = call <vscale x 32 x half> @llvm.riscv.vfadd.mask.nxv32f16.f16(788 <vscale x 32 x half> %0,789 <vscale x 32 x half> %1,790 half %2,791 <vscale x 32 x i1> %3,792 iXLen 0, iXLen %4, iXLen 1)793 794 ret <vscale x 32 x half> %a795}796 797define <vscale x 1 x float> @intrinsic_vfadd_vf_nxv1f32_nxv1f32_f32(<vscale x 1 x float> %0, float %1, iXLen %2) nounwind {798; CHECK-LABEL: intrinsic_vfadd_vf_nxv1f32_nxv1f32_f32:799; CHECK: # %bb.0: # %entry800; CHECK-NEXT: fsrmi a1, 0801; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma802; CHECK-NEXT: vfadd.vf v8, v8, fa0803; CHECK-NEXT: fsrm a1804; CHECK-NEXT: ret805entry:806 %a = call <vscale x 1 x float> @llvm.riscv.vfadd.nxv1f32.f32(807 <vscale x 1 x float> poison,808 <vscale x 1 x float> %0,809 float %1,810 iXLen 0, iXLen %2)811 812 ret <vscale x 1 x float> %a813}814 815define <vscale x 1 x float> @intrinsic_vfadd_mask_vf_nxv1f32_nxv1f32_f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {816; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv1f32_nxv1f32_f32:817; CHECK: # %bb.0: # %entry818; CHECK-NEXT: fsrmi a1, 0819; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu820; CHECK-NEXT: vfadd.vf v8, v9, fa0, v0.t821; CHECK-NEXT: fsrm a1822; CHECK-NEXT: ret823entry:824 %a = call <vscale x 1 x float> @llvm.riscv.vfadd.mask.nxv1f32.f32(825 <vscale x 1 x float> %0,826 <vscale x 1 x float> %1,827 float %2,828 <vscale x 1 x i1> %3,829 iXLen 0, iXLen %4, iXLen 1)830 831 ret <vscale x 1 x float> %a832}833 834define <vscale x 2 x float> @intrinsic_vfadd_vf_nxv2f32_nxv2f32_f32(<vscale x 2 x float> %0, float %1, iXLen %2) nounwind {835; CHECK-LABEL: intrinsic_vfadd_vf_nxv2f32_nxv2f32_f32:836; CHECK: # %bb.0: # %entry837; CHECK-NEXT: fsrmi a1, 0838; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma839; CHECK-NEXT: vfadd.vf v8, v8, fa0840; CHECK-NEXT: fsrm a1841; CHECK-NEXT: ret842entry:843 %a = call <vscale x 2 x float> @llvm.riscv.vfadd.nxv2f32.f32(844 <vscale x 2 x float> poison,845 <vscale x 2 x float> %0,846 float %1,847 iXLen 0, iXLen %2)848 849 ret <vscale x 2 x float> %a850}851 852define <vscale x 2 x float> @intrinsic_vfadd_mask_vf_nxv2f32_nxv2f32_f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {853; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv2f32_nxv2f32_f32:854; CHECK: # %bb.0: # %entry855; CHECK-NEXT: fsrmi a1, 0856; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu857; CHECK-NEXT: vfadd.vf v8, v9, fa0, v0.t858; CHECK-NEXT: fsrm a1859; CHECK-NEXT: ret860entry:861 %a = call <vscale x 2 x float> @llvm.riscv.vfadd.mask.nxv2f32.f32(862 <vscale x 2 x float> %0,863 <vscale x 2 x float> %1,864 float %2,865 <vscale x 2 x i1> %3,866 iXLen 0, iXLen %4, iXLen 1)867 868 ret <vscale x 2 x float> %a869}870 871define <vscale x 4 x float> @intrinsic_vfadd_vf_nxv4f32_nxv4f32_f32(<vscale x 4 x float> %0, float %1, iXLen %2) nounwind {872; CHECK-LABEL: intrinsic_vfadd_vf_nxv4f32_nxv4f32_f32:873; CHECK: # %bb.0: # %entry874; CHECK-NEXT: fsrmi a1, 0875; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma876; CHECK-NEXT: vfadd.vf v8, v8, fa0877; CHECK-NEXT: fsrm a1878; CHECK-NEXT: ret879entry:880 %a = call <vscale x 4 x float> @llvm.riscv.vfadd.nxv4f32.f32(881 <vscale x 4 x float> poison,882 <vscale x 4 x float> %0,883 float %1,884 iXLen 0, iXLen %2)885 886 ret <vscale x 4 x float> %a887}888 889define <vscale x 4 x float> @intrinsic_vfadd_mask_vf_nxv4f32_nxv4f32_f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {890; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv4f32_nxv4f32_f32:891; CHECK: # %bb.0: # %entry892; CHECK-NEXT: fsrmi a1, 0893; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu894; CHECK-NEXT: vfadd.vf v8, v10, fa0, v0.t895; CHECK-NEXT: fsrm a1896; CHECK-NEXT: ret897entry:898 %a = call <vscale x 4 x float> @llvm.riscv.vfadd.mask.nxv4f32.f32(899 <vscale x 4 x float> %0,900 <vscale x 4 x float> %1,901 float %2,902 <vscale x 4 x i1> %3,903 iXLen 0, iXLen %4, iXLen 1)904 905 ret <vscale x 4 x float> %a906}907 908define <vscale x 8 x float> @intrinsic_vfadd_vf_nxv8f32_nxv8f32_f32(<vscale x 8 x float> %0, float %1, iXLen %2) nounwind {909; CHECK-LABEL: intrinsic_vfadd_vf_nxv8f32_nxv8f32_f32:910; CHECK: # %bb.0: # %entry911; CHECK-NEXT: fsrmi a1, 0912; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma913; CHECK-NEXT: vfadd.vf v8, v8, fa0914; CHECK-NEXT: fsrm a1915; CHECK-NEXT: ret916entry:917 %a = call <vscale x 8 x float> @llvm.riscv.vfadd.nxv8f32.f32(918 <vscale x 8 x float> poison,919 <vscale x 8 x float> %0,920 float %1,921 iXLen 0, iXLen %2)922 923 ret <vscale x 8 x float> %a924}925 926define <vscale x 8 x float> @intrinsic_vfadd_mask_vf_nxv8f32_nxv8f32_f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {927; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv8f32_nxv8f32_f32:928; CHECK: # %bb.0: # %entry929; CHECK-NEXT: fsrmi a1, 0930; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu931; CHECK-NEXT: vfadd.vf v8, v12, fa0, v0.t932; CHECK-NEXT: fsrm a1933; CHECK-NEXT: ret934entry:935 %a = call <vscale x 8 x float> @llvm.riscv.vfadd.mask.nxv8f32.f32(936 <vscale x 8 x float> %0,937 <vscale x 8 x float> %1,938 float %2,939 <vscale x 8 x i1> %3,940 iXLen 0, iXLen %4, iXLen 1)941 942 ret <vscale x 8 x float> %a943}944 945define <vscale x 16 x float> @intrinsic_vfadd_vf_nxv16f32_nxv16f32_f32(<vscale x 16 x float> %0, float %1, iXLen %2) nounwind {946; CHECK-LABEL: intrinsic_vfadd_vf_nxv16f32_nxv16f32_f32:947; CHECK: # %bb.0: # %entry948; CHECK-NEXT: fsrmi a1, 0949; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma950; CHECK-NEXT: vfadd.vf v8, v8, fa0951; CHECK-NEXT: fsrm a1952; CHECK-NEXT: ret953entry:954 %a = call <vscale x 16 x float> @llvm.riscv.vfadd.nxv16f32.f32(955 <vscale x 16 x float> poison,956 <vscale x 16 x float> %0,957 float %1,958 iXLen 0, iXLen %2)959 960 ret <vscale x 16 x float> %a961}962 963define <vscale x 16 x float> @intrinsic_vfadd_mask_vf_nxv16f32_nxv16f32_f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, float %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {964; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv16f32_nxv16f32_f32:965; CHECK: # %bb.0: # %entry966; CHECK-NEXT: fsrmi a1, 0967; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu968; CHECK-NEXT: vfadd.vf v8, v16, fa0, v0.t969; CHECK-NEXT: fsrm a1970; CHECK-NEXT: ret971entry:972 %a = call <vscale x 16 x float> @llvm.riscv.vfadd.mask.nxv16f32.f32(973 <vscale x 16 x float> %0,974 <vscale x 16 x float> %1,975 float %2,976 <vscale x 16 x i1> %3,977 iXLen 0, iXLen %4, iXLen 1)978 979 ret <vscale x 16 x float> %a980}981 982define <vscale x 1 x double> @intrinsic_vfadd_vf_nxv1f64_nxv1f64_f64(<vscale x 1 x double> %0, double %1, iXLen %2) nounwind {983; CHECK-LABEL: intrinsic_vfadd_vf_nxv1f64_nxv1f64_f64:984; CHECK: # %bb.0: # %entry985; CHECK-NEXT: fsrmi a1, 0986; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma987; CHECK-NEXT: vfadd.vf v8, v8, fa0988; CHECK-NEXT: fsrm a1989; CHECK-NEXT: ret990entry:991 %a = call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.f64(992 <vscale x 1 x double> poison,993 <vscale x 1 x double> %0,994 double %1,995 iXLen 0, iXLen %2)996 997 ret <vscale x 1 x double> %a998}999 1000define <vscale x 1 x double> @intrinsic_vfadd_mask_vf_nxv1f64_nxv1f64_f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {1001; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv1f64_nxv1f64_f64:1002; CHECK: # %bb.0: # %entry1003; CHECK-NEXT: fsrmi a1, 01004; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu1005; CHECK-NEXT: vfadd.vf v8, v9, fa0, v0.t1006; CHECK-NEXT: fsrm a11007; CHECK-NEXT: ret1008entry:1009 %a = call <vscale x 1 x double> @llvm.riscv.vfadd.mask.nxv1f64.f64(1010 <vscale x 1 x double> %0,1011 <vscale x 1 x double> %1,1012 double %2,1013 <vscale x 1 x i1> %3,1014 iXLen 0, iXLen %4, iXLen 1)1015 1016 ret <vscale x 1 x double> %a1017}1018 1019define <vscale x 2 x double> @intrinsic_vfadd_vf_nxv2f64_nxv2f64_f64(<vscale x 2 x double> %0, double %1, iXLen %2) nounwind {1020; CHECK-LABEL: intrinsic_vfadd_vf_nxv2f64_nxv2f64_f64:1021; CHECK: # %bb.0: # %entry1022; CHECK-NEXT: fsrmi a1, 01023; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma1024; CHECK-NEXT: vfadd.vf v8, v8, fa01025; CHECK-NEXT: fsrm a11026; CHECK-NEXT: ret1027entry:1028 %a = call <vscale x 2 x double> @llvm.riscv.vfadd.nxv2f64.f64(1029 <vscale x 2 x double> poison,1030 <vscale x 2 x double> %0,1031 double %1,1032 iXLen 0, iXLen %2)1033 1034 ret <vscale x 2 x double> %a1035}1036 1037define <vscale x 2 x double> @intrinsic_vfadd_mask_vf_nxv2f64_nxv2f64_f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {1038; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv2f64_nxv2f64_f64:1039; CHECK: # %bb.0: # %entry1040; CHECK-NEXT: fsrmi a1, 01041; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu1042; CHECK-NEXT: vfadd.vf v8, v10, fa0, v0.t1043; CHECK-NEXT: fsrm a11044; CHECK-NEXT: ret1045entry:1046 %a = call <vscale x 2 x double> @llvm.riscv.vfadd.mask.nxv2f64.f64(1047 <vscale x 2 x double> %0,1048 <vscale x 2 x double> %1,1049 double %2,1050 <vscale x 2 x i1> %3,1051 iXLen 0, iXLen %4, iXLen 1)1052 1053 ret <vscale x 2 x double> %a1054}1055 1056define <vscale x 4 x double> @intrinsic_vfadd_vf_nxv4f64_nxv4f64_f64(<vscale x 4 x double> %0, double %1, iXLen %2) nounwind {1057; CHECK-LABEL: intrinsic_vfadd_vf_nxv4f64_nxv4f64_f64:1058; CHECK: # %bb.0: # %entry1059; CHECK-NEXT: fsrmi a1, 01060; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma1061; CHECK-NEXT: vfadd.vf v8, v8, fa01062; CHECK-NEXT: fsrm a11063; CHECK-NEXT: ret1064entry:1065 %a = call <vscale x 4 x double> @llvm.riscv.vfadd.nxv4f64.f64(1066 <vscale x 4 x double> poison,1067 <vscale x 4 x double> %0,1068 double %1,1069 iXLen 0, iXLen %2)1070 1071 ret <vscale x 4 x double> %a1072}1073 1074define <vscale x 4 x double> @intrinsic_vfadd_mask_vf_nxv4f64_nxv4f64_f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1075; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv4f64_nxv4f64_f64:1076; CHECK: # %bb.0: # %entry1077; CHECK-NEXT: fsrmi a1, 01078; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu1079; CHECK-NEXT: vfadd.vf v8, v12, fa0, v0.t1080; CHECK-NEXT: fsrm a11081; CHECK-NEXT: ret1082entry:1083 %a = call <vscale x 4 x double> @llvm.riscv.vfadd.mask.nxv4f64.f64(1084 <vscale x 4 x double> %0,1085 <vscale x 4 x double> %1,1086 double %2,1087 <vscale x 4 x i1> %3,1088 iXLen 0, iXLen %4, iXLen 1)1089 1090 ret <vscale x 4 x double> %a1091}1092 1093define <vscale x 8 x double> @intrinsic_vfadd_vf_nxv8f64_nxv8f64_f64(<vscale x 8 x double> %0, double %1, iXLen %2) nounwind {1094; CHECK-LABEL: intrinsic_vfadd_vf_nxv8f64_nxv8f64_f64:1095; CHECK: # %bb.0: # %entry1096; CHECK-NEXT: fsrmi a1, 01097; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma1098; CHECK-NEXT: vfadd.vf v8, v8, fa01099; CHECK-NEXT: fsrm a11100; CHECK-NEXT: ret1101entry:1102 %a = call <vscale x 8 x double> @llvm.riscv.vfadd.nxv8f64.f64(1103 <vscale x 8 x double> poison,1104 <vscale x 8 x double> %0,1105 double %1,1106 iXLen 0, iXLen %2)1107 1108 ret <vscale x 8 x double> %a1109}1110 1111define <vscale x 8 x double> @intrinsic_vfadd_mask_vf_nxv8f64_nxv8f64_f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, double %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {1112; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv8f64_nxv8f64_f64:1113; CHECK: # %bb.0: # %entry1114; CHECK-NEXT: fsrmi a1, 01115; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu1116; CHECK-NEXT: vfadd.vf v8, v16, fa0, v0.t1117; CHECK-NEXT: fsrm a11118; CHECK-NEXT: ret1119entry:1120 %a = call <vscale x 8 x double> @llvm.riscv.vfadd.mask.nxv8f64.f64(1121 <vscale x 8 x double> %0,1122 <vscale x 8 x double> %1,1123 double %2,1124 <vscale x 8 x i1> %3,1125 iXLen 0, iXLen %4, iXLen 1)1126 1127 ret <vscale x 8 x double> %a1128}1129