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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvfbfa \3; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvfbfa \5; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s6 7define <vscale x 1 x i16> @intrinsic_vfclass_v_nxv1i16_nxv1bf16(8; CHECK-LABEL: intrinsic_vfclass_v_nxv1i16_nxv1bf16:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a0, e16alt, mf4, ta, ma11; CHECK-NEXT: vfclass.v v8, v812; CHECK-NEXT: ret13 <vscale x 1 x bfloat> %0,14 iXLen %1) nounwind {15entry:16 %a = call <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1i16.nxv1bf16(17 <vscale x 1 x i16> poison,18 <vscale x 1 x bfloat> %0,19 iXLen %1)20 21 ret <vscale x 1 x i16> %a22}23 24define <vscale x 1 x i16> @intrinsic_vfclass_mask_v_nxv1i16_nxv1bf16(25; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv1i16_nxv1bf16:26; CHECK: # %bb.0: # %entry27; CHECK-NEXT: vsetvli zero, a0, e16alt, mf4, tu, mu28; CHECK-NEXT: vfclass.v v8, v9, v0.t29; CHECK-NEXT: ret30 <vscale x 1 x i16> %0,31 <vscale x 1 x bfloat> %1,32 <vscale x 1 x i1> %2,33 iXLen %3) nounwind {34entry:35 %a = call <vscale x 1 x i16> @llvm.riscv.vfclass.mask.nxv1i16.nxv1bf16(36 <vscale x 1 x i16> %0,37 <vscale x 1 x bfloat> %1,38 <vscale x 1 x i1> %2,39 iXLen %3, iXLen 0)40 41 ret <vscale x 1 x i16> %a42}43 44define <vscale x 2 x i16> @intrinsic_vfclass_v_nxv2i16_nxv2bf16(45; CHECK-LABEL: intrinsic_vfclass_v_nxv2i16_nxv2bf16:46; CHECK: # %bb.0: # %entry47; CHECK-NEXT: vsetvli zero, a0, e16alt, mf2, ta, ma48; CHECK-NEXT: vfclass.v v8, v849; CHECK-NEXT: ret50 <vscale x 2 x bfloat> %0,51 iXLen %1) nounwind {52entry:53 %a = call <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2i16.nxv2bf16(54 <vscale x 2 x i16> poison,55 <vscale x 2 x bfloat> %0,56 iXLen %1)57 58 ret <vscale x 2 x i16> %a59}60 61define <vscale x 2 x i16> @intrinsic_vfclass_mask_v_nxv2i16_nxv2bf16(62; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv2i16_nxv2bf16:63; CHECK: # %bb.0: # %entry64; CHECK-NEXT: vsetvli zero, a0, e16alt, mf2, tu, mu65; CHECK-NEXT: vfclass.v v8, v9, v0.t66; CHECK-NEXT: ret67 <vscale x 2 x i16> %0,68 <vscale x 2 x bfloat> %1,69 <vscale x 2 x i1> %2,70 iXLen %3) nounwind {71entry:72 %a = call <vscale x 2 x i16> @llvm.riscv.vfclass.mask.nxv2i16.nxv2bf16(73 <vscale x 2 x i16> %0,74 <vscale x 2 x bfloat> %1,75 <vscale x 2 x i1> %2,76 iXLen %3, iXLen 0)77 78 ret <vscale x 2 x i16> %a79}80 81define <vscale x 4 x i16> @intrinsic_vfclass_v_nxv4i16_nxv4bf16(82; CHECK-LABEL: intrinsic_vfclass_v_nxv4i16_nxv4bf16:83; CHECK: # %bb.0: # %entry84; CHECK-NEXT: vsetvli zero, a0, e16alt, m1, ta, ma85; CHECK-NEXT: vfclass.v v8, v886; CHECK-NEXT: ret87 <vscale x 4 x bfloat> %0,88 iXLen %1) nounwind {89entry:90 %a = call <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4i16.nxv4bf16(91 <vscale x 4 x i16> poison,92 <vscale x 4 x bfloat> %0,93 iXLen %1)94 95 ret <vscale x 4 x i16> %a96}97 98define <vscale x 4 x i16> @intrinsic_vfclass_mask_v_nxv4i16_nxv4bf16(99; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv4i16_nxv4bf16:100; CHECK: # %bb.0: # %entry101; CHECK-NEXT: vsetvli zero, a0, e16alt, m1, tu, mu102; CHECK-NEXT: vfclass.v v8, v9, v0.t103; CHECK-NEXT: ret104 <vscale x 4 x i16> %0,105 <vscale x 4 x bfloat> %1,106 <vscale x 4 x i1> %2,107 iXLen %3) nounwind {108entry:109 %a = call <vscale x 4 x i16> @llvm.riscv.vfclass.mask.nxv4i16.nxv4bf16(110 <vscale x 4 x i16> %0,111 <vscale x 4 x bfloat> %1,112 <vscale x 4 x i1> %2,113 iXLen %3, iXLen 0)114 115 ret <vscale x 4 x i16> %a116}117 118define <vscale x 8 x i16> @intrinsic_vfclass_v_nxv8i16_nxv8bf16(119; CHECK-LABEL: intrinsic_vfclass_v_nxv8i16_nxv8bf16:120; CHECK: # %bb.0: # %entry121; CHECK-NEXT: vsetvli zero, a0, e16alt, m2, ta, ma122; CHECK-NEXT: vfclass.v v8, v8123; CHECK-NEXT: ret124 <vscale x 8 x bfloat> %0,125 iXLen %1) nounwind {126entry:127 %a = call <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8i16.nxv8bf16(128 <vscale x 8 x i16> poison,129 <vscale x 8 x bfloat> %0,130 iXLen %1)131 132 ret <vscale x 8 x i16> %a133}134 135define <vscale x 8 x i16> @intrinsic_vfclass_mask_v_nxv8i16_nxv8bf16(136; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv8i16_nxv8bf16:137; CHECK: # %bb.0: # %entry138; CHECK-NEXT: vsetvli zero, a0, e16alt, m2, tu, mu139; CHECK-NEXT: vfclass.v v8, v10, v0.t140; CHECK-NEXT: ret141 <vscale x 8 x i16> %0,142 <vscale x 8 x bfloat> %1,143 <vscale x 8 x i1> %2,144 iXLen %3) nounwind {145entry:146 %a = call <vscale x 8 x i16> @llvm.riscv.vfclass.mask.nxv8i16.nxv8bf16(147 <vscale x 8 x i16> %0,148 <vscale x 8 x bfloat> %1,149 <vscale x 8 x i1> %2,150 iXLen %3, iXLen 0)151 152 ret <vscale x 8 x i16> %a153}154 155define <vscale x 16 x i16> @intrinsic_vfclass_v_nxv16i16_nxv16bf16(156; CHECK-LABEL: intrinsic_vfclass_v_nxv16i16_nxv16bf16:157; CHECK: # %bb.0: # %entry158; CHECK-NEXT: vsetvli zero, a0, e16alt, m4, ta, ma159; CHECK-NEXT: vfclass.v v8, v8160; CHECK-NEXT: ret161 <vscale x 16 x bfloat> %0,162 iXLen %1) nounwind {163entry:164 %a = call <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16i16.nxv16bf16(165 <vscale x 16 x i16> poison,166 <vscale x 16 x bfloat> %0,167 iXLen %1)168 169 ret <vscale x 16 x i16> %a170}171 172define <vscale x 16 x i16> @intrinsic_vfclass_mask_v_nxv16i16_nxv16bf16(173; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv16i16_nxv16bf16:174; CHECK: # %bb.0: # %entry175; CHECK-NEXT: vsetvli zero, a0, e16alt, m4, tu, mu176; CHECK-NEXT: vfclass.v v8, v12, v0.t177; CHECK-NEXT: ret178 <vscale x 16 x i16> %0,179 <vscale x 16 x bfloat> %1,180 <vscale x 16 x i1> %2,181 iXLen %3) nounwind {182entry:183 %a = call <vscale x 16 x i16> @llvm.riscv.vfclass.mask.nxv16i16.nxv16bf16(184 <vscale x 16 x i16> %0,185 <vscale x 16 x bfloat> %1,186 <vscale x 16 x i1> %2,187 iXLen %3, iXLen 0)188 189 ret <vscale x 16 x i16> %a190}191 192define <vscale x 32 x i16> @intrinsic_vfclass_v_nxv32i16_nxv32bf16(193; CHECK-LABEL: intrinsic_vfclass_v_nxv32i16_nxv32bf16:194; CHECK: # %bb.0: # %entry195; CHECK-NEXT: vsetvli zero, a0, e16alt, m8, ta, ma196; CHECK-NEXT: vfclass.v v8, v8197; CHECK-NEXT: ret198 <vscale x 32 x bfloat> %0,199 iXLen %1) nounwind {200entry:201 %a = call <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32i16.nxv32bf16(202 <vscale x 32 x i16> poison,203 <vscale x 32 x bfloat> %0,204 iXLen %1)205 206 ret <vscale x 32 x i16> %a207}208 209define <vscale x 32 x i16> @intrinsic_vfclass_mask_v_nxv32i16_nxv32bf16(210; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv32i16_nxv32bf16:211; CHECK: # %bb.0: # %entry212; CHECK-NEXT: vsetvli zero, a0, e16alt, m8, tu, mu213; CHECK-NEXT: vfclass.v v8, v16, v0.t214; CHECK-NEXT: ret215 <vscale x 32 x i16> %0,216 <vscale x 32 x bfloat> %1,217 <vscale x 32 x i1> %2,218 iXLen %3) nounwind {219entry:220 %a = call <vscale x 32 x i16> @llvm.riscv.vfclass.mask.nxv32i16.nxv32bf16(221 <vscale x 32 x i16> %0,222 <vscale x 32 x bfloat> %1,223 <vscale x 32 x i1> %2,224 iXLen %3, iXLen 0)225 226 ret <vscale x 32 x i16> %a227}228 229