190 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \3; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \4; RUN: --check-prefixes=CHECK,ZVFH5; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \6; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \7; RUN: --check-prefixes=CHECK,ZVFH8; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+v \9; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \10; RUN: --check-prefixes=CHECK,ZVFHMIN11; RUN: llc -mtriple=riscv64 -mattr=+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+v \12; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \13; RUN: --check-prefixes=CHECK,ZVFHMIN14 15define <vscale x 2 x i1> @isnan_nxv2bf16(<vscale x 2 x bfloat> %x) {16; CHECK-LABEL: isnan_nxv2bf16:17; CHECK: # %bb.0:18; CHECK-NEXT: lui a0, 819; CHECK-NEXT: addi a1, a0, -120; CHECK-NEXT: vsetvli a2, zero, e16, mf2, ta, ma21; CHECK-NEXT: vand.vx v8, v8, a122; CHECK-NEXT: addi a0, a0, -12823; CHECK-NEXT: vmsgt.vx v0, v8, a024; CHECK-NEXT: ret25 %1 = call <vscale x 2 x i1> @llvm.is.fpclass.nxv2bf16(<vscale x 2 x bfloat> %x, i32 3) ; nan26 ret <vscale x 2 x i1> %127}28 29define <vscale x 2 x i1> @isnan_nxv2f16(<vscale x 2 x half> %x) {30; ZVFH-LABEL: isnan_nxv2f16:31; ZVFH: # %bb.0:32; ZVFH-NEXT: vsetvli a0, zero, e16, mf2, ta, ma33; ZVFH-NEXT: vfclass.v v8, v834; ZVFH-NEXT: li a0, 76835; ZVFH-NEXT: vand.vx v8, v8, a036; ZVFH-NEXT: vmsne.vi v0, v8, 037; ZVFH-NEXT: ret38;39; ZVFHMIN-LABEL: isnan_nxv2f16:40; ZVFHMIN: # %bb.0:41; ZVFHMIN-NEXT: lui a0, 842; ZVFHMIN-NEXT: addi a0, a0, -143; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma44; ZVFHMIN-NEXT: vand.vx v8, v8, a045; ZVFHMIN-NEXT: li a0, 3146; ZVFHMIN-NEXT: slli a0, a0, 1047; ZVFHMIN-NEXT: vmsgt.vx v0, v8, a048; ZVFHMIN-NEXT: ret49 %1 = call <vscale x 2 x i1> @llvm.is.fpclass.nxv2f16(<vscale x 2 x half> %x, i32 3) ; nan50 ret <vscale x 2 x i1> %151}52 53define <vscale x 2 x i1> @isnan_nxv2f32(<vscale x 2 x float> %x) {54; CHECK-LABEL: isnan_nxv2f32:55; CHECK: # %bb.0:56; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma57; CHECK-NEXT: vfclass.v v8, v858; CHECK-NEXT: li a0, 92759; CHECK-NEXT: vand.vx v8, v8, a060; CHECK-NEXT: vmsne.vi v0, v8, 061; CHECK-NEXT: ret62 %1 = call <vscale x 2 x i1> @llvm.is.fpclass.nxv2f32(<vscale x 2 x float> %x, i32 639)63 ret <vscale x 2 x i1> %164}65 66define <vscale x 4 x i1> @isnan_nxv4f32(<vscale x 4 x float> %x) {67; CHECK-LABEL: isnan_nxv4f32:68; CHECK: # %bb.0:69; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma70; CHECK-NEXT: vfclass.v v8, v871; CHECK-NEXT: li a0, 76872; CHECK-NEXT: vand.vx v8, v8, a073; CHECK-NEXT: vmsne.vi v0, v8, 074; CHECK-NEXT: ret75 %1 = call <vscale x 4 x i1> @llvm.is.fpclass.nxv4f32(<vscale x 4 x float> %x, i32 3) ; nan76 ret <vscale x 4 x i1> %177}78 79define <vscale x 8 x i1> @isnan_nxv8f32(<vscale x 8 x float> %x) {80; CHECK-LABEL: isnan_nxv8f32:81; CHECK: # %bb.0:82; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma83; CHECK-NEXT: vfclass.v v8, v884; CHECK-NEXT: li a0, 51285; CHECK-NEXT: vmseq.vx v0, v8, a086; CHECK-NEXT: ret87 %1 = call <vscale x 8 x i1> @llvm.is.fpclass.nxv8f32(<vscale x 8 x float> %x, i32 2)88 ret <vscale x 8 x i1> %189}90 91define <vscale x 16 x i1> @isnan_nxv16f32(<vscale x 16 x float> %x) {92; CHECK-LABEL: isnan_nxv16f32:93; CHECK: # %bb.0:94; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma95; CHECK-NEXT: vfclass.v v8, v896; CHECK-NEXT: li a0, 25697; CHECK-NEXT: vmseq.vx v0, v8, a098; CHECK-NEXT: ret99 %1 = call <vscale x 16 x i1> @llvm.is.fpclass.nxv16f32(<vscale x 16 x float> %x, i32 1)100 ret <vscale x 16 x i1> %1101}102 103define <vscale x 2 x i1> @isnormal_nxv2f64(<vscale x 2 x double> %x) {104; CHECK-LABEL: isnormal_nxv2f64:105; CHECK: # %bb.0:106; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma107; CHECK-NEXT: vfclass.v v8, v8108; CHECK-NEXT: li a0, 129109; CHECK-NEXT: vand.vx v8, v8, a0110; CHECK-NEXT: vmsne.vi v0, v8, 0111; CHECK-NEXT: ret112 %1 = call <vscale x 2 x i1> @llvm.is.fpclass.nxv2f64(<vscale x 2 x double> %x, i32 516) ; 0x204 = "inf"113 ret <vscale x 2 x i1> %1114}115 116define <vscale x 4 x i1> @isposinf_nxv4f64(<vscale x 4 x double> %x) {117; CHECK-LABEL: isposinf_nxv4f64:118; CHECK: # %bb.0:119; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma120; CHECK-NEXT: vfclass.v v8, v8121; CHECK-NEXT: li a0, 128122; CHECK-NEXT: vmseq.vx v0, v8, a0123; CHECK-NEXT: ret124 %1 = call <vscale x 4 x i1> @llvm.is.fpclass.nxv4f64(<vscale x 4 x double> %x, i32 512) ; 0x200 = "+inf"125 ret <vscale x 4 x i1> %1126}127 128define <vscale x 8 x i1> @isneginf_nxv8f64(<vscale x 8 x double> %x) {129; CHECK-LABEL: isneginf_nxv8f64:130; CHECK: # %bb.0:131; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma132; CHECK-NEXT: vfclass.v v8, v8133; CHECK-NEXT: vmseq.vi v0, v8, 1134; CHECK-NEXT: ret135 %1 = call <vscale x 8 x i1> @llvm.is.fpclass.nxv8f64(<vscale x 8 x double> %x, i32 4) ; "-inf"136 ret <vscale x 8 x i1> %1137}138 139define <vscale x 16 x i1> @isfinite_nxv16f32(<vscale x 16 x float> %x) {140; CHECK-LABEL: isfinite_nxv16f32:141; CHECK: # %bb.0:142; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma143; CHECK-NEXT: vfclass.v v8, v8144; CHECK-NEXT: li a0, 126145; CHECK-NEXT: vand.vx v8, v8, a0146; CHECK-NEXT: vmsne.vi v0, v8, 0147; CHECK-NEXT: ret148 %1 = call <vscale x 16 x i1> @llvm.is.fpclass.nxv16f32(<vscale x 16 x float> %x, i32 504) ; 0x1f8 = "finite"149 ret <vscale x 16 x i1> %1150}151 152define <vscale x 16 x i1> @isposfinite_nxv16f32(<vscale x 16 x float> %x) {153; CHECK-LABEL: isposfinite_nxv16f32:154; CHECK: # %bb.0:155; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma156; CHECK-NEXT: vfclass.v v8, v8157; CHECK-NEXT: li a0, 112158; CHECK-NEXT: vand.vx v8, v8, a0159; CHECK-NEXT: vmsne.vi v0, v8, 0160; CHECK-NEXT: ret161 %1 = call <vscale x 16 x i1> @llvm.is.fpclass.nxv16f32(<vscale x 16 x float> %x, i32 448) ; 0x1c0 = "+finite"162 ret <vscale x 16 x i1> %1163}164 165define <vscale x 16 x i1> @isnegfinite_nxv16f32(<vscale x 16 x float> %x) {166; CHECK-LABEL: isnegfinite_nxv16f32:167; CHECK: # %bb.0:168; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma169; CHECK-NEXT: vfclass.v v8, v8170; CHECK-NEXT: vand.vi v8, v8, 14171; CHECK-NEXT: vmsne.vi v0, v8, 0172; CHECK-NEXT: ret173 %1 = call <vscale x 16 x i1> @llvm.is.fpclass.nxv16f32(<vscale x 16 x float> %x, i32 56) ; 0x38 = "-finite"174 ret <vscale x 16 x i1> %1175}176 177define <vscale x 16 x i1> @isnotfinite_nxv16f32(<vscale x 16 x float> %x) {178; CHECK-LABEL: isnotfinite_nxv16f32:179; CHECK: # %bb.0:180; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma181; CHECK-NEXT: vfclass.v v8, v8182; CHECK-NEXT: li a0, 897183; CHECK-NEXT: vand.vx v8, v8, a0184; CHECK-NEXT: vmsne.vi v0, v8, 0185; CHECK-NEXT: ret186 %1 = call <vscale x 16 x i1> @llvm.is.fpclass.nxv16f32(<vscale x 16 x float> %x, i32 519) ; 0x207 = "inf|nan"187 ret <vscale x 16 x i1> %1188}189 190